Semiconductor memory device

Abstract

A semiconductor memory device has: a support substrate; a memory cell structure over the support substrate, the memory cell structure including memory cells in the main chip region; a peripheral circuit structure over the support substrate such that the peripheral circuit structure and the memory cell structure are stacked in a vertical direction, the peripheral circuit structure including a peripheral circuit transistor in the main chip region; an intermediate substrate between the memory cell structure and the peripheral circuit structure; a deep isolation insulating layer in the deep trench passing through the intermediate substrate; and a guard ring structure including a guard ring via hole in a guard ring region, where the guard ring structure passes through the deep isolation insulating layer and extends beyond the upper surface of the intermediate substrate and beyond the lower surface of the intermediate substrate.

Description

Cross-references to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0165605, filed on November 19, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a semiconductor memory device. More specifically, this disclosure relates to a stacked semiconductor memory device in which memory cell structures and peripheral circuit structures are stacked. Background Technology

[0003] As semiconductor memory devices become more highly integrated, the semiconductor elements within them also become more highly integrated. Therefore, to achieve high integration of semiconductor elements and improve their operational characteristics, stacked semiconductor memory devices, in which memory cell structures and peripheral circuit structures are stacked, have been investigated. Summary of the Invention

[0004] One or more embodiments provide a stacked semiconductor memory device with structural reliability.

[0005] According to one aspect of an embodiment, a semiconductor memory device has a main chip region and a guard ring region surrounding the main chip region. The semiconductor memory device includes: a support substrate; a memory cell structure above the support substrate, the memory cell structure including a plurality of memory cells in the main chip region; a peripheral circuit structure located above the support substrate such that the peripheral circuit structure and the memory cell structure are stacked vertically, the peripheral circuit structure including a plurality of peripheral circuit transistors in the main chip region; an intermediate substrate located between the memory cell structure and the peripheral circuit structure; a deep isolation insulating layer in a deep trench passing through the intermediate substrate; and a guard ring structure including guard ring vias in the guard ring region, wherein the guard ring structure passes through the deep isolation insulating layer and extends beyond the upper surface and the lower surface of the intermediate substrate.

[0006] According to another aspect of the embodiment, a semiconductor memory device has a main chip region and a guard ring region. The guard ring region includes a chip guard ring region surrounding the main chip region and a dicing guard ring region surrounding the chip guard ring region. The semiconductor memory device includes: a substrate; a memory cell structure located above the substrate and including a plurality of memory cells located in the main chip region; a peripheral circuit structure located above the memory cell structure and including a peripheral circuit substrate located on the lower side of the peripheral circuit structure facing the memory cell structure and a plurality of peripheral circuit transistors on the upper surface of the peripheral circuit substrate located in the main chip region; a deep isolation insulating layer in a deep trench passing through the peripheral circuit substrate; and a plurality of guard ring structures, the plurality of guard ring structures including chip guard ring structures and dicing guard ring structures. The chip guard ring structure passes through the deep isolation insulating layer in the chip guard ring region and extends beyond the upper surface and the lower surface of the peripheral circuit substrate, and wherein the dicing guard ring structure passes through the deep isolation insulating layer in the dicing guard ring region and extends beyond the upper surface and the lower surface of the peripheral circuit substrate. Each of the plurality of guard ring structures includes a guard ring via having a tapered shape extending toward a horizontal width decreasing toward the substrate, and wherein each of the plurality of guard ring structures passes through a deep isolation insulating layer.

[0007] According to another aspect of the embodiment, the semiconductor memory device has a main chip region and a guard ring region. The guard ring region includes a chip guard ring region surrounding the main chip region and a dicing guard ring region surrounding the chip guard ring region. A semiconductor memory device includes: a substrate; a memory cell structure located above the substrate and including a plurality of memory cells located in a main chip region; a peripheral circuit structure located above the memory cell structure, the peripheral circuit structure including a peripheral circuit substrate located on the lower side of the peripheral circuit structure facing the memory cell structure, and a plurality of peripheral circuit transistors on the upper surface of the peripheral circuit substrate in the main chip region; a bonding insulating layer between the memory cell structure and the lower surface of the peripheral circuit substrate; a deep isolation insulating layer in a deep trench defined by the peripheral circuit substrate, the deep trench having a tapered shape extending toward the substrate with a horizontal width decreasing; and a plurality of guard ring structures including a chip guard ring structure and a dicing guard ring structure, wherein the chip guard ring structure passes through the deep isolation insulating layer and the bonding insulating layer in the chip guard ring region and extends beyond the upper surface and the lower surface of the peripheral circuit substrate, and the dicing guard ring structure passes through the deep isolation insulating layer and the bonding insulating layer in the dicing guard ring region and extends beyond the upper surface and the lower surface of the peripheral circuit substrate. Each of the plurality of guard ring structures includes a guard ring via having a tapered shape extending toward a horizontal width that decreases toward the substrate. The memory cell structure includes: a capacitor structure having a lower capacitor electrode above the substrate, a capacitor dielectric layer covering the lower capacitor electrode, and a capacitor upper electrode covering the lower capacitor electrode, the capacitor dielectric layer being located between the upper and lower capacitor electrodes; a contact plug connected to the lower capacitor electrode above the capacitor structure; a channel pattern connected to the contact plug above the contact plug; word lines and a back gate electrode disposed on opposite sides of the channel pattern; a gate dielectric layer located between the channel pattern and the word line; a back gate dielectric layer located between the channel pattern and the back gate electrode; and a cell bit line connected to the channel pattern above the channel pattern, the word line, and the back gate electrode. The guard ring via in each of the plurality of guard ring structures has a linear and planar shape extending along the boundary between a chip guard ring region and a dicing guard ring region. Attached Figure Description

[0008] The above and other aspects will become clearer from the following description of the embodiments taken in conjunction with the accompanying drawings, in which: Figure 1 This illustrates a planar layout of a semiconductor memory device according to an embodiment; Figure 2A , Figure 2B , Figure 2C and Figure 2DEach of these is a planar layout illustrating a portion of the guard ring region of a semiconductor memory device according to an embodiment; Figure 3A , Figure 3B , Figure 3C and Figure 3D Each of these is a cross-sectional view illustrating a semiconductor memory device according to an embodiment; Figure 4A and Figure 4B This is a cross-sectional view showing a semiconductor memory device according to an embodiment; Figure 5 This is a cross-sectional view showing a semiconductor memory device according to an embodiment; Figure 6 This is a cross-sectional view showing a semiconductor memory device according to an embodiment; Figure 7A and Figure 7B , Figure 8A and Figure 8B as well as Figure 9A and Figure 9B This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment; and Figure 10A and Figure 10B Each of these is a planar layout illustrating a semiconductor memory device according to an embodiment. Detailed Implementation

[0009] In the following, exemplary embodiments are described in detail with reference to the accompanying drawings. Throughout the specification, the same parts are designated by the same reference numerals, and repeated descriptions thereof are omitted. It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto, and various other forms may be implemented. Each exemplary embodiment provided in the following description does not exclude association with one or more features of another example or another example embodiment also provided herein or not provided herein but consistent with this disclosure.

[0010] Figure 1 This illustrates a planar layout of a semiconductor wafer including multiple semiconductor memory devices according to an embodiment.

[0011] Reference Figure 1Multiple semiconductor memory devices 1 can be formed on a semiconductor wafer WF. The semiconductor wafer WF has multiple chip regions CR defined by a scribe line region SL. The scribe line region SL can be located between the multiple chip regions CR, so that the multiple chip regions CR can be spaced apart from each other by the scribe line region SL. Each of the multiple semiconductor memory devices 1 may include one chip region CR. In some embodiments, each of the multiple semiconductor memory devices 1 may include one chip region CR and a portion of the scribe line region SL adjacent to that one chip region CR.

[0012] The guard ring region GR may have a planar shape extending along the boundary between each of the plurality of chip regions CR and the scribe line region SL. The guard ring region GR may include a chip guard ring region CGR and a scribe guard ring region SGR surrounding the chip guard ring region CGR. The chip guard ring region CGR represents the portion of the chip region CR adjacent to the scribe line region SL, and the scribe guard ring region SGR represents the portion of the scribe line region SL adjacent to the chip region CR. The chip region CR may include a main chip region MCR and a chip guard ring region CGR. The chip guard ring region CGR may surround the main chip region MCR. Components required for operating the semiconductor memory device 1 may be arranged in the main chip region MCR. For example, a plurality of memory cells and a plurality of peripheral circuit transistors disposed in the semiconductor memory device 1 may be arranged in the main chip region MCR, rather than in the chip guard ring region CGR. The scribe guard ring region SGR may surround the chip region CR. The guard ring region GR may surround the main chip region MCR.

[0013] Each of the plurality of semiconductor memory devices 1 may include at least a portion of a scribe guard ring region SGR surrounding a chip region CR included in each of the plurality of semiconductor memory devices 1. In some embodiments, each of the plurality of semiconductor memory devices 1 may include a guard ring region GR surrounding a main chip region MCR included in each of the plurality of semiconductor memory devices 1, i.e., both a chip guard ring region CGR and a scribe guard ring region SGR. In some embodiments, each of the plurality of semiconductor memory devices 1 may include all chip guard ring regions CGR surrounding the main chip region MCR included in each of the plurality of semiconductor memory devices 1, but may include only the portion of the scribe guard ring region SGR surrounding the chip region CR adjacent to the chip region CR.

[0014] Figures 2A to 2D Each of these is a planar layout illustrating a portion of the guard ring region of a semiconductor memory device according to an embodiment. Specifically, Figures 2A to 2D Each of them is shown Figure 1The enlarged view of the planar layout of region II. Figures 3A to 3D Each of these is a cross-sectional view illustrating a semiconductor memory device according to an embodiment.

[0015] Reference Figure 1 as well as Figures 2A to 2D and Figures 3A to 3D GRS (protective ring structure) Figures 3A to 3D The (middle) can be located in the guard ring region GR. The guard ring structure GRS can include the chip guard ring structure CGS (in Figures 3A to 3D (in the middle) and the dicing protection ring structure SGS (in Figures 3A to 3D (Middle). Each of the chip protection ring structure CGS and the dicing protection ring structure SGS can extend in the vertical direction (Z direction), such as... Figures 3A to 3D As shown. The chip guard ring structure CGS can be located in the chip guard ring region CGR, and the dicing guard ring structure SGS can be located in the dicing guard ring region SGR. The guard ring structure GRS can include guard ring vias GV. The guard ring vias GV can include chip guard ring vias CGV included in the chip guard ring structure CGS and dicing guard ring vias SGV included in the dicing guard ring structure SGS. The chip guard ring via CGV can include the portion of the chip guard ring structure CGS extending in the vertical direction (Z direction). The dicing guard ring via SGV can include the portion of the dicing guard ring structure SGS extending in the vertical direction (Z direction).

[0016] The planar arrangement of each component in the CGS chip protection ring structure and the planar arrangement of each component in the SGS chip protection ring structure can be compared with... Figures 2A to 2D The chip guard ring vias (CGV) and dicing guard ring vias (SGV) shown have the same planar arrangement. For example, the planar arrangement of the components of the chip guard ring structure (CGS) can be the same as that of the chip guard ring vias (CGV), but some components of the chip guard ring structure (CGS) can have a horizontal width different from that of the chip guard ring vias (CGV). Similarly, the planar arrangement of the components of the dicing guard ring structure (SGS) is the same as that of the dicing guard ring vias (SGV), but some components of the dicing guard ring structure (SGS) can have a horizontal width different from that of the dicing guard ring vias (SGV).

[0017] Refer to together Figure 1 and Figure 2AEach of a plurality of guard ring vias GV, including chip guard ring vias (CGVs) and dicing guard ring vias (SGVs), may be located within a guard ring region GR and has a linear and planar shape extending along the boundary between the chip region CR and the dicing track region SL. The guard ring region GR may include a chip guard ring region CGR and a dicing guard ring region SGR. At least one chip guard ring via (CGV) may be located within the chip guard ring region CGR, and at least one dicing guard ring via (SGV) may be located within the dicing guard ring region SGR.

[0018] Multiple guard ring vias, including chip guard ring vias (CGVs) and scriber guard ring vias (SGVs), can extend in the same (i.e., parallel) direction as the boundary between the chip region (CR) and the scriber region (SL) (i.e., the boundary between the chip guard ring region (CGR) and the scriber guard ring region (SGR), and can be spaced apart from each other in a direction perpendicular to the boundary between the chip guard ring region (CGR) and the scriber guard ring region (SGR). For example, a portion of the chip guard ring via (CGV) and a portion of the scriber guard ring via (SGV) located in the region extending in a first horizontal direction (X direction) between the boundary between the chip guard ring region (CGR) and the scriber guard ring region (SGR) can be spaced apart from each other in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction), and can extend in the first horizontal direction (X direction). For example, a portion of the chip protection ring via CGV and a portion of the dicing protection ring via SGV located in the region where the boundary between the chip protection ring region CGR and the dicing protection ring region SGR extends in the second horizontal direction (Y direction) can be spaced apart from each other in the first horizontal direction (X direction) and can extend in the second horizontal direction (Y direction).

[0019] In some embodiments, a plurality of chip guard ring vias (CGVs) may be arranged in a chip guard ring region (CGR). The CGVs may extend in the same direction as the boundary between the chip guard ring region (CGR) and the scribe guard ring region (SGR), and may be spaced apart from each other in a direction perpendicular to the boundary between the two regions. In some embodiments, a plurality of scribe guard ring vias (SGVs) may be arranged in a scribe guard ring region (SGR). The SGVs may extend in the same direction as the boundary between the chip guard ring region (CGR) and the scribe guard ring region (SGR), and may be spaced apart from each other in a direction perpendicular to the boundary between the two regions.

[0020] In some embodiments, the number of scribe ring vias (SGVs) arranged in the scribe ring region (SGR) can be greater than the number of chip protection ring vias (CGVs) arranged in the chip protection ring region (CGR). Figure 2A An example is shown in which the number of scribe ring vias (SGVs) arranged in the scribe ring region SGR is three, and the number of chip protection ring vias (CGVs) arranged in the chip protection ring region CGR is two; however, the embodiment is not limited to this. For example, the number of chip protection ring vias arranged in the chip protection ring region CGR can be one or more, and the number of scribe ring vias (SGVs) arranged in the scribe ring region SGR can be greater than the number of chip protection ring vias (CGVs) arranged in the chip protection ring region CGR. For example, the number of scribe ring vias (SGVs) arranged in the scribe ring region SGR can be two or more.

[0021] Refer to together Figure 1 and Figure 2B A chip guard ring via (CGV) can have a linear and planar shape extending along the boundary between a chip guard ring region (CGR) and a scribe guard ring region (SGR). When two or more CGVs are arranged in the chip guard ring region (CGR), the two or more CGVs can extend in parallel and be spaced apart from each other in a direction perpendicular to the boundary between the chip guard ring region (CGR) and the scribe guard ring region (SGR). A scribe guard ring via (SGV) can include at least two segments having a linear and planar shape and extending parallel to the boundary between the chip guard ring region (CGR) and the scribe guard ring region (SGR). The scribe guard ring via (SGV) can also include a segment extending in a direction perpendicular to the boundary between the chip guard ring region (CGR) and the scribe guard ring region (SGR) and connecting the at least two segments having a linear and planar shape to each other.

[0022] Refer to together Figure 1 and Figure 2C A chip guard ring via (CGV) may include at least two segments having a linear and planar shape and extending parallel to the boundary between a chip guard ring region (CGR) and a scribe guard ring region (SGR). The CGV may also include segments extending in a direction perpendicular to the boundary between the CGR and SGR, connecting the at least two segments having a linear and planar shape to each other. A scribe guard ring via (SGV) may have a linear and planar shape extending along the boundary between the CGR and SGR. When two or more scribe guard ring vias (SGVs) are arranged in the SGR, the two or more scribe guard ring vias (SGVs) may be spaced apart from each other in a direction perpendicular to the boundary between the CGR and SGR, and may extend parallel to the boundary between the CGR and SGR.

[0023] Reference Figure 1 and Figure 2D A chip guard ring via (CGV) may include at least two segments having linear and planar shapes and extending parallel to the boundary between a chip guard ring region (CGR) and a scribe guard ring region (SGR), and a segment extending in a direction perpendicular to the boundary between the chip guard ring region (CGR) and the scribe guard ring region (SGR) and connecting the at least two segments having linear and planar shapes to each other. A scribe guard ring via (SGV) may include at least two segments having linear and planar shapes and extending parallel to the boundary between the chip guard ring region (CGR) and the scribe guard ring region (SGR), and a segment extending in a direction perpendicular to the boundary between the chip guard ring region (CGR) and the scribe guard ring region (SGR) and connecting the at least two segments having linear and planar shapes to each other.

[0024] Reference Figure 3A The semiconductor memory device 1 may include a chip region CR defined by a scribe line region SL. The chip region CR and the scribe line region SL may each include a chip guard ring region CGR and a scribe guard ring region SGR that are adjacent to each other. The chip guard ring region CGR and the scribe guard ring region SGR may be collectively referred to as the guard ring region GR. The chip region CR may include a main chip region MCR and a chip guard ring region CGR. Figure 3A The lane marking area SL shown can represent Figure 1 This is a portion of the lane marking area SL shown. For example, Figure 3A The lane marking area SL shown can represent Figure 1 The scribe line region SL shown is used to scribe each of the plurality of semiconductor memory devices 1 from Figure 1 The semiconductor wafer WF separation process shown depicts the portion remaining after the dicing region SL is partially removed, and can represent the relationship between the dicing region SL and... Figure 1 The image shows the portion adjacent to the CR region of a chip.

[0025] Semiconductor memory device 1 includes a substrate BSUB, a memory cell structure MCS above the substrate BSUB, and a peripheral circuit structure PCRT above the memory cell structure MCS. The substrate BSUB may be disposed across a chip region CR and a scribe line region SL. The memory cell structure MCS and the peripheral circuit structure PCRT may be disposed in a main chip region MCR above the substrate BSUB. In some embodiments, a portion of a guard ring region GR located at the same vertical level as the memory cell structure MCS may represent a part of the memory cell structure MCS, and a portion of the guard ring region GR located at the same vertical level as the peripheral circuit structure PCRT may represent a part of the peripheral circuit structure PCRT. In some embodiments, semiconductor memory device 1 may have a cell-on-periphery (PoC) structure, wherein the memory cell structure MCS and the peripheral circuit structure PCRT overlap each other in the vertical direction (Z direction).

[0026] The memory cell structure (MCS) may include multiple memory cells. These memory cells may include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, electrically erasable programmable read-only memory (EPROM), phase-change random access memory (PRAM), magnetic random access memory (MRAM), or resistive random access memory (RRAM). In some embodiments, the DRAM may include recessed channel array transistor (RCAT) DRAM, buried channel array transistor (BCAT) DRAM, vertical channel transistor (VCT) DRAM, or 3D DRAM such as vertically stacked DRAM (VSDRAM). In some embodiments, the flash memory may include vertical NAND (VNAND). The peripheral circuit structure (PCRT) may include multiple peripheral circuit transistors for driving the memory cell structure (MCS).

[0027] The semiconductor memory device 1 may further include a plurality of guard ring structures GRS above a substrate BSUB. Each of the plurality of guard ring structures GRS may include a metal-containing material. For example, each of the plurality of guard ring structures GRS may include a metal material, a metal nitride, or a metal silicide. The plurality of guard ring structures GRS may include at least one chip guard ring structure CGS and at least one dicing guard ring structure SGS. The chip guard ring structure CGS may be disposed above the substrate BSUB in a chip guard ring region CGR, and the dicing guard ring structure SGS may be disposed above the substrate BSUB in a dicing guard ring region SGR.

[0028] The peripheral circuit structure (PCRT) may include a peripheral circuit substrate (PSUB). The PSUB may be located in the portion of the PCRT facing the memory cell structure (MCS), i.e., on the underside of the PCRT. That is, the PSUB may be stacked on top of the MCS, and the PCRT may be formed over at least a portion of the PSUB on its upper side. A bonding insulating layer (BDI) may be formed on the lower surface of the PSUB. The PCRT may be bonded to the MCS via the BDI. For example, the BDI and the insulating layer above the MCS may be covalently bonded to each other, thereby bonding the MCS to the PCRT. Alternatively, the MCS may be formed separately, flipped, and then attached to the substrate substrate (BSUB). After at least a portion of the peripheral circuit structure PCRT, including the peripheral circuit substrate PSUB, can be formed separately, the peripheral circuit structure PCRT can be attached to the memory cell structure MCS, such that the peripheral circuit substrate PSUB faces the memory cell structure MCS attached to the base substrate BSUB.

[0029] The memory cell structure (MCS) can be electrically connected to the peripheral circuit structure (PCRT) via cell peripheral circuit connection vias (CPIVs). The CPIVs can pass through the peripheral circuit substrate (PSUB) and extend towards each of the upper and lower sides of the PSUB. For example, the uppermost point of the CPIV can be at a vertical level higher than the upper surface of the PSUB, and the lowermost point can be at a vertical level lower than the lower surface of the PSUB.

[0030] Each of the plurality of guard ring structures GRS may include a guard upper pattern GSUP, a peripheral circuit connection structure PITS, a via upper pattern GVUP, a guard ring via GV located in the guard ring region GR and passing through the peripheral circuit substrate PSUB, a via lower pattern GVLP, a cell connection structure CITS, and a guard lower pattern GSLP. At least one chip guard ring structure CGS and at least one dicing guard ring structure SGS included in each of the plurality of guard ring structures GRS may have substantially the same structure. For example, each of at least one chip guard ring structure CGS and at least one dicing guard ring structure SGS included in each of the plurality of guard ring structures GRS may include a guard ring via GV. In the following description, the guard ring structure GRS may be the same as the description of each of the at least one chip guard ring structure CGS and at least one dicing guard ring structure SGS.

[0031] The guard ring via (GV) can pass through the peripheral circuit substrate (PSUB) and extend towards each of the upper and lower sides of the PSUB. For example, the uppermost end of the guard ring via (GV) can be at a vertical level lower than the uppermost end of the guard ring structure (GRS) but higher than the upper surface of the PSUB, and the lowermost end of the guard ring via (GV) can be at a vertical level higher than the lowermost end of the guard ring structure (GRS) but lower than the lower surface of the PSUB. In some embodiments, the cell peripheral circuit connection via (CPIV) can be at the same vertical level as the guard ring via (GV). For example, the uppermost end of the cell peripheral circuit connection via (CPIV) can be at the same vertical level as the uppermost end of the guard ring via (GV), and the lowermost end of the cell peripheral circuit connection via (CPIV) can be at the same vertical level as the lowermost end of the guard ring via (GV). Each of the cell peripheral circuit connection via (CPIV) and the guard ring via (GV) can be configured as a single body from its uppermost end to its lowermost end.

[0032] The peripheral circuit connection structure PITS can be disposed above the cell peripheral circuit connection via CPIV and the guard ring via GV, and the cell connection structure CITS can be disposed below the cell peripheral circuit connection via CPIV and the guard ring via GV. Each of the peripheral circuit connection structure PITS and the cell connection structure CITS may include at least one line pattern and at least one via connected to at least one line pattern.

[0033] The via upper trace pattern GVUP can be located between each of the peripheral circuit connection structure PITS and the cell peripheral circuit connection via CPIV and guard ring via GV, and the via lower trace pattern GVLP can be located between each of the cell connection structure CITS and the cell peripheral circuit connection via CPIV and guard ring via GV. For example, the via upper trace pattern GVUP can be connected to the upper end of each of the cell peripheral circuit connection via CPIV and guard ring via GV, and the via lower trace pattern GVLP can be connected to the lower end of each of the cell peripheral circuit connection via CPIV and guard ring via GV.

[0034] The upper protective pattern GSUP can be connected to the upper end of the protective ring structure GRS, and the lower protective pattern GSLP can be connected to the lower end of the protective ring structure GRS. The upper surface of the upper protective pattern GSUP can represent the uppermost end of the protective ring structure GRS, and the lower surface of the lower protective pattern GSLP can represent the lowermost end of the protective ring structure GRS.

[0035] The peripheral circuit substrate (PSUB) may have or define a deep trench (DTR) extending through the PSUB. A deep isolation layer (DTI) may fill the deep trench DTR. Each of the cell peripheral circuit connection vias (CPIV) and guard ring vias (GV) may extend through the deep isolation layer (DTI) filling the deep trench DTR and may extend toward each of the upper and lower sides of the PSUB. Each of the cell peripheral circuit connection vias (CPIV) and guard ring vias (GV) may be spaced apart from the PSUB, with a portion of the deep isolation layer (DTI) between them. For example, the deep trench DTR may have a tapered shape, having a wider portion facing the peripheral circuit structure (PCRT) and a narrower portion facing the memory cell structure (MCS) and the substrate (BSUB).

[0036] Each of the cell peripheral circuit connection via (CPIV) and guard ring via (GV) can have a tapered shape, extending with a horizontal width that decreases from its top to its bottom. For example, each of the cell peripheral circuit connection via (CPIV) and guard ring via (GV) can have a tapered shape, extending with a horizontal width that decreases towards the substrate (BSUB). Each of the deep isolation insulating layer (DTI) and deep trench (DTR) can have a tapered shape, extending with a horizontal width that decreases from its top to its bottom. For example, each of the deep isolation insulating layer (DTI) and deep trench (DTR) can have a tapered shape, extending with a horizontal width that decreases towards the substrate (BSUB). For example, each of the cell peripheral circuit connection via (CPIV) and guard ring via (GV) can have a tapered shape, which is wider in the peripheral circuit structure (PCRT) than in the memory cell structure (MCS).

[0037] Reference Figure 3B The semiconductor memory device 1a includes a substrate BSUB, a peripheral circuit structure PCRT above the substrate BSUB, and a memory cell structure MCS above the peripheral circuit structure PCRT. The semiconductor memory device 1a may also include a plurality of guard ring structures GRS above the substrate BSUB. In some embodiments, the semiconductor memory device 1a may have a peripheral upper cell (CoP) structure, wherein the memory cell structure MCS and the peripheral circuit structure PCRT overlap each other in the vertical direction (Z direction).

[0038] The peripheral circuit structure (PCRT) may include a peripheral circuit substrate (PSUB). The PSUB may be located in the portion of the PCRT facing the memory cell structure (MCS). That is, the MCS may be stacked on top of the PSUB, and the PCRT may be formed on the underside of the PSUB, spanning at least a portion of the PSUB. A bonding insulating layer (BDI) may be formed on the upper surface of the PSUB. The MCS may be bonded to the PCRT via the BDI. For example, the PCRT including the PSUB may be formed separately, flipped, and then attached to the substrate substrate (BSUB). The MCS may be formed separately, flipped, and then attached to the PSUB.

[0039] The memory cell structure (MCS) can be electrically connected to the peripheral circuit structure (PCRT) via cell peripheral circuit connection vias (CPIV). The CPIV can pass through the peripheral circuit substrate (PSUB) and extend towards each of the upper and lower sides of the PSUB. Each of the multiple guard ring structures (GRS) can include a guard ring via (GV) located in the guard ring region (GR) and passing through the PSUB. The guard ring via (GV) can pass through the PSUB and extend towards each of the upper and lower sides of the PSUB.

[0040] The cell connection structure CITS can be set above the cell peripheral circuit connection via CPIV and the guard ring via GV, and the peripheral circuit connection structure PITS can be set below the cell peripheral circuit connection via CPIV and the guard ring via GV.

[0041] The via upper line pattern GVUP can be located between each of the cell connection structure CITS and the cell peripheral circuit connection via CPIV and the guard ring via GV, and the via lower line pattern GVLP can be located between each of the peripheral circuit connection structure PITS and the cell peripheral circuit connection via CPIV and the guard ring via GV.

[0042] Each of the cell peripheral circuit connection vias (CPIV) and guard ring vias (GV) can pass through the deep isolation insulating layer (DTI) filling the deep trench DTR and can extend toward each of the upper and lower sides of the peripheral circuit substrate (PSUB). Each of the cell peripheral circuit connection vias (CPIV) and guard ring vias (GV) can have a tapered shape, extending with a decreasing horizontal width from its upper side to its lower side. Each of the deep isolation insulating layer (DTI) and the deep trench DTR can have a tapered shape, extending with an increasing horizontal width from its upper side to its lower side. For example, each of the deep isolation insulating layer (DTI) and the deep trench DTR can have a tapered shape, extending with an increasing horizontal width toward the substrate (BSUB). For example, the deep trench DTR can have a wider portion facing the peripheral circuit structure (PCRT) and the substrate (BSUB), and a narrower portion facing the memory cell structure (MCS).

[0043] Reference Figure 3C The semiconductor memory device 1b includes a substrate BSUB, a memory cell structure MCS above the substrate BSUB, and a peripheral circuit structure PCRT above the memory cell structure MCS. The semiconductor memory device 1b may also include a plurality of guard ring structures GRS above the substrate BSUB. In some embodiments, the semiconductor memory device 1b may have a PoC structure, wherein the memory cell structure MCS and the peripheral circuit structure PCRT overlap each other in the vertical direction (Z direction).

[0044] The peripheral circuit structure (PCRT) may include a peripheral circuit substrate (PSUB). The PSUB may be located in the portion of the PCRT opposite the memory cell structure (MCS). That is, the PCRT may be stacked on top of the MCS such that the PSUB is located on the opposite side of the MCS, and the PCRT may be formed across at least a portion of the PSUB on its underside. A bonding insulating layer (BDIa) and a plurality of bonding pads (BPDs) may be arranged between the MCS and the PCRT. The BDIa may be formed by bonding a cell bonding insulating layer (BDIC) located on the upper side of the MCS to a peripheral circuit bonding insulating layer (BDIP) located on the lower side of the PCRT. Each of the plurality of bonding pads (BPDs) may be formed by bonding a cell bonding pad (BPDC) surrounded by a cell bonding insulating layer (BDIC) to a peripheral circuit bonding pad (BPDP) surrounded by a peripheral circuit bonding insulating layer (BDIP).

[0045] The peripheral circuit structure PCRT can be bonded to the memory cell structure MCS via a bonding insulating layer BDIa and multiple bonding pads BPD. For example, the cell bonding insulating layer BDIC and the peripheral circuit bonding insulating layer BDIP can be covalently bonded together to form the bonding insulating layer BDIa. Furthermore, the cell bonding pads BPDC and the peripheral circuit bonding pads BPDP can be arranged facing each other, thermally expanded and contacting each other, and diffusely bonded to each other via the diffusion of metal atoms therein to form a single body, thereby forming each of the multiple bonding pads BPD. The memory cell structure MCS can be bonded to the peripheral circuit structure PCRT using a hybrid bonding method. For example, the memory cell structure MCS can be formed, flipped, and then attached to a substrate BSUB separately. After at least a portion of the peripheral circuit structure PCRT, including the peripheral circuit substrate PSUB, is formed and flipped separately, the peripheral circuit structure PCRT can be attached to the memory cell structure MCS using a hybrid bonding method, such that the peripheral circuit substrate PSUB faces the upper side opposite to the memory cell structure MCS attached to the substrate BSUB.

[0046] The memory cell structure (MCS) can be electrically connected to the peripheral circuit structure (PCRT) via cell peripheral circuit connection vias (CPIVa). The cell peripheral circuit connection vias (CPIVa) can include cell connection vias (CPIVC) and peripheral circuit connection vias (CPIVP). Each of the multiple guard ring structures (GRS) can include a guard ring via (GVa) located in a guard ring region (GR). The guard ring via (GVa) can include a cell guard ring via (GVC) and a peripheral circuit guard ring via (GVP). Bonding pads (BPDs) can be respectively positioned between the cell connection vias (CPIVC and CPIVP) of the cell peripheral circuit connection via (CPIVa), and between the cell guard ring vias (GVC and GVP) included in the guard ring vias (GVa). For example, the cell connection vias CPIVC and CPIVP included in the cell peripheral circuit connection via CPIVCa can be electrically connected to each other via bonding pads BPD, and the cell protection ring vias GVC and GVP included in the guard ring vias GVa can be electrically connected to each other via bonding pads BPD. Each of the cell connection vias CPIVC and GVC can extend from the bonding pads BPD into the memory cell structure MCS, and each of the peripheral circuit connection vias CPIVP and GVP can extend from the bonding pads BPD into the peripheral circuit structure PCRT.

[0047] The peripheral circuit connection structure PITS can be positioned above the peripheral circuit connection via CPCIVP and the peripheral circuit protection ring via GVP, and the unit connection structure CITS can be positioned below the unit connection via CPIVC and the unit protection ring via GVC. The via upper pattern GVUP can be located between the peripheral circuit connection structure PITS and each of the peripheral circuit connection via CPCIVP and the peripheral circuit protection ring via GVP, and the via lower pattern GVLP can be located between the unit connection structure CITS and each of the unit connection via CPIVC and the unit protection ring via GVC. The protection upper pattern GSUP can be connected to the upper end of the protection ring structure GRS, and the protection lower pattern GSLP can be connected to the lower end of the protection ring structure GRS.

[0048] The peripheral circuit substrate (PSUB) may have a deep trench (DTR) extending through the PSUB, and a deep isolation insulating layer (DTI) may fill the deep trench DTR. In some embodiments, an isolation layer extension structure (DITS) may be disposed on a guard top pattern (GSUP) and may be attached to the upper surface of the guard top pattern (GSUP) and extend into the deep isolation insulating layer (DTI) filling the deep trench DTR. A guard ring structure (GRS) may include the isolation layer extension structure (DITS). The guard ring structure (GRS) may overlap with the deep isolation insulating layer (DTI) filling the deep trench DTR in the vertical direction (Z direction). The guard ring structure (GRS) may not overlap with the peripheral circuit substrate (PSUB) in the vertical direction (Z direction).

[0049] Each of the cell connection via (CPIVC) and cell guard ring via (GVC) can have a tapered shape, extending with a horizontal width that decreases from its top to its bottom. For example, each of the cell connection via (CPIVC) and cell guard ring via (GVC) can have a tapered shape, extending with a horizontal width that decreases towards the substrate (BSUB). Each of the peripheral circuit connection via (CPIVP) and peripheral circuit guard ring via (GVP) can have a tapered shape, extending with a horizontal width that increases from its top to its bottom. For example, each of the peripheral circuit connection via (CPIVP) and peripheral circuit guard ring via (GVP) can have a tapered shape, extending with a horizontal width that increases towards the substrate (BSUB). Each of the deep isolation insulating layer (DTI) and deep trench (DTR) can have a tapered shape, extending with a horizontal width that increases from its top to its bottom. For example, each of the deep isolation insulating layer (DTI) and deep trench (DTR) can have a tapered shape, extending with a horizontal width that increases towards the substrate (BSUB).

[0050] Reference Figure 3DThe semiconductor memory device 1c includes a peripheral circuit structure PCRT having a peripheral circuit substrate PSUB and a memory cell structure MCS above the peripheral circuit structure PCRT. The semiconductor memory device 1c may also include a plurality of guard ring structures GRS above the peripheral circuit substrate PSUB. The peripheral circuit substrate PSUB may be located in the portion of the peripheral circuit structure PCRT opposite to the memory cell structure MCS. For example, the peripheral circuit substrate PSUB may be located below the peripheral circuit structure PCRT. In some embodiments, the semiconductor memory device 1c may have a CoP structure, wherein the memory cell structure MCS and the peripheral circuit structure PCRT overlap each other in the vertical direction (Z direction).

[0051] A bonding insulating layer BDIa and multiple bonding pads BPD can be arranged between the memory cell structure MCS and the peripheral circuit structure PCRT. The bonding insulating layer BDIa can be formed by bonding a cell bonding insulating layer BDIC located on the underside of the memory cell structure MCS to a peripheral circuit bonding insulating layer BDIP located on the upper side of the peripheral circuit structure PCRT. Each of the multiple bonding pads BPD can be formed by bonding a cell bonding pad BPDC surrounded by a cell bonding insulating layer BDIC to a peripheral circuit bonding pad BPDP surrounded by a peripheral circuit bonding insulating layer BDIP. The memory cell structure MCS can be bonded to the peripheral circuit structure PCRT via the bonding insulating layer BDIa and the multiple bonding pads BPD. The memory cell structure MCS can be bonded to the peripheral circuit structure PCRT using a hybrid bonding method. For example, after forming the peripheral circuit structure PCRT including a peripheral circuit substrate PSUB, the memory cell structure MCS can be flipped and attached to the peripheral circuit structure PCRT.

[0052] The unit connection structure CITS can be positioned above the unit connection via CPIVC and the unit protection ring via GVC, and the peripheral circuit connection structure PITS can be positioned below the peripheral circuit connection via CPIVP and the peripheral circuit protection ring via GVP. The via upper pattern GVUP can be located between the unit connection structure CITS and each of the unit connection via CPIVC and the unit protection ring via GVC, and the via lower pattern GVLP can be located between the peripheral circuit connection structure PITS and each of the peripheral circuit connection via CPIVP and the peripheral circuit protection ring via GVP. The protection upper pattern GSUP can be connected to the upper end of the protection ring structure GRS, and the protection lower pattern GSLP can be connected to the lower end of the protection ring structure GRS.

[0053] Each of the cell connection via (CPIVC) and the cell guard ring via (GVC) can have a tapered shape, extending with a horizontal width that increases from its top to its bottom. For example, each of the cell connection via (CPIVC) and the cell guard ring via (GVC) can have a tapered shape, extending with a horizontal width that increases towards the peripheral circuit substrate (PSUB). Each of the peripheral circuit connection via (CPIVP) and the peripheral circuit guard ring via (GVP) can have a tapered shape, extending with a horizontal width that decreases from its top to its bottom. For example, each of the peripheral circuit connection via (CPIVP) and the peripheral circuit guard ring via (GVP) can have a tapered shape, extending with a horizontal width that decreases towards the peripheral circuit substrate (PSUB).

[0054] Reference Figures 3A to 3D Semiconductor memory devices 1, 1a, 1b, and 1c include: a plurality of guard ring structures GRS, each guard ring structure GRS including guard ring vias GV and GVa extending from the region between the memory cell structure MCS and the peripheral circuit structure PCRT to each of the memory cell structure MCS and the peripheral circuit structure PCRT. The plurality of guard ring structures GRS may further include a guard upper pattern GSUP, a peripheral circuit connection structure PITS, a via upper line pattern GVUP, a via lower line pattern GVLP, a cell connection structure CITS, a guard lower pattern GSLP, and an isolation layer extension structure DITS. Therefore, in the case of... Figure 1 During the process of separating each of the multiple semiconductor memory devices 1, 1a, 1b and 1c on the semiconductor wafer WF shown, multiple guard ring structures GRS can prevent cracks from propagating inside the multiple semiconductor memory devices 1, 1a, 1b and 1c.

[0055] Figures 3A to 3C The substrate BSUB shown is Figure 3D The peripheral circuit substrate PSUB shown can be referred to as the support substrate. Figure 3A and Figure 3B The peripheral circuit substrate PSUB shown can be referred to as the intermediate substrate, and Figure 3C The peripheral circuit substrate (PSUB) shown may be referred to as a cover substrate. Each of the base substrate (BSUB) and the peripheral circuit substrate (PSUB) may include, for example, a semiconductor material, such as a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material, as well as a group II-VI oxide semiconductor material.

[0056] exist Figure 3A and Figure 3BIn the semiconductor memory devices 1 and 1a shown respectively, the integrally and continuously formed guard ring via GV extends from the memory cell structure MCS to the peripheral circuit structure PCRT via a deep isolation insulating layer DTI that fills the deep trench DTR of the intermediate substrate. Therefore, from Figure 1 During the process of separating each of the plurality of semiconductor memory devices 1 and 1a on the semiconductor wafer WF shown, crack propagation to the intermediate substrate included in each of the plurality of semiconductor memory devices 1 and 1a can be prevented. Figure 3C and Figure 3D The semiconductor memory devices 1b and 1c shown respectively include guard ring vias GVa extending from the memory cell structure MCS to the peripheral circuit structure PCRT, wherein the cell guard ring via GVC and the peripheral circuit guard ring via GVP are bonded to each other via bonding pads BPD, but do not include an intermediate substrate. Furthermore, respectively in Figures 3A to 3C The semiconductor memory devices 1, 1a, and 1b shown can have a deep isolation insulating layer (DTI) that fills the deep trench DTR, and thus can prevent the leakage of materials from the memory. Figure 1 The semiconductor wafer WF shown in the figure separates each of the multiple semiconductor memory devices 1, 1a and 1b during the process, and cracks propagate within the multiple semiconductor memory devices 1, 1a and 1b, thereby achieving structural reliability.

[0057] Although Figures 3A to 3D Semiconductor memory devices 1, 1a, 1b and 1c are shown to include multiple guard ring structures GRS, but it will be apparent to those skilled in the art that, in addition to guard ring structures GRS, semiconductor memory devices 1, 1a, 1b and 1c may also include other structures, such as chipping dam structures located in the scribe line region SL.

[0058] Figure 4A and Figure 4B This is a cross-sectional view showing a semiconductor memory device 1 according to an embodiment.

[0059] Refer to together Figure 4A and Figure 4B The semiconductor memory device 1 may include a chip region CR defined by a scribe line region SL. The chip region CR and the scribe line region SL may each include a chip guard ring region CGR and a scribe guard ring region SGR that are adjacent to each other. The chip region CR may include a main chip region MCR and a chip guard ring region CGR.

[0060] Semiconductor memory device 1 includes a substrate BSUB, a memory cell structure MCS above the substrate BSUB, and a peripheral circuit structure PCRT above the memory cell structure MCS. The memory cell structure MCS may include multiple memory cells. Figure 4A An example of a memory cell structure (MCS) including VCT DRAM is shown. The peripheral circuit structure (PCRT) may include a peripheral circuit substrate (PSUB) and multiple peripheral circuit transistors (PTRs). The multiple PTRs may be disposed on the upper surface of the PSUB. The multiple PTRs may be configured to deliver signals and / or power to multiple memory cells in the memory cell structure (MCS). For example, the multiple PTRs may constitute various circuits such as command decoders, control logic, address buffers, row decoders, column decoders, sense amplifiers, and data input / output circuits. Figure 4B The peripheral circuit transistor (PTR) shown includes a planar transistor, but the embodiments are not limited thereto. For example, the PTR may include a fin field-effect transistor (FinFET) or a vertical gate transistor. A bonding insulating layer (BDI) may be formed on the lower surface of the peripheral circuit substrate (PSUB). The peripheral circuit structure (PCRT) may be bonded to the memory cell structure (MCS) via the bonding insulating layer (BDI). The semiconductor memory device 1 may also include a plurality of guard ring structures (GRS) above the substrate (BSUB). The plurality of guard ring structures (GRS) may include at least one chip guard ring structure (CGS) and at least one dicing guard ring structure (SGS).

[0061] The memory cell structure (MCS) can be electrically connected to the peripheral circuit structure (PCRT) via a cell peripheral circuit connection via (CPIV). Each of the plurality of guard ring structures (GRS) may include a guard ring via (GV) located in the guard ring region (GR) and passing through the peripheral circuit substrate (PSUB). In some embodiments, the cell peripheral circuit connection via (CPIV) may be at the same vertical level as the guard ring via (GV).

[0062] The peripheral circuit bitline pattern PBL can be connected to the upper side of each of the cell peripheral circuit connection vias CPIV and GV. The peripheral circuit bitline pattern PBL can correspond to... Figure 3AThe via pattern GVUP is shown in the diagram. The peripheral circuit interlayer structure (PIS), peripheral circuit wiring structure (PMS), and pad structure (PDS) can be sequentially connected together above the peripheral circuit bit line pattern (PBL). The peripheral circuit interlayer structure (PIS) can include multiple peripheral circuit interlayer connection lines (PIL), multiple peripheral circuit interlayer connection vias (PIV), and a peripheral circuit interlayer insulating layer (PID). The peripheral circuit interlayer insulating layer (PID) can cover the peripheral circuit substrate (PSUB). The peripheral circuit interlayer insulating layer (PID) can surround the upper portion of the multiple peripheral circuit interlayer connection lines (PIL), the multiple peripheral circuit interlayer connection vias (PIV), the cell peripheral circuit connection vias (CPIV), the upper portion of the guard ring via (GV), and the peripheral circuit bit line pattern (PBL). The multiple peripheral circuit interlayer connection vias (PIV) can be connected to any one of the peripheral circuit transistors (PTR), the peripheral circuit bit line pattern (PBL), and the peripheral circuit interlayer connection lines (PIL).

[0063] The peripheral wiring structure (PMS) may include a plurality of peripheral wiring connectors (PMLs), a plurality of peripheral wiring connection vias (PMVs) connected to the plurality of peripheral wiring connectors (PMLs), and a peripheral wiring insulating layer (PMD) surrounding the plurality of peripheral wiring connectors (PMLs) and the plurality of peripheral wiring connection vias (PMVs). In some embodiments, the plurality of peripheral wiring connectors (PMLs) may be buried in the upper part of the peripheral wiring insulating layer (PMD), and the peripheral wiring structure (PMS) may further include a peripheral wiring protective layer (PMP) covering the plurality of peripheral wiring connectors (PMLs) and the peripheral wiring insulating layer (PMD). The lowermost peripheral wiring connection via (PMV) among the plurality of peripheral wiring connection vias (PMVs) may be connected to the uppermost peripheral circuit interlayer connection (PIL) among the plurality of peripheral circuit interlayer connections (PILs).

[0064] The pad structure PDS may include multiple pad pattern PDPs and multiple pad vias PDVs connected to the multiple pad pattern PDPs. The pad vias PDVs may be connected to the uppermost peripheral circuit routing connection PML among multiple peripheral circuit routing connections PMLs. A cover insulating layer CID may cover the multiple pad pattern PDPs and the multiple pad vias PDVs. In some embodiments, the cover insulating layer CID in the guard ring region GR may cover the upper surface of the pad pattern PDPs, and a guard layer PPSL and a photosensitive polyimide (PSPI) layer PSPI may be sequentially formed on the cover insulating layer CID in the guard ring region GR. In some embodiments, the PSPI layer PSPI may not cover a portion of the scribe line region SL. For example, the PSPI layer PSPI may not cover the portion of the scribe line region SL other than the scribe guard ring region SGR. For example, a portion of the scribe line region SL may be exposed by the PSPI layer PSPI. In some embodiments, the cover insulating layer CID, the guard layer PPSL, and the PSPI layer PSPI may not be disposed above at least a portion of the upper surface of the pad pattern PDPs in the main chip region MCR. In some embodiments, the overlay insulating layer CID, the protective layer PPSL, and the PSPI layer PSPI can be formed above the pad pattern PDP in the main chip region MCR, but the external pad pattern can be formed above the pad pattern PDP, such that the upper surface of the external pad pattern is at least partially not covered by the overlay insulating layer CID, the protective layer PPSL, and the PSPI layer PSPI.

[0065] Multiple peripheral circuit inter-layer interconnects (PIL), multiple peripheral circuit inter-layer interconnect vias (PIV), multiple peripheral circuit routing interconnects (PML), multiple peripheral circuit routing interconnect vias (PMV), and multiple pad vias (PDV) can correspond to Figure 3A The peripheral circuit connection structure PITS shown, and the pad pattern PDP located in the guard ring region GR, can correspond to Figure 3A The protective pattern shown is GSUP.

[0066] The peripheral circuit substrate (PSUB) may have a deep trench (DTR) extending through the PSUB, and a deep isolation insulating layer (DTI) may fill the deep trench DTR. Each of a plurality of cell peripheral circuit connection vias (CPIV) and a plurality of guard ring vias (GV) may extend through the deep isolation insulating layer (DTI) filling the deep trench DTR, and may extend toward each of the upper and lower sides of the PSUB. Each of the plurality of cell peripheral circuit connection vias (CPIV) and the plurality of guard ring vias (GV) may be spaced apart from the PSUB, with a portion of the deep isolation insulating layer (DTI) between them. Each of the plurality of cell peripheral circuit connection vias (CPIV) and the plurality of guard ring vias (GV) may extend through a bonding insulating layer (BDI). In some embodiments, a plurality of guard ring structures (GRS) may all extend through a single deep isolation insulating layer (DTI) that fills a deep trench DTR extending through the PSUB.

[0067] Each of the cell peripheral circuit connection via (CPIV) and the guard ring via (GV) can have a tapered shape, extending with a horizontal width that decreases from its top to its bottom. For example, each of the cell peripheral circuit connection via (CPIV) and the guard ring via (GV) can have a tapered shape, extending with a horizontal width that decreases towards the substrate (BSUB). Each of the deep isolation insulating layer (DTI) and the deep trench (DTR) can have a tapered shape, extending with a horizontal width that decreases from its top to its bottom. For example, each of the deep isolation insulating layer (DTI) and the deep trench (DTR) can have a tapered shape, extending with a horizontal width that decreases towards the substrate (BSUB). For example, the deep trench (DTR) can have a tapered shape having a wider portion facing away from the substrate (BSUB) and a narrower portion facing the substrate (BSUB).

[0068] The cell landing pattern CLP can be connected to the underside of each of the cell peripheral circuit connection vias CPIV and GV. The cell landing pattern CLP can correspond to... Figure 3AThe via pattern GVLP is shown. The inter-cell structure CIS, inter-cell connection structure BIS, and capacitor connection structure DIS can be sequentially connected together below the cell landing pattern CLP. The inter-cell structure CIS may include multiple inter-cell connection lines CIL, multiple inter-cell connection vias CIV, and an inter-cell insulation layer CIDa. The inter-cell insulation layer CIDa may cover the lower surface of the bonding insulation layer BDI. The inter-cell insulation layer CIDa may surround the lower portion of the multiple inter-cell connection lines CIL, the multiple inter-cell connection vias CIV, the lower portion of the cell peripheral circuit connection vias CPIV, the lower portion of the guard ring via GV, and the cell landing pattern CLP. Each of the multiple inter-cell connection vias CIV can be connected to at least one of the cell landing pattern CLP, the multiple inter-cell connection lines CIL, and the cell bit line BL. For example, the inter-cell connection vias CIV can connect the cell landing pattern CLP to the inter-cell connection line CIL, or connect the inter-cell connection line CIL to the cell bit line BL. The inter-cell interconnect structure (BIS) may include an intermediate interconnect line (BIL) and an inter-cell insulating layer (BID) surrounding the intermediate interconnect line (BIL). A cell wiring contact (CMC) may pass through the inter-cell insulating layer (CIDa) and the inter-cell insulating layer (BID) and connect any one of the multiple inter-cell interconnect lines (CIL) to the intermediate interconnect line (BIL). The cell wiring contact (CMC) may have a tapered shape extending with a horizontal width decreasing from its upper side to its lower side. For example, the cell wiring contact (CMC) may have a tapered shape extending with a horizontal width decreasing towards the substrate (BSUB). The capacitor connection structure (DIS) may include multiple capacitor connection lines (DIL), multiple capacitor connection vias (DIV), and a capacitor cover insulating layer (DID). The capacitor cover insulating layer (DID) may surround the multiple capacitor connection lines (DIL), the multiple capacitor connection vias (DIV), and the capacitor structure (CAP). The multiple capacitor connection vias (DIV) connect the capacitor connection lines (DIL) to the capacitor top electrode (TCE) and connect the capacitor connection lines (DIL) to the intermediate interconnect line (BIL). A cell protection layer (CPSL) may be located between the capacitor cover insulating layer (DID) and the substrate (BSUB). Multiple inter-layer interconnect (CIL), multiple inter-layer interconnect (CIV), multiple peripheral circuit wiring (PML), intermediate interconnect (BIL), and multiple capacitor connection vias (DIV) can correspond to Figure 3A The shown unit connection structure CITS, and the capacitor connection line DIL located in the guard ring region GR can correspond to Figure 3A The protected pattern GSLP is shown.

[0069] A memory cell structure (MCS) may include multiple cell bit lines (BL), multiple channel patterns (CHL), multiple word lines (GL), multiple back gate electrodes (BG), multiple contact plugs (CCT), and multiple capacitor structures (CAP). The multiple cell bit lines (BL) may extend longitudinally in a first horizontal direction (X direction) and may be spaced apart from each other in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction). In some embodiments, an insulating capping line (BLC) may be disposed on each of the multiple cell bit lines (BL). The multiple channel patterns (CHL), the multiple contact plugs (CCT), and the multiple capacitor structures (CAP) may be disposed below the multiple contact plugs (CCT).

[0070] Multiple channel patterns CHL can be spaced apart from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction) below multiple unit bit lines BL. Each of the multiple contact plugs CCT can be positioned below the corresponding channel pattern CHL among the multiple channel patterns CHL. Each of the multiple channel patterns CHL can extend in the vertical direction (Z direction) between any one of the multiple unit bit lines BL and any one of the multiple contact plugs CCT.

[0071] In some embodiments, each of the plurality of channel pattern CHLs may include a semiconductor material. For example, each of the plurality of channel pattern CHLs may include monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, each of the plurality of channel pattern CHLs may include at least one selected from the group consisting of Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, each of the plurality of channel pattern CHLs may include an oxide semiconductor material. Each of the plurality of channel pattern CHLs may include at least one of a binary or ternary oxide semiconductor material comprising a first metal element, a ternary oxide semiconductor material comprising a first metal element and a second metal element that are different from each other, and a quaternary oxide semiconductor material comprising a first metal element, a second metal element, and a third metal element that are different from each other. The binary or ternary oxide semiconductor material may include, but is not limited to, for example, zinc oxide (ZnO or Zn x O), gallium oxide (GaO or Ga) x O), tin oxide (SnO or Sn) x O), zinc oxide (ZnON or Zn) x O y N), indium zinc oxide (IZO or In) x Zn y O), zinc gallium oxide (GZO or Ga) x Zn y O), zinc tin oxide (TZO or Sn)x Zn y O) and gallium tin oxide (TGO or Sn) x Ga y Any of the following (O). The quaternary oxide semiconductor material may include, but is not limited to, for example, indium gallium zinc oxide (IGZO or In). x Ga Y Zn z O), indium gallium silicon oxide (IGSO or In) x Ga y Si z O), Indium tin zinc oxide (ITZO or In) x Sn Y Zn z O), Indium gallium tin oxide (IGTO or In) x Ga y Sn z O), Zirconia zinc tin (ZZTO or Zr) X Zn y Sn z O), hafnium indium zinc oxide (HIZO or Hf) x In Y Zn z O), gallium zinc tin oxide (GZTO or Ga) x Zn y Sn z O), aluminum zinc tin oxide (AZTO or Al) x Zn y Sn z O), ytterbium gallium zinc oxide (YGZO or Yb x Ga Y Zn z O) and indium aluminum zinc oxide (IAZO).

[0072] In some embodiments, each of the plurality of channel pattern CHLs may include a crystalline oxide semiconductor material or an amorphous oxide semiconductor material. When each of the plurality of channel pattern CHLs includes a crystalline oxide semiconductor material, each of the plurality of channel pattern CHLs may include at least one of single-crystal, polycrystalline, spinel, and c-axis aligned crystallization (CAAC) characteristics. In some embodiments, each of the plurality of channel pattern CHLs may be formed by stacking at least two layers, said at least two layers including a first layer comprising a crystalline oxide semiconductor material and a second layer comprising an amorphous oxide semiconductor material. For example, each of the plurality of channel pattern CHLs may be formed by sequentially stacking a first layer comprising a crystalline oxide semiconductor material, a second layer comprising an amorphous oxide semiconductor material, and a third layer comprising a crystalline oxide semiconductor material.

[0073] According to an embodiment, multiple contact plugs (CCTs) can be spaced apart from multiple element lines (BLs) in the vertical direction (Z direction), and multiple channel patterns (CHLs) are located between the multiple contact plugs (CCTs) and the multiple element lines (BLs). The multiple contact plugs (CCTs) can be arranged in a matrix to be spaced apart from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction). The multiple contact plugs (CCTs) and the multiple channel patterns (CHLs) can be connected to each other in a one-to-one correspondence.

[0074] In some embodiments, the plurality of contact plugs (CCTs) may each comprise a metal, a conductive metal nitride, a metal silicide, doped polysilicon, or a combination thereof. For example, the plurality of contact plugs (CCTs) may each comprise Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, doped polysilicon, or a combination thereof.

[0075] In some embodiments, each of the plurality of contact plugs CCT may include buried contacts BC and landing pads LP sequentially stacked beneath a plurality of channel patterns CHL. For example, the buried contacts BC may include doped polysilicon, and the landing pads LP may include metal, but embodiments are not limited thereto. In some embodiments, the landing pads LP and intermediate interconnects BIL may include the same material. In some embodiments, the landing pads LP and intermediate interconnects BIL may be formed together and at the same vertical level. The cell intermediate insulating layer BID may surround the plurality of contact plugs CCT.

[0076] Multiple back gate electrodes (BGs) and multiple word lines (GLs) can be disposed below multiple cell bit lines (BLs). Each of the multiple back gate electrodes (BGs) and multiple word lines (GLs) can extend longitudinally in a second horizontal direction (Y direction) between the multiple cell bit lines (BLs) and multiple contact plugs (CCTs). The multiple back gate electrodes (BGs) and multiple word lines (GLs) can be spaced apart from each other in a first horizontal direction (X direction). According to an embodiment, each of the multiple channel patterns (CHLs) can be disposed on a corresponding cell bit line (BL) among the multiple cell bit lines (BLs) between a back gate electrode (BG) and a word line (GL) adjacent to each other along the first horizontal direction (X direction). According to an embodiment, pairs of channel patterns (CHLs) can be arranged on opposite sides of each of the multiple back gate electrodes (BGs) along the first horizontal direction (X direction), and pairs of word lines (GLs) can be spaced apart from each of the multiple back gate electrodes (BGs), wherein the pairs of channel patterns (CHLs) are located therebetween.

[0077] In some embodiments, each of the plurality of back gate electrodes BG may include a metal, a conductive metal nitride, doped polysilicon, or a combination thereof. For example, each of the plurality of back gate electrodes BG may include, but is not limited to, Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, doped polysilicon, or a combination thereof. Each of the plurality of word lines GL may include a metal, a conductive metal nitride, or a combination thereof. For example, each of the plurality of word lines GL may include, but is not limited to, Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, or a combination thereof.

[0078] Semiconductor memory device 1 may include a plurality of back gate dielectric layers BGox and a plurality of gate dielectric layers Gox. The back gate dielectric layers BGox cover two sidewalls of each of the plurality of back gate electrodes BG in a first horizontal direction (X direction). The gate dielectric layers Gox are respectively located between a plurality of word lines GL and a plurality of adjacent channel patterns CHL. Each of the plurality of back gate dielectric layers BGox may be located between a back gate electrode BG and an adjacent channel pattern CHL. For example, each of the plurality of back gate dielectric layers BGox may be in contact with both the back gate electrode BG and the channel pattern CHL. Pairs of gate dielectric layers Gox may be arranged between pairs of adjacent channel patterns CHL along the first horizontal direction (X direction). Pairs of word lines GL may be arranged between pairs of gate dielectric layers Gox.

[0079] According to an embodiment, each of the gate dielectric layer Gox and the back gate dielectric layer BGox may comprise a silicon oxide layer, a high-k dielectric layer, or a combination thereof. As used herein, the term "high-k dielectric layer" refers to a dielectric layer having a higher dielectric constant than silicon oxide. In an embodiment, each of the gate dielectric layer Gox and the back gate dielectric layer BGox may include at least one material selected from the group consisting of silicon oxide, hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). Multiple back gate electrodes BG, multiple word lines GL, multiple channel patterns CHL, multiple back gate dielectric layers BGox, and multiple gate dielectric layers Gox arranged between multiple unit bit lines BL and multiple contact plugs CCT can constitute multiple VCTs.

[0080] Multiple capacitor structures (CAPs) may be disposed beneath multiple contact plugs (CCTs) and a cell intermediate insulating layer (BID). The multiple capacitor structures (CAPs) may include multiple lower capacitor electrodes (BCEs) connected to the multiple contact plugs (CCTs), a capacitor dielectric layer (DIC) conformally covering the surface of each of the multiple lower capacitor electrodes (BCEs), and a capacitor upper electrode (TCE) covering the multiple lower capacitor electrodes (BCEs), with the capacitor dielectric layer (DIC) located between the lower capacitor electrodes (BCEs) and the capacitor upper electrode (TCE). Each of the multiple lower capacitor electrodes (BCEs) may be connected to a channel pattern (CHL) selected from a plurality of channel patterns (CHLs) via a contact plug (CCT) selected from the plurality of contact plugs (CCTs). In some embodiments, at least one lower electrode support pattern (BES) may surround a portion of the multiple lower capacitor electrodes (BCEs), and the capacitor dielectric layer (DIC) may conformally cover the multiple lower capacitor electrodes (BCEs) and at least one lower electrode support pattern (BES). In some embodiments, at least two lower electrode support patterns (BESs) at different vertical levels may surround another portion of the multiple lower capacitor electrodes (BCEs) at different vertical levels.

[0081] Each capacitor bottom electrode BCE may have, but is not limited to, a solid columnar shape with a circular horizontal cross-section, i.e., a columnar shape. In some embodiments, each of the plurality of capacitor bottom electrodes BCEs may have a cylindrical shape with a closed bottom. In some embodiments, the plurality of capacitor bottom electrodes BCEs may be arranged in rows in each of a first horizontal direction (X direction) and a second horizontal direction (Y direction) to form a matrix pattern. In some embodiments, the plurality of capacitor bottom electrodes BCEs may be arranged in a zigzag pattern along the first horizontal direction (X direction) or the second horizontal direction (Y direction) to form a honeycomb shape. The plurality of capacitor bottom electrodes BCEs may include, for example, doped silicon, metals such as tungsten and copper, or conductive metal compounds such as titanium nitride.

[0082] The capacitor dielectric layer DIC can conformally cover the surfaces of multiple capacitor lower electrodes BCE. In some embodiments, the capacitor dielectric layer DIC may include a high-k dielectric layer. In some embodiments, the capacitor dielectric layer DIC may include a metal oxide, which includes at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), niobium (Nb), cerium (Ce), lanthanum (La), tantalum (Ta), and titanium (Ti). In some embodiments, each of the multiple capacitor lower electrodes BCE and capacitor upper electrodes TCE may include a metal, a conductive metal oxide, a conductive metal nitride, a conductive metal oxynitride, or a combination thereof. In some embodiments, each of the multiple capacitor lower electrodes BCE and capacitor upper electrodes TCE may include Nb, Nb oxide, Nb nitride, Nb oxynitride, Ti, Ti oxide, Ti nitride, Ti oxynitride, Co, Co oxide, Co nitride, Co oxynitride, Sn, Sn oxide, Sn nitride, Sn oxynitride, or a combination thereof. In some embodiments, each of the plurality of capacitor lower electrodes BCE and capacitor upper electrodes TCE may include TaN, TiAlN, TaAlN, V, VN, Mo, MoN, W, WN, Ru, RuO2, SrRuO3, Ir, IrO2, Pt, PtO, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCO (La,Sr)CoO3), or combinations thereof. However, the constituent materials of each of the plurality of capacitor lower electrodes BCE and capacitor upper electrodes TCE are not limited to the examples described above. In some embodiments, in addition to metallic materials, the capacitor upper electrode TCE may also include at least one of a doped semiconductor material layer and an interface layer, and may have a stacked structure thereof. The doped semiconductor material layer may include at least one of, for example, doped polycrystalline silicon and doped polycrystalline silicon germanium (poly-SiGe). The interface layer may include a metallic material. The interface layer may include at least one of, for example, a metal oxide, a metal nitride, a metal carbide, and a metal silicide.

[0083] Figure 3A The memory cell structure MCS shown can have the same characteristics as... Figure 4B The shape corresponding to the memory cell structure MCS shown is, and Figure 3A The peripheral circuit structure shown, PCRT, can have the same characteristics as... Figure 4B The shape corresponding to the peripheral circuit structure PCRT shown is illustrated. Figure 3B The memory cell structure MCS shown can have the same characteristics as... Figure 4B The shape corresponding to the inverted shape of the memory cell structure MCS shown, and Figure 3B The peripheral circuit structure shown, PCRT, can have the same characteristics as... Figure 4BThe shape corresponding to the inverted shape of the peripheral circuit structure PCRT shown is shown. For example, multiple peripheral circuit transistors PTR can be set... Figure 3B The lower surface of the peripheral circuit substrate PSUB shown. Figure 3C The memory cell structure MCS shown can have the same characteristics as... Figure 4B The shape of the shown memory cell structure MCS corresponds to the shape, and Figure 3C The peripheral circuit structure shown, PCRT, can have the same characteristics as... Figure 4B The shape corresponding to the inverted shape of the peripheral circuit structure PCRT shown. Figure 3D The memory cell structure MCS shown can have the same characteristics as... Figure 4B The shape of the shown memory cell structure MCS or the inverted shape of the memory cell structure MCS corresponds to the shape, and Figure 3D The peripheral circuit structure shown, PCRT, can have the same characteristics as... Figure 4B The shape of the peripheral circuit structure PCRT shown corresponds to the shape of the circuit.

[0084] Figure 5 This is a cross-sectional view showing a semiconductor memory device 1d according to an embodiment.

[0085] Reference Figure 5 The semiconductor memory device 1d may include a chip region CR defined by a scribe line region SL. The chip region CR and the scribe line region SL may each include adjacent chip guard ring regions CGR and SGR. The chip region CR may include a main chip region MCR (…). Figure 4B ) and the chip protection ring area CGR.

[0086] The semiconductor memory device 1d includes a substrate BSUB, a memory cell structure MCS above the substrate BSUB, and a peripheral circuit structure PCRT above the memory cell structure MCS. The semiconductor memory device 1d may also include multiple guard ring structures GRS above the substrate BSUB. The multiple guard ring structures GRS may include at least one chip guard ring structure CGS and at least one dicing guard ring structure SGS.

[0087] The peripheral circuit substrate (PSUB) may have at least two deep trenches (DTRa) extending through the PSUB, and at least two deep isolation insulating layers (DTIa) may fill the at least two deep trenches (DTRa). The at least two deep trenches (DTRa) and the at least two deep isolation insulating layers (DTIa) filling the at least two deep trenches (DTRa) may be spaced apart from each other in the horizontal direction. In some embodiments, at least one chip guard ring structure (CGS) and at least one dicing guard ring structure (SGS) may extend through different deep isolation insulating layers (DTIa) that fill different deep trenches (DTRa) among the at least two deep isolation insulating layers (DTIa) that fill the at least two deep trenches (DTRa) extending through the PSUB.

[0088] Figure 6 This is a cross-sectional view showing a semiconductor memory device 1e according to an embodiment. Figure 6 Repeated descriptions can be omitted in the description.

[0089] Reference Figure 6 The semiconductor memory device 1e includes a peripheral circuit structure PCRT and a memory cell structure MCSa above the peripheral circuit structure PCRT. In some embodiments, the semiconductor memory device 1e may have a CoP structure, wherein the memory cell structure MCSa and the peripheral circuit structure PCRT overlap each other in the vertical direction (Z direction). The memory cell structure MCSa may include a plurality of memory cells. Figure 6 An example is shown in which the semiconductor memory device 1e includes a memory cell structure MCSa with BCAT DRAM, but the embodiments are not limited thereto. For example, the semiconductor memory device 1e may include Figure 4B The memory cell structure MCS shown is an inverted shape, not... Figure 6 The memory cell structure MCSa is shown. The memory cell structure MCSa may include a cell substrate CSUB. The peripheral circuit structure PCRT may include a peripheral circuit substrate PSUB and a plurality of peripheral circuit transistors PTRs. The peripheral circuit substrate PSUB may be located on the underside of the peripheral circuit structure PCRT. A bonding insulating layer BDI may be formed on the lower surface of the cell substrate CSUB. The memory cell structure MCSa may be bonded to the peripheral circuit structure PCRT via the bonding insulating layer BDI. The memory cell structure MCSa may be electrically connected to the peripheral circuit structure PCRT via cell peripheral circuit connection vias CPIV. The peripheral circuit substrate PSUB may be referred to as a support substrate, and the cell substrate CSUB may be referred to as an intermediate substrate. Each of the cell substrate CSUB and the peripheral circuit substrate PSUB may include, for example, a semiconductor material, such as a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material, and a group II-VI oxide semiconductor material.

[0090] The peripheral circuit structure PCRT may include a peripheral circuit substrate PSUB, multiple peripheral circuit transistors PTR, a peripheral circuit bit line pattern PBL, a peripheral circuit interlayer structure PIS, and a peripheral circuit wiring structure PMS.

[0091] A memory cell structure (MCS) may include multiple active regions ACT defined by a device isolation layer (STI) filling device isolation trenches (STR) formed in a cell substrate (CSUB), multiple word lines (GL) spanning the multiple active regions ACT, multiple cell bit lines (BL) on the cell substrate CSUB, multiple direct contacts (DC) connecting the multiple cell bit lines (BL) to the multiple active regions ACT, multiple contact plugs (CCT) connected to the multiple active regions ACT and extending between the multiple cell bit lines (BL), and multiple capacitor structures (CAP) on the multiple contact plugs (CCT). The memory cell structure (MCS) may also include a cell intermediate connection structure (BIS) and a capacitor connection structure (DIS). The multiple word lines (GL) may extend parallel to each other across the multiple active regions ACT in a first horizontal direction (X direction). Multiple gate dielectric layers may be disposed between the multiple active regions ACT and the multiple word lines (GL). The multiple cell bit lines (BL) may extend parallel to each other in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). Each of the plurality of contact plugs (CCTs) may include buried contacts (BCs) and landing pads (LPs) sequentially stacked on a plurality of active regions (ACTs). The plurality of capacitor structures (CAPs) may include a plurality of capacitor lower electrodes (BCEs) connected to the plurality of contact plugs (CCTs), a capacitor dielectric layer (DIC) conformally covering the surface of each of the plurality of capacitor lower electrodes (BCEs), and a capacitor upper electrode (TCE) covering the plurality of capacitor lower electrodes (BCEs), with the capacitor dielectric layer (DIC) located between the capacitor lower electrodes (BCEs) and the capacitor upper electrode (TCE). In some embodiments, at least one lower electrode support pattern (BES) may surround a portion of the plurality of capacitor lower electrodes (BCEs), and the capacitor dielectric layer (DIC) may conformally cover the plurality of capacitor lower electrodes (BCEs) and at least one lower electrode support pattern (BES).

[0092] Figure 7A and Figure 7B , Figure 8A and Figure 8B as well as Figure 9A and Figure 9B This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 7A and Figure 7B , Figure 8A and Figure 8B as well as Figure 9A and Figure 9B Repeated descriptions can be omitted in the description.

[0093] Refer to together Figure 7A and Figure 7B A memory cell structure (MCS) is formed, and then the MCS is attached to the substrate BSUB, with the capacitor structure (CAP) facing the BSUB. A cell protection layer (CPSL) can be located between the MCS and the BSUB. The MCS includes multiple memory cells, each comprising multiple bit lines (BL), multiple channel patterns (CHL), multiple word lines (GL), multiple gate dielectric layers (Gox), multiple back gate electrodes (BG), multiple back gate dielectric layers (BGox), multiple contact plugs (CCT), and multiple capacitor structures (CAP), capacitor connection structures (DIS), cell intermediate connection structures (BIS), cell interlayer structures (CIS), cell wiring contacts (CMC), and cell landing patterns (CLP).

[0094] Refer to together Figure 8A and Figure 8B A peripheral circuit substrate (PSUB) with multiple peripheral circuit transistors (PTRs) formed thereon is attached to a memory cell structure (MCS). A bonding insulating layer (BDI) can be formed on the lower surface of the PSUB, and the PSUB can be bonded to the MCS via the BDI. The overlay insulating layer (CID) of the MCS can be covalently bonded to the BDI, thus allowing the MCS to be bonded to the peripheral circuit structure (PCRT).

[0095] The peripheral circuit substrate (PSUB) may have a deep trench (DTR) extending through the PSUB, and a deep isolation insulating layer (DTI) may fill the deep trench (DTR). Each of the deep isolation insulating layer (DTI) and the deep trench (DTR) may be formed in a tapered shape, the tapered shape extending with a decreasing horizontal width from its upper side to its lower side. For example, each of the deep isolation insulating layer (DTI) and the deep trench (DTR) may be formed in a tapered shape, the tapered shape extending with a decreasing horizontal width toward the substrate (BSUB).

[0096] Above the peripheral circuit substrate PSUB, peripheral circuit interlayer connection lines PIL, peripheral circuit interlayer connection vias PIV connecting peripheral circuit interlayer connection lines PIL to peripheral circuit transistors PTR, and peripheral circuit interlayer insulating layers PID covering multiple peripheral circuit transistors PTR and surrounding peripheral circuit interlayer connection lines PIL and peripheral circuit transistors PTR can be formed. Figure 8A and Figure 8B The peripheral circuit interlayer connection lines (PIL), peripheral circuit interlayer connection vias (PIV), and multiple peripheral circuit interlayer insulating layers (PID) shown can respectively and at least partially correspond to Figure 4A and Figure 4BThe peripheral circuit interlayer structure (PIS) shown includes multiple peripheral circuit interlayer connection lines (PIL), multiple peripheral circuit interlayer connection vias (PIV), and peripheral circuit interlayer insulation layers (PID).

[0097] Refer to together Figure 9A and Figure 9B The system forms a cell peripheral circuit connection via (CPIV) and multiple guard ring vias (GV), which are connected to the cell landing pattern (CLP) via a peripheral circuit interlayer insulating layer (PID), a deep isolation insulating layer (DTI), a bonding insulating layer (BDI), and a cover insulating layer (CID). The guard ring vias (GV) may include chip guard ring vias (CGV) located in the chip guard ring region (CGR) and scribe guard ring vias (SGV) located in the scribe guard ring region (SGR). Each of the cell peripheral circuit connection vias (CPIV) and multiple guard ring vias (GV) may be formed in a tapered shape, extending with a horizontal width that decreases from its upper side to its lower side. For example, each of the cell peripheral circuit connection vias (CPIV) and multiple guard ring vias (GV) may be formed in a tapered shape, extending with a horizontal width that decreases towards the substrate (BSUB).

[0098] Subsequently, referring to Figure 4A and Figure 4B It can form peripheral circuit bit line pattern PBL, peripheral circuit interlayer structure PIS, peripheral circuit wiring structure PMS and pad structure PDS. Therefore, it can form a semiconductor memory device 1 including a guard ring structure GRS, which includes a chip guard ring structure CGS and a dicing guard ring structure SGS.

[0099] Figure 10A and Figure 10B The planar layouts of semiconductor memory devices 1f and 1g according to embodiments are shown respectively.

[0100] Reference Figure 10A The semiconductor memory device 1f may include a chip region CR and a scribe line region SL adjacent to the chip region CR. A guard ring region GR may extend along the boundary between each of the plurality of chip regions CR and the scribe line region SL. The guard ring region GR may include a chip guard ring region CGR and a scribe guard ring region SGR. The chip region CR may include a main chip region MCR and a chip guard ring region CGR surrounding the main chip region MCR.

[0101] Multiple guard ring vias (GVs) can be arranged in the guard ring region (GR). The multiple guard ring vias (GVs) may include at least one chip guard ring via (CGV) located in the chip guard ring region (CGR) and at least one dicing guard ring via (SGV) located in the dicing guard ring region (SGR). The chip guard ring vias (CGVs) and the dicing guard ring vias (SGVs) may be spaced apart from each other.

[0102] Chip guard ring vias (CGVs) and scriber guard ring vias (SGVs) can extend along the boundary between the chip region (CR) and the scriber region (SL) in the chip guard ring region (CGR) and scriber guard ring region (SGR), respectively. In some embodiments, the chip guard ring via (CGV) can have a planar shape that continuously extends to completely surround the main chip region (MCR) in a quadrilateral ring, and the scriber guard ring via (SGV) can have a planar shape that continuously extends to completely surround the chip region (CR) in a quadrilateral ring. The chip guard ring via (CGV) can be located between the scriber guard ring via (SGV) and the main chip region (MCR).

[0103] Reference Figure 10B The semiconductor memory device 1g may include a chip region CR and a scribe line region SL adjacent to the chip region CR. A guard ring region GR may extend along the boundary between each of the plurality of chip regions CR and the scribe line region SL. The guard ring region GR may include a chip guard ring region CGR and a scribe guard ring region SGR. The chip region CR may include a main chip region MCR and a chip guard ring region CGR surrounding the main chip region MCR.

[0104] Multiple guard ring vias GVa can be arranged in the guard ring region GR. These multiple guard ring vias GVa may include multiple chip guard ring vias CGVa located in the chip guard ring region CGR and multiple dicing guard ring vias SGVa located in the dicing guard ring region SGR. The chip guard ring vias CGVa and the dicing guard ring vias SGVa can be spaced apart from each other.

[0105] Multiple chip guard ring vias (CGVa) can extend within the chip guard ring region (CGR) along the boundary between the chip region (CR) and the scribe line region (SL), and can be spaced apart from each other. Multiple scribe guard ring vias (SGVa) can extend within the scribe guard ring region (SGR) along the boundary between the chip region (CR) and the scribe line region (SL), and can be spaced apart from each other. For example, multiple chip guard ring vias (CGVa) can surround the main chip region (MCR), and can be spaced apart from each other to not completely surround the main chip region (MCR). For example, multiple scribe guard ring vias (SGVa) can surround the chip region (CR), and can be spaced apart from each other to not completely surround the chip region (CR).

[0106] Figure 10BThe illustration shows multiple chip guard ring vias (CGVa) and multiple scriber guard ring vias (SGVa), each having a straight planar shape and spaced apart from each other around the vertices of the boundary between the chip region CR and the scriber region SL. However, the embodiments are not limited to this. For example, some of the multiple chip guard ring vias (CGVa) and multiple scriber guard ring vias (SGVa) may have an L-shape extending across the vertices of the boundary between the chip region CR and the scriber region SL. For example, at least two of the multiple chip guard ring vias (CGVa) may be spaced apart from each other in the side region of the boundary between the chip region CR and the scriber region SL. For example, at least two of the multiple scriber guard ring vias (SGVa) may be spaced apart from each other in the side region of the boundary between the chip region CR and the scriber region SL.

[0107] Although various aspects of the embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device having a main chip region and a guard ring region surrounding the main chip region, the semiconductor memory device comprising: Support substrate; A memory cell structure above the supporting substrate, the memory cell structure comprising a plurality of memory cells located in the main chip region; A peripheral circuit structure is located above the supporting substrate, such that the peripheral circuit structure and the memory cell structure are stacked vertically, and the peripheral circuit structure includes a plurality of peripheral circuit transistors located in the main chip region; An intermediate substrate is located between the memory cell structure and the peripheral circuit structure; A deep insulating layer is formed in a deep trench that passes through the intermediate substrate; as well as A protective ring structure comprising a protective ring via located in the protective ring region, wherein the protective ring structure passes through the deep isolation insulating layer and extends beyond the upper surface of the intermediate substrate and beyond the lower surface of the intermediate substrate.

2. The semiconductor memory device according to claim 1, wherein, The protective ring via has a tapered shape, and the tapered shape has a horizontal width that decreases toward the supporting substrate.

3. The semiconductor memory device according to claim 2, wherein, The protective ring through-hole is formed as a single body extending from the uppermost end to the lowermost end of the protective ring through-hole.

4. The semiconductor memory device according to claim 2, wherein, The protective ring via has a linear and planar shape extending along the protective ring region.

5. The semiconductor memory device according to claim 2, wherein, The protective ring via has a planar shape of a quadrilateral ring surrounding the main chip region.

6. The semiconductor memory device of claim 1, further comprising a bonding insulating layer located between the memory cell structure and the intermediate substrate. in, The memory cell structure and the peripheral circuit structure are stacked sequentially on the support substrate along the vertical direction, and The protective ring through-hole passes through the deep isolation insulation layer and the bonding insulation layer along the vertical direction.

7. The semiconductor memory device according to claim 6, wherein, The plurality of peripheral circuit transistors are located on the upper surface of the intermediate substrate.

8. The semiconductor memory device according to claim 7, wherein, Each of the deep trenches and the deep insulating layer has a tapered shape that extends toward the supporting substrate with a horizontal width that decreases.

9. The semiconductor memory device according to claim 6, wherein, The memory cell structure includes a vertical channel transistor dynamic random access memory, and The vertical channel transistor dynamic random access memory includes a cell bit line, a word line and a back gate electrode below the cell bit line, a channel pattern between the word line and the back gate electrode below the cell bit line, a contact plug below the channel pattern, and a capacitor structure below the contact plug.

10. The semiconductor memory device according to claim 1, wherein, The peripheral circuit structure and the memory cell structure are stacked sequentially on the support substrate along the vertical direction. The protective ring via has a tapered shape extending with a horizontal width that decreases toward the supporting substrate, and Each of the deep trench and the deep insulating layer has a tapered shape that extends toward the supporting substrate with a horizontal width that increases.

11. A semiconductor memory device having a main chip region and a guard ring region, wherein, The protection ring region includes a chip protection ring region surrounding the main chip region and a dicing protection ring region surrounding the chip protection ring region. The semiconductor memory device includes: Substrate; A memory cell structure located above the substrate and comprising a plurality of memory cells located in the main chip region; A peripheral circuit structure is located above the memory cell structure and includes a peripheral circuit substrate located on the lower side of the peripheral circuit structure facing the memory cell structure and a plurality of peripheral circuit transistors on the upper surface of the peripheral circuit substrate located in the main chip region. A deep insulating layer, which is located in a deep trench penetrating the peripheral circuit substrate; and Multiple guard ring structures are provided, including a chip guard ring structure and a dicing guard ring structure. The chip guard ring structure passes through the deep isolation insulating layer in the chip guard ring region and extends beyond the upper surface and lower surface of the peripheral circuit substrate. Similarly, the dicing guard ring structure passes through the deep isolation insulating layer in the dicing guard ring region and extends beyond the upper surface and lower surface of the peripheral circuit substrate. Each of the plurality of guard ring structures includes a guard ring via having a tapered shape extending toward the substrate with a decreasing horizontal width, and each of the plurality of guard ring structures passes through the deep isolation insulating layer.

12. The semiconductor memory device according to claim 11, wherein, The guard ring via in each of the plurality of guard ring structures extends vertically horizontally from the uppermost point of each of the plurality of guard ring structures to the upper surface of the peripheral circuit substrate, and then vertically horizontally from the lowermost point of each of the plurality of guard ring structures to the lower surface of the peripheral circuit substrate.

13. The semiconductor memory device according to claim 11, wherein, The number of dicing protection ring structures arranged in the dicing protection ring region is at least two and greater than the number of chip protection ring structures.

14. The semiconductor memory device of claim 11, wherein, The via in each of the plurality of guard ring structures has a linear and planar shape extending along the boundary between the chip guard ring region and the dicing guard ring region.

15. The semiconductor memory device according to claim 14, wherein, Each of the plurality of protective ring structures includes a plurality of protective ring through holes. The plurality of protective ring vias, each disposed in the plurality of protective ring structures, extend along the same direction as the boundary between the chip protective ring region and the dicing protective ring region, and The plurality of protection ring vias are spaced apart from each other along a direction perpendicular to the boundary between the chip protection ring region and the dicing protection ring region.

16. The semiconductor memory device of claim 11, wherein, The memory cell structure includes: A capacitor structure above the substrate; Contact plugs above the capacitor structure; The groove pattern above the contact plug; Word lines and back gate electrodes arranged on opposite sides of the channel pattern; and The cell bit line above the channel pattern, the word line, and the back gate electrode.

17. The semiconductor memory device of claim 11, wherein, The protective ring via in each of the plurality of protective ring structures has a planar shape that extends continuously and surrounds the main chip region as a quadrilateral ring.

18. A semiconductor memory device having a main chip region and a guard ring region, wherein, The protection ring region includes a chip protection ring region surrounding the main chip region and a dicing protection ring region surrounding the chip protection ring region. The semiconductor memory device includes: Substrate; A memory cell structure located above the substrate and comprising a plurality of memory cells located in the main chip region; A peripheral circuit structure is located above the memory cell structure. The peripheral circuit structure includes a peripheral circuit substrate located on the lower side of the peripheral circuit structure facing the memory cell structure, and a plurality of peripheral circuit transistors on the upper surface of the peripheral circuit substrate in the main chip region. A bonding insulating layer is formed between the lower surfaces of the memory cell structure and the peripheral circuit substrate; A deep insulating layer comprising a deep trench defined by the peripheral circuit substrate, the deep trench having a tapered shape extending with a horizontal width decreasing toward the substrate; and Multiple guard ring structures are provided, including a chip guard ring structure and a dicing guard ring structure. The chip guard ring structure passes through the deep isolation insulating layer and the bonding insulating layer in the chip guard ring region, and extends beyond the upper surface and lower surface of the peripheral circuit substrate. Similarly, the dicing guard ring structure passes through the deep isolation insulating layer and the bonding insulating layer in the dicing guard ring region, and extends beyond the upper surface and lower surface of the peripheral circuit substrate. Each of the plurality of guard ring structures includes a guard ring via having a tapered shape extending toward the substrate with a horizontal width that decreases. The memory cell structure includes: A capacitor structure includes a lower capacitor electrode above the substrate, a capacitor dielectric layer covering the lower capacitor electrode, and a upper capacitor electrode covering the lower capacitor electrode, wherein the capacitor dielectric layer is located between the upper capacitor electrode and the lower capacitor electrode. A contact plug is connected to the lower electrode of the capacitor above the capacitor structure; A channel pattern that connects to the contact plug above it; Word lines and back grid electrodes arranged on opposite sides of the channel pattern; A gate dielectric layer is located between the channel pattern and the word line; A back gate dielectric layer located between the channel pattern and the back gate electrode; and A cell bit line, which connects to the channel pattern above the channel pattern, the word line, and the back gate electrode, and The via in each of the plurality of protection ring structures has a linear and planar shape extending along the boundary between the chip protection ring region and the dicing protection ring region.

19. The semiconductor memory device of claim 18, wherein, Each of the plurality of protective ring structures includes metal, and In each of the plurality of protective ring structures, the protective ring through-hole is formed as a single body extending from the uppermost end to the lowermost end of the protective ring through-hole.

20. The semiconductor memory device of claim 18, further comprising a cell peripheral circuit connection via, the cell peripheral circuit connection via passing through the deep isolation insulating layer in the main chip region to connect the memory cell structure to the peripheral circuit structure. in, The peripheral circuit connection vias of the unit have a tapered shape extending with a horizontal width decreasing toward the substrate, and The peripheral circuit connection via and the protective ring via are at the same vertical level.

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