Transistor device and method for forming recess for trench gate electrode

Abstract

Transistor devices and methods for forming recesses for trench gate electrodes are disclosed. In an embodiment, a method includes forming a recess for a trench gate electrode, the method including: forming a trench in a first major surface of a semiconductor substrate, the trench having a bottom and sidewalls extending from the bottom to the first major surface; forming a first insulating layer on the bottom and the side wall of the groove; inserting a first conductive material into the trench, the first conductive material at least partially covering the first insulating layer to form a field plate in a lower portion of the trench; applying a second insulating layer to the first main surface and the trench such that the second insulating layer fills the trench and covers the conductive material; removing the second insulating layer from the first main surface and partially removing the second insulating layer from the trench by wet chemical etching; and forming a recess for the gate electrode in the second insulating layer in the trench.

Description

Background Technology

[0001] Many functions of modern devices in automotive, consumer, and industrial applications (such as those controlling electric motors or electric motors) are based on semiconductor transistor devices, such as field-effect transistors (e.g., MOSFETs (metal-oxide-semiconductor field-effect transistors) and IGBTs (insulated-gate bipolar transistors)).

[0002] The capacitance between the gate electrode and each power supply electrode—the source and drain electrodes for MOSFETs and the emitter and collector electrodes for IGBTs—and the transistor's blocking voltage are operating parameters that can be optimized to improve the performance of the transistor device. Buried field plates can be used to increase the on-resistance R for specific applications. on The blocking voltage. A field plate and gate electrode can be arranged in a trench, with the field plate facing downwards and the gate electrode facing upwards. The gate electrode is electrically isolated from the field plate and the semiconductor body, and the field plate is typically electrically isolated from the semiconductor body by an insulating material such as an oxide. While the buried field plate can be used to reduce the gate-drain capacitance (Qgd), a capacitance is generated between the gate electrode and the field plate, which forms part of the gate-source capacitance (Qgs) because the field plate is typically coupled to the source potential.

[0003] The gate-source capacitance can be influenced by adjusting the dielectric constant and thickness of the insulating layer between the gate electrode and the field plate. However, further improvements are desirable to further enhance the performance of transistor devices. Summary of the Invention

[0004] In one embodiment, the transistor device includes a semiconductor substrate having a first main surface and a plurality of transistor cells. Each transistor cell includes: a trench extending from the first main surface into the semiconductor substrate and having a bottom and sidewalls extending from the bottom to the first main surface; a field plate in the trench; a gate electrode in the trench disposed above and electrically insulated from the field plate; and a mesa including a drift region, a body region on the drift region, and a source region on the body region. The lower surface of the gate electrode is disposed at a depth d from the first main surface. g Location. The body region at a depth d from the first primary surface. pn A pn junction is formed between the semiconductor material and the semiconductor substrate at a depth d. pn and depth d g The difference between them is less than d g 8%.

[0005] In an embodiment, a method of forming a recess for a trench gate electrode includes: forming a trench in a first main surface of a semiconductor substrate, the trench having a bottom and sidewalls extending from the bottom to the first main surface; forming a first insulating layer on the bottom and sidewalls of the trench; inserting a first conductive material into the trench, the first conductive material at least partially covering the first insulating layer to form a field plate in a lower portion of the trench; applying a second insulating layer to the first main surface and the trench such that the second insulating layer fills the trench and covers the conductive material of the field plate; removing the second insulating layer from the first main surface and partially removing the second insulating layer from the trench by wet chemical etching; and forming a recess for a gate electrode in the second insulating layer in the trench.

[0006] When reading the following detailed description and when viewing the accompanying drawings, those skilled in the art will recognize the additional features and advantages. Attached Figure Description

[0007] The elements in the accompanying drawings are not necessarily to scale. The same reference numerals indicate corresponding similar parts. Features of various illustrated embodiments can be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the drawings and are described in detail in the following description.

[0008] Figures 1A to 1G The diagram illustrates a method for forming recesses for trench electrodes.

[0009] Figure 2 The diagram illustrates a flowchart of a method for forming a recess for a trench gate electrode.

[0010] Figure 3 The illustration shows a transistor device including a trench gate electrode. Detailed Implementation

[0011] In the following detailed description, reference is made to the accompanying drawings, which are formed in part herein and in which specific embodiments (in which the invention may be practiced) are illustrated by way of illustration. In this regard, directional terms such as “above,” “below,” “front,” “rear,” “front end,” “end,” etc., are used to indicate orientation with reference to the described figures. Because components of various embodiments may be positioned in many different orientations, these directional terms are used for illustrative purposes and are by no means limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. The following detailed description of the invention should not be viewed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0012] Many exemplary embodiments will now be explained. In this context, the same structural features are identified by the same or similar reference numerals in the figures. In the context of this description, “lateral” or “lateral direction” should be understood to mean a direction or range generally parallel to the lateral extent of the semiconductor material or semiconductor carrier. Thus, the lateral direction generally extends parallel to these surfaces or sides. In contrast, the term “vertical” or “vertical direction” is understood to mean a direction generally perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Thus, the vertical direction travels in the thickness direction of the semiconductor material or semiconductor carrier.

[0013] As used in this specification, when an element such as a layer, region, or substrate is referred to as "on another element" or "extending to another element," it may be directly on or directly extended to another element, or there may be an intermediate element. Conversely, when an element is referred to as "directly on another element" or "extending directly to another element," there is no intermediate element.

[0014] As used in this specification, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected to or coupled to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0015] In power MOSFET devices, the gate-drain capacitance (Qgd) has a strong influence on the device's switching behavior. The ratio between Qgd and Qgs (gate-source capacitance) determines the sensitivity to inductive turn-on (during turn-off, a rapidly rising drain voltage turns the device on via capacitive coupling). The value of the gate-drain capacitance adds to switching losses, and it affects the drift behavior of the channel resistance when the device is subjected to stress conditions. To control these issues, precise control of the process is required to achieve a precise target value for the gate-drain capacitance and to allow for small variations across each wafer, which can be challenging for vertical gate structures.

[0016] The geometric equivalent of the Qgd value is the overlap of the lower end of the gate electrode on the end of the transistor body. For transistor structures with trenches including the gate electrode positioned on the field plate—also known as dual polysilicon MOSFETs—this geometry typically depends at least on the lower polysilicon electrode, i.e., the recess of the field plate, and the growth of the IPD (inter-polysilicon dielectric), since both the field plate and the gate electrode are formed from polysilicon. Using conventional processes for etching the gate recess and subsequent deposition / growth, production limitations are expected to vary on the order of >~+ / -40nm.

[0017] The embodiments described herein are based on the understanding that, for a vertical gate structure, the Qgd value can depend on the history of the trench treatment prior to gate oxide growth, since the vertical position of the gate electrode in the trench is defined by the initial recess entering the trench, while the body implantation is defined with respect to the mesa surface; and based on the understanding that this difference can lead to alignment variations between the gate electrode and the MOSFET channel across wafers and batches.

[0018] As described herein, a process is provided in which the gate electrode positioning in such a vertical dual polysilicon MOSFET is independent of the trench processing history. Therefore, better control over the target Qgd value is provided. Gate overlap is defined at the ends of the transistor body using the following method. In a first step, after forming a lower polysilicon electrode (i.e., a field plate) in the lower portion of the trench and removing oxide from the sidewalls of the upper portion of the trench above the field plate, the entire trench is refilled with oxide. In a second step, the oxide overfill is planarized using a chemical mechanical polishing (CMP) process, and the CMP is designed to stop at the top of the transistor mesa with very high selectivity. In some embodiments, silicon removal from the mesa is only on the order of a few (2 to 3) nm. This method defines a new surface from which the gate electrode and all implantation of both are defined. Thus, the upper portion of the transistor becomes independent of all the processes involved in forming the lower polysilicon electrode. Since the entire upper portion of the trench is filled with oxide, the lower end of the gate electrode can be defined solely by a wet chemical etching process used to form a recess for the gate electrode in the upper portion of the trench. In this way, the geometric variation between the overlap of the gate electrode and the body region can be reduced to approximately + / - 15 nm. This, in turn, results in a reduction in variation by a factor of approximately 2.5 to 3 compared to current standard methods.

[0019] Figures 1A to 1G The diagram illustrates a recess for forming a trench gate electrode and a method for forming the trench gate electrode within the recess. The trench gate electrode can be used in transistor devices such as MOSFET devices.

[0020] Figure 1A The illustration shows a semiconductor substrate 10, which may be a silicon substrate. The silicon substrate may be a single-crystal silicon wafer, or may include an epitaxially deposited single-crystal silicon layer, typically known as an epitaxial layer, disposed on a support substrate, which may be a single-crystal silicon wafer. The semiconductor substrate 10 includes a first main surface 11.

[0021] The trench 12 is formed in the first main surface 11 of the semiconductor substrate 10 and has a bottom 13 and sidewalls 14 extending from the bottom 13 to the first main surface 11. The trench may extend substantially perpendicular to the first main surface 11. The first main surface 11 may be described as a lateral or horizontal surface and the trench 12 may be considered as a vertical trench.

[0022] The trench 12 may have an elongated strip shape, wherein the length of the trench 12 extends into the plane of the drawing. Typically, a MOSFET device includes a plurality of trenches 12 that extend substantially parallel to each other such that adjacent trenches 12 define mesas 30. In other embodiments, the trenches 12 may have a columnar or needle-like shape and may be substantially circular, square, or hexagonal in plan view. In these embodiments, the region between the columnar trenches forms a mesas.

[0023] The sidewall 14 is continuously adjacent to the bottom 13 to form a groove 12. In embodiments in which the groove 12 has an elongated strip shape, the sidewall 14 may have two substantially parallel long portions connected by two substantially parallel short portions extending substantially perpendicular to the long portions to form a rectangular shape in a plan view.

[0024] The method will be described with respect to a single trench 12. However, the fabrication of the recess and trench gate electrode is typically performed substantially simultaneously for multiple trenches. The trench 12 may form part of the active switching region of a transistor device and be located in a portion commonly referred to as the active region 15 or cell field of the transistor device. Some of the trenches 12' may also be located in the edge-terminating region 16 and form part of the edge-terminating structure of the transistor device. The trenches 12' in the edge-terminating region may have one or more dimensions, such as width, that differ from the dimensions of the trenches 12 in the active region 15.

[0025] After forming a trench 12 in the first main surface, a first insulating layer 17 is formed on the bottom 13 and sidewalls 14 of the trench 12, and the first insulating layer 17 can completely cover the semiconductor material forming the bottom 13 and sidewalls 14 of the trench 12. The first insulating material 17 has a thickness such that it pads the bottom 13 and sidewalls 14 and defines a gap or unfilled area at the center of the width of the trench 12. A first conductive material 18 is inserted into the trench, and in particular into the gap defined by the first insulating layer 17, to form a field plate 19 in the lower portion of the trench 12.

[0026] In some embodiments, such as in Figure 1AAs illustrated, in the upper portion of trench 12, the first insulating layer 17 is completely removed from the sidewall 14 of the upper portion of trench 12, thereby exposing the semiconductor material of the substrate 10. The uppermost portion of the field plate 19 may protrude above the upper surface of the remaining portion of the first insulating layer 17. In some embodiments, a very thin insulating layer having a thickness of a few nanometers may be present on the sidewall 14 of the upper portion of trench 12.

[0027] The first conductive material 18 can be inserted into the trench 12 by completely filling the trench 12 with the first conductive material 18 and applying the first conductive material 18 onto the first main surface 11 of the semiconductor substrate 10. The first conductive material 18 is then removed from the first main surface 11, for example, by chemical mechanical polishing, and from the upper portion of the trench 12, for example, by etching, to form a field plate 19 in the lower portion of the trench 12. The upper portion of the trench 12 is unfilled or empty and may be laterally defined by the semiconductor material of the semiconductor substrate 10 forming the sidewalls 14 of the trench 12, and at the bottom by the field plate 19 and a first insulating layer 17 laterally disposed between the field plate 19 and the sidewalls 14. The first insulating layer 17 may be formed of silicon oxide (e.g., silicon dioxide), and the first conductive material 18 and the field plate 19 may be formed of polysilicon.

[0028] Figure 1B The illustration shows the semiconductor substrate 10 after a second insulating layer 20 has been applied to the first main surface 11 of the semiconductor substrate 10 such that the second insulating layer 20 fills the trench 12 and covers the conductive material 18 and the field plate 19. The second insulating layer 20 covers the portion of the field plate 19 that protrudes from the first insulating layer 17 and contacts the portions of the field plate 19 that are not covered by the first insulating layer 17, including the upper surface and sidewalls. The second insulating layer 20 also contacts the first insulating layer 17 and the sidewalls 14 of the upper portion of the trench 12, or contacts a thin oxide layer (if present) retained on the upper portion of the sidewalls 14 of the trench 12.

[0029] The second insulating layer 20 may be deposited conformally such that it has peaks above the mesa 30 and valleys above the trench 12. The bottom of the valleys lies above the first master surface 11, so that the trench 12 is completely filled by the second insulating layer 20. The second insulating layer 20 may be deposited using high-density plasma deposition (HDP) and may be formed of silicon dioxide.

[0030] Figure 1CThe diagram shows a semiconductor substrate after the second insulating layer 20 has been removed from the first main surface 11 of the semiconductor substrate 10 to expose the semiconductor material of the mesa 30 and form the uppermost surface of the semiconductor substrate 10, and the second insulating material 20 located in the trench 12 is substantially coplanar with the upper surface of the mesa 30 to provide a flat first main surface 11.

[0031] The flat first primary surface 11 can then be used to determine the depth of the gate in the trench 12 and the location of the injection region within the mesa 30, as per [reference to...]. Figures 1D to 1G As described.

[0032] The second insulating layer 20 is partially removed from the trench 12, and a recess 21 for the gate electrode is formed in the second insulating layer 20 in the trench 12, as shown in... Figure 1D As shown in the diagram, the recess 21 has a bottom 24 formed of a second insulating material 20, such that it is spaced from the field plate 19 by the area of ​​the second insulating layer 20. The second insulating layer 20 provides electrical insulation on the top of the field plate 19. The sidewalls 22 of the recess 21 are formed of a semiconductor material of the semiconductor substrate 10. The recess 21 has a depth d. r So that the bottom 24 of the recess 21 is located at a depth or distance d from the first main surface 11. r Place.

[0033] The second insulating layer 20 is removed from the trench 12 by wet chemical etching to form the recess 21. The depth d of the recess 21 can be controlled using the first main surface 11 by removing the second insulating material 20 from the trench 12 and forming the recess 21 through wet chemical etching. r Because the first primary surface 11 can act as an etching stop. Since the top portion of the trench 12 is filled with a single insulating material—the material of the second insulating layer 20—wet etching allows for more precise control of the depth d of the recess 21. r .

[0034] In some embodiments, the second insulating layer 20 is selectively removed with respect to the material of the semiconductor substrate 10. For example, the first main surface 11 of the semiconductor substrate 10 may serve as an etch stop. The second insulating layer 20 may be selectively removed by chemical mechanical polishing (CMP). Chemical mechanical polishing may include using a slurry with a polishing selectivity of the material of the second insulating layer 20 having approximately 100:1 to the material of the semiconductor substrate.

[0035] Figure 1EThe illustration shows a semiconductor substrate 10 after a third insulating layer 23 has been formed on the exposed sidewall 22 of the recess 21. The third insulating layer 23 forms a gate oxide and is thinner than the first insulating layer 17. In some embodiments, the third insulating layer 23 is conformally deposited and covers the first main surface 11, the sidewall 22 of the recess 21, and the bottom 24.

[0036] As in Figure 1F As shown in the diagram, a second conductive material 25 is inserted into a recess 21 that now includes a third insulating layer 23, at least on the sidewalls 22, serving as a gate oxide, to form a gate electrode 26 in the upper portion of the trench 12. The gate electrode 26 is separated from the semiconductor material of the mesa 30 by the third insulating material 23 and from the field plate 19 by the second insulating layer 20. In embodiments where the gate oxide is deposited on the second insulating layer 20, the gate electrode 26 is separated from the field plate by the gate oxide and the second insulating layer 20.

[0037] The first insulating layer 17, the second insulating layer 20, and the third insulating layer 23 may comprise silicon oxide. The semiconductor substrate 10 may comprise silicon. The first conductive material 18 forming the field plate 19 and the second conductive material 25 forming the gate electrode 26 may comprise polycrystalline silicon.

[0038] The depth d of the recess 21 formed r The depth d of the gate electrode in the final device structure can be compared with that of the gate electrode. g Similarly, for example, if the third insulating layer 23 forming the gate oxide is deposited only on the silicon forming the sidewalls 22. In some embodiments, the depth d of the recess... r Can be used with d g There is an offset. For example, if the third insulating layer 23 forming the gate oxide is deposited on the bottom 24 of the recess 21, then the depth d of the recess... r Possibly related to d g There is an offset. If the third insulating layer 23 forming the gate oxide is formed by thermal annealing, then the depth d of the recess... r The wear and tear on the top portion of the platform or the effects of other processing parameters (such as those affecting the upper surface of the platform, like thermal oxides, e.g., masking oxides) may affect the d. g There is an offset.

[0039] As in Figure 1GAs schematically illustrated by the arrow, a body region 27 of a second conductivity type can be formed by implantation into the first main surface 11 of the semiconductor substrate 10. The body region 27 forms a pn junction 28 with the underlying semiconductor material of the semiconductor substrate 10 (which includes a first conductivity type opposite to the second conductivity type). For example, the semiconductor substrate can be n-type and the body region 27 can be p-type. The pn junction 28 is formed at a depth d from the first main surface 11. pn At the location. A source region 29, including a first conductivity type, is formed on the body region 27.

[0040] The lower surface of the gate electrode 26 is located at a depth d from the first main surface 11. g The pn junction 28 between the body region 27 and the underlying semiconductor substrate 10 is disposed at a depth d from the first main surface 11. pn Since both the implantation process used to form the body region 27 and the wet etching process used to form the recess 21 are determined by measurements taken from the position of the first main surface 11, the relationship between the bottom position of the recess 21, and therefore the lowermost portion of the gate electrode 26, and the position of the body region 27, and therefore the pn junction 28, can be more tightly controlled. Therefore, the overlap between the gate electrode 26 and the body region 27 can be more tightly controlled, and the gate-drain capacitance Qgd is reduced.

[0041] In some embodiments, depth d pn and depth d g The change in the difference between them is less than d g 8%. This difference in depth is an absolute difference in depth. The difference in depth can have a distribution defined in sigma terms. In some embodiments, depth d pn and depth d g The change in the difference between them is less than d g 8%, with ±4.5σ. As an example, the depth d of the recess... r It can be 200±20nm, with a distribution of ±4.5σ. If the depth d pn With a variation of ±10 nm with a standard deviation of 4.5σ, the total variation is √(20 2 +10 2 =√(500) = ±22.4nm, with ±6.4σ, because √(4.5) 2 +4.5 2 = ±6.4σ, and each treatment is independent.

[0042] Depth d pn and depth d gThe variation in differences is lower not only for cells within the cell field of a single transistor device, but also for edge termination regions and for different wafers and different batches.

[0043] The lower surface of the gate electrode 26 has a depth d in the final product. g The depth d of the concave portion directly after its formation. r Possibly related to the depth d in the final product g The difference lies in the fact that the growth of the gate oxide consumes some of the silicon on the mesa. If the gate oxide is deposited on the bottom of recess 21, for example, in... Figure 1E The third insulating layer 23 shown in the diagram, then the initial recess depth d r The thickness of the deposited layer is modified. For the deposited gate oxide layer, at the initial recess depth d... r This thickness is taken into account. Since the thickness of the gate oxide layer is controlled very precisely, it should not adversely affect Q. gd The accuracy achieved.

[0044] In some embodiments, the depth d of the recess 21 can be further controlled as follows. r Determine the depth d of the recess 21 r1 The determined depth d r1 Compare with the predetermined depth, and if the determined depth d r1 If the depth is less than the predetermined depth, the second insulating layer 21 can be further removed, for example, by wet chemical etching, thus increasing the depth of the recess 21. This method can be repeated until the determined depth equals the depth d. r It can respond to the determined depth d of the recess 21. r1 To adjust the composition and / or one or more etching conditions of wet chemical etching.

[0045] Figure 2 The diagram illustrates a flowchart 40 of a method for forming a recess for a trench gate electrode. In block 41, a trench is formed in a first main surface of a semiconductor substrate, the trench having a bottom and sidewalls extending from the bottom to the first main surface.

[0046] In block 42, a first insulating layer is formed on the bottom and sidewalls of the trench. In block 43, a first conductive material is inserted into the trench such that it at least partially covers the first insulating layer to form a field plate in the lower portion of the trench. In block 44, a second insulating layer is applied to the first main surface and the trench such that the second insulating layer fills the trench and covers the conductive material. In block 45, the second insulating layer is removed from the first main surface. In block 46, the second insulating layer is partially removed from the trench by wet chemical etching, and a recess for a gate electrode is formed in the second insulating layer in the trench. The use of wet chemical etching allows for control of the depth of the recess relative to the first main surface of the substrate.

[0047] In some embodiments, the second insulating layer is selectively removed, and the first main surface of the semiconductor substrate acts as an etch stop. Further aids in depth control can be provided by using chemical mechanical polishing (CMP) to remove the second insulating layer from the first main surface, and a slurry selective for the material of the second insulating layer, such as silicon oxide, compared to the material of the semiconductor substrate, such as silicon. CMP can be performed using a slurry having a polishing selectivity of approximately 100:1 for the second insulating layer compared to the semiconductor substrate.

[0048] A second insulating layer can be deposited onto the first main surface using high-density plasma (HDP) deposition. HDP deposition can be used to ensure that the upper portion of the trench is completely filled with a single bulk of material comprising the second insulating layer. Since different oxides have different etch rates, filling the trench with one type of oxide only allows control over the depth of the recess and thus the position of the gate electrode below the device, as well as its spacing from or depth from the first main surface. Filling the upper portion of the trench with a single material further aids in providing predictable and controllable removal of the second insulating layer from the trench via wet etching, and thus helps to provide a well-defined depth to the recess and a well-defined position of the gate electrode relative to the first main surface of the semiconductor substrate.

[0049] In some embodiments, removing the second insulating layer from the trench by wet chemical etching includes exposing the semiconductor material at the sidewalls of the trench above the first conductive material. The first conductive material of the field plate remains covered by the second insulating material.

[0050] Before refilling the trench, the first insulating layer can be removed from the sidewalls by wet chemical etching (if the first insulating layer is present on the sidewalls in the upper portion of the trench) to expose the semiconductor material of the semiconductor substrate.

[0051] In some embodiments, the recess for the gate electrode may be formed using multiple steps. For example, in one embodiment, the method further includes: determining the depth of the recess; comparing the determined depth with a predetermined depth; and further removing a second insulating layer and increasing the depth of the recess using wet chemical etching. The method may be repeated until the recess reaches the predetermined depth. The composition and / or etching conditions of the wet chemical etching may be adjusted in response to the determined depth.

[0052] In some embodiments, the composition and / or etching conditions of wet chemical etching can be adjusted in response to the determined depth of the recess for use in manufacturing subsequent wafers or wafer batches.

[0053] In some embodiments, the method further includes: forming a third insulating layer on the exposed sidewalls to form a gate oxide; and inserting a second conductive material into the recess to form a gate electrode in the upper portion of the trench. The third insulating layer can be formed by depositing insulating material into the trench or by oxidizing the semiconductor material of the exposed sidewalls of the trench.

[0054] In some embodiments, a field plate can be formed in a lower portion of a trench by filling the trench with the first conductive material and applying the first conductive material on a first main surface, and then removing the first conductive material from the first main surface and from the upper portion of the trench.

[0055] The method may further include: forming a body region of a second conductivity type by implanting it into a first main surface of a semiconductor substrate, the body region being at a depth d from the first main surface. pn A pn junction is formed between the semiconductor material and the semiconductor substrate, and a source region is formed on the body region. The semiconductor material of the semiconductor substrate in contact with the body region forms the drift region of the transistor structure. A drain region can be formed in the semiconductor substrate below the drift region to form a vertical transistor structure such as a vertical MOSFET structure. The drain region can be provided by a semiconductor support substrate, which is, for example, heavily doped with a first conductivity type, wherein the drift region, body region, and source region of the mesa, as well as the trench, are formed in an epitaxial semiconductor layer formed on the support substrate.

[0056] The positions of the recess and the gate electrode formed in the recess are independent of the prior methods and processes used to form the field plate in the bottom of the trench. Therefore, any change in the position of the field plate is not propagated to the position of the gate electrode. Additionally, since the body region is formed by implantation into the semiconductor substrate from the first main surface, the position of the body region with respect to the first main surface, and the depth of the pn junction between the body region and the portion of the semiconductor substrate below the drift region, are controlled with respect to the same surface, i.e., the first main surface used to control the depth of the gate electrode. Therefore, the difference between the depth of the recess and its gate electrode and the depth of the pn junction between the body region and the drift region can be defined more precisely not only within a single transistor device cell but also on a wafer-by-wafer and batch-by-batch basis. Therefore, the gate-drain capacitance can be reduced not only for a single transistor device but also for multiple wafers and multiple batches of wafers.

[0057] In some embodiments, the improved Qgd control process can be implemented as follows: The starting point is a vertical dual polysilicon transistor with a completed lower polysilicon electrode, i.e., a field plate. The insulating layer or field oxide (FOX) at the sidewalls of the upper portion of the trench above the field plate has been removed to optimize the aspect ratio of the top opening for oxide filling of the trench. Depending on the aspect ratio of the trench, this removal of the field oxide can be omitted.

[0058] In the next step, the trenches are filled with oxide, including overfill portions. The height of the overfill portion can depend on the properties of the paste used in the subsequent CMP process. Depending on the paste requirements for subsequent planarization, the fill can be transferred to a topology or flattened. If high-density plasma (HDP) is used to deposit the oxide, a thin protective layer can be grown or deposited before oxide filling to protect the exposed silicon from plasma damage.

[0059] In the next step, the surface is planarized in a CMP process. This process requires very high selectivity for oxides compared to silicon, so as not to significantly affect trench depth and trench depth variation. Necessary cleaning steps are performed after planarization, which may have resulted in small, initial, constant recesses of oxides that have entered the trenches.

[0060] Finally, the oxide is recessed to create a recess for the gate electrode, according to the requirements for entering the trench. Due to the previous planarization, this recess becomes independent of the trench's processing history. Both the gate electrode and the implantation are defined from the same surface, resulting in optimized alignment between the channel and the gate electrode. This allows for minimizing the overlap of the resulting gate over the channel and helps reduce / control Qgd. The wet recess etching can be divided into multiple sections to finely tune the final depth after the first initial etching / measurement. A constant offset can also be added by possible wet cleaning before subsequent gate oxide growth. The offset can also be used in the deposited gate oxide, reducing the initial size of the recess by the width of the deposited and annealed gate oxide layer.

[0061] Figure 3 The illustration shows a transistor device 50, such as a MOSFET device, which includes a gate structure 51 fabricated using the methods described herein. The transistor device 50 includes a semiconductor substrate 52 having a first main surface 53 and a plurality of transistor cells 54. Each transistor cell 54 includes: a trench 55 extending substantially perpendicularly from the first main surface 53 into the semiconductor substrate 52 and having a bottom 56 and sidewalls 57 extending from the bottom 56 to the first main surface 53; a field plate 58 in the trench 55; and a gate electrode 59 in the trench 55, disposed above and electrically insulated from the field plate 58. The gate electrode 59 is recessed into a top portion of the trench 55, such that its upper surface lies below the first main surface 53. The transistor cell 54 also includes a mesa 60 defined by adjacent trenches in the trench 55, the trench 55 including a drift region 61, a body region 62 on the drift region 61, and a source region 63 on the body region 62. The lower surface 64 of the gate electrode 59 is disposed at a depth d from the first main surface 53. g At that location, and the body region 62 at a depth d from the first main surface. pn A pn junction 65 is formed between the semiconductor material and the semiconductor substrate 52. Depth d pn and depth d g The difference between them is less than d g 8%.

[0062] The transistor device 50 also includes a drain region 66, on which a drift region 61 is formed. The drain region 66 can be formed in a support substrate, such as a highly doped silicon single-crystal substrate, and the drift region 61, body region 62, and source region 63 can be formed in an epitaxial silicon layer grown on the support substrate. The drain region can form the back surface of the transistor device 60. The semiconductor substrate 52, drift region 61, source region 63, and drain region 66 have a first conductivity type, such as n-type, and the body region 62 has a second conductivity type, such as p-type.

[0063] The trench 55 includes a first insulating layer 67 forming a field oxide that liner the lower portion 68 of the bottom 56 and sidewall 57 and is laterally positioned between the field plate 58 and the sidewall 57. A second insulating layer 69 is positioned on the field plate 58 and extends between the field plate 58 and the gate electrode 59. The top portion of the field plate 58 is covered by the second insulating layer 69. A third insulating layer 70, providing gate insulation or gate oxide, is disposed on the portion 71 of the sidewall 57 at the top of the trench 55 and extends from the second insulating layer 69 to the first main surface 53 of the semiconductor substrate 52.

[0064] Since the overlap of the gate electrode 59 below the body region 62 between the gate electrode 59 can be more precisely controlled by using the method described herein to manufacture the transistor device 50, the gate-drain capacitance can be easily and more precisely controlled and the performance of the transistor device 50 can be improved.

[0065] For ease of description, spatial relative terms such as "below," "under," "lower part," "above," and "upper part" are used to explain the positioning of one element relative to a second element. These terms are intended to cover different device orientations other than those depicted in the figures. Furthermore, terms such as "first," "second," etc., are used to describe various elements, areas, sections, etc., without any intention of limitation. The same terms are used throughout the description to refer to the same elements.

[0066] As used herein, the terms “having,” “comprising,” “including,” and “containing,” etc., are open-ended terms that indicate the presence of a stated element or feature but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the quantifiers “a,” “an,” and the pronoun “the” are intended to include both plural and singular forms. It is to be understood that, unless otherwise specifically indicated, features of the various embodiments described herein may be combined with each other.

[0067] While specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternatives and / or equivalent implementations may be made in place of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A method for forming a recess (21) of a gate electrode (26) in a trench, the method comprising: A trench (12) is formed in the first main surface (11) of the semiconductor substrate (10), the trench (12) having a bottom (13) and a sidewall (14) extending from the bottom (13) to the first main surface (11). A first insulating layer (17) is formed on the bottom (13) and sidewall (14) of the trench (12) and on the first main surface. A first conductive material (18) is inserted into a trench (12), the first conductive material (18) at least partially covering the first insulating layer (17) to form a field plate (19) in the lower portion of the trench (12). The first insulating layer (17) is removed from the first main surface and from the sidewall (14) at the upper portion of the trench (12) to expose the semiconductor material of the semiconductor substrate (10); A second insulating layer (20) is formed on the first main surface (11) and on the trench (12), such that the second insulating layer (20) fills the trench (12) and covers the conductive material (18). Remove the second insulating layer (20) from the first main surface (11); as well as The second insulating layer (20) is partially removed from the trench (12) by wet chemical etching, and a recess (21) for the gate electrode (26) is formed in the second insulating layer (20) in the trench (12).

2. The method according to claim 1, wherein the second insulating layer (20) is selectively removed from the first main surface (11) by chemical mechanical polishing, and the first main surface (11) of the semiconductor substrate (10) serves as an etch stop.

3. The method according to claim 1 or 2, further comprising: A third insulating layer (23) is formed on the exposed sidewall (22), and A second conductive material (25) is inserted into the recess to form a gate electrode (26) in the upper portion of the trench (12).

4. The method according to any one of claims 3, further comprising: After forming the gate electrode (26), a second conductivity type body region (27) is formed by implanting it into the first main surface (11) of the semiconductor substrate (10), the body region (27) being at a depth d from the first main surface (11). pn A pn junction (28) is formed between the semiconductor material and the semiconductor substrate (10), and A source pole region (29) is formed on the body region (27).

5. The method according to any one of claims 1 to 4, wherein inserting the first conductive material (18) comprises: The trench (12) is filled with a first conductive material (18), and the first conductive material (18) is applied on the first main surface (11). The first conductive material (18) is removed from the first main surface (11) and from the upper portion of the trench (12) to form a field plate (19) in the lower portion of the trench.

6. The method according to any one of claims 1 to 5, further comprising: Determine the depth d of the recess (21) r1 ; The determined depth d r1 With the predetermined depth d r Comparison, and Wet chemical etching was used to further remove the second insulating layer (20) and increase the depth of the recess (21).

7. The method of claim 6, further comprising adjusting the composition and / or etching conditions of the wet chemical etching in response to the determined depth.

8. The method of claim 2, wherein performing chemical mechanical polishing comprises using a slurry having a polishing selectivity of a second insulating layer (20) having a ratio of 100 to 1 over the semiconductor substrate (10).

9. The method according to any one of claims 1 to 8, wherein a second insulating layer (20) is applied using high-density plasma deposition.

10. The method according to any one of claims 1 to 9, wherein removing the second insulating layer (20) from the trench (12) by wet chemical etching includes exposing semiconductor material at the sidewall (14) of the trench above the first conductive material (18), which is covered by the second insulating material (20).

11. The method according to any one of claims 1 to 10, wherein the first insulating layer (17) and the second insulating layer (20) comprise silicon oxide, the semiconductor substrate (10) comprises silicon, and the first conductive material (18) comprises polycrystalline silicon.

12. The method according to any one of claims 4, wherein the method is performed substantially simultaneously on a plurality of trenches, and the gate electrode (26) has been positioned at a depth d from the first main surface (11). g The lower surface at the location and for the depth d of multiple trenches pn and depth d g The difference between them is less than d g 8%.

13. A transistor device, comprising: A semiconductor substrate having a first main surface and a plurality of transistor units, each transistor unit comprising: A trench extends from a first main surface into a semiconductor substrate and has a bottom and sidewalls extending from the bottom to the first main surface; The field plate in the trench The gate electrode in the trench is arranged on the field plate and electrically insulated from the field plate. The first insulating layer (17) is disposed between the field plate and the trench and is not disposed on the first main surface. The second insulating layer is disposed between the field plate and the gate electrode and is not disposed on the first main surface. A third insulating layer is disposed between the gate electrode and the trench, and The platform includes a drift region, a body region on the drift region, and a source region on the body region.

14. The transistor device of claim 13, wherein the substrate comprises a source region, a body region, and a drift region.

15. The transistor device according to claim 14, The lower surface of the gate electrode is positioned at a depth dg from the first main surface. The body region forms a pn junction with the drift region at a depth dpn starting from the first main surface, and Depth d pn and depth d g The difference between them is less than d g 8%.

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