NMOS (N-channel metal oxide semiconductor) transistor and preparation method thereof
By using a polysilicon gate electrode doped with P-type impurity ions in conjunction with a P-type well region in an NMOS transistor to form a buried conductive channel, the problem of limited electron mobility is solved, and the speed of the NMOS transistor is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GTA SEMICON CO LTD
- Filing Date
- 2026-02-10
- Publication Date
- 2026-05-19
AI Technical Summary
The electron mobility of existing NMOS transistors is limited, which affects their speed.
By combining a polycrystalline silicon gate electrode doped with P-type impurity ions with a P-type well region, a buried conductive channel is formed inside the substrate. The threshold voltage is adjusted by regulating the distance between the top surface of the shallow trench isolation structure and the top surface of the active region, thus fabricating low-threshold, standard-threshold, and high-threshold NMOS transistors.
This improved the electron mobility and speed of the NMOS transistor, increasing the current speed by approximately 10%-15%.
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Figure CN122069743A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the semiconductor field, and in particular to an NMOS transistor and its fabrication method. Background Technology
[0002] MOS (Metal-Oxide-Semiconductor) transistors are among the most important components in modern integrated circuits. The basic structure of a MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, which includes: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; and source and drain regions located on both sides of the gate structure in the semiconductor substrate.
[0003] MOS transistors include PMOS transistors and NMOS transistors. The gate dielectric layer of existing NMOS transistors is generally made of silicon oxide, and the gate electrode layer is generally made of polycrystalline silicon doped with N-type impurity ions (such as phosphorus ions). When an NMOS transistor is working, the conductive channel is formed on the surface of the substrate, which limits the electron mobility and affects the speed of the NMOS transistor. Summary of the Invention
[0004] Based on this, this application provides an NMOS transistor and a method for fabricating the same, in order to improve electron mobility and thus increase the speed of the NMOS transistor.
[0005] In a first aspect, embodiments of this application provide a method for fabricating an NMOS transistor, comprising:
[0006] A substrate is provided, wherein a plurality of discrete active regions extending along a first direction are provided, a P-type well region is formed within the active regions, and a shallow trench isolation structure is formed between the active regions, wherein the top surface of the shallow trench isolation structure is equal to or lower than the top surface of the active regions.
[0007] A gate oxide dielectric layer is formed on the surface of the active region;
[0008] A polysilicon gate electrode is formed on the gate oxide dielectric layer, spanning several active regions along a second direction. The polysilicon gate electrode is doped with P-type impurity ions, and the second direction is perpendicular to the first direction.
[0009] Source and drain regions are formed in the P-type well regions on both sides of the polysilicon gate electrode.
[0010] In some embodiments of this application, the formation process of the active region and the shallow trench isolation structure includes:
[0011] A patterned mask layer is formed on the substrate;
[0012] Using a patterned mask layer as a mask, the substrate is etched to form several discrete trenches extending along a first direction in the substrate, and the substrate between adjacent trenches is the active region.
[0013] A shallow trench isolation structure is formed by filling the trench with insulating material.
[0014] In some embodiments of this application, when a shallow trench isolation structure is formed by filling the trench with isolation material, the threshold voltage of the NMOS transistor is adjusted by adjusting the distance between the top surface of the shallow trench isolation structure and the top surface of the active region.
[0015] In some embodiments of this application, the distance between the top surface of the shallow trench isolation structure and the top surface of the active region is adjustable from 0 angstroms to 400 angstroms.
[0016] In some embodiments of this application, the width of the active region along the second direction is 40nm~90nm, and the spacing between adjacent active regions along the second direction is 80nm~140nm.
[0017] In some embodiments of this application, the process of forming a polysilicon gate electrode includes:
[0018] A polycrystalline silicon material layer doped with P-type impurity ions is formed on the active region and the shallow trench isolation structure;
[0019] A patterned polycrystalline silicon material layer is used to form a polycrystalline silicon gate electrode.
[0020] In some embodiments of this application, the steps of forming a polycrystalline silicon material layer doped with P-type impurity ions include, in sequence, a first deposition step, an etching step, and a second deposition step.
[0021] In some embodiments of this application, P-type impurity ions are self-doped into the polycrystalline silicon material during the first deposition step and the second deposition step.
[0022] In some embodiments of this application, the P-type impurity ion includes boron ions, and the concentration of the P-type impurity ion is 1 × 10e20 atom / cm³. 3 ~1×10e21atom / cm 3 .
[0023] In some embodiments of this application, the process temperature for performing the first deposition step and the second deposition step is 400°C to 500°C.
[0024] Secondly, embodiments of this application also provide an NMOS transistor, comprising:
[0025] The substrate has several discrete active regions extending along a first direction, a P-type well region is formed in the active region, and a shallow trench isolation structure is formed between the active regions. The top surface of the shallow trench isolation structure is equal to or lower than the top surface of the active region.
[0026] The gate oxide dielectric layer located on the surface of the active region;
[0027] A polysilicon gate electrode located on the gate oxide dielectric layer, spanning several active regions along a second direction, is doped with P-type impurity ions, and the second direction is perpendicular to the first direction.
[0028] The source and drain regions are located in the P-type well region on both sides of the polysilicon gate electrode.
[0029] The embodiments of this application may have, or at least have, the following advantages:
[0030] The method for fabricating an NMOS transistor in this application includes providing a substrate having a plurality of discrete active regions extending along a first direction, a P-type well region formed within the active regions, and a shallow trench isolation structure formed between the active regions, the top surface of the shallow trench isolation structure being equal to or lower than the top surface of the active regions; a gate oxide dielectric layer is formed on the surface of the active regions; a polysilicon gate electrode is formed on the oxide dielectric layer, spanning the plurality of active regions along a second direction, the polysilicon gate electrode being doped with P-type impurity ions, the second direction being perpendicular to the first direction; and source and drain regions are formed in the P-type well regions on both sides of the polysilicon gate electrode. In this application, the polysilicon gate electrode of the NMOS transistor is doped with P-type impurity ions, which is the opposite of the type of impurity ions (N-type impurity ions) doped in the polysilicon gate electrode of a conventional NMOS transistor. This means that when the NMOS transistor is working, a conductive channel (i.e., a buried channel) is formed inside the substrate through the cooperation of the polysilicon gate electrode doped with P-type impurity ions and the P-type well region. The buried conductive channel inside the substrate has a faster electron carrier migration speed than the conductive channel located on the substrate surface, thereby improving the speed of NMOS formation (e.g., current speed).
[0031] Furthermore, in some embodiments, the threshold voltage (VT) of the formed NMOS transistor can be adjusted by adjusting the distance between the top surface of the shallow trench isolation structure and the top surface of the active region, thereby enabling the fabrication of low threshold voltage (SVT) NMOS transistors, standard threshold voltage (SVT) NMOS transistors, and high threshold voltage (VT) NMOS transistors to meet different requirements.
[0032] Furthermore, in some embodiments, the steps of forming a polycrystalline silicon material layer doped with P-type impurity ions sequentially include: performing a first deposition step, performing an etching step, and performing a second deposition step. When the top surface of the shallow trench isolation structure is lower than the top surface of the active region, that is, a second trench is formed on the shallow trench isolation structure between adjacent active regions. The second trench has a smaller width and a higher aspect ratio. By adopting a combination of steps of precipitation (depositing a polycrystalline silicon material layer of a certain thickness), etching (etching away part of the polycrystalline silicon at the opening position of the second trench to prevent the opening of the second trench from closing during deposition and forming void defects), and deposition (depositing another polycrystalline silicon material layer of a certain thickness), the polycrystalline silicon material layer can effectively fill the second trench above the top surface of the shallow trench isolation structure, preventing voids and other defects from being generated in the formed polycrystalline silicon material layer, thereby improving the quality and performance of the formed polycrystalline silicon gate electrode 105.
[0033] Furthermore, in some embodiments, the P-type impurity ion includes boron ions, and the concentration of the P-type impurity ion is 1 × 10e20 atom / cm³. 3 ~1×10e21atom / cm 3 This concentration of doped impurity ions helps to improve the polysilicon depletion effect. The process temperature for the first and second deposition steps is 400°C to 500°C. At this lower deposition temperature, it helps to reduce the grain size of the formed polysilicon material layer, thereby further improving the polysilicon depletion effect.
[0034] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 This application provides a three-dimensional structural diagram of the NMOS transistor after the formation of the active region and shallow trench isolation structure in some embodiments of the present application.
[0037] Figure 2 This application provides a schematic diagram of the three-dimensional structure of an NMOS transistor after the formation of a polycrystalline silicon material layer in some embodiments of the present application.
[0038] Figure 3 for Figure 2 A schematic diagram of the cross-sectional structure along the cutting line AB;
[0039] Figure 4 This is a schematic diagram of the structure after forming a polysilicon gate electrode in a method for fabricating an NMOS transistor according to some embodiments of this application;
[0040] Figure 5 A three-dimensional structural schematic diagram of a method for fabricating an NMOS transistor according to some embodiments of this application, wherein the distance between the top surface of the shallow trench isolation structure and the top surface of the active region is different;
[0041] Figure 6 A three-dimensional structural schematic diagram of a high threshold voltage (HVT) NMOS transistor formed in a fabrication method of an NMOS transistor provided in some embodiments of this application;
[0042] Figure 7 A comparison of the IV characteristics of an NMOS transistor fabricated using the method of this application with those of an existing NMOS transistor.
[0043] Explanation of reference numerals in the attached figures:
[0044] Substrate 100; Active region 101; Shallow trench isolation structure 102; Gate oxide dielectric layer 103; Polysilicon material layer 104; Polysilicon gate electrode 105; Trench 106. Detailed Implementation
[0045] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0046] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0047] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.
[0048] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0049] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0050] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.
[0051] This application first provides a method for fabricating an NMOS transistor. Figures 1-6The accompanying drawings are schematic diagrams illustrating the various stages of a method for fabricating an NMOS transistor according to some embodiments of this application. The fabrication method for the NMOS transistor will now be described in detail with reference to the accompanying drawings.
[0052] refer to Figure 1 A substrate 100 is provided, wherein the substrate 100 has a plurality of discrete active regions 101 extending along a first direction D1, a P-type well region (not shown) is formed in the active regions 101, and a shallow trench isolation structure 102 is formed between the active regions 101, wherein the top surface of the shallow trench isolation structure 102 is equal to or lower than the top surface of the active regions 101.
[0053] The substrate 100 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 100 may be a layered substrate comprising Si / SiGe, Si / SiC, silicon-on-insulator (SOI), germanium-on-insulator (SOI), or silicon-germanium-on-insulator.
[0054] A plurality of discrete active regions 101 extending along a first direction D1 are formed within the substrate 100, and adjacent active regions 101 are isolated by a shallow trench isolation structure 102. A P-type well region of an NMOS transistor is formed within the active region 101, and the source and drain regions of the NMOS transistor can subsequently be formed within the P-type well region.
[0055] P-type well regions can be formed through ion implantation. Specifically, ion implantation is used to implant P-type impurity ions into the active region 101 to form a P-type well region. In one example, the P-type impurity ions include one or more of boron ions, aluminum ions, gallium ions, or indium ions.
[0056] In some embodiments, each active region 101 may subsequently form a plurality of NMOS transistors arranged along a first direction.
[0057] In some embodiments, the width of the active region 101 along the second direction D2 is 40nm to 90nm, and the spacing between adjacent active regions 101 along the second direction D2 is 80nm to 140nm (or the width of the trench 106 along the second direction D2 is 80nm to 140nm).
[0058] The top surface of the formed shallow trench isolation structure 102 can be flush with the top surface of the active region 101, or the top surface of the formed shallow trench isolation structure 102 can be lower than the top surface of the active region 101. In this application, the threshold voltage (VT) of the formed NMOS transistor is adjusted by adjusting the distance H between the top surface of the formed shallow trench isolation structure 102 and the top surface of the active region 101. Specifically, the smaller the distance H between the top surface of the shallow trench isolation structure 102 and the top surface of the active region 101, the larger the threshold voltage of the formed NMOS transistor; conversely, the larger the distance H between the top surface of the shallow trench isolation structure 102 and the top surface of the active region 101, the smaller the threshold voltage of the formed NMOS transistor.
[0059] By adjusting the distance H between the top surface of the shallow trench isolation structure 102 and the top surface of the active region 101, the subsequently formed NMOS transistors can include low threshold voltage (SVT) NMOS transistors (such as...). Figure 4 As shown), standard threshold voltage (SVT) NMOS transistors (such as...) Figure 5 (as shown) and high threshold voltage (HVT) NMOS transistors (such as Figure 6 As shown in the figure, the distance H between the top surface of the shallow trench isolation structure 102 and the top surface of the active region 101 in the low threshold voltage (SVT) NMOS transistor is greater than the distance H between the top surface of the shallow trench isolation structure 102 and the top surface of the active region 101 in the standard threshold voltage (SVT) NMOS transistor. The distance H between the top surface of the shallow trench isolation structure 102 and the top surface of the active region 101 in the standard threshold voltage (SVT) NMOS transistor is greater than the distance H between the top surface of the shallow trench isolation structure 102 and the top surface of the active region 101 in the high threshold voltage (HVT) NMOS transistor. Correspondingly, the threshold voltage of the low threshold voltage (SVT) NMOS transistor is less than the threshold voltage of the standard threshold voltage (SVT) NMOS transistor, and the threshold voltage of the standard threshold voltage (SVT) NMOS transistor is less than the threshold voltage of the high threshold voltage (HVT) NMOS transistor.
[0060] In one specific embodiment, the distance H between the top surface of the shallow trench isolation structure 102 and the top surface of the active region 101 is adjustable in the range of 0 angstroms to 400 angstroms. Specifically, in a low threshold voltage (SVT) NMOS transistor, the distance H between the top surface of the shallow trench isolation structure 102 and the top surface of the active region 101 is greater than 0 angstroms and less than or equal to 400 angstroms; in a standard threshold voltage (SVT) NMOS transistor, the distance H between the top surface of the shallow trench isolation structure 102 and the top surface of the active region 101 is greater than 0 angstroms and less than or equal to 300 angstroms; and in a standard threshold voltage (SVT) NMOS transistor, the distance H between the top surface of the shallow trench isolation structure 102 and the top surface of the active region 101 is greater than or equal to 0 angstroms and less than or equal to 100 angstroms.
[0061] In one specific embodiment, when the supply voltage of the NMOS transistor is 0.9V, the threshold voltage range of the low threshold voltage (SVT) NMOS transistor is 0.15V-0.35V, the threshold voltage range of the standard threshold voltage (SVT) NMOS transistor is 0.3V-0.45V, and the threshold voltage range of the high threshold voltage (HVT) NMOS transistor is 0.38V-0.55V.
[0062] In some embodiments, the formation process of the active region 101 and the shallow trench isolation structure 102 includes:
[0063] A patterned mask layer (not shown in the figure) is formed on the substrate 100. The patterned mask layer can be a single layer or a multi-layer stacked structure. The material of the patterned mask layer can include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. In one example, the formation process of the patterned mask layer includes: forming a mask material layer on the substrate; forming a photoresist layer on the mask material layer; exposing and developing the photoresist layer to pattern the photoresist layer; and etching the mask layer using the patterned photoresist layer as a mask to form the patterned mask layer.
[0064] Using a patterned mask layer as a mask, the substrate 100 is etched to form a plurality of discrete trenches 106 extending along the first direction D1 in the substrate 100. The substrate 100 between adjacent trenches 106 is an active region 101. In the example, the etching of the substrate 100 can be carried out using an anisotropic dry etching process, such as anisotropic plasma etching process.
[0065] A shallow trench isolation structure 102 is formed by filling the trench 106 with an isolation material. The trench 106 can be filled with a single layer or multiple layers of isolation material. The isolation material can include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. In one example, the formation process of the shallow trench isolation structure 102 includes: forming an isolation material layer that fills the trench 106 and covers the top surface of the active region 101; planarizing the isolation material layer using a chemical mechanical masking process until the top surface of the active region 101 is exposed, forming the shallow trench isolation structure 102. The top surface of the shallow trench isolation structure 102 is flush with the top surface of the active region 101. In another example, when the top surface of the shallow trench isolation structure 102 to be formed is lower than the top surface of the active region 101 (e.g., ... Figure 1 As shown), for the planarization of the chemical mechanical mask process, an etching process is also required to remove part of the thickness of the shallow trench isolation structure 102, so that the top surface of the remaining shallow trench isolation structure 102 is lower than the top surface of the source region 101.
[0066] Continue to refer to Figure 1 After forming the shallow trench isolation structure 102, a gate oxide dielectric layer 103 is formed on the surface of the active region 101.
[0067] The gate oxide dielectric layer 103 is made of silicon oxide, and the process for forming the gate oxide dielectric layer 103 includes a thermal oxidation process.
[0068] Next, refer to Figures 2-4 A polysilicon gate electrode 105 is formed on the gate oxide dielectric layer 103, spanning several active regions 101 along the second direction D2. Figure 4 As shown, the polysilicon gate electrode 105 is doped with P-type impurity ions, and the second direction D2 is perpendicular to the first direction D1.
[0069] In this application, the polysilicon gate electrode 105 of the NMOS transistor is doped with P-type impurity ions, which is the opposite of the type of impurity ions (N-type impurity ions) doped in the polysilicon gate electrode of a conventional NMOS transistor. This means that when the NMOS transistor is working, a conductive channel (i.e., a buried conductive channel) is formed inside the substrate 100 through the cooperation of the polysilicon gate electrode 105 doped with P-type impurity ions and the P-type well region. The buried conductive channel inside the substrate 100 has a faster electron carrier migration speed than the conductive channel located on the substrate surface, thereby improving the speed of NMOS formation (e.g., current speed).
[0070] In some embodiments, the process of forming the polysilicon gate electrode 105 includes:
[0071] refer to Figure 2 and Figure 3 , Figure 3for Figure 2 A cross-sectional view along the cutting line AB shows a polycrystalline silicon material layer 104 doped with P-type impurity ions formed on the active region 101 and the shallow trench isolation structure 102.
[0072] refer to Figure 4 A patterned polycrystalline silicon material layer 104 is formed to create a polycrystalline silicon gate electrode 105.
[0073] In some embodiments, the step of forming a polycrystalline silicon material layer 104 doped with P-type impurity ions includes, in sequence, a first deposition step, an etching step, and a second deposition step. When the top surface of the shallow trench isolation structure 102 is lower than the top surface of the active region 101, that is, a second trench is formed on the shallow trench isolation structure 102 between adjacent active regions 101. The second trench has a smaller width and a higher aspect ratio. By employing a combination of steps including deposition (depositing a polycrystalline silicon material layer of a certain thickness), etching (etching away part of the polycrystalline silicon at the opening position of the second trench to prevent the opening of the second trench from closing during deposition and forming void defects), and deposition (re-depositing a polycrystalline silicon material layer of a certain thickness), the polycrystalline silicon material layer can effectively fill the second trench above the top surface of the shallow trench isolation structure 102, preventing void defects from being generated in the formed polycrystalline silicon material layer 104, thereby improving the quality and performance of the formed polycrystalline silicon gate electrode 105.
[0074] In some embodiments, self-doping of P-type impurity ions in the polycrystalline silicon material during the first deposition step and the second deposition step can improve the uniformity of the distribution of doped P-type impurity ions in the formed polycrystalline silicon material layer 104, which is beneficial to improving the polycrystalline silicon depletion effect caused by the uneven distribution of impurity ions in the polycrystalline silicon material layer 104, and further improving the speed of NMOS transistors.
[0075] In some embodiments, the P-type impurity ion includes boron ions, and the concentration of the P-type impurity ion is 1 × 10⁻²⁰ atom / cm³. 3 ~1×10e21atom / cm 3 This concentration of doped impurity ions is beneficial for improving the polydepletion effect of polycrystalline silicon.
[0076] In some embodiments, the process temperature for performing the first deposition step and the second deposition step is 400°C to 500°C. At this lower deposition temperature, it helps to reduce the grain size of the formed polycrystalline silicon material layer 104, thereby further improving the polycrystalline silicon depletion effect.
[0077] The number of polysilicon gate electrodes 105 formed can be one or more. A polysilicon gate electrode 105 can span one or more active regions 101 along the second direction D2.
[0078] Finally, continue to refer to Figure 4 Source and drain regions (not shown in the figure) are formed in the P-type well regions on both sides of the polysilicon gate electrode 105.
[0079] The source and drain regions are formed using an ion implantation process. Specifically, N-type impurity ions are implanted into the P-type well regions on both sides of the polysilicon gate electrode 105 to form the source and drain regions. In one example, the N-type impurity ions include one or more of nitrogen ions, phosphorus ions, arsenic ions, or antimony ions.
[0080] This application also provides an NMOS transistor, see reference. Figure 4 ,include:
[0081] The substrate 100 has a plurality of discrete active regions 101 extending along a first direction. A P-type well region is formed in the active region 101. A shallow trench isolation structure 102 is formed between the active regions 101. The top surface of the shallow trench isolation structure 102 is equal to or lower than the top surface of the active region 101.
[0082] A gate oxide dielectric layer 103 is located on the surface of the active region 101;
[0083] A polysilicon gate electrode 105 is located on the gate oxide dielectric layer 103 and spans several active regions 101 along a second direction. The polysilicon gate electrode 105 is doped with P-type impurity ions, and the second direction is perpendicular to the first direction.
[0084] The source and drain regions are located in the P-type well region on both sides of the polysilicon gate electrode 105.
[0085] refer to Figure 7 , Figure 7 A comparison diagram of the IV characteristics of an NMOS transistor fabricated using the method of this application and existing NMOS transistors, wherein... Figure 7 In the diagram, the horizontal axis represents voltage (V), and the vertical axis represents current (I). Different colored triangles represent low threshold voltage (SVT) NMOS transistors, standard threshold voltage (SVT) NMOS transistors, and high threshold voltage (HVT) NMOS transistors fabricated using the method described in this application, respectively. Different colored circles represent existing low threshold voltage (SVT) NMOS transistors, standard threshold voltage (SVT) NMOS transistors, and high threshold voltage (HVT) NMOS transistors, respectively. Figure 7It can be clearly seen that the NMOS transistors prepared by the method of this application have significantly better IV characteristics than existing NMOS transistors. The NMOS transistors prepared by the method of this application have a faster speed (e.g., current speed). Specifically, the speed of the NMOS transistors prepared by the method of this application can be increased by about 10%-15%.
[0086] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0088] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for fabricating an NMOS transistor, characterized in that, include: A substrate is provided having a plurality of discrete active regions extending along a first direction, wherein a P-type well region is formed within the active regions, and a shallow trench isolation structure is formed between the active regions, wherein the top surface of the shallow trench isolation structure is equal to or lower than the top surface of the active regions. A gate oxide dielectric layer is formed on the surface of the active region; A polysilicon gate electrode is formed on the gate oxide dielectric layer, spanning a plurality of the active regions along a second direction. The polysilicon gate electrode is doped with P-type impurity ions, and the second direction is perpendicular to the first direction. Source and drain regions are formed in the P-type well regions on both sides of the polysilicon gate electrode.
2. The method for fabricating an NMOS transistor according to claim 1, characterized in that, The formation process of the active region and the shallow trench isolation structure includes: A patterned mask layer is formed on the substrate; Using the patterned mask layer as a mask, the substrate is etched to form a plurality of discrete trenches extending along a first direction in the substrate, and the substrate between adjacent trenches is the active region. The shallow trench isolation structure is formed by filling the trench with an insulating material.
3. The method for fabricating an NMOS transistor according to claim 2, characterized in that, When the shallow trench isolation structure is formed by filling the trench with isolation material, the threshold voltage of the NMOS transistor is adjusted by adjusting the distance between the top surface of the shallow trench isolation structure and the top surface of the active region.
4. The method for fabricating an NMOS transistor according to claim 3, characterized in that, The distance between the top surface of the shallow trench isolation structure and the top surface of the active area can be adjusted from 0 angstroms to 400 angstroms.
5. The method for fabricating an NMOS transistor according to claim 1 or 2, characterized in that, The width of the active region along the second direction is 40nm~90nm, and the spacing between adjacent active regions along the second direction is 80nm~140nm.
6. The method for fabricating an NMOS transistor according to claim 5, characterized in that, The process of forming the polysilicon gate electrode includes: A polycrystalline silicon material layer doped with P-type impurity ions is formed on the active region and the shallow trench isolation structure. The polycrystalline silicon material layer is patterned to form the polycrystalline silicon gate electrode.
7. The method for fabricating an NMOS transistor according to claim 6, characterized in that, The steps for forming the polycrystalline silicon material layer doped with P-type impurity ions include, in sequence, a first deposition step, an etching step, and a second deposition step.
8. The method for fabricating an NMOS transistor according to claim 7, characterized in that, During the first and second deposition steps, P-type impurity ions are self-doped into the polycrystalline silicon material.
9. The method for fabricating an NMOS transistor according to claim 8, characterized in that, The P-type impurity ion includes boron ions, and the concentration of the P-type impurity ion is 1 × 10⁻²⁰ atom / cm³. 3 ~1×10e21atom / cm 3 The process temperature for the first and second deposition steps is 400℃~500℃.
10. An NMOS transistor, characterized in that, include: A substrate having a plurality of discrete active regions extending along a first direction, wherein a P-type well region is formed within the active regions, and a shallow trench isolation structure is formed between the active regions, wherein the top surface of the shallow trench isolation structure is equal to or lower than the top surface of the active regions. A gate oxide dielectric layer located on the surface of the active region; A polysilicon gate electrode located on the gate oxide dielectric layer and spanning several active regions along a second direction, wherein the polysilicon gate electrode is doped with P-type impurity ions, and the second direction is perpendicular to the first direction; The source and drain regions are located in the P-type well regions on both sides of the polysilicon gate electrode.