Semiconductor structure and preparation method thereof
By setting isolation structures on the substrate layer, including grooves and insulating material-filled or ion-doped regions, the problem of vertical breakdown between the substrate and buffer layer in gallium nitride bidirectional power devices under high voltage is solved, and the stability and reliability of the device's high-frequency, low-noise and high-power performance are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ENKRIS SEMICON
- Filing Date
- 2026-04-17
- Publication Date
- 2026-05-19
AI Technical Summary
Gallium nitride bidirectional power devices are prone to vertical breakdown between the substrate and the buffer layer under high voltage, leading to device failure.
An isolation structure is set on the substrate layer, including grooves and regions filled with insulating material or ion-doped regions, to form a dual physical and electrical isolation, blocking the longitudinal leakage path and preventing the buffer layer from breaking down vertically.
It effectively blocks longitudinal leakage current channels under high voltage, prevents buffer layer breakdown, maintains the high-frequency and high-power performance of the device, and improves the long-term stability and reliability of the device.
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Figure CN122069747A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its preparation method. Background Technology
[0002] Gallium nitride (GaN) bidirectional power devices possess advantages such as high frequency, low noise, and high power, and are widely used in radio frequency, microwave, and millimeter-wave fields. However, under off-state conditions, a strong electric field is generated between the source and drain of GaN bidirectional power devices. Due to the superposition of electric fields between the two gates, an electric field concentration region is formed in the entire device. The corresponding substrate layer and buffer layer in this region are prone to forming a longitudinal leakage channel under the induction of the strong electric field, which can lead to vertical breakdown of the buffer layer. Summary of the Invention
[0003] The present invention provides a semiconductor structure and its fabrication method, which at least solves the problem in the related art that gallium nitride bidirectional power devices are easily vertically broken down between the substrate and the buffer layer under high voltage.
[0004] This invention provides a semiconductor structure comprising: a substrate layer, a buffer layer, and a functional layer stacked together; a source and a drain are disposed on the functional layer, and a plurality of gates are located between the source and the drain, wherein a target region is defined between the plurality of gates; an isolation structure is disposed on the substrate layer corresponding to the target region, wherein the projection of the target region on the substrate layer and the projection of the isolation structure on the substrate layer at least partially overlap.
[0005] The present invention also provides a method for fabricating a semiconductor structure, comprising: providing a first intermediate structure, the first intermediate structure comprising a substrate layer, a buffer layer and a functional layer stacked thereon; a source electrode and a drain electrode are disposed on the functional layer, and a plurality of gate electrodes are located between the source electrode and the drain electrode, the plurality of gate electrodes being configured as a target region; and an isolation structure is disposed on the substrate layer corresponding to the target region, wherein the projection of the target region on the substrate layer and the projection of the isolation structure on the substrate layer at least partially overlap.
[0006] The semiconductor structure provided by the present invention, by setting an isolation structure, blocks the longitudinal leakage channel under high voltage, prevents the buffer layer from undergoing vertical breakdown, and can avoid interfering with the lateral conductivity and multi-gate control of the functional layer. This solves the problem in related technologies where gallium nitride bidirectional power devices are easily vertically broken down between the substrate and the buffer layer under high voltage. Attached Figure Description
[0007] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the embodiments will be briefly introduced below.
[0008] Figure 1 This is a schematic diagram of a semiconductor structure in an embodiment of the present invention.
[0009] Figure 2 This is a schematic diagram of another semiconductor structure in an embodiment of the present invention.
[0010] Figure 3 This is a schematic diagram of another semiconductor structure in an embodiment of the present invention.
[0011] Figure 4 This is a schematic diagram of another semiconductor structure in an embodiment of the present invention.
[0012] Figure 5 This is a schematic diagram of another semiconductor structure in an embodiment of the present invention.
[0013] Figure 6 This is a schematic diagram of a semiconductor structure having multiple protruding structures and multiple isolation structures in an embodiment of the present invention.
[0014] Figure 7 This is a flowchart of a method for preparing a semiconductor structure according to an embodiment of the present invention.
[0015] The attached figures are labeled as follows.
[0016] 1. Substrate layer; 11. Isolation structure; 111. Trench; 112. Insulating material; 113. Thermally oxidized region; 2. Buffer layer; 3. Functional layer; 31. Channel layer; 32. Barrier layer; 4. Source; 5. Drain; 6. Gate; 61. First gate; 62. Second gate; 71. First p-type layer; 72. Second p-type layer; 711. First protrusion structure; 721. Second protrusion structure; 8. Insulating dielectric layer; 9. Ion-doped region; 10. Target region. Detailed Implementation
[0017] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.
[0018] Gallium nitride (GaN) bidirectional power devices are bidirectional power devices based on the high electron mobility transistor (HEMT) structure, using gallium nitride (GaN) as the core third-generation semiconductor material. They possess the advantages of high frequency, low noise, and high power, and are widely used in radio frequency, microwave, and millimeter-wave fields.
[0019] Gallium nitride bidirectional power devices have a symmetrical structure where the source and drain are interchangeable.
[0020] In forward conduction mode, the source is used as the positive terminal and the drain as the negative terminal, and a forward bias voltage is applied to the dual gate relative to the source. This forward bias voltage is coupled to the heterojunction interface between the channel layer and the barrier layer through a Schottky contact, maintaining the stable existence of the two-dimensional electron gas at the interface and forming a lateral conductive channel connecting the source, the target region between the dual gates, and the drain. The two-dimensional electron gas migrates directionally under the drive of the electric field between the source and the drain, forming the forward conduction current.
[0021] In reverse conduction mode, the drain is switched to the positive terminal as the new source and the source is switched to the negative terminal as the new drain, applying a forward bias voltage relative to the drain to the dual gates. The bias control logic is the same as in forward conduction mode, maintaining the continuous distribution of the two-dimensional electron gas at the heterojunction interface, forming a reverse conductive channel connecting the drain, the target region between the dual gates, and the source, thus achieving stable reverse current conduction.
[0022] During turn-off, a reverse bias voltage or zero bias voltage is applied to the dual gates, completely depleting the two-dimensional electron gas at the heterojunction interface. The previously continuous lateral conductive channel disappears, and both forward and reverse currents are turned off. At this time, the high voltage between the source and drain will form a strong electric field inside the device. Due to the superposition effect of the electric fields of multiple gates, a concentrated peak region of electric field will be formed in the target area, which will then form a vertical leakage channel between the substrate and the buffer layer, causing the buffer layer to be vertically broken down.
[0023] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention, as shown below. Figure 1 As shown, an embodiment of the present invention provides a semiconductor structure, including: a substrate layer 1, a buffer layer 2, and a functional layer 3 stacked together; a source electrode 4 and a drain electrode 5 are disposed on the functional layer 3, and a plurality of gate electrodes 6 are located between the source electrode 4 and the drain electrode 5, and a target region 10 is disposed between the plurality of gate electrodes 6; an isolation structure 11 is disposed on the substrate layer 1 corresponding to the target region 10, and the projection of the target region 10 on the substrate layer 1 and the projection of the isolation structure 11 on the substrate layer 1 at least partially overlap.
[0024] Substrate 1 serves as the physical support substrate. Buffer layer 2 is used to alleviate the lattice mismatch between substrate 1 and functional layer 3, while also preventing unintentional doping from substrate 1 into functional layer 3. Functional layer 3 adopts a bilayer composite structure of channel layer 31 and barrier layer 32. Due to spontaneous / piezoelectric polarization effect, a high-density, high-mobility two-dimensional electron gas (2DEG) is generated at the interface between channel layer 31 and barrier layer 32, which serves as the charge carrier for lateral conduction between source 4 and drain 5.
[0025] The surface of the functional layer 3 away from the substrate layer 1 provides contact sites for the source 4, drain 5, and multiple gates 6. Ohmic contacts can be formed between the source 4, drain 5 and the functional layer 3, which is beneficial for the transport of two-dimensional electron gas. Schottky contacts can be formed between the gates 6 and the functional layer 3, which is beneficial for voltage regulation of the two-dimensional electron gas.
[0026] In this embodiment, to specifically block longitudinal leakage under high voltage, prevent vertical breakdown of the buffer layer 2, and avoid interfering with the lateral conductivity and multi-gate control of the functional layer 3, an isolation structure 11 is provided on the substrate layer 1 corresponding to the target region 10. It is required that the projection of the target region 10 onto the substrate layer 1 and the projection of the isolation structure 11 onto the substrate layer 1 at least partially overlap. This forms physical isolation in the substrate layer 1, blocking the longitudinal physical contact and conductive path between the substrate layer 1 and the buffer layer 2 corresponding to the target region 10.
[0027] In summary, this embodiment provides an isolation structure 11 on the substrate layer 1 corresponding to the target region 10, so that when the device is turned off and subjected to high voltage, even if a strong longitudinal electric field is formed in the target region 10, the charge carriers cannot migrate from the substrate layer 1 to the buffer layer 2 to form an effective leakage channel. This solves the problem in related technologies where gallium nitride bidirectional power devices are easily vertically broken down between the substrate and the buffer layer under high voltage.
[0028] This embodiment provides an optional solution, such as Figure 1 As shown, the isolation structure 11 is a groove 111, which penetrates the substrate layer 1.
[0029] By setting a groove 111 that penetrates the substrate layer 1 as an isolation structure 11, the formation of a longitudinal leakage current channel between the substrate layer 1 and the buffer layer 2 under high voltage is blocked at the physical level, thereby preventing the buffer layer 2 from undergoing vertical breakdown due to longitudinal leakage current.
[0030] The dimension of the groove 111 in the first direction is greater than or equal to the distance between adjacent gate electrodes. The first direction is the direction from the source 4 to the drain 5. In high-voltage applications, the dimension of the groove 111 in the first direction is on the order of micrometers, for example, 1-5 μm.
[0031] because Figure 1 The semiconductor structure shown has a first p-type layer 71 and a second p-type layer 72. A first gate 61 is disposed on the first p-type layer 71, and a second gate 62 is disposed on the second p-type layer 72. The target region between the first gate 61 and the second gate 62 is specifically the target region between the first p-type layer 71 and the second p-type layer 72. The dimension of the groove 111 in the first direction only needs to be greater than or equal to the distance between the first p-type layer 71 and the second p-type layer 72. This embodiment provides an optional solution. Figure 2 This is a schematic diagram of another semiconductor structure in an embodiment of the present invention, such as... Figure 2As shown, the groove 111 is filled with insulating material 112.
[0032] The groove 111 serves as a physical spatial barrier, acting as an isolation structure 11. It breaks the longitudinal physical conductive path between the substrate layer 1 and the buffer layer 2 in the corresponding target region 10, thus achieving leakage resistance interruption. However, the space provided by the groove 111 itself has pseudo-insulating properties. After filling with insulating material 112, a dual protective barrier of physical spatial isolation and insulating medium barrier is formed, which can further enhance the leakage resistance interruption effect and improve the longitudinal withstand voltage level of the device.
[0033] Secondly, the insulating material 112 filling the groove 111 can prevent impurities from intruding into the buffer layer 2 or even the functional layer 3, which helps protect the heterojunction and ensures that the core performance of the device, such as high frequency and low on-resistance, does not degrade. At the same time, the insulating material 112 can mechanically strengthen the substrate layer 1 after the groove 111 is formed, reduce the risk of stress cracking, and help improve the fabrication yield and long-term structural stability of the device.
[0034] As an alternative, the insulating material 112 includes at least one of the following: silicon dioxide, silicon nitride.
[0035] Silicon dioxide (SiO2) has a resistivity of 100% at room temperature. With a breakdown field strength exceeding 10 MV / cm, far surpassing that of gallium nitride, it achieves absolute leakage resistance at the purely electrical level. Combined with the physical isolation of the groove 111, this dual protection significantly reduces the longitudinal leakage current in the target region 10. Simultaneously, silicon dioxide has an extremely low dielectric constant (approximately 3.9), preventing the introduction of additional electric field polarization in the groove 111 region. This avoids interference with the lateral electric field distribution in the target region 10, ensuring the normal regulation of the two-dimensional electron gas in functional layer 3.
[0036] Silicon nitride (Si3N4) is an atomically dense amorphous thin film with far superior resistance to water vapor and metal impurities compared to silicon dioxide. After filling, it seals the groove 111 into a vacuum protective cavity, preventing external contaminants from penetrating from the groove 111 to the interface between the buffer layer 2 and the functional layer 3. This avoids a decrease in the two-dimensional electron gas mobility due to impurity scattering, thus ensuring that the device's high-frequency performance does not degrade. Simultaneously, the dense silicon nitride film effectively wraps around the edges of the groove 111, preventing microcracks in the substrate layer 1 caused by the groove 111 from propagating under high pressure or thermal stress, thereby improving the mechanical stability of the device.
[0037] As an alternative, the groove 111 is partially filled with insulating material 112, which may be located on the side of the groove 111 near the buffer layer 2. Alternatively, the insulating material 112 is filled in the groove 111 with a porous morphology, in which case it can be regarded as the insulating material 112 and the voids filling the groove 111 as a whole.
[0038] This embodiment provides an optional solution. Figure 3 This is a schematic diagram of another semiconductor structure in an embodiment of the present invention, such as... Figure 3 As shown, the region near the groove 111 in the buffer layer 2 is set as the ion-doped region 9. The projection of the groove 111 on the substrate layer 1 and the projection of the ion-doped region 9 on the substrate layer 1 overlap at least partially. The doping type of the ion-doped region 9 is different from the doping type of the buffer layer 2.
[0039] The region near the groove 111 in the buffer layer 2 is set as the ion-doped region 9, and the doping type of the ion-doped region 9 is different from that of the buffer layer 2. Based on the use of the groove 111 as a physical spatial barrier, electrical isolation is introduced to form a dual isolation barrier of physical and electrical, while realizing the homogenization of the local electric field of the buffer layer 2.
[0040] As an alternative, the projection of the ion-doped region 9 onto the substrate 1 covers the projection of the groove 111 onto the substrate 1. Optionally, the projected area of the ion-doped region 9 onto the substrate 1 is larger than the projected area of the groove 111 onto the substrate 1.
[0041] As an alternative, the buffer layer 2 is doped with n-type, and the ion-doped region 9 is doped with p-type. The buffer layer 2 and the ion-doped region 9 form a pn junction. When the device is turned off and subjected to high voltage, the strong longitudinal electric field between the source 4 and the drain 5 will cause the pn junction to be in a reverse bias state, thereby forming a wide and dense space charge depletion region in the buffer layer 2 near the groove 111, which can completely deplete the free carriers in this region. This electrically blocks the longitudinal leakage path inside the buffer layer, achieving dual isolation of physical path interruption in the groove 111 and electrical carrier depletion in the depletion region.
[0042] As an alternative, the material of the ion-doped region 9 includes at least one of the following: p-type aluminum gallium nitride, p-type gallium nitride.
[0043] The ion-doped region 9 of p-type gallium nitride (p-GaN) is made of the same material as the buffer layer of n-type gallium nitride (n-GaN), which improves the lattice mismatch problem. The space charge depletion region formed under reverse bias is continuous and uniform, which can avoid carrier leakage caused by interface defects and improve the long-term stability of the device under high voltage operation.
[0044] The ion-doped region 9, employing p-type aluminum gallium nitride (p-AlGaN), exhibits a significant spontaneous polarization effect due to the strong electronegativity of the Al-N bond. Furthermore, the lattice matching difference with buffer layer 2 induces piezoelectric polarization. The superposition of these two polarization effects generates a large amount of polarization-fixed charge at the pn junction interface, enhancing the space charge region of the pn junction. Compared to p-type gallium nitride, p-type aluminum gallium nitride does not require high-concentration ion doping to form a wider and denser depletion region, avoiding the intensified carrier scattering caused by high doping and reducing the risk of dopant atom diffusion.
[0045] As an optional solution, in Figure 3 Based on the structure shown, insulating material is filled into the groove 111 to further enhance the leakage resistance and improve the longitudinal withstand voltage rating of the device.
[0046] This embodiment provides an optional solution. Figure 4 This is a schematic diagram of another semiconductor structure in an embodiment of the present invention, such as... Figure 4 As shown, the portion of the substrate layer 1 corresponding to the target region 10 is set as a thermal oxidation region 113. The thermal oxidation region 113 penetrates the substrate layer 1 as an isolation structure 11. The thickness h of the substrate layer 1 is less than or equal to 1 micrometer.
[0047] The thickness h of the substrate layer 1 is set to be less than or equal to 1 micrometer, which can ensure that the thermally oxidized region 113 obtained by thermal oxidation penetrates the substrate layer 1.
[0048] By thermally oxidizing the bulk material of the target region 10 of the substrate layer 1 in situ into an insulating oxide to form a thermally oxidized region 113, the longitudinal leakage channel can be blocked on the one hand, and external impurities and moisture can be prevented from penetrating from the substrate layer 1 to the buffer layer 2 and the functional layer 3 on the other hand, thus ensuring the long-term stability of the longitudinal isolation effect.
[0049] Furthermore, the portion of the substrate layer 1 corresponding to the target region 10, and the portion of the buffer layer 2 corresponding to the target region 10 and adjacent to the substrate layer 1, are both set as thermally oxidized regions.
[0050] The portion of the buffer layer 2 corresponding to the target region 10 and adjacent to the substrate layer 1 can be thermally oxidized together with the portion of the substrate layer 1 corresponding to the target region 10. This enhances the blocking effect on the longitudinal leakage current channel.
[0051] For example, such as Figures 1 to 4 As shown, in a bidirectional power device, there are two gates 6, namely a first gate 61 and a second gate 62, and the target region 10 is set between the first gate 61 and the second gate 62. A first p-type layer 71 and a second p-type layer 72 are disposed on the functional layer 3. The first gate 61 is disposed on the first p-type layer 71, and the second gate 62 is disposed on the second p-type layer 72.
[0052] The first p-type layer 71 and the second p-type layer 72 deplete the two-dimensional electron gas located at the heterojunction below, putting the device in a turn-off state at zero gate voltage and achieving an enhancement-mode operation. Compared to traditional depletion-mode devices, this avoids leakage current caused by zero-bias conduction during bidirectional turn-off, improving the blocking reliability of the device during high-voltage turn-off.
[0053] This embodiment provides an optional solution. Figure 5 This is a schematic diagram of another semiconductor structure in an embodiment of the present invention, such as... Figure 5 As shown, a first protruding structure 711 is provided on the side of the first p-type layer 71 near the second p-type layer 72, and a second protruding structure 721 is provided on the side of the second p-type layer 72 near the first p-type layer 71. A target region 10 is formed between the first protruding structure 711 and the second protruding structure 721.
[0054] There may be one first protruding structure 711 and one second protruding structure 721, or there may be multiple first protruding structures 711 and multiple second protruding structures 721.
[0055] By providing the first protruding structure 711 and the second protruding structure 721, the contact area between the edge of the first gate 61 and the second gate 62 near the target region 10 and the functional layer 3 is covered, which can disperse the peak surface electric field of the target region 10 and reduce the electric field intensity on the side of the first gate 61 and the second gate 62 near the target region 10. This, combined with the groove 111 penetrating the substrate layer 1, forms a synergistic protection on the surface and vertically.
[0056] As an alternative, there are multiple first protruding structures 711 and multiple isolation structures 11. The projection of the gap between two adjacent first protruding structures 711 onto the substrate layer 1 overlaps with the projection of at least one isolation structure 11 onto the substrate layer 1.
[0057] Figure 6 This is a schematic diagram of a semiconductor structure with multiple protruding structures and multiple isolation structures in an embodiment of the present invention, such as... Figure 6 As shown, there are multiple first protruding structures 711 and second protruding structures 721, and multiple grooves 111 serving as isolation structures 11. The projection of the target region 10 onto the substrate layer 1 and the projections of the multiple grooves 111 onto the substrate layer 1 overlap.
[0058] Multiple first protruding structures 711 and second protruding structures 721 extend toward the target region 10 to form a multi-level RESURF structure. Compared with the single-level RESURF structure formed when there is only one first protruding structure 711 and one second protruding structure 721, it can achieve gradient electric field dispersion from the edges of the first gate 61 and the second gate 62 to the target region 10.
[0059] The gaps between adjacent first protruding structures 711 and between adjacent second protruding structures 721 easily form secondary electric field concentration areas, and the target region 10 may include multiple secondary electric field concentration areas. Compared to setting only one groove 111 or setting multiple grooves 111 but not corresponding one-to-one with each secondary electric field concentration area, setting each groove 111 for each secondary electric field concentration area can more accurately isolate the longitudinal leakage current path. Of course, setting only one groove 111, or setting multiple grooves 111 but not corresponding one-to-one with each secondary electric field concentration area, can achieve a certain isolation effect while reducing the difficulty of the manufacturing process.
[0060] As an alternative, such as Figures 1 to 5 As shown, the functional layer 3 includes a channel layer 31 and a barrier layer 32 sequentially stacked on the buffer layer 2. The source electrode 4 and drain electrode 5 are disposed at least on the channel layer 31, allowing direct contact between the electrodes and the channel layer 31. This enables low-resistance, stable ohmic contact by utilizing the material properties of the channel layer 31, reducing device conduction losses. Optionally, the source electrode 4 and drain electrode 5 are metal electrodes; alternatively, both the source electrode 4 and drain electrode 5 include an N-type heavily doped semiconductor film and a metal electrode, with the N-type heavily doped semiconductor film located between the metal electrode and the channel layer 31.
[0061] As an alternative, the channel layer 31 is a gallium nitride layer, and the barrier layer 32 is an aluminum gallium nitride layer. Gallium nitride and aluminum gallium nitride both belong to group III-V nitride semiconductors, and their lattice structures and chemical properties are highly compatible. Moreover, they have precise gradient differences in band width, lattice constant, and polarization effect, which can form heterojunctions and induce the generation of two-dimensional electron gas.
[0062] As an alternative, such as Figures 1 to 5 As shown, an insulating dielectric layer 8 is disposed between the source 4, gate 6, and drain 5. By providing the insulating dielectric layer 8, surface leakage current generated between the source 4, gate 6, and drain 5 under high voltage can be blocked, which helps to improve device reliability.
[0063] This invention also provides a method for preparing a semiconductor structure. Figures 1 to 5 This is a schematic diagram of the semiconductor structure prepared based on the preparation method provided in this embodiment. Figure 7 This is a flowchart of a method for preparing a semiconductor structure according to an embodiment of the present invention, such as... Figure 7 As shown, it includes steps S1 and S2.
[0064] Step S1, a first intermediate structure is provided, the first intermediate structure includes a substrate layer 1, a buffer layer 2 and a functional layer 3 stacked together; a source electrode 4 and a drain electrode 5 are disposed on the functional layer 3, and a plurality of gate electrodes 6 are located between the source electrode 4 and the drain electrode 5, and a target region 10 is set between the plurality of gate electrodes 6.
[0065] It should be noted that when the above semiconductor structure is used as a bidirectional power device, the source 4 and drain 5 need to be symmetrically arranged on both sides of the upper surface of the functional layer 3.
[0066] Step S2: An isolation structure 11 is provided in the substrate layer 1 corresponding to the target region 10, wherein the projection of the target region 10 on the substrate layer 1 and the projection of the isolation structure 11 on the substrate layer 1 at least partially overlap.
[0067] By setting an isolation structure 11 in the target region 10 of the substrate layer 1, physical isolation can be formed in the substrate layer 1, breaking the longitudinal physical contact and conductive path between the substrate layer 1 and the target region 10 of the buffer layer 2. This can block longitudinal leakage under high voltage, prevent vertical breakdown of the buffer layer 2, and not interfere with the lateral conductivity and multi-gate control of the functional layer 3.
[0068] As an optional approach, step S2 involves setting an isolation structure 11 in the target region 10 of the substrate layer 1, including: forming a groove 111 on the surface of the substrate layer 1 away from the buffer layer 2, the groove 111 penetrating the substrate layer 1 as the isolation structure 11. The resulting semiconductor structure can be referenced... Figure 1 As shown. By creating the groove 111, the formation of a longitudinal leakage current channel between the substrate layer 1 and the buffer layer 2 under high voltage is completely blocked at the physical level.
[0069] As an optional approach, in step S2, after setting the isolation structure 11 on the substrate layer 1 corresponding to the target region 10, the method further includes filling the groove 111 by depositing an insulating material 112. The resulting semiconductor structure can be referred to... Figure 2 As shown. After filling with insulating material 112, a dual longitudinal protective barrier is formed, consisting of physical spatial isolation and insulating dielectric barrier, which can further enhance the leakage resistance interruption effect and improve the longitudinal withstand voltage level of the device.
[0070] As an optional approach, in step S2, after setting the isolation structure 11 on the substrate layer 1 corresponding to the target region 10, the method further includes: implanting ions along the groove 111 into the region of the buffer layer 2 near the groove 111 to form an ion-doped region 9, wherein the ion type of the ion-doped region 9 is different from the ion type of the buffer layer 2. The resulting semiconductor structure can be referred to... Figure 3 As shown.
[0071] Since the groove 111 provides the ion implantation channel, the ion implantation step needs to be performed after the groove 111 is created. Based on the use of the groove 111 as a physical spatial barrier, ions are implanted into the region of the buffer layer 2 near the groove 111 to form an ion-doped region 9 for electrical isolation. This can form a dual vertical isolation barrier of physical and electrical properties, effectively preventing the buffer layer 2 from vertically breaking down due to vertical leakage.
[0072] As an optional approach, step S2 involves setting an isolation structure 11 on the substrate 1 corresponding to the target region 10, including: thinning the substrate 1 to make its thickness h less than or equal to 1 micrometer; and thermally oxidizing the portion of the thinned substrate 1 corresponding to the target region 10 to obtain a thermally oxidized region 113, which penetrates the substrate 1 as the isolation structure 11. The resulting semiconductor structure can be referenced. Figure 4 As shown.
[0073] In order for the thermally oxidized region 113 to penetrate the substrate layer 1, which is typically tens to hundreds of micrometers thick, the substrate layer 1 needs to be thinned first. By thermally oxidizing the bulk material of the target region 10 of the substrate layer 1 in situ into an insulating oxide to form the thermally oxidized region 113, it is possible to block the longitudinal leakage current channel while preventing external impurities and moisture from penetrating from the substrate layer 1 to the buffer layer 2 and the functional layer 3, thus ensuring the long-term stability of the longitudinal isolation effect.
[0074] As an optional approach, step S1 provides a first intermediate structure, comprising: a substrate layer 1, a buffer layer 2, and a functional layer 3 stacked together. A semiconductor material is grown on the functional layer 3 to form an initial cap layer. The initial cap layer is etched, and by controlling the etching depth, a first p-type layer 71, a second p-type layer 72, a first protrusion structure 711 located on the side of the first p-type layer 71 near the second p-type layer 72, and a second protrusion structure 721 located on the side of the second p-type layer 72 near the first p-type layer 71 are obtained. A source electrode 4 and a drain electrode 5 are disposed on the functional layer 3, and a first gate electrode 61 is disposed on the first p-type layer 71, and a second gate electrode 62 is disposed on the second p-type layer 72, thus obtaining the first intermediate structure. The resulting semiconductor structure can be referred to... Figure 5 As shown.
[0075] By setting the first protruding structure 711 and the second protruding structure 721, the contact area between the edge of the first gate 61 and the second gate 62 near the target region 10 and the functional layer 3 is covered. This can directionally disperse the peak surface electric field of the target region 10 and reduce the electric field intensity on the side of the first gate 61 and the second gate 62 near the target region 10. Combined with the groove 111 penetrating the substrate layer 1, this forms a synergistic surface and longitudinal protection, solving the problem in related technologies where gallium nitride bidirectional power devices are easily vertically broken down between the substrate and the buffer layer under high voltage.
[0076] It should be noted that the term "comprising" and its variations used in the embodiments of this invention are open-ended, meaning "including but not limited to". The terms "first", "second", etc., are used for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features.
[0077] The appearance of the term "embodiment" in various places in this specification does not necessarily mean the same embodiment, nor does it imply that it is independent of or alternative to other embodiments. The various embodiments in this specification are described in a related manner, and the same or similar parts between the various embodiments can be referred to each other.
Claims
1. A semiconductor structure, characterized in that, include: A substrate layer (1), a buffer layer (2), and a functional layer (3) are stacked together. The functional layer (3) is provided with a source (4) and a drain (5), and a plurality of gates (6) located between the source (4) and the drain (5), and the plurality of gates (6) are configured as a target region (10). An isolation structure (11) is provided on the substrate (1) corresponding to the target region (10), and the projection of the target region (10) on the substrate (1) and the projection of the isolation structure (11) on the substrate (1) overlap at least partially.
2. The semiconductor structure according to claim 1, characterized in that, The isolation structure (11) is a groove (111) that penetrates the substrate layer (1).
3. The semiconductor structure according to claim 2, characterized in that, The groove (111) is filled with insulating material (112).
4. The semiconductor structure according to claim 3, characterized in that, The insulating material (112) includes at least one of the following: Silicon dioxide and silicon nitride.
5. The semiconductor structure according to claim 2, characterized in that, The region of the buffer layer (2) near the groove (111) is set as an ion-doped region (9). The projection of the groove (111) on the substrate layer (1) and the projection of the ion-doped region (9) on the substrate layer (1) overlap at least partially. The doping type of the ion-doped region (9) is different from the doping type of the buffer layer (2).
6. The semiconductor structure according to claim 5, characterized in that, The buffer layer (2) is n-type doped, and the ion-doped region (9) is p-type doped.
7. The semiconductor structure according to claim 1, characterized in that, The portion of the substrate layer (1) corresponding to the target region (10) is set as a thermal oxidation region (113), the thermal oxidation region (113) penetrates the substrate layer (1) as the isolation structure (11), and the thickness (h) of the substrate layer (1) is less than or equal to 1 micrometer.
8. The semiconductor structure according to claim 1, characterized in that, There are two gates (6), namely a first gate (61) and a second gate (62), and the target region (10) is set between the first gate (61) and the second gate (62). The functional layer (3) is provided with a first p-type layer (71) and a second p-type layer (72); The first gate (61) is disposed on the first p-type layer (71), and the second gate (62) is disposed on the second p-type layer (72).
9. The semiconductor structure according to claim 8, characterized in that, The first p-type layer (71) has a first protruding structure (711) on the side near the second p-type layer (72), and the second p-type layer (72) has a second protruding structure (721) on the side near the first p-type layer (71). The target region (10) is formed between the first protruding structure (711) and the second protruding structure (721).
10. The semiconductor structure according to claim 9, characterized in that, There are multiple first protruding structures (711) and multiple isolation structures (11). The projection of the gap between two adjacent first protruding structures (711) on the substrate layer (1) overlaps with the projection of at least one isolation structure (11) on the substrate layer (1).
11. The semiconductor structure according to claim 1, characterized in that, The functional layer (3) includes a channel layer (31) and a barrier layer (32) stacked sequentially on the buffer layer (2). The source (4) and the drain (5) are at least disposed on the channel layer (31).
12. A method for fabricating a semiconductor structure, characterized in that, include: A first intermediate structure is provided, the first intermediate structure includes a substrate layer (1), a buffer layer (2) and a functional layer (3) stacked together; a source (4) and a drain (5) are disposed on the functional layer (3), and a plurality of gates (6) are located between the source (4) and the drain (5), and a target region (10) is set between the plurality of gates (6). An isolation structure (11) is provided on the substrate layer (1) corresponding to the target region (10), wherein the projection of the target region (10) on the substrate layer (1) and the projection of the isolation structure (11) on the substrate layer (1) at least partially overlap.
13. The preparation method according to claim 12, characterized in that, An isolation structure (11) is provided on the substrate layer (1) corresponding to the target region (10), including: A groove (111) is formed on the surface of the substrate layer (1) away from the buffer layer (2), and the groove (111) penetrates the substrate layer (1) as the isolation structure (11).
14. The preparation method according to claim 13, characterized in that, After the isolation structure (11) is provided on the substrate layer (1) corresponding to the target region (10), the method further includes: Ions are injected into the region of the buffer layer (2) near the groove (111) along the groove (111) to form an ion-doped region (9), wherein the ion type of the ion-doped region (9) is different from the ion type of the buffer layer (2).
15. The preparation method according to claim 13, characterized in that, After the isolation structure (11) is provided on the substrate layer (1) corresponding to the target region (10), the method further includes: The groove (111) is filled by depositing insulating material (112).
16. The preparation method according to claim 12, characterized in that, An isolation structure (11) is provided on the substrate layer (1) corresponding to the target region (10), including: The substrate layer (1) is thinned so that the thickness (h) of the substrate layer (1) is less than or equal to 1 micrometer; The portion of the thinned substrate layer (1) corresponding to the target region (10) is subjected to thermal oxidation treatment to obtain a thermally oxidized region (113), which penetrates the substrate layer (1) as the isolation structure (11).
17. The preparation method according to claim 12, characterized in that, Provide a first intermediate structure, including: A substrate layer (1), a buffer layer (2), and a functional layer (3) are provided in a stacked configuration. Semiconductor material is grown on the functional layer (3) to form an initial cap layer; The initial cap layer is etched, and by controlling the etching depth, a first p-type layer (71), a second p-type layer (72), a first protruding structure (711) located on the side of the first p-type layer (71) close to the second p-type layer (72), and a second protruding structure (721) located on the side of the second p-type layer (72) close to the first p-type layer (71). The source (4) and drain (5) are disposed on the functional layer (3), and a first gate (61) is disposed on the first p-type layer (71), and a second gate (62) is disposed on the second p-type layer (72) to obtain the first intermediate structure.