Semiconductor device, preparation method, power module, conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle, and the semiconductor device comprises a semiconductor body which comprises a first region, a well region, a second region and a drift region which are sequentially away from a first surface; the first region and the drift region are set as a first conductive type, and the well region and the second region are set as a second conductive type; the first surface is provided with a groove which comprises a first sub-groove and a second sub-groove at the bottom of the first sub-groove; the semiconductor device further comprises third and fifth regions of the first conductivity type and a fourth region of the second conductivity type. The third region is located at the groove corner of the first sub-groove; the fourth region is positioned on the side wall and the groove corner of the second sub-groove; the fifth region is located at one side of the third and fourth regions away from the first surface and can communicate the drift region and the third region; the dielectric layer is located in the second sub-trench; the grid electrode is located in the first sub-trench; the parasitic capacitance of the device is reduced, the problem of groove bottom gate oxide electric field concentration is improved, and meanwhile the on-resistance is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device, a fabrication method, a power module, a conversion circuit, and a vehicle. Background Technology

[0002] As a representative of third-generation semiconductor materials, silicon carbide (SiC) possesses excellent physical and electrical properties. Compared to silicon, SiC has a larger bandgap and advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices fabricated using SiC can not only operate stably at higher temperatures but are also suitable for high-voltage and high-frequency applications.

[0003] SiC MOSFETs have evolved from planar to trench types. By improving the gate structure, the direction of current flow on the gate has changed from planar to vertical. Trench semiconductor devices have advantages such as small cell size and high current density; however, in trench semiconductor devices, the high electric field at the bottom and corners of the trench increases the electric field on the gate insulating layer, which in turn makes the gate insulating layer more susceptible to breakdown. Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in the prior art, for reference. Figure 1 Ion implantation can be used to form a semi-enclosed P+ region (01) on the sidewall and part of the bottom of the gate trench as an electric field shielding structure. However, in existing trench structures, the overlap area between the gate and source, and between the gate and drain, as well as the structural layout, result in high parasitic capacitance, especially Miller capacitance (Cgd), which severely limits the performance and efficiency improvement of the device in high-frequency applications. Moreover, under high-voltage blocking conditions, electric field lines tend to accumulate in the gate oxide layer (02) in the trench corner region, forming extremely high electric field peaks, still posing a risk of breakdown. In addition, to obtain higher breakdown voltage, it is usually necessary to increase the thickness of the drift region or reduce its doping concentration, but this directly leads to an increase in the on-resistance of the device. Conversely, optimizing the on-resistance often requires adjusting structural parameters, which may weaken the blocking capability. Existing semiconductor devices are still insufficient in balancing this classic contradiction, making it difficult to achieve extremely low on-resistance while maintaining high breakdown voltage, thus limiting further improvement in the overall product value of the device.

[0004] Therefore, how to effectively reduce the parasitic capacitance of the device, improve the problem of gate oxide electric field concentration at the bottom of the trench, and at the same time reduce the on-resistance, and better optimize the trade-off between breakdown voltage and on-resistance, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This application provides a semiconductor device, a fabrication method, a power module, a conversion circuit, and a vehicle to effectively reduce the parasitic capacitance of the device, improve the problem of gate oxide electric field concentration at the bottom of the trench, and reduce the on-resistance, thereby better optimizing the trade-off between breakdown voltage and on-resistance.

[0006] According to one aspect of this application, a semiconductor device is provided, comprising: A semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region, a first region, a second region, and a drift region; the first region is configured with a first conductivity type and is located on the first surface, the well region is configured with a second conductivity type and is located on the side of the first region away from the first surface, the second region is configured with a second conductivity type and is located on the side of the well region away from the first surface, and the drift region is configured with a first conductivity type and is located on the side of the second region away from the first surface; the first conductivity type and the second conductivity type are different, and the first surface is provided with a trench, the trench including a first sub-trench and a second sub-trench located at the bottom of the first sub-trench; the semiconductor body further includes a third region, a fourth region, and a fifth region; the third region is configured with a first conductivity type and is located at the corner of the first sub-trench; the fourth region is configured with a second conductivity type and is located at the sidewall and corner of the second sub-trench; the fifth region is configured with a first conductivity type and is used to connect the drift region and the third region; wherein, the surface of the fourth region away from the second sub-trench is in contact with the third region and the fifth region; The dielectric layer is located in the second sub-trench; The gate is located in the first sub-trench; The source electrode is located on the first surface; The drain electrode is located on the second surface.

[0007] Optionally, the semiconductor device further includes a gate insulating layer located on the sidewall of the gate and the surface of the gate near the second surface; The gate insulating layer located on the side of the gate near the second surface is in contact with the dielectric layer.

[0008] Optionally, the concentration of the first conductivity type doped ion in the third region is greater than the concentration of the first conductivity type doped ion in the fifth region.

[0009] Optionally, the fourth region covers the sidewalls of the dielectric layer and at least a portion of the surface of the dielectric layer on the side away from the first surface; The third region is in contact with the fourth region located on the sidewall of the dielectric layer, and with the second region located on the side of the third region away from the dielectric layer; The fifth region is in contact with the fourth region located on the side of the dielectric layer away from the first surface, and with the second region located on the side of the fifth region away from the dielectric layer.

[0010] Optionally, the fourth region covers the sidewalls of the dielectric layer on both sides, and also covers a portion of the surface of the dielectric layer at the two opposite corners of the second sub-trench.

[0011] Optionally, the width of the first sub-groove is greater than the width of the second sub-groove; The first sub-groove extends from the first surface to the second surface to at least penetrate the well region; the distance from the bottom surface of the second sub-groove to the second surface is less than the distance from the second region to the second surface.

[0012] Optionally, the semiconductor body further includes: A sixth region is located on the first surface and on the side of the first region away from the trench; the sixth region is configured with a second conductivity type and is in contact with the source electrode.

[0013] Optionally, the semiconductor body further includes: Substrate: The first epitaxial layer, configured with a first conductivity type, is located on one side of the substrate; The second epitaxial layer, configured as a second semiconductor type, is located on the side of the first epitaxial layer away from the substrate; The third epitaxial layer, configured as a second semiconductor type, is located on the side of the second epitaxial layer away from the substrate; The first region and the well region are disposed in the third epitaxial layer; the second region, the third region, the fourth region and at least part of the fifth region are all disposed in the second epitaxial layer.

[0014] According to another aspect of this application, a method for fabricating a semiconductor device is provided, for fabricating the semiconductor device described in any embodiment of this application; comprising, A semiconductor body is formed, and a trench is formed on a first surface of the semiconductor body. The semiconductor body includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region, a first region, a second region, and a drift region. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The second region is configured with a second conductivity type and is located on the side of the well region away from the first surface. The drift region is configured with a first conductivity type and is located on the side of the second region away from the first surface. The first conductivity type and the second conductivity type are different. The trench includes a first sub-trench and a second sub-trench located at the bottom of the first sub-trench. The semiconductor body also includes a third region, a fourth region, and a fifth region. The third region is configured with a first conductivity type and is located at the corner of the first sub-trench. The fourth region is configured with a second conductivity type and is located at the sidewall and corner of the second sub-trench. The fifth region is configured with a first conductivity type and is used to connect the drift region and the third region. The surface of the fourth region away from the second sub-trench is in contact with the third region and the fifth region. A dielectric layer is formed in the second sub-trench; A gate is formed in the first sub-trench; A source electrode is formed on the first surface; The second surface forms the drain electrode.

[0015] Optionally, a semiconductor body is formed, and a trench is formed on a first surface of the semiconductor body, including: Provide substrate; A first epitaxial layer is formed on one side of the substrate; the first epitaxial layer is configured with a first conductivity type; A second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate; the second epitaxial layer is configured with a second conductivity type; A third epitaxial layer is formed on the side of the second epitaxial layer away from the substrate; the third epitaxial layer is configured with a second conductivity type; The first region and the well region are formed in the third epitaxial layer; The trench is formed on the side of the third epitaxial layer away from the substrate, and the second region, the third region, the fourth region and the fifth region are formed in the second epitaxial layer; Optionally, forming the first region and the well region in the third epitaxial layer includes: The first region is formed from the surface of the third epitaxial layer on the side away from the substrate; wherein the third epitaxial layer located between the first region and the second epitaxial layer serves as the well region; The process of forming the trench on the side of the third epitaxial layer away from the substrate, and forming the second region, the third region, the fourth region, and the fifth region in the second epitaxial layer, includes: A mask layer is formed on the side of the third epitaxial layer away from the substrate, and the mask layer is patterned. Based on the patterned mask layer, a first sub-trench is formed on the surface of the third epitaxial layer away from the substrate, and the first sub-trench penetrates the first region and the well region; A first spacer layer is formed on the sidewall of the first sub-trench, and a third initial region is formed at the bottom and corner of the first sub-trench based on the patterned mask layer and the first spacer layer. A second sub-groove is formed at the bottom of the first sub-groove, and the second sub-groove penetrates the third initial region; A fifth initial region is formed at the bottom of the second sub-trench, and the fifth initial region extends to connect with the third initial region; A second spacer layer is formed on the side of the first spacer layer away from the sidewall of the first sub-groove and on the sidewall of the second sub-groove; A third spacer layer is formed in the remaining space of the first sub-groove and the second sub-groove; the third spacer layer and the first spacer layer are both made of different materials than the second spacer layer; The second spacer layer is removed, forming a fourth region on the exposed sidewalls and bottom of the second sub-trench; wherein the region outside the fourth region in the third initial region forms the third region, and the region outside the fourth region in the fifth initial region forms the fifth region; Remove the third spacer layer and the second spacer layer.

[0016] According to another aspect of this application, a power module is provided, including a substrate and at least one semiconductor device as described in any embodiment of this application, the substrate being used to support the semiconductor device.

[0017] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, the semiconductor device being electrically connected to the circuit board.

[0018] According to another aspect of this application, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of this application, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0019] The technical solution provided in this application, by setting the trench as a first sub-trench and a second sub-trench, and setting a dielectric layer in the second sub-trench, is equivalent to increasing the thickness of the gate insulating layer at the bottom of the gate. This can increase the withstand voltage of the gate insulating layer at the bottom of the gate, reduce the parasitic capacitance Cgd, and improve the high-frequency characteristics of the device. On this basis, a third region with a different conductivity type than the second region is set at the corner of the first sub-trench. The PN junction formed by the third region and the second region can provide electric field shielding for the corner of the first sub-trench. A fourth region with a different conductivity type than the third and fifth regions is set on the sidewalls and corners of the second sub-trench. The PN junction formed by the fourth region and the third and fifth regions can provide electric field shielding for the sidewalls and corners of the second sub-trench, respectively. This can further effectively improve the electric field distribution and increase the breakdown voltage of the device. In addition, a fifth region with the same conductivity type as the third region and the drift region of the semiconductor body is set. The fifth region can connect the drift region and the third region, which can reduce the on-resistance Rdson of the device and reduce the conduction loss of the device. Therefore, while effectively suppressing parasitic capacitance and alleviating the problem of concentrated gate oxide electric field at the bottom of the trench, it can better optimize the trade-off between breakdown voltage and on-resistance.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in the prior art; Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figure 3 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application; Figure 4 This is a schematic cross-sectional view of step S110 in a method for fabricating a semiconductor device according to an embodiment of this application. Figure 5 This is a cross-sectional structural diagram corresponding to step S120 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 6 This is a cross-sectional structural diagram corresponding to step S130 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 7 This is a schematic cross-sectional view of the sixth region formed in a semiconductor device fabrication method provided in this application embodiment; Figure 8 This is a cross-sectional structural diagram corresponding to step S140 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 9 This is a cross-sectional structural diagram corresponding to step S150 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 10 This is a schematic cross-sectional view of step S1510 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 11 This is a schematic cross-sectional view of step S1520 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 12 This is a schematic cross-sectional view of step S1540 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 13 This is a schematic cross-sectional view of step S1550 in a method for fabricating a semiconductor device provided in this application embodiment; Figures 14-15 This is a schematic cross-sectional view of step S1560 in a method for fabricating a semiconductor device provided in this application embodiment; Figures 16-17 This is a schematic cross-sectional view of step S210 in a method for fabricating a semiconductor device according to an embodiment of this application. Figure 18 This is a cross-sectional structural diagram corresponding to step S310 in a method for fabricating a semiconductor device provided in this application embodiment. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] This application provides a semiconductor device. Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application, with reference to... Figure 2 Semiconductor devices include: Semiconductor body 1, configured as a first conductivity type, includes a first surface 11 and a second surface 12 disposed opposite to each other; semiconductor body 1 also includes a well region QJ, a first region Q1, a second region Q2, and a drift region 21; the first region Q1 is configured as a first conductivity type and is located on the first surface 11, the well region QJ is configured as a second conductivity type and is located on the side of the first region Q1 away from the first surface 11, the second region Q2 is configured as a second conductivity type and is located on the side of the well region QJ away from the first surface 11, and the drift region 21 is configured as a first conductivity type and is located on the side of the second region Q2 away from the first surface 11; the first conductivity type and the second conductivity type are different, the first surface 11... The semiconductor body 1 is provided with a trench, which includes a first sub-trench and a second sub-trench located at the bottom of the first sub-trench; the semiconductor body 1 also includes a third region Q3, a fourth region Q4 and a fifth region Q5; the third region Q3 is configured with a first conductivity type and is located at the corner of the first sub-trench; the fourth region Q4 is configured with a second conductivity type and is located at the sidewall and corner of the second sub-trench; the fifth region Q5 is configured with a first conductivity type and is located on the side of the third region Q3 and the fourth region Q4 away from the first surface 11, for connecting the drift region 21 and the third region Q3; wherein, the surface of the fourth region Q2 away from the second sub-trench is in contact with the third region Q3 and the fifth region Q5; Dielectric layer 60 is located in the second sub-trench; Gate 71 is located in the first sub-trench; The source electrode S is located on the first surface 11; The drain electrode D is located on the second surface 12.

[0026] The technical solution provided in this application provides a method to increase the thickness of the gate insulating layer 72 located at the bottom of the gate 71 by setting the trench as a first sub-trench and a second sub-trench, and by setting a dielectric layer 60 in the second sub-trench. This increases the withstand voltage of the gate insulating layer 72 located at the bottom of the gate 71, and also reduces the parasitic capacitance Cgd, thereby improving the high-frequency characteristics of the device. Furthermore, a third region Q3 with a different conductivity type than the second region Q2 is set at the corner of the first sub-trench. The PN junction formed by the third region Q3 and the second region Q2 can provide electric field shielding for the corner of the first sub-trench. A fourth region Q4, with a different conductivity type than the third region Q3 and the fifth region Q5, is provided on the sidewalls and corners of the trench. The PN junction formed by the fourth region Q4, the third region Q3, and the fifth region Q5 can respectively shield the electric field of the sidewalls and corners of the second sub-trench, thereby further improving the electric field distribution and increasing the breakdown voltage of the device. In addition, the fifth region Q5, with the same conductivity type as the third region Q3 and the drift region 21 of the semiconductor body 1, can connect the drift region 21 and the third region Q3, which can reduce the on-resistance Rdson of the device and reduce the conduction loss of the device. Therefore, while effectively suppressing parasitic capacitance and alleviating the problem of gate oxide electric field concentration at the bottom of the trench, the trade-off between breakdown voltage and on-resistance can be better optimized.

[0027] The above are the core inventive points of this application. The structure of the semiconductor device will be described in detail below with reference to the accompanying drawings.

[0028] The semiconductor body 1 can be formed by a single epitaxial layer or by multiple epitaxial layers. That is, the semiconductor body 1 can be a single semiconductor epitaxial layer or a stacked structure formed by multiple semiconductor epitaxial layers. The semiconductor body 1 may also include a substrate 10, that is, the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer formed on one side of the substrate 10.

[0029] The material of the substrate 10 can be the same as the material of the semiconductor epitaxial layer, or the material of the substrate 10 can be different from the material of the semiconductor epitaxial layer. In a specific embodiment of this application, both the material of the semiconductor epitaxial layer and the material of the substrate 10 can be SiC. Compared with silicon, SiC has a larger bandgap and advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices made of SiC can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency applications.

[0030] The semiconductor body 1 includes a first surface 11 and a second surface 12 disposed opposite to each other. When the semiconductor body 1 includes only a semiconductor epitaxial layer, the second surface 12 is the surface of the semiconductor body 1 closest to the substrate 10, and the first surface 11 is the surface of the semiconductor body 1 furthest from the substrate 10. When the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer, the second surface 12 is the surface of the substrate 10 furthest from the semiconductor epitaxial layer, and the first surface 11 is the surface of the semiconductor epitaxial layer furthest from the substrate 10 furthest from the substrate 10.

[0031] Figure 2 The semiconductor body 1 in the structure shown includes: a substrate 10; a first epitaxial layer 20, configured as a first conductivity type, located on one side of the substrate 10; a second epitaxial layer 30, configured as a second semiconductor type, located on the side of the first epitaxial layer 20 away from the substrate 10; and a third epitaxial layer 40, configured as a second semiconductor type, located on the side of the second epitaxial layer 30 away from the substrate 10. A first region Q1 and a well region QJ are disposed on the third epitaxial layer 40; a second region Q2, a third region Q3, and a fourth region Q4 are all disposed on the second epitaxial layer 30; a portion of a fifth region Q5 is disposed on the second epitaxial layer 30, and another portion of the fifth region Q5 is disposed on the first epitaxial layer 20; and a drift region is located on the first epitaxial layer 20. A second surface 12 is the surface of the substrate 10 away from the semiconductor epitaxial layer, and a first surface 11 is the surface of the third epitaxial layer 40 away from the substrate 10. This application, by setting three epitaxial layers and using the second epitaxial layer 30 to form the second region Q2, allows the thickness of the second region Q2 to be not limited by the ion implantation depth, thereby providing sufficient space for the formation of the third region Q3, the fourth region Q4, and the fifth region Q5, and reducing the fabrication difficulty of the third region Q3, the fourth region Q4, and the fifth region Q5. In other embodiments of this application, all of the fifth region Q5 can be located in the second epitaxial layer 30, ensuring that the side of the fifth region Q5 closest to the second surface 12 is in contact with the drift region, thus connecting the drift region and the third region Q3.

[0032] Based on the above embodiments, optionally, the first conductivity type can be N-type and the second conductivity type can be P-type; or, the first conductivity type can be P-type and the second conductivity type can be N-type.

[0033] Figure 2 In the structure shown, the semiconductor body 1 has an N-type conductivity. Therefore, the first region Q1 has an N-type conductivity and is located on the first surface 11; the first region Q1 is a heavily doped region. The well region QJ has a P-type conductivity and is located on the side of the first region Q1 away from the first surface 11. The second region Q2 has a P-type conductivity and is located on the side of the well region QJ away from the first surface 11; the second region Q2 can also be a heavily doped region. The third region Q3 has an N-type conductivity and is located at the corner of the first sub-trench. The fourth region Q4 has a P-type conductivity and is located on the sidewall and corner of the second sub-trench. The fifth region Q5 has an N-type conductivity and is located on the side of the third region Q3 and the fourth region Q4 away from the first surface 11, used to connect the drift region 21 with the third region Q3. The third region Q3, the fourth region Q4, and the fifth region Q5 can all be heavily doped regions.

[0034] The first epitaxial layer 20 is an N-type semiconductor epitaxial layer, doped with N-type dopant ions. The second epitaxial layer 30 is a P-type semiconductor epitaxial layer, doped with P-type dopant ions. The third region Q3 and the fifth region Q5 are formed by implanting N-type dopant ions into the second epitaxial layer 30, and the fourth region Q4 is formed by implanting P-type dopant ions into the second epitaxial layer 30. The third epitaxial layer 40 is a P-type semiconductor epitaxial layer, doped with P-type dopant ions. The first region Q1 is formed by implanting N-type dopant ions into the third epitaxial layer 40. The depletion layer formed by the first epitaxial layer 20 and the second epitaxial layer 30 can affect the charge coupling between capacitors in the vertical direction, thereby further reducing the parasitic capacitance Cgd of the device.

[0035] In semiconductors, when N-type dopant ions (donor dopant ions, such as phosphorus) and P-type dopant ions (acceptor dopant ions, such as boron) are simultaneously doped in the same region, their effects interact through a "compensation effect." Specifically, the charge carriers (electrons and holes) of the N-type and P-type dopant ions cancel each other out. Free electrons provided by N-type dopant ions fill the holes generated by P-type dopant ions, and the final conductivity type of the material depends on the dopant concentration. If the donor concentration (N-type dopant concentration) is greater than the acceptor concentration (P-type dopant concentration), the material behaves as an N-type semiconductor, with the remaining electrons being the majority carriers; if the acceptor concentration (P-type dopant concentration) is greater than the donor concentration (N-type dopant concentration), the material behaves as a P-type semiconductor, with the remaining holes being the majority carriers; if the concentrations of both dopant ions are equal (complete compensation), the material approaches an intrinsic semiconductor with extremely low conductivity.

[0036] refer to Figure 2 The semiconductor device further includes a gate insulating layer 72 located on the sidewall of the gate 71 and the surface of the gate 71 near the second surface 12; and the gate insulating layer 72 located on the side of the gate 71 near the second surface 12 is in contact with the dielectric layer 60. The gate 71 can be made of polysilicon; the material of the gate insulating layer 72 can be the same as or different from the material of the dielectric layer 60. In one embodiment of this application, both the gate insulating layer 72 and the dielectric layer 60 are made of silicon oxide.

[0037] Based on the above embodiments, optionally, the fourth region Q4 covers the sidewall of the dielectric layer 60 and at least a portion of the surface of the dielectric layer 60 away from the first surface 11; the third region Q3 contacts the fourth region Q4 located on the sidewall of the dielectric layer 60, and contacts the second region Q2 located on the side of the third region Q3 away from the dielectric layer 60; the fifth region Q5 contacts the fourth region Q4 located on the side of the dielectric layer 60 away from the first surface 11, and contacts the second region Q2 located on the side of the fifth region Q5 away from the dielectric layer 60.

[0038] Specifically, a fourth region Q4 is configured to cover the sidewall of the dielectric layer 60 and at least a portion of the surface of the dielectric layer 60 away from the first surface 11. A third region Q3 is configured to contact the fourth region Q4 located on the sidewall of the dielectric layer 60, and a fifth region Q5 is configured to contact the fourth region Q4 located on the sidewall of the dielectric layer 60 away from the first surface 11. This allows a PN junction to be formed between the fourth region Q4 and the third region Q3 located on the sidewall of the dielectric layer 60, and between the fourth region Q4 and the fifth region Q5 located on the sidewall of the dielectric layer 60 away from the first surface 11. The depletion effect of the PN junction is used to actively modulate the electric field, transferring the electric field peak from the interface of the dielectric layer 60 and the interface of the gate insulating layer 72 located at the corner of the first sub-trench to the semiconductor body with stronger withstand voltage, thereby preventing the dielectric layer 60 and the gate insulating layer 72 from being broken down.

[0039] Based on the above embodiments, optionally, the concentration of the first conductivity type doped ion in the third region Q3 is greater than the concentration of the first conductivity type doped ion in the fifth region Q5.

[0040] Specifically, setting the concentration of the first conductivity type doped ions in the third region Q3 to be greater than the concentration of the first conductivity type doped ions in the fifth region Q5 can effectively weaken the electric field at the corner of the first sub-trench, further improving the long-term reliability of the device. Moreover, increasing the concentration of the first conductivity type doped ions in the third region Q3 can further reduce the on-resistance Rdson of the device, thus reducing the conduction loss. Optionally, the doping concentration of the first conductivity type doped ions in the third region Q3 is in the range of 1×10⁻⁶. 18 cm -3 Up to 9×10 19 cm -3 The doping concentration range of the first conductivity type doped ions in region Q5 is 1×10⁻⁶. 17 cm -3 Up to 9×10 17 cm -3 .

[0041] Based on the above embodiments, refer to Figure 2 Optionally, the fourth region Q4 covers the sidewalls of the dielectric layer 60 on both sides, as well as the partial surfaces of the dielectric layer 60 located at the two opposite corners of the second sub-trench; the fifth region Q5 also contacts the surface of the dielectric layer 60 not covered by the fourth region Q4 on the side away from the first surface 11.

[0042] Specifically, the dielectric layer 60 includes a first sidewall and a second sidewall disposed opposite to each other. A fourth region Q4 covering the first sidewall extends from the first sidewall toward the bottom surface of the dielectric layer 60 (the surface near the second surface 12) until it covers a portion of the bottom surface of the dielectric layer 60. A fourth region Q4 covering the second sidewall extends from the second sidewall toward the bottom surface of the dielectric layer 60 (the surface near the second surface 12) until it covers a portion of the bottom surface of the dielectric layer 60. A third region Q3 is also located on opposite sides of the dielectric layer 60. One third region Q3 covers the corner of the first sub-trench near the first sidewall of the dielectric layer 60, and this third region Q3 contacts the fourth region Q4 located on the first sidewall of the dielectric layer 60, and contacts the second region Q2 on the side away from the dielectric layer 60. Another third region Q3 covers the corner of the first sub-trench near the second sidewall of the dielectric layer 60, and this third region Q3 contacts the fourth region Q4 located on the second sidewall of the dielectric layer 60, and contacts the second region Q2 on the side away from the dielectric layer 60. The fifth region Q5 covers the two fourth regions Q4 located on the side of the dielectric layer 60 near the second surface 12. In this embodiment, the bottom of the first sub-trench has two third regions Q3, two fourth regions Q4, and a continuous fifth region Q5, achieving all-round electric field shielding for the bottom and corners of the trench.

[0043] Based on the above embodiments, optionally, the width of the first sub-trench is greater than the width of the second sub-trench; wherein, the first sub-trench extends from the first surface 11 to the second surface 12 to at least penetrate the well region QJ; the distance from the bottom surface of the second sub-trench to the second surface 12 is less than the distance from the second region Q2 to the second surface 12. The first sub-trench and the second sub-trench are connected.

[0044] Based on the above embodiments, refer to Figure 2 Optionally, the semiconductor body 1 further includes a sixth region Q6, located on the first surface 11 and on the side of the first region Q1 away from the trench; the sixth region Q6 is configured with a second conductivity type and is in contact with the source S. The sixth region Q6 is a heavily doped region, for example, a heavily doped P+ region, providing a defined potential for the P-type well region QJ.

[0045] Based on the above embodiments, optionally, the semiconductor device further includes an interlayer insulating layer 80 located between the source S and the gate 71 for electrically isolating the source S and the gate 71.

[0046] This application also provides a method for fabricating a semiconductor device, used to fabricate the semiconductor device described in any embodiment of this application; Figure 3 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application, see reference. Figure 3 The methods for fabricating semiconductor devices include: S10. A semiconductor body is formed, and a trench is formed on a first surface of the semiconductor body; the semiconductor body is configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region, a first region, a second region, and a drift region; the first region is configured with a first conductivity type and is located on the first surface, the well region is configured with a second conductivity type and is located on the side of the first region away from the first surface, the second region is configured with a second conductivity type and is located on the side of the well region away from the first surface, and the drift region is configured with a first conductivity type and is located on the side of the second region away from the first surface; the first conductivity type and the second conductivity type are different; the trench includes a first sub-trench and a second sub-trench located at the bottom of the first sub-trench; the semiconductor body also includes a third region, a fourth region, and a fifth region; the third region is configured with a first conductivity type and is located at the corner of the first sub-trench; the fourth region is configured with a second conductivity type and is located at the sidewall and corner of the second sub-trench; the fifth region is configured with a first conductivity type and is used to connect the drift region and the third region; wherein, the surface of the fourth region away from the second sub-trench is in contact with the third region and the fifth region.

[0047] S20, a dielectric layer is formed in the second sub-trench.

[0048] S30, A gate is formed in the first sub-trench.

[0049] S40, a source electrode is formed on the first surface.

[0050] S50, the second surface of the sub-sub ...

[0051] The technical solution provided in this application forms a trench including a first sub-trench and a second sub-trench on the first surface 11, and sets a dielectric layer 60 in the second sub-trench. This effectively increases the thickness of the gate insulating layer 72 located at the bottom of the gate 71, which can increase the withstand voltage of the gate insulating layer 72 located at the bottom of the gate 71, and also reduce the parasitic capacitance Cgd, thereby improving the high-frequency characteristics of the device. Based on this, a third region Q3 with a different conductivity type than the second region Q2 is formed at the corner of the first sub-trench. The PN junction formed by the third region Q3 and the second region can provide electric field shielding for the corner of the first sub-trench. The sidewalls and corners of the sub-trench form a fourth region Q4 with a different conductivity type than the third region Q3 and the fifth region Q5. The PN junction formed by the fourth region Q4, the third region Q3, and the fifth region Q5 can respectively shield the electric field of the sidewalls and corners of the second sub-trench, thereby further improving the electric field distribution and increasing the breakdown voltage of the device. In addition, the fifth region Q5 is formed with the same conductivity type as the third region Q3 and the drift region of the semiconductor body 1. The fifth region Q5 can connect the drift region and the third region Q3, which can reduce the on-resistance Rdson of the device and reduce the conduction loss of the device. Therefore, while effectively suppressing parasitic capacitance and alleviating the problem of gate oxide electric field concentration at the bottom of the trench, the trade-off between breakdown voltage and on-resistance can be better optimized.

[0052] Optionally, step S10 forms a semiconductor body and forms a trench on the first surface of the semiconductor body, including: S110. Provide a substrate and form a first epitaxial layer on one side of the substrate; the first epitaxial layer is configured with a first conductivity type.

[0053] For details, please refer to Figure 4 The material of the substrate 10 and the material of the first epitaxial layer 20 may be the same or different. In the embodiments of this application, the material of the substrate 10 and the material of the first epitaxial layer 20 are the same, both of which can be SiC. The conductivity type of the first epitaxial layer 20 is the same as that of the substrate 10, for example, both are N-type. The N-type first epitaxial layer 20 is used to form the drift region of the device.

[0054] S120, a second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate; the second epitaxial layer is configured with a second conductivity type.

[0055] For details, please refer to Figure 5The material of the second epitaxial layer 30 may be the same as or different from the material of the first epitaxial layer 20. In the embodiments of this application, the material of the second epitaxial layer 30 is the same as that of the first epitaxial layer 20, both being SiC. The conductivity type of the first epitaxial layer 20 is different from that of the second epitaxial layer 30. For example, the conductivity type of the first epitaxial layer 20 is N-type, and the conductivity type of the second epitaxial layer 30 is P-type, and the second epitaxial layer 30 is a heavily P-type doped semiconductor epitaxial layer.

[0056] S130, a third epitaxial layer is formed on the side of the second epitaxial layer away from the substrate; the third epitaxial layer is configured as a second conductivity type.

[0057] For details, please refer to Figure 6 The material of the third epitaxial layer 40 may be the same as or different from the material of the second epitaxial layer 30. In the embodiments of this application, the material of the third epitaxial layer 40 is the same as that of the second epitaxial layer 30, both being SiC. The conductivity type of the third epitaxial layer 40 is the same as that of the second epitaxial layer 30, for example, both being P-type.

[0058] S140, A first region and a trap region are formed in the third epitaxial layer.

[0059] For details, please refer to Figure 8 The formation of a first region Q1 and a well region QJ in the third epitaxial layer 40 includes: implanting ions of a first conductivity type from the surface of the third epitaxial layer 40 away from the substrate 10 to form the first region Q1; wherein the third epitaxial layer 40 located between the first region Q1 and the second epitaxial layer 30 serves as the well region QJ. Further, the semiconductor body 1 also includes a sixth region Q6, configured as a second conductivity type and located on the first surface 11. The sixth region Q6 is formed by implanting ions of a second conductivity type from the surface of the third epitaxial layer 40 away from the substrate 10 before or after the formation of the first region Q1 in the third epitaxial layer 40. The sixth region Q6 is, for example, a heavily doped P-type region. (See reference...) Figure 7 An example is shown where a sixth region Q6 is formed by implanting ions of a second conductivity type from the surface of the third epitaxial layer 40 away from the substrate 10 before forming the first region Q1 in the third epitaxial layer 40.

[0060] S150, a trench is formed on the side of the third epitaxial layer away from the substrate, and a second region, a third region, a fourth region and a fifth region are formed in the second epitaxial layer.

[0061] For details, please refer to Figure 9A trench 50 can be formed on the surface of the third epitaxial layer 40 away from the substrate 10 by etching. Based on the etched trench 50, a second region Q2, a third region Q3, a fourth region Q4 and a fifth region Q5 are formed in the second epitaxial layer 30 by ion implantation.

[0062] In this embodiment, by setting three epitaxial layers and using the second epitaxial layer 30 to form the second region Q2, the thickness of the second region Q2 is not limited by the ion implantation depth, thereby providing sufficient space for the formation of the third region Q3, the fourth region Q4 and the fifth region Q5, and reducing the preparation difficulty of the second region Q2, the third region Q3, the fourth region Q4 and the fifth region Q5.

[0063] Further, step S150 involves forming a trench on the side of the third epitaxial layer away from the substrate, and forming a second region, a third region, a fourth region, and a fifth region in the second epitaxial layer, specifically including: S1510, a mask layer 101 is formed and patterned on the side of the third epitaxial layer 40 away from the substrate 10. Based on the patterned mask layer 101, a first sub-trench 51 is formed on the surface of the third epitaxial layer 40 away from the substrate 10. The first sub-trench 51 penetrates the first region Q1 and the well region QJ. Specifically, refer to... Figure 10 The material of the mask layer 101 can be silicon oxide.

[0064] S1520, a first spacer layer 102 is formed on the sidewall of the first sub-trench 51. Based on the patterned mask layer 101 and the first spacer layer 102, a third initial region Q30 is formed at the bottom and corner of the first sub-trench 51.

[0065] For details, please refer to Figure 11 A third initial region Q30 can be formed by implanting first conductive type ions at the bottom of the first sub-trench 51 through ion implantation process; the first spacer layer 102 can prevent the first conductive type ions from implanting into the sidewall of the first sub-trench 51 when forming the third initial region Q30. Moreover, forming the first spacer layer 102 on the sidewall of the first sub-trench 51 can also reduce the width of the first sub-trench 51, which is convenient for the subsequent formation of a second sub-trench 52 with a width smaller than that of the first sub-trench 51.

[0066] S1530, a second sub-groove 52 is formed at the bottom of the first sub-groove 51, and the second sub-groove 52 penetrates the third initial region. For details, refer to... Figure 12 A second sub-groove 52 can be formed at the bottom of the first sub-groove 51 by an etching process, and the second sub-groove 52 is connected to the first sub-groove 51.

[0067] S1540, a fifth initial region Q50 is formed at the bottom of the second sub-groove 52, and the fifth initial region Q50 diffuses to connect with the third initial region Q30.

[0068] For details, please refer to Figure 12 A fifth initial region Q50 can be formed by implanting ions of a first conductivity type into the bottom of the second sub-trench 52 using an ion implantation process. The ion doping concentration in the third initial region Q30 can be greater than the ion doping concentration in the fifth initial region Q50.

[0069] S1550, a second spacer layer 103 is formed on the side of the first spacer layer 102 away from the sidewall of the first sub-groove 51 and on the sidewall of the second sub-groove 52.

[0070] For details, please refer to Figure 13 The second spacer layer 103 covers the side of the first spacer layer 102 away from the sidewall of the first sub-groove 51 and the sidewall of the second sub-groove 52. The material of the second spacer layer 103 is different from the material of the first spacer layer 102.

[0071] S1560, a third spacer layer is formed in the remaining space of the first sub-groove 51 and the second sub-groove 52; the third spacer layer and the first spacer layer 102 are both made of different materials than the second spacer layer 103.

[0072] S1570, Remove the second spacer layer 103 to form a fourth region Q4 on the sidewall and bottom of the exposed second sub-trench 52; wherein, the region outside the fourth region Q4 in the third initial region forms the third region Q3, and the region outside the fourth region Q4 in the fifth initial region forms the fifth region Q5.

[0073] For details, please refer to Figure 14 The second spacer layer 103, located between the third spacer layer 104 and the first spacer layer 102, is removed. The materials of both the third spacer layer 104 and the first spacer layer 102 are different from those of the second spacer layer 103. This prevents the removal of the second spacer layer 103 from affecting the third spacer layer 104 and the first spacer layer 102. The materials of the third spacer layer 104 and the first spacer layer 102 can be the same or different. For example, the materials of both the third spacer layer 104 and the first spacer layer 102 are silicon nitride, and the material of the second spacer layer 103 is polycrystalline silicon. (Reference) Figure 15 A fourth region Q4 is formed by implanting ions of a second conductivity type into the bottom and sidewalls of the exposed second sub-trench 52 using an ion implantation process.

[0074] S1580, Remove the third spacer layer 104, the second spacer layer 103, and the mask layer 101. (Reference) Figure 9 ) Optionally, step S20, forming a dielectric layer in the second sub-trench, specifically includes: S210: A dielectric layer 60 is formed in the trench 50 and on the first surface of the semiconductor body 1, and the dielectric layer 60 located on the first surface of the semiconductor body 1 and in the first sub-trench 51 is removed. (Reference) Figures 16-17 ) Optionally, step S30, forming a gate in the first sub-trench, specifically includes: S310, after forming a gate insulating layer 71 on the trench wall of the first sub-trench 51 and on the side of the dielectric layer 60 away from the second surface, a gate 72 is formed on the side of the gate insulating layer 71 away from the dielectric layer 60. The material of the gate insulating layer 71 can be silicon oxide; the material of the gate 72 can be polysilicon.

[0075] Embodiments of this application also provide a power module, including a substrate and at least one semiconductor device as described in any embodiment of this application, wherein the substrate is used to support the semiconductor device. It has the same technical effects and will not be described again here.

[0076] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, wherein the semiconductor device is electrically connected to the circuit board. It has the same technical effects and will not be described again here.

[0077] According to another aspect of this application, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of this application, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load. It has the same technical effects and will not be described again here.

[0078] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region, a first region, a second region, and a drift region; the first region is configured with a first conductivity type and is located on the first surface, the well region is configured with a second conductivity type and is located on the side of the first region away from the first surface, the second region is configured with a second conductivity type and is located on the side of the well region away from the first surface, and the drift region is configured with a first conductivity type and is located on the side of the second region away from the first surface; the first conductivity type and the second conductivity type are different, and the first surface is provided with a trench, the trench including a first sub-trench and a second sub-trench located at the bottom of the first sub-trench; the semiconductor body further includes a third region, a fourth region, and a fifth region; the third region is configured with a first conductivity type and is located at the corner of the first sub-trench; the fourth region is configured with a second conductivity type and is located at the sidewall and corner of the second sub-trench; the fifth region is configured with a first conductivity type and is used to connect the drift region and the third region; wherein, the surface of the fourth region away from the second sub-trench is in contact with the third region and the fifth region; The dielectric layer is located in the second sub-trench; The gate is located in the first sub-trench; The source electrode is located on the first surface; The drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, characterized in that, It also includes a gate insulating layer located on the sidewall of the gate and the surface of the gate near the second surface; The gate insulating layer located on the side of the gate near the second surface is in contact with the dielectric layer.

3. The semiconductor device according to claim 1, characterized in that, The concentration of the first conductivity type doped ion in the third region is greater than the concentration of the first conductivity type doped ion in the fifth region.

4. The semiconductor device according to claim 1, characterized in that, The fourth region covers the sidewalls of the dielectric layer and at least a portion of the surface of the dielectric layer on the side away from the first surface; The third region is in contact with the fourth region located on the sidewall of the dielectric layer, and with the second region located on the side of the third region away from the dielectric layer; The fifth region is in contact with the fourth region located on the side of the dielectric layer away from the first surface, and with the second region located on the side of the fifth region away from the dielectric layer.

5. The semiconductor device according to claim 4, characterized in that, The fourth region covers the sidewalls on both sides of the dielectric layer, as well as the portion of the surface of the dielectric layer located at the two opposite corners of the second sub-trench.

6. The semiconductor device according to claim 1, characterized in that, The width of the first sub-groove is greater than the width of the second sub-groove; The first sub-groove extends from the first surface to the second surface to at least penetrate the well region; the distance from the bottom surface of the second sub-groove to the second surface is less than the distance from the second region to the second surface.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor body also includes: A sixth region is located on the first surface and on the side of the first region away from the trench; the sixth region is configured with a second conductivity type and is in contact with the source electrode.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The semiconductor body also includes: Substrate: The first epitaxial layer, configured with a first conductivity type, is located on one side of the substrate; The second epitaxial layer, configured as a second semiconductor type, is located on the side of the first epitaxial layer away from the substrate; The third epitaxial layer, configured as a second semiconductor type, is located on the side of the second epitaxial layer away from the substrate; The first region and the well region are disposed in the third epitaxial layer; the second region, the third region, the fourth region and at least part of the fifth region are all disposed in the second epitaxial layer.

9. A method for fabricating a semiconductor device, characterized in that, Used to prepare the semiconductor device according to any one of claims 1 to 8; include, A semiconductor body is formed, and a trench is formed on a first surface of the semiconductor body. The semiconductor body includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region, a first region, a second region, and a drift region. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The second region is configured with a second conductivity type and is located on the side of the well region away from the first surface. The drift region is configured with a first conductivity type and is located on the side of the second region away from the first surface. The first conductivity type and the second conductivity type are different. The trench includes a first sub-trench and a second sub-trench located at the bottom of the first sub-trench. The semiconductor body also includes a third region, a fourth region, and a fifth region. The third region is configured with a first conductivity type and is located at the corner of the first sub-trench. The fourth region is configured with a second conductivity type and is located at the sidewall and corner of the second sub-trench. The fifth region is configured with a first conductivity type and is used to connect the drift region and the third region. The surface of the fourth region away from the second sub-trench is in contact with the third region and the fifth region. A dielectric layer is formed in the second sub-trench; A gate is formed in the first sub-trench; A source electrode is formed on the first surface; The second surface forms the drain electrode.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, Forming a semiconductor body and forming a trench on a first surface of the semiconductor body includes: Provide substrate; A first epitaxial layer is formed on one side of the substrate; the first epitaxial layer is configured with a first conductivity type; A second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate; the second epitaxial layer is configured with a second conductivity type; A third epitaxial layer is formed on the side of the second epitaxial layer away from the substrate; the third epitaxial layer is configured with a second conductivity type; The first region and the well region are formed in the third epitaxial layer; The trench is formed on the side of the third epitaxial layer away from the substrate, and the second region, the third region, the fourth region and the fifth region are formed in the second epitaxial layer.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The first region and the well region are formed in the third epitaxial layer, including: The first region is formed from the surface of the third epitaxial layer on the side away from the substrate; wherein the third epitaxial layer located between the first region and the second epitaxial layer serves as the well region; The process of forming the trench on the side of the third epitaxial layer away from the substrate, and forming the second region, the third region, the fourth region, and the fifth region in the second epitaxial layer, includes: A mask layer is formed on the side of the third epitaxial layer away from the substrate, and the mask layer is patterned. Based on the patterned mask layer, a first sub-trench is formed on the surface of the third epitaxial layer away from the substrate, and the first sub-trench penetrates the first region and the well region; A first spacer layer is formed on the sidewall of the first sub-trench, and a third initial region is formed at the bottom and corner of the first sub-trench based on the patterned mask layer and the first spacer layer. A second sub-groove is formed at the bottom of the first sub-groove, and the second sub-groove penetrates the third initial region; A fifth initial region is formed at the bottom of the second sub-trench, and the fifth initial region extends to connect with the third initial region; A second spacer layer is formed on the side of the first spacer layer away from the sidewall of the first sub-groove and on the sidewall of the second sub-groove; A third spacer layer is formed in the remaining space of the first sub-groove and the second sub-groove; the third spacer layer and the first spacer layer are both made of different materials than the second spacer layer; The second spacer layer is removed, forming a fourth region on the exposed sidewalls and bottom of the second sub-trench; wherein the region outside the fourth region in the third initial region forms the third region, and the region outside the fourth region in the fifth initial region forms the fifth region; Remove the third spacer layer and the second spacer layer.

12. A power module, characterized in that, It includes a substrate and at least one semiconductor device as described in any one of claims 1 to 8, wherein the substrate is used to support the semiconductor device.

13. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1 to 8, wherein the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 13, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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