Groove type silicon carbide MOSFET device and preparation method thereof

Abstract

According to the trench gate silicon carbide MOSFET device and the preparation method thereof, a source electrode step trench and a P-type shielding layer are introduced to form a follow current nMOS together with a CSL region, a P-type base region and an N-type ohmic contact region, and form a self-bias pMOS together with the CSL region, the P-type base region and a P-type ohmic contact region. During reverse conduction, the source trench freewheeling nMOS is conducted, bipolar conduction of the body diode is inhibited, and the long-term working reliability of the device is improved; in a short-circuit state, the pMOS is started, the P-type shielding layer is grounded, the depletion region is rapidly expanded, pinch-off is formed with the depletion region of the P-type shielding region at the bottom of the trench gate, a current path is limited, saturation current is reduced, and the short-circuit capability of the device is improved; and in a blocking state, the pMOS is opened, and the P-type shielding layer is grounded, so that the electric field intensity of the oxide layer is effectively reduced. According to the invention, the forward conduction capability and low switching loss of the device are ensured, the short circuit and third quadrant capability of the device is improved, and the transient robustness of the device is obviously improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically to a trench-gate silicon carbide MOSFET device and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) is a representative of third-generation semiconductor materials, possessing characteristics such as a large bandgap, high critical avalanche breakdown field strength, high thermal conductivity, and strong radiation resistance, making it a promising candidate for high-voltage, high-power power electronic systems. MOSFETs are the most widely used gate-controlled device structure among SiC power devices. Because SiC MOSFETs operate on a unipolar transport mechanism, only one type of charge carrier (electrons or holes) conducts electricity, eliminating charge storage effects. Therefore, compared to bipolar devices, they exhibit lower switching losses and higher frequency characteristics. Furthermore, their low on-resistance and excellent high-temperature characteristics make SiC MOSFETs a highly competitive new generation of low-loss power devices.

[0003] Currently, commercially available silicon carbide MOSFETs mainly fall into two structural types: trench and planar. Trench-type silicon carbide MOSFETs, due to their higher channel density and channel mobility, exhibit lower conduction losses and represent an important development direction for silicon carbide MOSFETs. Compared to Si-based devices, silicon carbide MOSFETs not only have smaller chip areas and higher current densities, but also poorer forward current saturation characteristics. This results in a short-circuit peak current that is 6 times or more of the rated current, while that of Si IGBTs is only about 4 times. Therefore, the short-circuit withstand time of silicon carbide MOSFET devices is more than half that of Si IGBTs.

[0004] Furthermore, due to the high forward PN junction voltage drop of silicon carbide bulk diodes, silicon carbide MOSFETs will generate higher power consumption when reverse biased. Long-term use will also lead to their unique bipolar degradation problem, affecting the efficiency and reliability of power electronic systems. The current mainstream solution is to connect an external silicon carbide Schottky barrier diode (SBD) in parallel, but this method is subject to parasitic inductance and increases cost and size. Summary of the Invention

[0005] To address the aforementioned issues, this invention proposes a trench-gate silicon carbide MOSFET device and its fabrication method. By introducing a source-stepped trench and a P-type shielding layer, a self-biased pMOS is formed together with the CSL region, P-base region, and P-type ohmic contact region. A freewheeling nMOS is formed together with the CSL region, P-base region, and N-type ohmic contact region. In reverse conduction, the source-trench freewheeling nMOS conducts, suppressing bipolar conduction of the body diode and improving the long-term reliability of the device. In short-circuit state, the pMOS is turned on, the P-type shielding layer is grounded, and the depletion region rapidly widens, forming a pinch-off with the depletion region of the P-type shielding region at the bottom of the trench gate, limiting the current path, reducing saturation current, and improving the device's short-circuit capability. In blocking state, the pMOS is turned on, the P-type shielding layer is grounded, effectively reducing the oxide layer electric field strength. In forward conduction, the pMOS is turned off, the P-type shielding layer floats, reducing the JFET resistance caused by grounding the P+ shielding layer, and optimizing the device's on-resistance and dynamic conduction loss. This invention improves the device's short-circuit and third-quadrant capabilities while maintaining forward conduction capability and low switching losses, significantly enhancing its transient robustness. To achieve the above objectives, this invention employs the following technical solution:

[0006] A trench-type silicon carbide MOSFET device includes: a drain metal 12, an N-type substrate 11 above the drain metal 12, an N-type buffer layer 10 above the N-type substrate 11, an N-drift region 9 above the N-drift region 10, and an N-type current spreading layer 8 above the N-drift region 9; a first groove, a second groove, and a third groove are sequentially provided on the upper left side, the upper center, and the upper right side of the N-type current spreading layer 8.

[0007] The first groove forms a first source trench. The first groove contains a first source trench polysilicon 5 and a first source trench dielectric 6 filling the first groove. Below the first groove is a first P+ shielding layer 7, and to the right of the first groove is a first P-type base region 4. Above the left of the first P-type base region 4 is a first N+ ohmic contact region 2, above the center of the first P-type base region 4 is a first P+ ohmic contact region 3, and above the right of the first P-type base region 4 is a second N+ ohmic contact region 13. The first P-type base region 4, the first N+ ohmic contact region 2, the first P+ ohmic contact region 3, and the second N+ ohmic contact region 13 are all located between the first groove and the second groove.

[0008] The second groove contains a gate trench polysilicon 15 and a gate dielectric 14 filling the second groove. Below the second groove is a second P+ shielding layer 16, and above the second groove is an insulating dielectric 18.

[0009] The third groove forms the second source trench. The third groove contains the second source trench polysilicon 22 and the second source trench dielectric 23 filling the third groove. Below the third groove is the third P+ shielding layer 24. To the left of the third groove is the second P-type base region 21. Above the left of the second P-type base region 21 is the third N+ ohm contact region 17. Above the center of the first P-type base region 21 is the second P+ ohm contact region 20. Above the right of the second P-type base region 21 is the fourth N+ ohm contact region 19. The second P-type base region 21, the third N+ ohm contact region 17, the second P+ ohm contact region 20, and the fourth N+ ohm contact region 19 are all located between the second groove and the third groove.

[0010] The source metal 1 is located above the first N+ ohm contact region 2, the first P+ ohm contact region 3, the second N+ ohm contact region 13, the third N+ ohm contact region 17, the fourth N+ ohm contact region 19, and the second P+ ohm contact region 20.

[0011] As a preferred embodiment, the first source trench medium 6, the gate medium 14, and the second source trench medium 23 are SiO2.

[0012] As a preferred embodiment, the first source trench and the second source trench are two-stage stepped trenches, formed by two etching processes. The second etching is performed at the bottom of the trench formed by the first etching, and the width of the second etched trench is narrower and the depth is shallower than that of the first etched trench.

[0013] As a preferred embodiment, the first N+ ohmic contact region 2, the first P+ ohmic contact region 3, the first P-type base region 4, the first P+ shielding layer 7, the N-type current spreading layer 8, the second N+ ohmic contact region 13, the second P+ shielding layer 16, the third N+ ohmic contact region 17, the fourth N+ ohmic contact region 19, the second P+ ohmic contact region 20, the second P-type base region 21, and the third P+ shielding layer 24 are all formed by multiple ion implantations.

[0014] As a preferred embodiment, the first P+ shielding layer 7 and the third P+ shielding layer 24 are formed by ion implantation after the formation of the secondary step source trench.

[0015] As a preferred embodiment, the materials of the first N+ ohmic contact region 2, the first P+ ohmic contact region 3, the first P-type base region 4, the first P+ shielding layer 7, the N-type current spreading layer 8, the N- drift region 9, the N-type buffer layer 10, the N+ substrate 11, the second N+ ohmic contact region 13, the second P+ shielding layer 16, the third N+ ohmic contact region 17, the fourth N+ ohmic contact region 19, the second P+ ohmic contact region 20, the second P-type base region 21, and the third P+ shielding layer 24 are all silicon carbide.

[0016] As a preferred embodiment, the second P+ shielding layer 16 is short-circuited to the emitter, and the first P+ shielding layer 7 and the third P+ shielding layer 24 are in a floating state.

[0017] A second objective of this invention is to provide a method for manufacturing the trench-gate silicon carbide MOSFET device, comprising the following steps:

[0018] Step 1: Clean the epitaxial wafer, and form a current spreading layer by epitaxy or N-type ion implantation on the N-type drift region;

[0019] Step 2: Ion implantation to form a P-type base region;

[0020] Step 3: Aluminum ion implantation to form the P+ ohmic contact region;

[0021] Step 4: Inject nitrogen ions to form an N+ ohmic contact region and activate annealing;

[0022] Step 6: Etch the gate trench and source trench, and etch again at the source trench location to form a secondary stepped source trench;

[0023] Step 7: Aluminum ion implantation is performed at the bottom of the etched gate trench and the secondary step source trench to form a P+ shielding layer;

[0024] Step 6: Dry oxygen oxidation to generate a gate oxide layer, followed by annealing and deposition of polysilicon in a nitrogen atmosphere;

[0025] Step 7: Deposit interlayer dielectric and perform etching;

[0026] Step 8: Etch source contact holes, deposit metal, and alloy; etch gate contact holes, deposit metal, and alloy; deposit metal on the back side and alloy.

[0027] This invention introduces a source-stepped trench and a P-type shielding layer, which together with the CSL region, P-base region, and P-type ohmic contact region form a self-biased pMOS, and together with the CSL region, P-base region, and N-type ohmic contact region form a freewheeling nMOS. In the third quadrant state, the source-trench freewheeling nMOS is turned on, effectively suppressing the bipolar conduction of the body diode, reducing the on-state voltage drop in the third quadrant, improving the bipolar degradation effect of silicon carbide devices, and effectively improving the long-term reliability of the device. In the short-circuit state, the pMOS is turned on, the P-type shielding layer is grounded, the depletion region widens rapidly, and forms a pinch-off with the depletion region of the P-type shielding region at the bottom of the trench gate, limiting the current path, reducing the saturation current, and improving the short-circuit capability of the device. In the blocking state, the pMOS is turned on, the P-type shielding layer is grounded, effectively reducing the oxide electric field strength. In forward conduction, the pMOS is turned off, the P-type shielding layer is floating, reducing the JFET resistance caused by the grounding of the device's P+ shielding layer, and optimizing the device's on-resistance and dynamic conduction loss. This invention improves the device's short-circuit and third-quadrant capabilities while ensuring forward conduction capability and low switching losses, thus significantly enhancing the device's transient robustness. Attached Figure Description

[0028] Figure 1 This is a cross-sectional view of a silicon carbide semiconductor device in an embodiment of the present invention.

[0029] Figure 2 This is a schematic diagram of the three-quadrant characteristics of a silicon carbide semiconductor device in an embodiment of the present invention.

[0030] Figure 3 This is a schematic diagram of the short-circuit current and peak temperature of the silicon carbide semiconductor device in an embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram of ion implantation in the current spreading layer of a silicon carbide semiconductor device according to an embodiment of the present invention.

[0032] Figure 5 This is a schematic diagram of aluminum ion implantation to form a P-type base region in a silicon carbide semiconductor device according to an embodiment of the present invention.

[0033] Figure 6 This is a schematic diagram of the formation of a P+ ohmic contact region by aluminum ion implantation in a silicon carbide semiconductor device according to an embodiment of the present invention.

[0034] Figure 7 This is a schematic diagram of nitrogen ion implantation to form an N+ ohmic contact region and activation annealing in a silicon carbide semiconductor device according to an embodiment of the present invention.

[0035] Figure 8 This is a schematic diagram of etching the gate trench and source trench of the silicon carbide semiconductor device in the embodiment of the present invention, and then etching again at the source trench location to form a secondary stepped source trench.

[0036] Figure 9 This is a schematic diagram of aluminum ion implantation to form a P+ shielding layer at the bottom of the etching trench and the secondary step source trench of the silicon carbide semiconductor device in an embodiment of the present invention.

[0037] Figure 10 This is a schematic diagram of the oxidation of a silicon carbide semiconductor device to form a gate oxide layer and the deposition of polysilicon in an embodiment of the present invention.

[0038] Figure 11 A schematic diagram of the deposition and etching of the interlayer dielectric of a silicon carbide semiconductor device in an embodiment of the present invention.

[0039] Figure 12 A schematic diagram of the source, gate, and drain contacts of a silicon carbide semiconductor device in an embodiment of the present invention.

[0040] In the figure, 1 is the source metal, 2 is the first N+ ohmic contact region, 3 is the first P+ ohmic contact region, 4 is the first P-type base region, 5 is the first source trench polysilicon, 6 is the first source trench dielectric, 7 is the first P+ shielding layer, 8 is the N-type current spreading layer, 9 is the N- drift region, 10 is the N-type buffer layer, 11 is the N+ substrate, 12 is the drain metal, 13 is the second N+ ohmic contact region, 14 is the gate dielectric, 15 is the gate trench polysilicon, 16 is the second P+ shielding layer, 17 is the third N+ ohmic contact region, 18 is the insulating dielectric, 19 is the fourth N+ ohmic contact region, 20 is the second P+ ohmic contact region, 21 is the second P-type base region, 22 is the second source trench polysilicon, 23 is the second source trench dielectric, and 24 is the third P+ shielding layer. Detailed Implementation

[0041] The principles and characteristics of the present invention will now be described in detail with reference to the accompanying drawings of specific embodiments.

[0042] In the accompanying drawings, the same reference numerals denote the same structures. The silicon carbide MOSFET device provided by this invention can be an N-channel MOSFET device or a P-channel MOSFET device. The following description uses an N-channel MOSFET device. Those skilled in the art will be able to understand the structure and working principle of the P-channel device based on the disclosure of the N-channel MOSFET device.

[0043] Example:

[0044] This embodiment provides a trench-type silicon carbide MOSFET device, the cross-sectional view of which is shown below. Figure 1 As shown, it includes: a drain metal 12, an N-type substrate 11 above the drain metal 12, an N-type buffer layer 10 above the N-type substrate 11, an N-drift region 9 above the N-drift region 10, and an N-type current spreading layer 8 above the N-drift region 9; a first groove, a second groove, and a third groove are sequentially provided on the upper left side, the upper center, and the upper right side of the N-type current spreading layer 8.

[0045] The first groove forms a first source trench. The first groove contains a first source trench polysilicon 5 and a first source trench dielectric 6 filling the first groove. Below the first groove is a first P+ shielding layer 7, and to the right of the first groove is a first P-type base region 4. Above the left of the first P-type base region 4 is a first N+ ohmic contact region 2, above the center of the first P-type base region 4 is a first P+ ohmic contact region 3, and above the right of the first P-type base region 4 is a second N+ ohmic contact region 13. The first P-type base region 4, the first N+ ohmic contact region 2, the first P+ ohmic contact region 3, and the second N+ ohmic contact region 13 are all located between the first groove and the second groove.

[0046] The second groove contains a gate trench polysilicon 15 and a gate dielectric 14 filling the second groove. Below the second groove is a second P+ shielding layer 16, and above the second groove is an insulating dielectric 18.

[0047] The third groove forms the second source trench. The third groove contains the second source trench polysilicon 22 and the second source trench dielectric 23 filling the third groove. Below the third groove is the third P+ shielding layer 24. To the left of the third groove is the second P-type base region 21. Above the left of the second P-type base region 21 is the third N+ ohm contact region 17. Above the center of the first P-type base region 21 is the second P+ ohm contact region 20. Above the right of the second P-type base region 21 is the fourth N+ ohm contact region 19. The second P-type base region 21, the third N+ ohm contact region 17, the second P+ ohm contact region 20, and the fourth N+ ohm contact region 19 are all located between the second groove and the third groove.

[0048] The source metal 1 is located above the first N+ ohm contact region 2, the first P+ ohm contact region 3, the second N+ ohm contact region 13, the third N+ ohm contact region 17, the fourth N+ ohm contact region 19, and the second P+ ohm contact region 20.

[0049] As a preferred embodiment, the first source trench medium 6, the gate medium 14, and the second source trench medium 23 are SiO2.

[0050] As a preferred embodiment, the first source trench and the second source trench are two-stage stepped trenches, formed by two etching processes. The second etching is performed at the bottom of the trench formed by the first etching, and the width of the second etched trench is narrower and the depth is shallower than that of the first etched trench.

[0051] As a preferred embodiment, the first N+ ohmic contact region 2, the first P+ ohmic contact region 3, the first P-type base region 4, the first P+ shielding layer 7, the N-type current spreading layer 8, the second N+ ohmic contact region 13, the second P+ shielding layer 16, the third N+ ohmic contact region 17, the fourth N+ ohmic contact region 19, the second P+ ohmic contact region 20, the second P-type base region 21, and the third P+ shielding layer 24 are all formed by multiple ion implantations.

[0052] As a preferred embodiment, the first P+ shielding layer 7 and the third P+ shielding layer 24 are formed by ion implantation after the formation of the secondary step source trench.

[0053] As a preferred embodiment, the materials of the first N+ ohmic contact region 2, the first P+ ohmic contact region 3, the first P-type base region 4, the first P+ shielding layer 7, the N-type current spreading layer 8, the N- drift region 9, the N-type buffer layer 10, the N+ substrate 11, the second N+ ohmic contact region 13, the second P+ shielding layer 16, the third N+ ohmic contact region 17, the fourth N+ ohmic contact region 19, the second P+ ohmic contact region 20, the second P-type base region 21, and the third P+ shielding layer 24 are all silicon carbide.

[0054] As a preferred embodiment, the second P+ shielding layer 16 is short-circuited to the emitter, and the first P+ shielding layer 7 and the third P+ shielding layer 24 are in a floating state.

[0055] This embodiment also provides a method for manufacturing the trench-gate silicon carbide MOSFET device, comprising the following steps:

[0056] Step 1: Clean the epitaxial wafer, and form a current-spreading layer by epitaxy or N-type ion implantation on the N-type drift region; such as Figure 4 As shown;

[0057] Step 2: Ion implantation to form a P-type base region; such as... Figure 5 As shown;

[0058] Step 3: Aluminum ion implantation forms the P+ ohmic contact region; such as... Figure 6 As shown;

[0059] Step 4: Inject nitrogen ions to form an N+ ohmic contact region and activate annealing; such as Figure 7 As shown;

[0060] Step 6: Etch the gate trenches and source trenches, and then etch again at the source trench locations to form secondary stepped source trenches; such as Figure 8 As shown;

[0061] Step 7: Perform aluminum ion implantation at the bottom of the etched gate trench and the secondary step source trench to form a P+ shielding layer; such as Figure 9 As shown;

[0062] Step 6: Dry oxygen oxidation to form a gate oxide layer, followed by annealing and deposition of polysilicon under a nitrogen atmosphere; such as Figure 10 As shown;

[0063] Step 7: Deposit interlayer dielectric and perform etching; such as Figure 11 As shown;

[0064] Step 8: Etch source contact holes, deposit metal, and alloy; etch gate contact holes, deposit metal, and alloy; deposit metal on the back side and alloy. (Example:) Figure 12 As shown;

[0065] The working principle of the device of the present invention will be explained using an N-type silicon carbide MOSFET as an example:

[0066] To suppress bipolar conduction of the body diode in silicon carbide MOSFETs and reduce the on-state voltage drop in the third quadrant, the trench-type silicon carbide MOSFET of this invention introduces a source stepped trench and a P-type shielding layer, which together with the CSL region, P-base region and N-type ohmic contact region form a freewheeling nMOS. When reverse turn-on, the freewheeling nMOS has a lower turn-on voltage, suppressing body diode conduction, improving the bipolar degradation effect of silicon carbide devices, and effectively improving the long-term operational reliability of the device.

[0067] To improve the oxide layer reliability of silicon carbide MOSFET devices while ensuring forward conduction capability and low switching losses, the trench-type silicon carbide MOSFET of this invention introduces a source stepped trench and a P-type shielding layer, forming a self-biased pMOS with the CSL region, P-base region, and P-type ohmic contact region. In the forward conduction state, the P-type shielding layer is in a floating state, reducing the JFET resistance caused by grounding the P+ shielding layer, and optimizing the device's on-resistance and dynamic switching losses. In the blocking state, the pMOS is turned on, the P-type shielding layer is grounded, effectively reducing the oxide layer electric field strength and improving the device's oxide layer reliability.

[0068] To improve the short-circuit withstand time of silicon carbide MOSFETs, the trench-type silicon carbide MOSFET of the present invention introduces a self-biased pMOS and a P-type shielding region at the bottom of the trench gate. When the pMOS is turned on and the P-type shielding layer is grounded, the depletion region widens rapidly, forming a pinch-off with the depletion region of the P-type shielding region at the bottom of the trench gate, limiting the current path, reducing the saturation current, and effectively improving the short-circuit capability of the device.

Claims

1. A trench-type silicon carbide MOSFET device, characterized in that, include: Drain metal (12), N-type substrate (11) above drain metal (12), N-type buffer layer (10) above N-type substrate (11), N-drift region (9) above N-drift region (9), N-type current extension layer (8) above N-drift region (9); the left side, center and right side of the upper part of the N-type current extension layer (8) are provided with a first groove, a second groove and a third groove respectively; The first groove forms a first source trench. The first groove contains a first source trench polysilicon (5) and a first source trench dielectric (6) filling the first groove. Below the first groove is a first P+ shielding layer (7). To the right of the first groove is a first P-type base region (4). Above the left of the first P-type base region (4) is a first N+ ohmic contact region (2). Above the center of the first P-type base region (4) is a first P+ ohmic contact region (3). Above the right of the first P-type base region (4) is a second N+ ohmic contact region (13). The first P-type base region (4), the first N+ ohmic contact region (2), the first P+ ohmic contact region (3), and the second N+ ohmic contact region (13) are all located between the first groove and the second groove. The second groove contains a gate trench polysilicon (15) and a gate dielectric (14) filling the second groove. Below the second groove is a second P+ shielding layer (16), and above the second groove is an insulating dielectric (18). The third groove forms the second source trench. The third groove contains the second source trench polysilicon (22) and the second source trench dielectric (23) filling the third groove. Below the third groove is the third P+ shielding layer (24). To the left of the third groove is the second P-type base region (21). Above the second P-type base region (21) to the left is the third N+ ohmic contact region (17). Above the first P-type base region (21) to the center is the second P+ ohmic contact region (20). Above the second P-type base region (21) to the right is the fourth N+ ohmic contact region (19). The second P-type base region (21), the third N+ ohmic contact region (17), the second P+ ohmic contact region (20), and the fourth N+ ohmic contact region (19) are all located between the second groove and the third groove. The source metal (1) is located above the first N+ ohm contact region (2), the first P+ ohm contact region (3), the second N+ ohm contact region (13), the third N+ ohm contact region (17), the fourth N+ ohm contact region (19), and the second P+ ohm contact region (20).

2. The trench-type silicon carbide MOSFET device according to claim 1, characterized in that: The first source trench medium (6), the gate medium (14), and the second source trench medium (23) are SiO2.

3. The trench-type silicon carbide MOSFET device according to claim 1, characterized in that: The first and second source trenches are two-stage stepped trenches, formed by two etching processes. The second etching is performed at the bottom of the trench formed by the first etching, and the width of the second etched trench is narrower and the depth is shallower than that of the first etched trench.

4. A trench-type silicon carbide MOSFET device according to claim 1, characterized in that: The first N+ ohmic contact region (2), the first P+ ohmic contact region (3), the first P-type base region (4), the first P+ shielding layer (7), the N-type current spreading layer (8), the second N+ ohmic contact region (13), the second P+ shielding layer (16), the third N+ ohmic contact region (17), the fourth N+ ohmic contact region (19), the second P+ ohmic contact region (20), the second P-type base region (21), and the third P+ shielding layer (24) are all formed by multiple ion implantations.

5. A trench-type silicon carbide MOSFET device according to claim 1, characterized in that: The first P+ shielding layer (7) and the third P+ shielding layer (24) are formed by ion implantation after the formation of the secondary step source trench.

6. A trench-type silicon carbide MOSFET device according to claim 1, characterized in that: The materials of the first N+ ohmic contact region (2), the first P+ ohmic contact region (3), the first P-type base region (4), the first P+ shielding layer (7), the N-type current spreading layer (8), the N- drift region (9), the N-type buffer layer (10), the N+ substrate (11), the second N+ ohmic contact region (13), the second P+ shielding layer (16), the third N+ ohmic contact region (17), the fourth N+ ohmic contact region (19), the second P+ ohmic contact region (20), the second P-type base region (21), and the third P+ shielding layer (24) are all silicon carbide.

7. A trench-type silicon carbide MOSFET device according to claim 1, characterized in that: The second P+ shielding layer (16) is short-circuited to the emitter, and the first P+ shielding layer (7) and the third P+ shielding layer (24) are in a floating state.

8. The method for fabricating a trench-type silicon carbide MOSFET device according to any one of claims 1 to 7, characterized in that, Includes the following steps: Step 1: Clean the epitaxial wafer, and form a current spreading layer by epitaxy or N-type ion implantation on the N-type drift region; Step 2: Ion implantation to form a P-type base region; Step 3: Aluminum ion implantation to form the P+ ohmic contact region; Step 4: Inject nitrogen ions to form an N+ ohmic contact region and activate annealing; Step 6: Etch the gate trench and source trench, and etch again at the source trench location to form a secondary stepped source trench; Step 7: Aluminum ion implantation is performed at the bottom of the etched gate trench and the secondary step source trench to form a P+ shielding layer; Step 6: Dry oxygen oxidation to generate a gate oxide layer, followed by annealing and deposition of polysilicon in a nitrogen atmosphere; Step 7: Deposit interlayer dielectric and perform etching; Step 8: Etch source contact holes, deposit metal, and alloy; etch gate contact holes, deposit metal, and alloy; deposit metal on the back side and alloy.

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