A non-volatile non-monotonic neuron device and a method of manufacturing the same
By constructing neuronal devices with p-type and n-type two-dimensional semiconductor heterojunctions and floating gate structures, the problems of non-monotonic response, non-volatile memory, and fully optically controlled synaptic plasticity in existing technologies have been solved, realizing a high-efficiency, low-power biosignal compatible neuronal device suitable for edge devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN HOTCHIP TECH
- Filing Date
- 2026-04-10
- Publication Date
- 2026-06-26
Smart Images
Figure CN122069760B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of artificial neuron device technology, and in particular to a non-volatile, non-monotonic neuron device and its fabrication method. Background Technology
[0002] With the rapid development of artificial intelligence, the Internet of Things, and edge computing, the demand for high-energy-efficiency hardware capable of simulating biological nervous systems is becoming increasingly urgent. Biological neurons possess unique non-monotonic response characteristics, exhibiting a maximum response to moderately strong input signals and a diminished response to excessively strong or weak signals, while also possessing synaptic plasticity and memory functions. How to efficiently implement these functions at the hardware level is currently a research hotspot in the field of neuromorphic computing.
[0003] Currently, non-monotonic neurons are mostly implemented based on silicon-based CMOS circuits or multi-transistor combinations, which suffer from problems such as low integration density, high power consumption, and slow response speed. In recent years, although some research has attempted to construct synaptic devices using two-dimensional materials, the following problems still exist:
[0004] Monotonic response: Existing two-dimensional material synaptic devices have multidimensional monotonic responses (conductance increases or decreases monotonically with increasing stimulation), which cannot simulate the non-monotonic response characteristics of biological neurons and cannot process medium-intensity signals (such as normal heart rate and blood pressure range).
[0005] Lack of non-volatility: Some two-dimensional material synaptic devices rely on charge traps or defect states to achieve short-term memory, and the charge retention time is short, making it difficult to achieve long-term memory and unsupervised learning;
[0006] Insufficient optical or all-optical modulation capabilities: Existing devices mainly rely on electrical signal modulation, which has a weak response to optical signals and makes it difficult to achieve all-optical control of synaptic plasticity;
[0007] Complex device structure: To realize memory and computing functions, external storage units or complex circuits are required to achieve memory functions. The system is highly complex, which leads to complex manufacturing processes and high costs.
[0008] High energy consumption: Traditional silicon-based devices or multi-transistor structures consume a lot of power, making them difficult to use in portable or implantable devices;
[0009] Lack of biosignal compatibility: It cannot directly process physiological signals and requires additional analog-to-digital conversion and preprocessing circuits;
[0010] In summary, existing technologies have not yet provided a neuronal device that is simple in structure, highly energy-efficient, possesses non-monotonic response and non-volatile memory functions, and is compatible with biological signals. Therefore, we propose a non-volatile non-monotonic neuronal device and its fabrication method. Summary of the Invention
[0011] The purpose of this invention is to provide a non-volatile, non-monotonic neuron device and its fabrication method to solve the problems mentioned in the background art.
[0012] To achieve the above objectives, the present invention provides the following technical solution: a non-volatile, non-monotonic neuron device, comprising:
[0013] Substrate;
[0014] A floating gate structure, wherein the floating gate structure is disposed on the substrate;
[0015] A two-dimensional material heterojunction is disposed on the side of a floating gate structure away from the substrate. The two-dimensional material heterojunction is composed of a semiconductor channel layer, which includes a bridging layer, a p-type two-dimensional semiconductor, and an n-type two-dimensional semiconductor. The p-type two-dimensional semiconductor is disposed on one side of the bridging layer, and the n-type two-dimensional semiconductor is disposed on the side of the bridging layer away from the p-type two-dimensional semiconductor. The bridging layer is used to form the cross-section of the heterojunction and realize the transport of charge carriers.
[0016] An electrode structure is provided, comprising a top electrode and a bottom electrode. The top electrode is disposed on the side of the floating gate structure away from the substrate and electrically connected to a two-dimensional material heterojunction. The bottom electrode is disposed on the side of the substrate away from the floating gate structure.
[0017] Preferably, the p-type two-dimensional semiconductor is made of black phosphorus material, the n-type two-dimensional semiconductor is made of WS2 material, and the bridging layer is made of PtSe2 material.
[0018] Preferably, the p-type two-dimensional semiconductor is made of WTe2 material, the n-type two-dimensional semiconductor is made of InSe material, and the bridging layer is made of graphene material.
[0019] Preferably, the top electrode is made of Pt, the bottom electrode is made of silicon back gate, and the floating gate structure includes:
[0020] A floating gate layer, wherein the floating gate layer is disposed on a substrate;
[0021] A dielectric layer is disposed between the floating gate layer and the two-dimensional material heterojunction.
[0022] Preferably, the floating gate layer is an HfZrO2 ferroelectric layer, and the dielectric layer is an Al2O3 layer.
[0023] Preferably, the floating gate layer is made of MoS2 nanocrystals, and the dielectric layer is made of HfO2.
[0024] On the other hand, the present invention also provides a method for fabricating a non-volatile, non-monotonic neuron device as described in any one of the above claims, characterized by comprising the following steps:
[0025] Step S1: Prepare a substrate in advance and fabricate a floating gate structure on the substrate;
[0026] Step S2: Sequentially transfer or grow p-type two-dimensional semiconductor material, bridging layer material and n-type two-dimensional semiconductor material on the floating gate structure to form a semiconductor channel layer having p-type semiconductor, bridging layer and n-type semiconductor;
[0027] Step S3: Prepare a top electrode on the semiconductor channel layer and prepare a bottom electrode on the substrate.
[0028] Preferably, in step S2, the p-type two-dimensional semiconductor material, the bridging layer material, and the n-type two-dimensional semiconductor material are directly grown on the floating gate structure using chemical vapor deposition (CVD) to form an integrated heterojunction channel layer.
[0029] Preferably, in step S2, p-type two-dimensional nanosheets, bridging layer nanosheets, and n-type two-dimensional nanosheets are prepared by liquid phase exfoliation and solution assembly methods, respectively, and then assembled on the floating gate structure by sequential spin coating or LB film method to form the semiconductor channel layer.
[0030] The technical effects and advantages of this invention are as follows:
[0031] The neuron device provided by this invention constructs a transistor with anti-bipolar characteristics by combining p-type two-dimensional semiconductors and n-type two-dimensional semiconductors with a bridging layer. Under gate voltage control, this structure can generate a bell-shaped response curve similar to that of a neuron to moderate intensity input. At the same time, the integrated floating gate structure endows the device with non-volatility, enabling it to simulate the long-term memory and synaptic plasticity of biological neurons. This realizes both computation and memory functions in a single device, greatly simplifying circuit design.
[0032] This invention uses HfZrO2 ferroelectric layer or MoS2 nanocrystals as charge storage layer in the floating gate structure, combined with HfO2 or Al2O3 dielectric layer, to achieve multi-level non-volatile storage through the residual polarization of ferroelectric materials or charge trapping of nanocrystals. It can still maintain multiple resistance states after power failure, supporting long-term memory and unsupervised learning.
[0033] The two-dimensional material used in this invention has excellent photoelectric response characteristics. The photogenerated carriers can modulate the channel conductivity, realize fully optically controlled synaptic plasticity, establish a photoelectric synergistic regulation mechanism, enable neuronal devices to support optical pulse or electrical pulse regulation, and realize the transformation from short-term plasticity to long-term plasticity.
[0034] This invention integrates the floating gate structure and the semiconductor channel into the same neuron device, which can simultaneously possess non-monotonic response and non-volatile storage functions, without the need for external storage units or complex feedback circuits, thereby greatly improving integration, simplifying the fabrication process, and reducing fabrication costs. Attached Figure Description
[0035] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention, but do not constitute a limitation thereof. In the drawings:
[0036] Figure 1 This is a schematic diagram of the neuron device structure of the present invention.
[0037] Figure 2 This is a graph showing the conductivity transfer characteristics of the semiconductor channel layer in this invention. Detailed Implementation
[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0039] This invention provides, for example Figures 1-2 This illustrates a non-volatile, non-monotonic neuronal device.
[0040] Example 1: Includes a substrate, a floating gate structure, a two-dimensional material heterojunction, and an electrode structure. The substrate is generally made of silicon oxide, which provides a flat and clean surface for the growth or transfer of upper-layer materials. Simultaneously, silicon oxide as a substrate isolates the back gate from the floating gate structure, preventing leakage. The floating gate structure is disposed on the substrate and includes a floating gate layer and a dielectric layer. The floating gate layer is disposed on the substrate, and the dielectric layer is disposed between the floating gate layer and the two-dimensional material heterojunction. The floating gate structure enables multi-level non-volatile storage, maintaining multiple resistance states even after power failure. It supports long-term memory and unsupervised learning, eliminating the need for external storage chips, reducing system complexity and data transfer power consumption. It is suitable for edge devices, retaining learning results after power failure and enabling instant startup. A two-dimensional material heterojunction is disposed on the side of the floating gate structure away from the substrate. The two-dimensional material heterojunction consists of a semiconductor channel layer, which includes a bridging layer, a p-type two-dimensional semiconductor, and an n-type two-dimensional semiconductor. The p-type two-dimensional semiconductor is disposed on one side of the bridging layer, and the n-type two-dimensional semiconductor is disposed on the side of the bridging layer away from the p-type two-dimensional semiconductor. The bridging layer is used to form the cross-section of the heterojunction and realize the transport of charge carriers. By combining the p-type two-dimensional semiconductor and the n-type two-dimensional semiconductor with the bridging layer, a transistor with anti-bipolar characteristics is constructed. Under gate voltage regulation, this transistor structure can generate a response similar to that of a neuron to moderate-intensity input. The device exhibits a bell-shaped (non-monotonic) response curve. Simultaneously, the integrated floating gate structure endows the device with non-volatility, enabling it to simulate the long-term memory and synaptic plasticity of biological neurons. This achieves simultaneous computation and memory functions in a single device, greatly simplifying circuit design. It addresses the problems of traditional silicon-based neuronal devices, such as complex structures (requiring multiple transistor combinations), singular response behavior (only monotonically increasing or decreasing), and the inability to simultaneously achieve non-monotonic response and non-volatile storage within a single device. Furthermore, it is suitable for physiological signal recognition (such as heart rate, blood pressure, and brain waves), automatically filtering abnormally high or low signals and improving the signal-to-noise ratio. The electrode structure includes a top electrode and a bottom electrode. The top electrode is located on the side of the floating gate structure away from the substrate and electrically connected to a two-dimensional material heterojunction. The bottom electrode is located on the side of the substrate away from the floating gate structure. The top electrode uses Pt and is mainly used for local fine-tuning of the semiconductor channel conductance, while the bottom electrode uses a silicon back gate and is mainly used for global coarse-tuning.
[0041] It should be noted that the p-type two-dimensional semiconductor uses black phosphorus (BP) material, the n-type two-dimensional semiconductor uses WS2 material, and the bridging layer uses PtSe2 material; this enables the formation of a BP-PtSe2-WS2 heterojunction system in the neuronal device. The black phosphorus (BP) material of the p-type two-dimensional semiconductor has high hole mobility and a direct bandgap, while the WS2 material of the n-type two-dimensional semiconductor has high electron mobility and strong photoluminescence properties. The PtSe2 material of the bridging layer, as a transition metal chalcogenide, has a work function between BP and WS2, which can form a heterojunction with energy level matching. At the same time, the valence band top of BP material is close to that of PtSe2 material, which can form an ohmic contact for holes. Meanwhile, the conduction band bottom of PtSe2 material and the conduction band bottom of WS2 material form a high barrier, which can block the back diffusion of electrons. Thus, the two-dimensional material heterojunction as a whole forms an interlaced energy band alignment, which is conducive to the spatial separation of electrons and holes and reduces recombination. In addition, both BP and WS2 are direct bandgap semiconductors with high light absorption coefficients, which are suitable for photoelectric synergistic modulation.
[0042] Example 2: Includes a substrate, a floating gate structure, a two-dimensional material heterojunction, and an electrode structure. The substrate is generally made of silicon oxide, which provides a flat and clean surface for the growth or transfer of upper-layer materials. Simultaneously, silicon oxide as a substrate isolates the back gate from the floating gate structure, preventing leakage. The floating gate structure is disposed on the substrate and includes a floating gate layer and a dielectric layer. The floating gate layer is disposed on the substrate, and the dielectric layer is disposed between the floating gate layer and the two-dimensional material heterojunction. The floating gate structure enables multi-level non-volatile storage, maintaining multiple resistance states even after power failure. It supports long-term memory and unsupervised learning, eliminating the need for external storage chips, reducing system complexity and data transfer power consumption. It is suitable for edge devices, retaining learning results after power failure and enabling immediate startup. A two-dimensional material heterojunction is disposed on the side of the floating gate structure away from the substrate. The two-dimensional material heterojunction consists of a semiconductor channel layer, which includes a bridging layer, a p-type two-dimensional semiconductor, and an n-type two-dimensional semiconductor. The p-type two-dimensional semiconductor is disposed on one side of the bridging layer, and the n-type two-dimensional semiconductor is disposed on the side of the bridging layer away from the p-type two-dimensional semiconductor. The bridging layer is used to form the cross-section of the heterojunction and realize the transport of charge carriers. By combining the p-type two-dimensional semiconductor and the n-type two-dimensional semiconductor with the bridging layer, a transistor with anti-bipolar characteristics is constructed. Under gate voltage regulation, this transistor structure can generate a response similar to that of a neuron to moderate-intensity input. The device exhibits a bell-shaped (non-monotonic) response curve. Simultaneously, the integrated floating gate structure endows the device with non-volatility, enabling it to simulate the long-term memory and synaptic plasticity of biological neurons. This achieves simultaneous computation and memory functions in a single device, greatly simplifying circuit design. It addresses the problems of traditional silicon-based neuronal devices, such as complex structures (requiring multiple transistor combinations), singular response behavior (only monotonically increasing or decreasing), and the inability to simultaneously achieve non-monotonic response and non-volatile storage within a single device. Furthermore, it is suitable for physiological signal recognition (such as heart rate, blood pressure, and brain waves), automatically filtering abnormally high or low signals and improving the signal-to-noise ratio. The electrode structure includes a top electrode and a bottom electrode. The top electrode is located on the side of the floating gate structure away from the substrate and electrically connected to a two-dimensional material heterojunction. The bottom electrode is located on the side of the substrate away from the floating gate structure. The top electrode uses Pt and is mainly used for local fine-tuning of the semiconductor channel conductance, while the bottom electrode uses a silicon back gate and is mainly used for global coarse-tuning.
[0043] It should be noted that the p-type two-dimensional semiconductor uses WTe2 material, the n-type two-dimensional semiconductor uses InSe material, and the bridging layer uses graphene material. WTe2 material has both high hole concentration and mobility, resulting in extremely low resistance in the hole-dominated region of the neuron device. Furthermore, its high conductivity makes the series circuitry of the two-dimensional semiconductor channel itself negligible. InSe material's high electron mobility ensures low resistance in the electron-dominated region, and its weak electron scattering maintains high mobility even at GHz frequencies. In the high gate voltage region, the high conductivity electron channels of InSe complement the hole channels of WTe2, ensuring… The device exhibits high conductivity across the entire gate voltage range. The combination of p-type two-dimensional semiconductor WTe2 and n-type two-dimensional semiconductor InSe enables dual high-mobility channels for electrons and holes. Graphene, acting as a bridging layer, forms ohmic contacts with both WTe2 and InSe, reducing contact resistance to a level far lower than that between traditional metal electrodes and two-dimensional materials. Furthermore, as the gate voltage approaches its peak, the carrier concentrations of both WTe2 and InSe are low, and the high conductivity of graphene can serve as a low-resistance bypass, ensuring extremely high conductivity in the peak region. This effectively improves the conductivity of the two-dimensional semiconductor channel, making it suitable for high-frequency applications.
[0044] Example 3: Includes a substrate, a floating gate structure, a two-dimensional material heterojunction, and an electrode structure. The substrate is generally made of silicon oxide, which provides a flat and clean surface for the growth or transfer of upper-layer materials. Simultaneously, silicon oxide as a substrate isolates the back gate from the floating gate structure, preventing leakage. The floating gate structure is disposed on the substrate and includes a floating gate layer and a dielectric layer. The floating gate layer is disposed on the substrate, and the dielectric layer is disposed between the floating gate layer and the two-dimensional material heterojunction. The floating gate structure enables multi-level non-volatile storage, maintaining multiple resistance states even after power failure. It supports long-term memory and unsupervised learning, eliminating the need for external storage chips, reducing system complexity and data transfer power consumption. It is suitable for edge devices, retaining learning results after power failure and enabling instant startup. A two-dimensional material heterojunction is disposed on the side of the floating gate structure away from the substrate. The two-dimensional material heterojunction consists of a semiconductor channel layer, which includes a bridging layer, a p-type two-dimensional semiconductor, and an n-type two-dimensional semiconductor. The p-type two-dimensional semiconductor is disposed on one side of the bridging layer, and the n-type two-dimensional semiconductor is disposed on the side of the bridging layer away from the p-type two-dimensional semiconductor. The bridging layer is used to form the cross-section of the heterojunction and realize the transport of charge carriers. By combining the p-type two-dimensional semiconductor and the n-type two-dimensional semiconductor with the bridging layer, a transistor with anti-bipolar characteristics is constructed. Under gate voltage regulation, this transistor structure can generate a response similar to that of a neuron to moderate-intensity input. The device exhibits a bell-shaped (non-monotonic) response curve. Simultaneously, the integrated floating gate structure endows the device with non-volatility, enabling it to simulate the long-term memory and synaptic plasticity of biological neurons. This achieves simultaneous computation and memory functions in a single device, greatly simplifying circuit design. It addresses the problems of traditional silicon-based neuronal devices, such as complex structures (requiring multiple transistor combinations), singular response behavior (only monotonically increasing or decreasing), and the inability to simultaneously achieve non-monotonic response and non-volatile storage within a single device. Furthermore, it is suitable for physiological signal recognition (such as heart rate, blood pressure, and brain waves), automatically filtering abnormally high or low signals and improving the signal-to-noise ratio. The electrode structure includes a top electrode and a bottom electrode. The top electrode is located on the side of the floating gate structure away from the substrate and electrically connected to a two-dimensional material heterojunction. The bottom electrode is located on the side of the substrate away from the floating gate structure. The top electrode uses Pt and is mainly used for local fine-tuning of the semiconductor channel conductance, while the bottom electrode uses a silicon back gate and is mainly used for global coarse-tuning.
[0045] It should be noted that the floating gate layer uses HfZrO2 ferroelectric layer and the dielectric layer uses Al2O3. HfZrO2 is a typical ferroelectric material with spontaneous polarization characteristics. Under the action of an external electric field, the ferroelectric domains flip, and the polarization direction changes. After the electric field is removed, the remaining polarization intensity can still be maintained. This polarization state modulates the carrier concentration of the upper channel by the depolarization field, thereby achieving non-volatile storage. At the same time, the ferroelectric flip is an intrinsic physical process that does not involve carrier injection, tunneling, or thermionic emission, so the write speed is extremely fast. Moreover, by controlling the amplitude or width of the write pulse, the partial flip of the ferroelectric domains can be controlled, thereby achieving multi-level polarization states. Each polarization state corresponds to a different channel conductivity, thus achieving multi-level storage. In addition, the role of Al2O3 as the dielectric layer is to act as a barrier layer to prevent polarization charge leakage, and at the same time, to form a high-quality interface with HfZrO2, reducing interface defects.
[0046] Example 4: Includes a substrate, a floating gate structure, a two-dimensional material heterojunction, and an electrode structure. The substrate is generally made of silicon oxide, which provides a flat and clean surface for the growth or transfer of upper-layer materials. Simultaneously, silicon oxide as a substrate isolates the back gate from the floating gate structure, preventing leakage. The floating gate structure is disposed on the substrate and includes a floating gate layer and a dielectric layer. The floating gate layer is disposed on the substrate, and the dielectric layer is disposed between the floating gate layer and the two-dimensional material heterojunction. The floating gate structure enables multi-level non-volatile storage, maintaining multiple resistance states even after power failure. It supports long-term memory and unsupervised learning, eliminating the need for external storage chips, reducing system complexity and data transfer power consumption. It is suitable for edge devices, retaining learning results after power failure and enabling instant startup. A two-dimensional material heterojunction is disposed on the side of the floating gate structure away from the substrate. The two-dimensional material heterojunction consists of a semiconductor channel layer, which includes a bridging layer, a p-type two-dimensional semiconductor, and an n-type two-dimensional semiconductor. The p-type two-dimensional semiconductor is disposed on one side of the bridging layer, and the n-type two-dimensional semiconductor is disposed on the side of the bridging layer away from the p-type two-dimensional semiconductor. The bridging layer is used to form the cross-section of the heterojunction and realize the transport of charge carriers. By combining the p-type two-dimensional semiconductor and the n-type two-dimensional semiconductor with the bridging layer, a transistor with anti-bipolar characteristics is constructed. Under gate voltage regulation, this transistor structure can generate a response similar to that of a neuron to moderate-intensity input. The device exhibits a bell-shaped (non-monotonic) response curve. Simultaneously, the integrated floating gate structure endows the device with non-volatility, enabling it to simulate the long-term memory and synaptic plasticity of biological neurons. This achieves simultaneous computation and memory functions in a single device, greatly simplifying circuit design. It addresses the problems of traditional silicon-based neuronal devices, such as complex structures (requiring multiple transistor combinations), singular response behavior (only monotonically increasing or decreasing), and the inability to simultaneously achieve non-monotonic response and non-volatile storage within a single device. Furthermore, it is suitable for physiological signal recognition (such as heart rate, blood pressure, and brain waves), automatically filtering abnormally high or low signals and improving the signal-to-noise ratio. The electrode structure includes a top electrode and a bottom electrode. The top electrode is located on the side of the floating gate structure away from the substrate and electrically connected to a two-dimensional material heterojunction. The bottom electrode is located on the side of the substrate away from the floating gate structure. The top electrode uses Pt and is mainly used for local fine-tuning of the semiconductor channel conductance, while the bottom electrode uses a silicon back gate and is mainly used for global coarse-tuning.
[0047] It should be noted that the floating gate layer uses MoS2 nanocrystals, and the dielectric layer uses HfO2. The MoS2 nanocrystals act as discrete charge-trapping centers, using quantum confinement and Coulomb blocking effects to stably confine the injected charge within the nanocrystals. Each nanocrystal can trap several electrons, and the statistical distribution of multiple nanocrystals achieves multi-level storage. Simultaneously, the MoS2 nanocrystals form deep-level traps, requiring trapped electrons to overcome high potential barriers to escape, thus resulting in long charge retention times and non-volatile storage. Furthermore, the amount of charge injected into the MoS2 nanocrystals can be controlled by adjusting the amplitude, width, or number of write pulses. Due to the small size of the nanocrystals, the number of electrons trapped by each nanocrystal is discretely controllable, and the statistical averaging of multiple nanocrystals achieves multi-level storage. At the same time, the MoS2 nanocrystal floating gate exhibits excellent material stability and structural reliability, making it suitable for long-term stable operation.
[0048] On the other hand, this embodiment provides a method for fabricating a non-volatile, non-monotonic neuron device.
[0049] Example 5: Includes the following steps:
[0050] Step S1: Prepare a substrate in advance and fabricate a floating gate structure on the substrate;
[0051] Step S2: Using chemical vapor deposition (CVD), p-type two-dimensional semiconductor materials, bridging layer materials, and n-type two-dimensional semiconductor materials are directly grown on the floating gate structure to form an integrated heterojunction channel layer with p-type semiconductors, bridging layer, and n-type semiconductors.
[0052] Step S3: Fabricate a top electrode on the semiconductor channel layer and a bottom electrode on the substrate.
[0053] CVD growth involves a chemical reaction on a substrate surface using a gaseous precursor, resulting in atomic-level layer-by-layer deposition. P-type two-dimensional semiconductors, bridging layers, and n-type two-dimensional semiconductors can be epitaxially grown by continuously switching precursors within the same growth chamber, forming atomically sharp and lattice-continuous heterojunction interfaces. The three functional regions—p-type, bridging layers, and n-type two-dimensional semiconductors—are completed in the same process step, avoiding the contamination and damage risks associated with multiple transfers. Simultaneously, growth parameters (such as temperature, pressure, and carrier gas flow rate) can be precisely controlled, allowing for strain regulation between lattice-mismatched materials. This results in high-quality van der Waals epitaxial interfaces, reducing defects and dangling bonds, and ensuring consistent device performance. This solves the problems of interface contamination, adsorbate residue, high interface state density, defects and trapped states caused by lattice mismatch, and low yield due to poor alignment accuracy inherent in traditional mechanical stacking methods.
[0054] Example 6:
[0055] Step S1: Prepare a substrate in advance and fabricate a floating gate structure on the substrate;
[0056] Step S2: Using liquid phase exfoliation and solution assembly methods, p-type two-dimensional nanosheets, bridging layer nanosheets and n-type two-dimensional nanosheets are prepared respectively, and then assembled on the floating gate structure by sequential spin coating or LB film method to form a semiconductor channel layer with p-type semiconductor, bridging layer and n-type semiconductor.
[0057] Step S3: Fabricate a top electrode on the semiconductor channel layer and a bottom electrode on the substrate.
[0058] First, bulk two-dimensional materials are exfoliated into single-layer or few-layer nanosheets through liquid-phase exfoliation (such as ultrasound, electrochemistry, etc.) to form a stable dispersion. This step decouples material growth from device fabrication, allowing for the pre-production of high-quality nanosheets in batches. Simultaneously, spin coating or LB film method can complete large-area film coverage within seconds to minutes. By adjusting the concentration and mixing ratio of the dispersion, the relative content and thickness of p-type two-dimensional semiconductor, bridging layer, and n-type two-dimensional semiconductor materials can be precisely controlled, facilitating the optimization of device performance. It also allows different two-dimensional materials to be independently prepared and then arbitrarily combined without being limited by lattice matching and growth compatibility, facilitating the rapid screening of the optimal material combination. Compared with CVD method, it can solve the problems of incompatibility of different material growth conditions and the problem of high-temperature processes easily damaging the floating gate structure, simplifying process steps and reducing preparation costs.
[0059] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A non-volatile, non-monotonic neuronal device, characterized in that, include: Substrate; A floating gate structure, wherein the floating gate structure is disposed on the substrate; A two-dimensional material heterojunction is disposed on the side of a floating gate structure away from the substrate. The two-dimensional material heterojunction is composed of a semiconductor channel layer, which includes a bridging layer, a p-type two-dimensional semiconductor, and an n-type two-dimensional semiconductor. The p-type two-dimensional semiconductor is disposed on one side of the bridging layer, and the n-type two-dimensional semiconductor is disposed on the side of the bridging layer away from the p-type two-dimensional semiconductor. The bridging layer is used to form the cross-section of the heterojunction and realize the transport of charge carriers. An electrode structure is provided, comprising a top electrode and a bottom electrode. The top electrode is disposed on the side of the floating gate structure away from the substrate and electrically connected to a two-dimensional material heterojunction. The bottom electrode is disposed on the side of the substrate away from the floating gate structure.
2. The non-volatile, non-monotonic neuron device according to claim 1, characterized in that, The p-type two-dimensional semiconductor is made of black phosphorus material, the n-type two-dimensional semiconductor is made of WS2 material, and the bridging layer is made of PtSe2 material.
3. The non-volatile, non-monotonic neuron device according to claim 1, characterized in that, The p-type two-dimensional semiconductor is made of WTe2 material, the n-type two-dimensional semiconductor is made of InSe material, and the bridging layer is made of graphene material.
4. The non-volatile, non-monotonic neuron device according to claim 1, characterized in that, The top electrode is made of Pt, the bottom electrode is made of silicon back gate, and the floating gate structure includes: A floating gate layer, wherein the floating gate layer is disposed on a substrate; A dielectric layer is disposed between the floating gate layer and the two-dimensional material heterojunction.
5. The non-volatile, non-monotonic neuron device according to claim 4, characterized in that, The floating gate layer is an HfZrO2 ferroelectric layer, and the dielectric layer is an Al2O3 layer.
6. The non-volatile, non-monotonic neuron device according to claim 4, characterized in that, The floating gate layer is made of MoS2 nanocrystals, and the dielectric layer is made of HfO2.
7. A method for fabricating a non-volatile, non-monotonic neuronal device as described in any one of claims 1-6, characterized in that, Includes the following steps: Step S1: Prepare a substrate in advance and fabricate a floating gate structure on the substrate; Step S2: Sequentially transfer or grow p-type two-dimensional semiconductor material, bridging layer material and n-type two-dimensional semiconductor material on the floating gate structure to form a semiconductor channel layer having p-type semiconductor, bridging layer region and n-type semiconductor; Step S3: Prepare a top electrode on the semiconductor channel layer and prepare a bottom electrode on the substrate.
8. The method for fabricating a non-volatile, non-monotonic neuron device according to claim 7, characterized in that, In step S2, the p-type two-dimensional semiconductor material, the bridging layer material, and the n-type two-dimensional semiconductor material are directly grown on the floating gate structure using chemical vapor deposition (CVD) to form an integrated heterojunction channel layer.
9. The method for fabricating a non-volatile, non-monotonic neuron device according to claim 7, characterized in that, In step S2, p-type two-dimensional nanosheets, bridging layer nanosheets, and n-type two-dimensional nanosheets are prepared by liquid phase exfoliation and solution assembly methods, respectively, and then assembled on the floating gate structure by sequential spin coating or LB film method to form the semiconductor channel layer.