Manufacturing method of semiconductor structure and semiconductor structure
By forming a high-low-high-low-high gradient height structure on the top surface of the active region of the field-effect transistor device, the problem of excessive electric field concentration is solved, and the electrical performance and reliability of the device are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-04-17
- Publication Date
- 2026-05-19
AI Technical Summary
In the existing technology, the electric field is still excessively concentrated even after the corners of the field-effect transistor device are rounded.
By forming a high-low-high-low-high gradient height structure on the top surface of the active region, combined with etching and oxidation processes, a recess and rounded corners are formed, which modulates the electric field intensity distribution, avoids excessive concentration of the electric field in a single location, and increases the contact area between the gate and the channel region.
It reduces the peak electric field intensity, reduces impact ionization and hot carrier injection effects, reduces leakage current, disperses mechanical stress, and improves the gate's control over the channel region.
Smart Images
Figure CN122069766A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductors, and in particular to methods for fabricating semiconductor structures and semiconductor structures. Background Technology
[0002] In the manufacturing process of some semiconductor devices, it is necessary to round the corners of the active region to alleviate the problem of electric field concentration within the device and improve the reliability of the device under relatively high operating voltages.
[0003] However, for field-effect transistor devices, simply rounding the corners may still result in excessive concentration of the electric field at a single location. Summary of the Invention
[0004] This application provides a method for fabricating a semiconductor structure and a semiconductor structure, which at least helps to avoid the problem of excessive concentration of electric field at a single location in a semiconductor device.
[0005] This application provides a method for fabricating a semiconductor structure, comprising the following steps: providing a substrate structure, the substrate structure including a substrate and an active region located on the substrate, a mask structure formed on the top surface of the active region, the top surface of the active region extending along a first direction, and in a second direction, the top surface of the active region including a first region and a second region located on opposite sides of the first region, wherein the second region is adjacent to the side of the active region to form a corner, and the second direction is perpendicular to the first direction; performing a first etching process on the mask structure to expose the second region; forming a first oxide layer, the first oxide layer at least covering the second region and the corner; performing a second etching process on the mask structure to expose a portion of the first region adjacent to the second region; performing a third etching process on the exposed active region to form a recess; and forming a second oxide layer, the second oxide layer at least covering the recess, the second region, and the corner.
[0006] Optionally, the mask structure includes a first mask layer and a second mask layer, the first mask layer being located on the top surface of the active region, the second mask layer being located on the top surface of the first mask layer, and the hardness of the second mask layer being greater than the hardness of the first mask layer.
[0007] Optionally, the material forming the first oxide layer is the same as the material of the first mask layer, and / or, during the second etching process, a portion of the thickness of the first oxide layer is etched.
[0008] Optionally, the first etching process is wet etching, and in the second direction, the first etching process etches the mask structure to a size of 10% to 20% of the top surface size of the active region, and / or, in the second direction, the second etching process etches the mask structure to a size of 20% to 40% of the top surface size of the active region.
[0009] Optionally, the third etching process is isotropic etching, and the depth to which the third etching process etches the active region is 2% to 5% of the height of the active region.
[0010] Optionally, in the second direction, the first region includes a first sub-region and a second sub-region located on opposite sides of the first sub-region, the second sub-region extending along the first direction; the second etching process is wet etching, the second etching process is used to expose the second sub-region, and the recess formed by the third etching process extends along the first direction.
[0011] Optionally, in the second direction, the first region includes a third sub-region and a fourth sub-region located on opposite sides of the third sub-region, the fourth sub-regions being spaced apart in the first direction; before performing the second etching process on the mask structure, the process further includes: forming a protective layer on the top surface of the mask structure; the second etching process is to etch away the exposed mask structure according to the protective layer to expose the fourth sub-regions, and the recesses formed by the third etching process are spaced apart in the first direction.
[0012] A second aspect of this application provides a semiconductor structure, comprising: a substrate, and an active region located on the substrate; the top surface of the active region extends along a first direction, and in a second direction, the top surface of the active region includes a first region and a second region located on opposite sides of the first region, wherein the second region is adjacent to the side surface of the active region to form a corner, and the second direction is perpendicular to the first direction; the corner is a rounded corner structure, and the height of the top surface of the active region in the second region is lower than the height of the top surface of the active region in the first region; a recess located in the first region and adjacent to the second region, the bottom surface of the recess being lower than the height of the top surface of the active region in the second region; the surfaces of the corner, the active region in the second region, the recess, and the active region in the first region are smoothly connected.
[0013] Optionally, in the second direction, the size of the second region is 10% to 20% of the size of the top surface of the active region, the size of the recess is 20% to 40% of the size of the top surface of the active region, and the depth of the recess is 2% to 5% of the height of the active region.
[0014] Optionally, the recessed portion extends in the first direction; or, in the first direction, the recessed portions are spaced apart.
[0015] As described above, the semiconductor structure fabrication method provided in this application forms an active region with a high-low-high-low-high gradient height structure on its top surface. An unexpected effect of this is that the gradient height structure modulates the electric field intensity distribution in the channel region through the high-low-high-low-high height variation, preventing excessive concentration of the electric field at a single location (such as the drain terminal of a short-channel device), thereby reducing the peak electric field intensity, minimizing impact ionization and hot carrier injection effects, and reducing leakage current. Furthermore, the gradient height structure disperses the mechanical stress generated during packaging or operation, reducing the risk of interface delamination. Secondly, the formation of a recessed portion increases the contact area between the gate and the channel region after the gate is formed covering the top surface of the active region in subsequent processes, increasing the gate's control area over the channel region in the active region and enhancing gate control capability. Attached Figure Description
[0016] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A schematic flowchart corresponding to the method for fabricating the semiconductor structure provided in the embodiments of this application; Figure 2 This is a schematic diagram of the cross-sectional structure of the base structure provided in step S1 of the embodiments of this application; Figure 3 This is a top view of the base structure provided in step S1 of the embodiments of this application. Figure 4 A schematic cross-sectional view of the substrate and mask structure required for forming the substrate structure provided in the embodiments of this application; Figure 5 The embodiment of this application provides a substrate etched according to a mask structure to form a structure as shown below. Figure 2 The diagram shows a cross-sectional view of the base structure. Figure 6 This is a schematic diagram of the cross-sectional structure of the mask structure after the first etching process is performed on the mask structure in step S2 of the embodiment of this application; Figure 7This is a top view of the mask structure after the first etching process is performed on the mask structure in step S2 of the embodiment of this application. Figure 8 This is a schematic diagram of the cross-sectional structure after the formation of the first oxide layer in step S3 of this application embodiment; Figure 9 This is a schematic diagram of the cross-sectional structure of the mask structure after the second etching process is performed on the mask structure in step S4 of the embodiment of this application; Figure 10 This is a top view of the mask structure after the second etching process is performed on the mask structure in step S4 of the embodiment of this application. Figure 11 A top view of the mask structure after the second etching process is performed on the mask structure in step S4, which is provided in another embodiment of this application; Figure 12 This is a schematic diagram of the cross-sectional structure after the recess is formed in step S5 of this application embodiment; Figure 13 This is a schematic diagram of the cross-sectional structure after the formation of the second oxide layer in step S6 of this application embodiment; Figure 14 A schematic diagram of the cross-sectional structure of the double-layer mask structure provided in the embodiment of this application after step S4; Figure 15 This is a schematic cross-sectional view of the semiconductor structure provided in the embodiments of this application; Figure 16 This is a top view schematic diagram of the semiconductor structure provided in the embodiments of this application; Figure 17 This is a top view of a semiconductor structure provided in another embodiment of this application. Detailed Implementation
[0018] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values of the components and steps set forth in these embodiments do not limit the scope of the present application.
[0019] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.
[0020] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this application and its application or use.
[0021] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.
[0022] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.
[0023] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.
[0024] This application provides a method for fabricating a semiconductor structure, comprising the following steps: providing a substrate structure, the substrate structure including a substrate and an active region located on the substrate, a mask structure formed on the top surface of the active region, the top surface of the active region extending along a first direction, and in a second direction, the top surface of the active region including a first region and a second region located on opposite sides of the first region, and the second region adjacent to the side of the active region forming a corner, the second direction being perpendicular to the first direction; performing a first etching process on the mask structure to expose the second region; forming a first oxide layer, the first oxide layer at least covering the second region and the corner; performing a second etching process on the mask structure to expose a portion of the first region adjacent to the second region; performing a third etching process on the exposed active region to form a recess; forming a second oxide layer, the second oxide layer at least covering the recess and the second region.
[0025] Figure 1 This document illustrates a flowchart corresponding to the semiconductor structure fabrication method provided in the embodiments of this application. Figures 2 to 14 The following schematic diagrams illustrate cross-sectional and top views of the semiconductor structure fabrication method provided in this application at different stages; (The following is a continuation of the previous paragraph, which is not directly related to the previous paragraph.) Figure 1 as well as Figures 2 to 14 The method for fabricating the semiconductor structure provided in the embodiments of this application is described in detail.
[0026] refer to Figure 1 The method for fabricating the semiconductor structure includes steps S1 to S6, as detailed below: Step S1: Provide the base structure.
[0027] Step S2: Perform the first etching process on the mask structure.
[0028] Step S3: Form the first oxide layer.
[0029] Step S4: Perform a second etching process on the mask structure.
[0030] Step S5: Perform a third etching process on the exposed active region.
[0031] Step S6: Form the second oxide layer.
[0032] In some embodiments, the method for fabricating a semiconductor structure is used to form a field-effect transistor device.
[0033] Figure 2 This is a schematic diagram of the cross-sectional structure of the base structure provided in step S1 of this application embodiment. Figure 3 This is a top view of the base structure provided in step S1 of this application embodiment.
[0034] For step S1, refer to Figure 2 and Figure 3 A substrate structure 101 is provided, which includes a substrate 110 and an active region 120 located on the substrate 110. A mask structure 102 is formed on the top surface of the active region 120. The top surface of the active region 120 extends along a first direction X. In a second direction Y, the top surface of the active region 120 includes a first region 100 and a second region 200 located on opposite sides of the first region 100. The second region 200 is adjacent to the side of the active region 120 to form a corner 103. The second direction Y is perpendicular to the first direction X.
[0035] The materials of substrate 110 and active region 120 can both be semiconductor materials, which may include any one of silicon, germanium, silicon carbide, silicon germanide, gallium arsenide, or indium gallium ionide. In some examples, the material of substrate 110 may be the same as that of active region 120. In addition, substrate 110 and active region 120 may also be an integral structure, which may provide a substrate and pattern the substrate to form substrate 110 and active region 120.
[0036] In other examples, the material of substrate 110 may also be different from the material of active region 120.
[0037] To facilitate a clear description of the scheme, the following detailed explanation will use silicon as the material of the active region 120 as an example.
[0038] The active region 120 contains doped elements, which can be N-type or P-type doped elements. N-type doped elements can be Group VA (Group 5) elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). P-type doped elements can be Group IIIA (Group 3) elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In). It is understood that the type of doped element in the active region 120 is the same as the doping type of the channel region of the field-effect transistor to be formed. Therefore, the type of doped element in the active region 120 is related to the type of field-effect transistor to be formed. If the field-effect transistor to be formed is an NMOS transistor, the doped element is a P-type doped element; if the field-effect transistor to be formed is a PMOS transistor, the doped element is an N-type doped element.
[0039] It should be noted that the first direction X is the direction in which the source points to the drain (or the drain points to the source) in a field-effect transistor device; the second direction Y is the direction of the channel width of a field-effect transistor device.
[0040] In addition, the first region 100 and the second region 200 defined in this application are only used to distinguish the top surface location of the exposed active region 120 and the size of the top surface of the exposed active region 120 in subsequent processes.
[0041] Since the active region 120 extends in the first direction X, the second region 200 is adjacent to the side of the active region 120, forming a corner 103 that also extends in the first direction X, presenting an angular shape.
[0042] In some embodiments, the active region 120 can be used to form a device with a high operating voltage (which may be called a high voltage device), such as a P-channel high voltage MOS device or an N-channel high voltage MOS device.
[0043] Figure 4 This is a schematic cross-sectional view of the substrate and mask structure required for forming the substrate structure according to an embodiment of this application. Figure 5 The embodiment of this application provides a substrate etched according to a mask structure to form a structure as shown below. Figure 2 The diagram shows a cross-sectional view of the base structure.
[0044] refer to Figure 4 and Figure 5 In some embodiments, the substrate structure 101 may be provided by the following steps: providing a substrate 90 and forming a patterned mask structure 102 on the substrate 90; then etching a portion of the thickness of the substrate 90 based on the patterned mask structure 102 to form trenches 104; the remaining substrate 90 located between adjacent trenches 104 is defined as an active region 120; and the remaining substrate 90 with a surface height lower than the bottom of the trenches 104 is defined as a substrate 110, thereby forming a... Figure 2 The substrate structure 101 shown.
[0045] It should be noted that the above example uses the mask structure 102 to define the formation of the active region 120, which helps to save process costs. Of course, the embodiments of this application do not limit the timing of forming the mask structure, and the mask structure can also be reformed after the active region is formed.
[0046] It should also be noted that, Figures 2-14 In the example provided, the single-layer mask structure 102 is used only to illustrate the embodiments of this application, and the number of layers and specific structure of the mask structure 102 do not constitute a limitation on this embodiment; in other embodiments, the mask structure may also be a multi-layer mask, for example, Figure 15 The mask structure 102 corresponding to the example is a double-layer mask scheme.
[0047] In some embodiments, between steps S1 and S2, ion implantation can also be performed on the active region 120 to serve as drift region implantation for the source or drain region of a high-voltage device. For drift region implantation of the high-voltage device, if the active region 120 is an N-type well region, P-type ions are implanted; if the active region 120 is a P-type well region, N-type ions are implanted. The number of implantations, implantation dose, and implantation energy can be determined according to actual needs.
[0048] Figure 6 This is a schematic diagram of the cross-sectional structure of the mask structure after the first etching process in step S2 of the embodiments of this application. Figure 7 This is a top view of the mask structure after the first etching process is performed on the mask structure in step S2 of the embodiment of this application.
[0049] For step S2, refer to Figure 6 and Figure 7 The mask structure 102 is subjected to a first etching process to expose the second region 200.
[0050] Specifically, the first etching process is a pull-back process of the mask structure 102 to expose the corner 103 of the active region 120 and the second region 200. The exposed corner 103 and the second region 200 are used for subsequent corner rounding processing of the corner 103. The corner rounding processing is used to improve the edge morphology of the active region 120, avoid the appearance of sharp corner structures, and thus avoid charge concentration within the device.
[0051] In some embodiments, the first etching process can be performed using wet etching, which has a lower process cost and can greatly reduce the overall process cost of the semiconductor structure fabrication method provided in the embodiments of this application.
[0052] In one example, since the material of the mask structure 102 contains silicon nitride or silicon oxide, the first etching process can use an etchant containing phosphoric acid to process the mask structure 102 by wet etching. This etchant can react with silicon nitride or silicon oxide to etch the mask structure 102, and the etchant has a high selectivity for silicon nitride, silicon oxide, and silicon. The etchant has a high etching rate for silicon nitride and silicon oxide and reacts minimally with silicon, thereby preventing the etchant from etching the substrate structure 101.
[0053] In some embodiments, in the second direction Y, the size of the first etching process etching mask structure 102 is 10% to 20% of the size of the top surface of the active region 120. For example, the size of the first etching process etching mask structure 102 is 12%, 15%, or 18% of the size of the top surface of the active region 120. When the size of the first etching process etching mask structure 102 is less than 10% of the size of the top surface of the active region 120, the exposed corner 103 is smaller, and the radius of curvature of the corner 103 after rounding is smaller, but the problem of electric field concentration in the device may still occur. When the size of the first etching process etching mask structure 102 is greater than 20% of the size of the top surface of the active region 120, the exposed corner 103 is larger, and the rounding process will consume more of the active region 120, thereby reducing the size of the top surface of the active region 120, which may affect the electrical performance of the formed device.
[0054] In one example, the size of the first etching process etching mask structure 102 is 4nm. At this time, after the first oxide layer 201 is formed, the corner 103 is modified from a sharp corner to a rounded corner with a radius of curvature of 4nm~8nm.
[0055] It should be noted that the "size of the etching mask structure 102" mentioned in the embodiments of this application refers to the sum of the etching sizes on both sides of the mask structure 102, that is, the size of the etching mask structure 102 is 10% to 20% of the size of the top surface of the active region 120. In one example, the sizes of the etching mask structures 102 on both sides are the same, that is, the size of the etching mask structure 102 on one side is 5% to 10% of the size of the top surface of the active region 120; in another example, the sizes of the etching mask structures 102 on both sides can be different. In this case, the size of the etching mask structure 102 on one side also needs to be maintained at a reasonable value to prevent the radius of curvature of the corner 103 from being too small after rounding.
[0056] Figure 8 This is a schematic diagram of the cross-sectional structure after the formation of the first oxide layer in step S3 of the embodiment of this application.
[0057] For step S3, refer to Figure 8 A first oxide layer 201 is formed, which at least covers the second region 200 and the corner 103. By forming the first oxide layer 201, the exposed corner 103 is rounded.
[0058] Specifically, a first oxide layer 201 is formed on the exposed substrate structure 101 surface through oxidation (e.g., thermal oxidation (including thermal growth oxidation process, etc.) or water vapor oxidation (including in-situ water vapor growth process, etc.). During the oxidation process, the surface of corner 103 and the surface of active region 120 of the second region 200 are oxidized. Since the oxidation consumes some of the surface material of corner 103 and active region 120 of the second region 200, the corner 103 is rounded, resulting in a rounded corner structure. In addition, due to the back-pushing process of mask structure 102 in step S2, the second region 200 is exposed, that is, a larger corner 103 is exposed, increasing the surface area of the rounded corner 103, so that the rounded corner 103 has a larger radius of curvature, and the edge shape of active region 120 is smoother.
[0059] In addition, by performing rounding treatment after pushing back the mask structure 102, the curvature radius of the corner 103 after rounding can be controlled by precisely controlling the size of the push-back mask structure 102, thereby achieving controllable rounding of the edge of the active region 120, avoiding charge concentration in the device, and reducing leakage current in the device.
[0060] Due to the cost of rounding, the top surface height of corner 103 is now lower than the top surface height of active region 120 in the first region 100.
[0061] Figure 9 This is a schematic diagram of the cross-sectional structure of the mask structure after the second etching process is performed on the mask structure in step S4 of the embodiment of this application. Figure 10 This is a top view of the mask structure after the second etching process is performed on the mask structure in step S4 of the embodiment of this application. Figure 11 This is a top view of the mask structure after the second etching process is performed on the mask structure in step S4, as provided in another embodiment of this application. Figure 12 This is a schematic diagram of the cross-sectional structure after the recess is formed in step S5 of the embodiment of this application.
[0062] For step S4, in some embodiments, refer to Figure 9 and Figure 10 A second etching process is performed on the mask structure 102 to expose a portion of the first region 100 adjacent to the second region 200. Specifically, the second etching process is a push-back process of the mask structure 102 to expose a portion of the first region 100 adjacent to the second region 200. The exposed portion of the first region 100 adjacent to the second region 200 is used to subsequently form a groove on the top surface of the active region 120, changing the top surface morphology of the active region 120. Compared with a planar top surface, the groove can increase the contact area between the subsequently formed gate structure and the top surface of the active region 120, thereby improving the gate structure's control over the channel region and further improving the electrical performance of the device.
[0063] In the second direction Y, the first region 100 includes a first sub-region 301 and second sub-regions 302 located on opposite sides of the first sub-region 301, with the second sub-regions 302 extending along the first direction X. In the first direction X, since the edges of the desired final formed first sub-region 301 and second sub-region 302 exhibit relatively regular straight-line morphology, selective etching of the mask structure 102 is not required. Similar to the first etching process, in some embodiments, the second etching process can also be performed using wet etching. Wet etching has lower process costs and can significantly reduce the overall process cost of the semiconductor structure fabrication method provided in this application embodiment.
[0064] In one example, since the material of the mask structure 102 contains silicon nitride or silicon oxide, the second etching process can use an etchant containing phosphoric acid to process the mask structure 102 by wet etching. This etchant can react with silicon nitride or silicon oxide to etch the mask structure 102, and the etchant has a high selectivity for silicon nitride, silicon oxide, and silicon. The etchant has a high etching rate for silicon nitride and silicon oxide and reacts minimally with silicon, thereby preventing the etchant from etching the substrate structure 101.
[0065] In some embodiments, in the second direction Y, the size of the second etching process etching mask structure 102 is 20% to 40% of the size of the top surface of the active region 120. For example, the size of the second etching process etching mask structure 102 is 22%, 25%, 27%, 30%, 33%, 35%, or 38% of the size of the top surface of the active region 120. When the size of the second etching process etching mask structure 102 is less than 20% of the size of the top surface of the active region 120, the position for forming the recess 401 is smaller, and the morphology of the recess 401 formed by the subsequent third etching process may be irregular, thereby affecting the electrical performance of the device. When the size of the second etching process etching mask structure 102 is greater than 40% of the size of the top surface of the active region 120, the recess 401 occupies most of the position of the top surface of the active region 120, which greatly affects the effective width of the channel region formed based on the active region 120, thereby affecting the electrical performance of the device.
[0066] In one example, the size of the second etching process etch mask structure 102 is 10 nm.
[0067] Figure 14 This is a schematic diagram of the cross-sectional structure of the double-layer mask structure provided in the embodiment of this application after step S4.
[0068] refer to Figure 14In some embodiments, the mask structure 102 includes a first mask layer 501 and a second mask layer 502. The first mask layer 501 is located on the top surface of the active region 120, and the second mask layer 502 is located on the top surface of the first mask layer 501. The hardness of the second mask layer 502 is greater than the hardness of the first mask layer 501.
[0069] In some embodiments, during the second etching process, a portion of the thickness of the first oxide layer 201 is also etched. Specifically, the material of one of the first mask layer 501 or the second mask layer 502 is selected from materials with similar chemical properties to the first oxide layer 201. Thus, during the second etching process of pushing back the mask structure 102, since one of the first mask layer 501 or the second mask layer 502 has similar properties to the first oxide layer 201, the second etching process will also etch a portion of the thickness of the first oxide layer 201, thereby thinning the thickness of the first oxide layer 201 and preventing the thicker first oxide layer 201 from hindering the oxidation of the substrate structure 101, thereby hindering the formation of the second oxide layer 202. It should be noted that the aforementioned "materials with similar chemical properties" means that the corresponding film layers can be etched using the same etchant. In one example, the material of the first mask layer 501 is selected from materials with similar chemical properties to the first oxide layer 201; in another example, the material of the second mask layer 502 is selected from materials with similar chemical properties to the first oxide layer 201.
[0070] Furthermore, if the first mask layer 501 is made of a material with similar chemical properties to the first oxide layer 201, the thickness of the first oxide layer 201 formed in step S3 must be greater than the thickness of the first mask layer 501 to ensure that there is remaining first oxide layer 201 after the mask structure 102 is pushed back in step S4, thus preventing subsequent etching processes from etching the corner 103. Similarly, if the second mask layer 502 is made of a material with similar chemical properties to the first oxide layer 201, the thickness of the first oxide layer 201 formed in step S3 must be greater than the thickness of the second mask layer 502.
[0071] In some embodiments, the material forming the first oxide layer 201 is the same as the material of the first mask layer 501. That is, the material of the first mask layer 501 is silicon oxide. Correspondingly, since the hardness of the second mask layer 502 is greater than that of the first mask layer 501, the material of the second mask layer 502 can be silicon nitride. Since the material forming the first oxide layer 201 is the same as the material of the first mask layer 501, the process of pushing back the mask structure 102 will inevitably etch a portion of the thickness of the first oxide layer 201, which facilitates the selection of the etchant for the second etching process.
[0072] Continue to refer to Figure 9 , Figure 10 and Figure 12In step S5, a third etching process is performed on the exposed active region 120 to form a recess 401. Since the second sub-region 302 exposed by the second etching process extends along the first direction X, the recess 401 formed by the third etching process also extends along the first direction X. The recess 401 is formed to increase the contact area between the gate and the channel region after the gate covers the top surface of the active region 120 in the subsequent process, thereby increasing the control area of the gate over the channel region in the active region 120 and enhancing the gate control capability.
[0073] Due to the consumption of the top of the active region 120 by the third etching process, the bottom surface height of the recess 401 is lower than the top surface height of the corner 103. In the second direction Y, the top surface of the active region 120 presents a high-low-high-low-high gradient height structure. Among them, the corners 103 on both sides of the top surface of the active region 120 are rounded and the height is slightly reduced, serving as the "high" height structure on both sides to avoid the problem of electric field concentration in the device and reduce the leakage current in the device. The area of the active region 120 near the corner 103 is a gradually recessed recess 401, serving as the "low" height structure near the edge, serving to optimize gate coverage and improve gate control capability. The middle region of the active region 120 maintains its original height, serving as the "high" height structure in the middle, serving to ensure the effective width of the channel region in the active region 120. The gradient height structure modulates the electric field distribution in the channel region through a high-low-high-low-high height variation, preventing excessive concentration of the electric field at a single location (such as the source / drain of short-channel devices). This reduces the peak electric field intensity, decreases impact ionization and hot carrier injection (HCI) effects, and lowers leakage current (Ioff). Furthermore, the gradient height structure disperses mechanical stresses generated during packaging or operation [such as coefficient of thermal expansion (CTE) mismatch stress], reducing the risk of interface delamination.
[0074] In some embodiments, the third etching process is isotropic etching (Cavity Etch). The overall shape of the recess 401 formed by isotropic etching is an arc-shaped pit, so that the recess 401 does not have sharp corner structures, thus avoiding the problem of electric field concentration caused by sharp corner positions.
[0075] In one example, the third etching process uses an etchant with a high selectivity for silicon as well as silicon nitride and silicon oxide. The etchant has a high etching rate for silicon and does not react with silicon nitride and silicon oxide, thereby preventing the etching solution from etching the mask structure 102 and the first oxide layer 201.
[0076] In some embodiments, the depth of the third etching process etching the active region 120 is 2% to 5% of the height of the active region 120, that is, the depth of the recess 401 etched in the third direction Z (the height direction of the active region 120) is 2% to 5% of the height of the active region 120. For example, the depth of the third etching process etching the active region 120 is 2.5%, 3.0%, 3.5%, 4.0%, or 4.5% of the height of the active region 120. When the depth of the active region 120 etched in the third etching process is less than 2% of the height of the active region 120, the gate oxide layer formed earlier may fill this height difference (the height difference between the bottom surface of the recess 401 and the top surface of the active region 120) during the subsequent gate formation process, so that the recess 401 no longer has the effect of increasing the gate contact area; when the depth of the active region 120 etched in the third etching process is greater than 5% of the height of the active region 120, the blocking effect of the recess 401 greatly affects the effective width of the channel region and reduces the electrical performance of the device.
[0077] In one example, the third etching process etches the active region 120 to a depth of 5nm~8nm.
[0078] For step S4, in some other embodiments, refer to Figure 9 and Figure 11 In the second direction Y, the first region 100 includes a third sub-region 303 and fourth sub-regions 304 located on opposite sides of the third sub-region 303, with the fourth sub-regions 304 spaced apart in the first direction X. In the first direction X, since the edges of the desired final third sub-region 303 and the edges of the fourth sub-region 304 exhibit an embedded configuration, selective etching of the mask structure 102 is required. In this example, before performing the second etching process on the mask structure 102, the semiconductor structure fabrication method further includes: forming a protective layer (not shown) on the top surface of the mask structure 102; the second etching process involves etching away the exposed mask structure 102 according to the protective layer to expose the fourth sub-regions 304.
[0079] In some embodiments, the second etching process may be performed using a dry etching method.
[0080] Continue to refer to Figure 9 , Figure 11 and Figure 12In step S5, a third etching process is performed on the exposed active region 120 to form a recess 401. Since the fourth sub-region 304 exposed by the second etching process is spaced apart in the first direction X, the recesses 401 formed by the third etching process are also spaced apart along the first direction X. Compared to the recesses 401 extending in the first direction X, the arrangement of the recesses 401 spaced apart in the first direction X avoids the reduction in the size of the top surface of the active region 120 in the second direction Y, thereby increasing the effective width of the channel region within the active region 120 and improving the electrical performance of the device.
[0081] Figure 13 This is a schematic diagram of the cross-sectional structure after the formation of the second oxide layer in step S6 of the embodiment of this application.
[0082] For step S6, refer to Figure 12 and Figure 13 A second oxide layer 202 is formed, which at least covers the recess 401, the second region 200, and the corner 103. By forming the second oxide layer 202, the connection area between the corner 103 and the recess 401 is rounded to make the top surface of the active region 120 smooth. Specifically, since the rounding of the corner 103 and the recess 401 are formed in stages, sharp corners or other burrs may appear between the corner 103 and the recess 401, which may cause electric field concentration. Through further oxidation treatment, the connection area between the corner 103 and the recess 401 is rounded to make the top surface of the active region 120 smooth.
[0083] It should be noted that steps S3 and S6 are both oxidation processes. Therefore, the second oxide layer 202 is formed by further oxidation on the basis of the first oxide layer 201. It can be said that the second oxide layer 202 contains the first oxide layer 201.
[0084] After step S6 is completed, the active region 120, as the active region of the field-effect transistor device, needs to be subsequently covered by a gate. Specifically, in the first direction X, the active region 120 includes a source region, a channel region, and a drain region, and the gate covers the top and side surfaces of the channel region in the second direction Y. In some embodiments, the gradient height structure provided in this embodiment is located only on the top surface of the channel region; in other embodiments, the gradient height structure provided in this embodiment is located on the top surfaces of the source region, the channel region, and the drain region.
[0085] In summary, the semiconductor structure fabrication method provided in this application creates a high-low-high-low-high gradient height structure on the top surface of the active region. An unexpected effect of this is that the gradient height structure modulates the electric field intensity distribution in the channel region through the high-low-high-low-high height variation, preventing excessive concentration of the electric field at a single location, thereby reducing the peak electric field intensity, minimizing impact ionization and hot carrier injection effects, and reducing leakage current. Furthermore, the gradient height structure disperses the mechanical stress generated during packaging or operation, reducing the risk of interface delamination. Secondly, the recessed portion increases the contact area between the gate and the channel region after the gate is formed covering the top surface of the active region in subsequent processes, increasing the gate's control area over the channel region in the active region and enhancing gate control capability.
[0086] The fabrication method of the semiconductor structure according to this application has now been described in detail. To avoid obscuring the concept of this application, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.
[0087] Another aspect of this application embodiment also provides a semiconductor structure.
[0088] Figure 15 This is a schematic cross-sectional view of the semiconductor structure provided in an embodiment of this application. Figure 16 This is a top view schematic diagram of the semiconductor structure provided in an embodiment of this application. Figure 17 This is a top view of a semiconductor structure provided in another embodiment of this application. The following is a schematic diagram in conjunction with... Figures 15 to 17 The semiconductor structure provided in the embodiments of this application is described in detail.
[0089] refer to Figures 15-17 The semiconductor structure includes a substrate 110 and an active region 120 located on the substrate 110.
[0090] The materials of substrate 110 and active region 120 can both be semiconductor materials, including any one of silicon, germanium, silicon carbide, silicon germanide, gallium arsenide, or indium gallium ionide. In some examples, the material of substrate 110 can be the same as that of active region 120. Alternatively, substrate 110 and active region 120 can be a single structure, where a substrate is provided and patterned to form substrate 110 and active region 120. In other examples, the material of substrate 110 can be different from that of active region 120.
[0091] To facilitate a clear description of the scheme, the following detailed explanation will use silicon as the material of the active region 120 as an example.
[0092] The active region 120 contains doped elements, which can be N-type or P-type doped elements. N-type doped elements can be Group VA (Group 5) elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). P-type doped elements can be Group IIIA (Group 3) elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In). It is understood that the type of doped element in the active region 120 is the same as the doping type of the channel region of the field-effect transistor to be formed. Therefore, the type of doped element in the active region 120 is related to the type of field-effect transistor to be formed. If the field-effect transistor to be formed is an NMOS transistor, the doped element is a P-type doped element; if the field-effect transistor to be formed is a PMOS transistor, the doped element is an N-type doped element.
[0093] The top surface of the active region 120 extends along the first direction X and along the second direction Y. The top surface of the active region 120 includes a first region 100 and a second region 200 located on opposite sides of the first region 100. The second region 200 and the side of the active region 120 are adjacent to each other to form a corner 103. The second direction Y is perpendicular to the first direction X.
[0094] Since the active region 120 extends in the first direction X, the second region 200 is adjacent to the side of the active region 120, forming a corner 103 that also extends in the first direction X, presenting an angular shape.
[0095] The corner 103 has a rounded corner structure, and the top surface height of the active region 120 in the second region 200 is lower than the top surface height of the active region 120 in the first region 100. The rounded corner structure of the corner 103 is used to avoid electric field concentration within the device and to reduce leakage current within the device.
[0096] The recess 401 is located in the first region 100 and adjacent to the second region 200. The bottom surface of the recess 401 is lower than the top surface of the active region 120 in the second region 200. The recess 401 is used to increase the contact area between the gate and the channel region after the gate covers the top surface of the active region 120 in subsequent processes, thereby increasing the control area of the gate over the channel region in the active region 120 and enhancing the gate control capability.
[0097] The surfaces of corner 103, active region 120 in the second region 200, recess 401, and active region 120 in the first region 100 are smoothly connected. Since the top surface height of active region 120 in the second region 200 is lower than the top surface height of active region 120 in the first region 100, and the bottom surface height of recess 401 is lower than the top surface height of active region 120 in the second region 200, the top surface of active region 120 presents a high-low-high-low-high gradient height structure. In this design, the corners 103 on both sides of the top surface of the active region 120 are rounded and their height is slightly reduced, serving as a "high" height structure on both sides to avoid electric field concentration within the device and reduce leakage current. The area of the active region 120 near the corners 103 is a gradually recessed portion 401, serving as a "low" height structure near the edges to optimize gate coverage and improve gate control capability. The middle region of the active region 120 maintains its original height, serving as a "high" height structure in the middle to ensure the effective width of the channel region within the active region 120. This gradient height structure modulates the electric field intensity distribution in the channel region through a high-low-high-low-high height variation, preventing excessive electric field concentration at a single location, thereby reducing peak electric field intensity, minimizing impact ionization and hot carrier injection effects, and reducing leakage current. Furthermore, the gradient height structure disperses mechanical stress generated during packaging or operation, reducing the risk of interface delamination.
[0098] Regarding the recess 401, in some embodiments, refer to Figure 16 The recess 401 extends in the first direction X. In other embodiments, reference is made to... Figure 17 In the first direction X, the recesses 401 are spaced apart. It should be noted that... Figure 16 and Figure 17 In this context, the second region 200 and the recessed portion 401 are filled differently relative to the substrate 110 and the active region 120. This is only used to indicate the position of the second region 200 and the recessed portion 401 and does not constitute a limitation on other attributes.
[0099] In some embodiments, in the second direction Y, the size of the second region 200 is 10% to 20% of the size of the top surface of the active region 120. For example, the size of the second region 200 is 12%, 15%, or 18% of the size of the top surface of the active region 120. When the size of the second region 200 is less than 10% of the size of the top surface of the active region 120, the radius of curvature of the corner 103 is small, and the problem of electric field concentration within the device may still occur. When the size of the second region 200 is greater than 20% of the size of the top surface of the active region 120, the size of the corner 103 is large, and the rounded corner structure formed by rounding the corner 103 will consume more of the active region 120, thereby reducing the size of the active region 120, which may affect the electrical performance of the formed device.
[0100] In one example, in the second direction Y, the size of the second region 200 is 4nm, and the corner 103 is a rounded corner with a curvature radius of 4nm~8nm.
[0101] In some embodiments, in the second direction Y, the size of the recess 401 is 20% to 40% of the size of the top surface of the active region 120. For example, the size of the recess 401 is 22%, 25%, 27%, 30%, 33%, 35%, or 38% of the size of the top surface of the active region 120. When the size of the recess 401 is less than 20% of the size of the top surface of the active region 120, the overall size of the recess 401 is small, and the morphology of the recess 401 may be irregular, thus affecting the electrical performance of the device. When the size of the recess 401 is greater than 40% of the size of the top surface of the active region 120, the recess 401 occupies most of the top surface of the active region 120, greatly affecting the effective width of the channel region formed by the active region 120, thus affecting the electrical performance of the device.
[0102] In one example, the size of the recess 401 in the second direction Y is 10 nm.
[0103] In some embodiments, the depth of the recess 401 is 2% to 5% of the height of the active region 120. For example, the depth of the recess 401 is 2.5%, 3.0%, 3.5%, 4.0%, or 4.5% of the height of the active region 120. When the depth of the recess 401 is less than 2% of the height of the active region 120, the gate oxide layer formed earlier may fill this height difference (the height difference between the bottom surface of the recess 401 and the top surface of the active region 120) during the subsequent gate formation process, thereby making the recess 401 no longer have the effect of increasing the gate contact area; when the depth of the recess 401 is greater than 5% of the height of the active region 120, the blocking effect of the recess 401 greatly affects the effective width of the channel region and reduces the electrical performance of the device.
[0104] In one example, the depth of the recess 401 is 5nm to 8nm.
[0105] The semiconductor structure provided in this embodiment is a field-effect transistor device. Specifically, in the first direction X, the active region 120 includes a source region, a channel region, and a drain region, and the gate covers the top surface and side surface of the channel region in the second direction Y. In some embodiments, the gradient height structure provided in this embodiment is located only on the top surface of the channel region; in other embodiments, the gradient height structure provided in this embodiment is located on the top surface of the source region, the channel region, and the drain region.
[0106] In summary, the semiconductor structure provided in this application features a high-low-high-low-high gradient height structure on the top surface of the active region. An unexpected effect of this is that the gradient height structure modulates the electric field distribution in the channel region through the high-low-high-low-high height variation, preventing excessive concentration of the electric field at a single location, thereby reducing the peak electric field intensity, minimizing impact ionization and hot carrier injection effects, and reducing leakage current. Furthermore, the gradient height structure disperses the mechanical stress generated during packaging or operation, reducing the risk of interface delamination. Secondly, the recessed portion increases the contact area between the gate and the channel region after the gate is formed covering the top surface of the active region in subsequent processes, increasing the gate's control area over the channel region in the active region, thus enhancing gate control capability.
[0107] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate structure is provided, the substrate structure including a substrate and an active region located on the substrate, a mask structure is formed on the top surface of the active region, the top surface of the active region extends along a first direction, and in a second direction, the top surface of the active region includes a first region and a second region located on opposite sides of the first region, and the second region is adjacent to the side of the active region to form a corner, and the second direction is perpendicular to the first direction; The mask structure is subjected to a first etching process to expose the second region; A first oxide layer is formed, which at least covers the second region and the corner. The mask structure is subjected to a second etching process to expose a portion of the first region that is adjacent to the second region. The exposed active region is subjected to a third etching process to form a recess; A second oxide layer is formed, which at least covers the recess, the second region, and the corner.
2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The mask structure includes a first mask layer and a second mask layer. The first mask layer is located on the top surface of the active region, and the second mask layer is located on the top surface of the first mask layer. The hardness of the second mask layer is greater than that of the first mask layer.
3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The material forming the first oxide layer is the same as the material of the first mask layer, and / or, during the second etching process, a portion of the thickness of the first oxide layer is etched.
4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The first etching process is a wet etching process, and in the second direction, the first etching process etches the mask structure to a size of 10% to 20% of the top surface size of the active region; And / or, in the second direction, the second etching process etches the mask structure to a size of 20% to 40% of the top surface size of the active region.
5. The method for fabricating a semiconductor structure according to claim 1 or 4, characterized in that, The third etching process is isotropic etching, and the depth of etching the active region by the third etching process is 2% to 5% of the height of the active region.
6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, In the second direction, the first region includes a first sub-region and a second sub-region located on opposite sides of the first sub-region, the second sub-region extending along the first direction; The second etching process is a wet etching process, which is used to expose the second sub-region, and the recess formed by the third etching process extends along the first direction.
7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, In the second direction, the first region includes a third sub-region and a fourth sub-region located on opposite sides of the third sub-region, the fourth sub-regions being spaced apart in the first direction; Before performing the second etching process on the mask structure, the method further includes: forming a protective layer on the top surface of the mask structure; The second etching process involves etching away the exposed mask structure according to the protective layer to expose the fourth sub-region, and the recesses formed by the third etching process are spaced apart in the first direction.
8. A semiconductor structure, characterized in that, Includes: a substrate, and an active region located on the substrate; The top surface of the active region extends along a first direction. In a second direction, the top surface of the active region includes a first region and a second region located on opposite sides of the first region. The second region is adjacent to the side of the active region to form a corner. The second direction is perpendicular to the first direction. The corner is a rounded structure, and the top surface height of the active area in the second region is lower than the top surface height of the active area in the first region; A recessed portion is located in the first region and adjacent to the second region, wherein the bottom surface height of the recessed portion is lower than the top surface height of the active region in the second region; The surfaces of the corner, the active area in the second region, the recess, and the active area in the first region are smoothly connected.
9. The semiconductor structure according to claim 8, characterized in that, include: In the second direction, the size of the second region is 10% to 20% of the size of the top surface of the active region, and the size of the recess is 20% to 40% of the size of the top surface of the active region. The depth of the recess is 2% to 5% of the height of the active region.
10. The semiconductor structure according to claim 9, characterized in that, The recessed portion extends in the first direction; Alternatively, the recesses are spaced apart in the first direction.