Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a semiconductor structure which comprises a substrate, a groove is formed in the substrate, a shielding gate layer filling the groove for partial depth is formed in the groove, and an inter-gate dielectric layer is formed on the shielding gate layer, a first gate dielectric layer is formed on the side wall of the groove above the inter-gate dielectric layer and the surface of the substrate, a gate material layer is formed on the inter-gate dielectric layer, and the gate material layer fills the groove and covers the first gate dielectric layer on the surface of the substrate; removing the gate material layer on the surface of the substrate to expose the first gate dielectric layer on the surface of the substrate; sequentially doping in the substrate at the two sides of the groove to form a body region and a source region; and the remaining gate material layer is etched back by a predetermined depth to form a gate in the groove, and the top surface of the gate is lower than the surface of the substrate. According to the invention, the threshold voltage range can be improved, so that product requirements are met.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Shielded gate trench (SGT) transistors have excellent characteristics such as simple driving, low on-resistance, fast switching speed, and low switching loss, and have become the mainstream device in the medium and low voltage field.

[0003] As the critical dimensions of SGT products become smaller, the requirements for controlling their channel length become increasingly stringent. In the manufacturing process of SGT products using related technologies, the gate is typically formed by etching back first, followed by ion implantation to form the body and source regions. Due to the deep etching back depth, differences in critical parameters at different locations on the same wafer, and differences in the average critical parameters between wafers produced in the same or different batches, dopant ions are implanted from the sidewalls of the gate dielectric layer during the ion implantation to form the body / source regions. This results in large fluctuations in ion implantation depth and uneven channel length, which in turn causes the threshold voltage range to fail to meet product requirements. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, this application provides a method for manufacturing a semiconductor device, the method comprising: A semiconductor structure is provided, the semiconductor structure including a substrate, a trench extending from the surface of the substrate into the substrate is formed therein, a shielding gate layer filling a portion of the depth of the trench is formed therein, an inter-gate dielectric layer is formed on the shielding gate layer, and a first gate dielectric layer is formed on the sidewalls of the trench above the inter-gate dielectric layer and on the surface of the substrate, and a gate material layer is formed on the inter-gate dielectric layer, the gate material layer filling the trench and covering the first gate dielectric layer on the surface of the substrate; Remove the gate material layer on the surface of the substrate to expose the first gate dielectric layer on the surface of the substrate; In the substrate located on both sides of the trench, a body region and a source region are sequentially doped to form; The remaining gate material layer is etched back to a predetermined depth to form a gate in the trench, the top surface of the gate being lower than the surface of the substrate.

[0006] In one embodiment, a chemical mechanical polishing process is used to remove the gate material layer on the substrate surface.

[0007] In one embodiment, at least two trenches are formed in the substrate, and the gates formed in the at least two different trenches have different thicknesses.

[0008] In one embodiment, a second gate dielectric layer is formed between the shielding gate layer and the substrate.

[0009] In one embodiment, the step of sequentially doping to form a body region and a source region in the substrate located on both sides of the trench includes: The substrates on both sides of the trench are first doped using an ion implantation process to form a bulk region of a predetermined depth, the bulk region extending from the surface of the substrate into the interior of the substrate; The body region is subjected to a second doping process using ion implantation to form a source region in the body region. The source region extends from the substrate surface into the interior of the body region, and the depth of the source region is less than the depth of the body region.

[0010] In one embodiment, the method further includes: After the first doping is performed, the substrate is subjected to a first annealing treatment; After the gate is formed, the substrate is subjected to a second annealing process.

[0011] In one embodiment, the dopant ions forming the body region include ions of a first conductivity type, and the dopant ions forming the source region include ions of a second conductivity type.

[0012] In one embodiment, the predetermined depth ranges from 100nm to 150nm.

[0013] In one embodiment, the inter-gate dielectric layer, the first gate dielectric layer, and the second gate dielectric layer may be made of the same or different materials.

[0014] This application also provides a semiconductor device, which is manufactured using the above-described semiconductor device manufacturing method.

[0015] The semiconductor device and manufacturing method of the present application embodiment first remove a portion of the gate material layer to expose the first gate dielectric layer on the substrate surface, and then perform doping to form a body region and a source region. During this doping process, since the gate material layer fills the trench above the inter-gate dielectric layer and the first gate dielectric layer covers the sidewalls of the trench above the gate dielectric layer and the surface of the substrate, it effectively prevents dopant ions from being injected into the substrate from the trench sidewalls. Then, the remaining gate material layer is etched back to form the gate in the trench. Using this method, the dopant ion implantation depth fluctuation is significantly reduced, and the channel length uniformity is improved, thereby effectively improving the threshold voltage range and meeting product performance requirements. Attached Figure Description

[0016] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0017] In the attached image: Figures 1A-1E A schematic cross-sectional view of a semiconductor device obtained by sequentially performing a manufacturing method of a semiconductor device using existing technology is shown. Figure 2 A flowchart of a specific embodiment of this application is shown; Figures 3A-3F A schematic cross-sectional view of a semiconductor device obtained by sequentially performing a manufacturing method of a semiconductor device according to a specific embodiment of this application is shown. Detailed Implementation

[0018] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0019] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0020] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.

[0023] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0024] SGT transistors possess excellent characteristics such as simple driving, low on-resistance, fast switching speed, and low switching losses, making them the mainstream devices in medium and low voltage applications. An SGT transistor consists of a shield gate and a gate located in the same trench. In a commonly used SGT transistor, the gate and shield gate have an upper and lower structure, meaning that the gate and shield gate are distributed along the thickness direction of the device within the trench, with the gate located in the upper part of the trench and the shield gate in the lower part, isolated by an inter-gate dielectric layer.

[0025] As the critical dimensions of SGT products become smaller, the requirements for controlling their channel length become increasingly stringent. In the manufacturing methods for producing SGT products using related technologies, such as... Figures 1A to 1E As shown, firstly, as Figure 1A As shown, a semiconductor structure including a substrate 200 is provided. A trench is formed in the substrate 200. A shielding gate layer 201 filling a portion of the trench depth is formed within the trench. An inter-gate dielectric layer 202 is formed on the shielding gate layer 201. A first gate dielectric layer 203 is formed on the sidewalls of the trench above the inter-gate dielectric layer 202 and on the surface of the substrate. A gate material layer 204 is formed on the inter-gate dielectric layer 202. The gate material layer 204 fills the trench and covers the first gate dielectric layer 203 on the substrate surface. A second gate dielectric layer 205 is formed between the shielding gate layer 201 and the substrate 200. Then, as... Figure 1B As shown, the gate 208 is formed by etching back, and then, as Figure 1C As shown, the substrate is annealed, and the annealing process forms an oxide layer 209 on the top surface of the gate. Then, as... Figure 1D and Figure 1E As shown, ion implantation is then performed to sequentially form body region 206 and source region 207.

[0026] Due to the deep etch-back depth, differences in key parameters at different locations on the same wafer, and differences in average key parameters between wafers produced in the same or different batches, the top of the gate may be lower than the substrate surface. This results in the sidewalls of the gate dielectric layer (i.e., the first gate dielectric layer described above) above the trench being directly exposed, losing the protection of polysilicon. When ion implantation is performed to form the body / source region, high-energy ions will directly bombard the exposed sidewalls of the gate dielectric layer, causing dopant ions to be implanted from the sidewalls of the gate dielectric layer. Furthermore, the varying etch-back depths lead to large fluctuations in ion implantation depth and uneven channel lengths, which in turn cause the threshold voltage range to fail to meet product performance requirements.

[0027] Therefore, in view of the aforementioned technical problems, this application proposes a method for manufacturing a semiconductor device, the method comprising: Step S110: Provide a semiconductor structure, the semiconductor structure including a substrate, a trench extending from the surface of the substrate into the substrate is formed in the substrate, a shielding gate layer filling a portion of the depth of the trench is formed in the trench, an inter-gate dielectric layer is formed on the shielding gate layer, and a first gate dielectric layer is formed on the sidewalls of the trench above the inter-gate dielectric layer and on the surface of the substrate, and a gate material layer is formed on the inter-gate dielectric layer, the gate material layer filling the trench and covering the first gate dielectric layer on the surface of the substrate; Step S120: Remove the gate material layer on the surface of the substrate to expose the first gate dielectric layer on the surface of the substrate; Step S130: Sequentially doping forms a body region and a source region in the substrate located on both sides of the trench; In step S140, the remaining gate material layer is etched back to a predetermined depth to form a gate in the trench, the top surface of the gate being lower than the surface of the substrate.

[0028] The semiconductor device and its manufacturing method according to embodiments of this application first remove a portion of the gate material layer to expose the first gate dielectric layer on the substrate surface, then perform doping to form a body region and a source region. During this doping process, since the gate material layer fills the trench above the inter-gate dielectric layer and the first gate dielectric layer covers the sidewalls of the trench above the gate dielectric layer and the surface of the substrate, it effectively prevents dopant ions from being implanted into the substrate from the trench sidewalls. Then, the remaining gate material layer is etched back to form the gate in the trench. Using this method, the dopant ion implantation depth fluctuation is significantly reduced, and the channel length uniformity is improved, thereby effectively improving the threshold voltage range and meeting product performance requirements.

[0029] Below, for reference Figure 2 , Figures 3A-3FThe method for manufacturing the semiconductor device of this application is described in detail, wherein, Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown; Figures 3A-3F A schematic cross-sectional view of a semiconductor device obtained by sequentially performing a method for manufacturing a semiconductor structure according to a specific embodiment of this application is shown.

[0030] For example, the method for manufacturing a semiconductor device according to this application includes the following steps: refer to Figure 2 Step S110 is executed to provide a semiconductor structure, the semiconductor structure including a substrate, a trench extending from the surface of the substrate into the substrate is formed in the substrate, a shielding gate layer filling a portion of the depth of the trench is formed in the trench, an inter-gate dielectric layer is formed on the shielding gate layer, and a first gate dielectric layer is formed on the sidewalls of the trench above the inter-gate dielectric layer and on the surface of the substrate, and a gate material layer is formed on the inter-gate dielectric layer, the gate material layer filling the trench and covering the first gate dielectric layer on the surface of the substrate.

[0031] like Figure 3A As shown, the semiconductor structure includes a substrate 200, which is any suitable substrate material known in the art, such as a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, epitaxial silicon substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, or other suitable materials, but is not limited thereto.

[0032] A trench extending from the surface of substrate 200 into the substrate 200 is formed in the substrate. For example, a mask layer (not shown) may be formed on the surface of substrate 200, and then the mask layer may be patterned to form a patterned mask layer (not shown). Using the patterned mask layer as a mask, an etching process, such as at least one of dry etching or wet etching, is used to form the trench extending from the surface of substrate 200 into the substrate 200. Exemplarily, at least two trenches are formed in substrate 200.

[0033] Next, refer to Figure 3A A second gate dielectric layer 205 is formed on the sidewalls and bottom of the trench, for example, a dense second gate dielectric layer 205 is formed by thermal oxidation process, and the material of the second gate dielectric layer 205 includes, but is not limited to, silicon dioxide.

[0034] Next, a shielding gate material layer (not shown) is deposited in the trench using a process such as Low Pressure Chemical Vapor Deposition (LPCVD). The shielding gate material layer fills the trench. Then, the shielding gate material layer outside the trench is removed by a dry or wet etching process, and the shielding gate material layer inside the trench is etched back to a first depth, such as half or two-thirds of the total trench depth, thereby forming a shielding gate layer 201 that fills part of the trench depth.

[0035] Next, continue to refer to Figure 3A On the shielding gate layer 201, an inter-gate dielectric layer 202 is formed by thermal oxidation or deposition. The material of the inter-gate dielectric layer 202 includes, but is not limited to, silicon oxide. Next, the second gate dielectric layer 205 located on the trench sidewalls above the inter-gate dielectric layer 202 is etched away to form clean substrate sidewalls, preparing for subsequent gate formation.

[0036] Next, a first gate dielectric layer 203 is formed on the sidewalls of the trench above the inter-gate dielectric layer 202 and on the surface of the substrate.

[0037] For example, the thickness of the first gate dielectric layer 203 is different from the thickness of the second gate dielectric layer 205. Since the first gate dielectric layer 203 is used to form the channel and for switching control, while the second gate dielectric layer 205 is used for high-voltage isolation and capacitor control, the second gate dielectric layer 205 bears most of the high voltage between the drain and gate when in the off state, while the first gate dielectric layer 203 mainly bears the gate-source drive voltage. Furthermore, the first gate dielectric layer 203 requires a sufficiently large gate-source capacitance to achieve strong gate control, while the second gate dielectric layer 205 requires a very small gate-drain capacitance to reduce switching losses. Therefore, based on these differences, the thickness of the first gate dielectric layer 203 is different from the thickness of the second gate dielectric layer 205. For example, the thickness of the second gate dielectric layer 205 is greater than the thickness of the first gate dielectric layer 203.

[0038] For example, the inter-gate dielectric layer 202, the first gate dielectric layer 203, and the second gate dielectric layer 205 may be made of the same material or different materials.

[0039] Next, continue to refer to Figure 3A A gate material layer 204 is deposited on the inter-gate dielectric layer 202, filling the remaining space of the trench and covering the first gate dielectric layer 203 on the surface of the substrate 200. Next, the gate material layer 204 is planarized to make the surface of the gate material layer 204 flat. The planarization process includes, but is not limited to, chemical mechanical polishing.

[0040] Next, continue to refer to Figure 2Step S120 is executed to remove the gate material layer on the surface of the substrate to expose the first gate dielectric layer on the surface of the substrate.

[0041] For example, such as Figure 3B As shown, a chemical mechanical polishing (CMP) process is used to remove the gate material layer 204 on the surface of the substrate 200, thereby exposing the first gate dielectric layer 203 on the surface of the substrate 200. Using CMP to remove the gate material layer 204 from the substrate surface yields a flat surface. If an etching process is used to remove the corresponding gate material layer, the surface of the remaining gate material layer will be uneven, for example, it may form a V-shaped surface. This could lead to an increase in the series resistance of the gate electrode after subsequent gate formation, resulting in a slower gate charging speed and increased switching delay. Furthermore, it may cause premature local breakdown of the first gate oxide dielectric layer, leading to a decrease in device withstand voltage or even failure, thus affecting the stability of the device.

[0042] Next, continue to refer to Figure 2 Step S130 is executed, in which a body region and a source region are sequentially doped in the substrate located on both sides of the trench.

[0043] Exemplarily, the sequential doping of the substrate located on both sides of the trench to form a body region and a source region includes the following steps: First, such as Figure 3C As shown, an ion implantation process is used to perform a first doping on the substrate 200 on both sides of the trench to form a body region 206 of a predetermined depth. The body region 206 extends from the surface of the substrate 200 into the interior of the substrate 200. Exemplarily, the dopant ions forming the body region 206 include ions of a first conductivity type, such as boron ions. Exemplarily, after the first doping, the substrate undergoes a first annealing treatment. Since the impurity atoms are located in interstitial positions of the crystal lattice after ion implantation, and the crystal lattice is severely damaged by bombardment and lacks electrical activity, high-temperature annealing rearranges the atoms, repairs the lattice damage, and "pushes" the impurity atoms into the lattice positions, enabling them to provide conductive holes. Simultaneously, the implanted impurity atoms diffuse into the interior of the substrate. By precisely controlling the temperature and time, the final depth of the body junction and the impurity distribution profile can be controlled, thereby precisely setting the channel length.

[0044] Next, as Figure 3DAs shown, the body region 206 is second-doped using an ion implantation process to form a source region 207 within the body region 206. The source region 207 extends from the surface of the substrate 200 into the interior of the body region 206, and the depth of the source region 207 is less than the depth of the body region 206. Exemplarily, the dopant ions forming the source region 207 include ions of a second conductivity type, such as phosphorus ions or arsenic ions. In the embodiments of this application, the first conductivity type is P-type and the second conductivity type is N-type, or vice versa, where N and P represent the conductivity types of the semiconductor device.

[0045] When performing ion implantation on the substrate, the substrate surface and trench sidewalls are covered by the first gate dielectric layer, resulting in very small fluctuations in the doped ion implantation depth.

[0046] Next, continue to refer to Figure 2 Step S140 is performed to etch the remaining gate material layer back to a predetermined depth to form a gate in the trench, wherein the top surface of the gate is lower than the surface of the substrate.

[0047] For example, such as Figure 3E As shown, a dry etching process is used to etch the remaining gate material layer to a predetermined depth, forming a gate 208 in a trench. The top surface of the gate 208 is lower than the top surface of the substrate 200. When at least two trenches are formed in the substrate 200, the gates 208 formed in the at least two different trenches have different thicknesses, and the top surface of each gate 208 is higher than the bottom surface of the source region 207. It can be understood that the gate thickness refers to the dimension extending from the top of the gate into the interior of the substrate. By etching back to make the top surface of the gate lower than the top surface of the substrate, polysilicon residue on the substrate surface can be prevented, thus affecting the quality of the semiconductor device. At the same time, the gate thickness is reduced after etching back, resulting in a smaller capacitance.

[0048] For example, the range of the predetermined depth is 100nm-150nm, such as 100nm, 120nm or 150nm, which can be reasonably selected according to actual needs.

[0049] During the etch-back process, differences in key parameters at different locations on the same substrate lead to different etch-back depths in different trenches, resulting in gates of varying thicknesses. However, since the ion implantation steps for forming the body and source regions occur before the etch-back steps in this application, the difference in etch-back depth does not lead to a difference in implantation junction depth, thereby effectively improving the threshold voltage range to meet product requirements.

[0050] Next, the substrate undergoes a second annealing process. The energy provided by the annealing drives the atoms to rearrange, repairing defects such as lattice damage caused to the gate by the etching process, restoring the lattice integrity of the material, thereby reducing the gate resistance and eliminating electrical instability caused by defects.

[0051] For example, such as Figure 3F As shown, the second annealing process also forms an oxide layer 209 on the top surface of the gate 208. The oxide layer 209 can passivate and improve the electrical stability of the device. At the same time, it acts as a barrier in subsequent processes, making it easy to detect the end of the process and preventing over-etching damage to the gate.

[0052] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. The complete semiconductor device manufacturing method may also include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0053] The semiconductor device manufacturing method of this application embodiment involves first removing a portion of the gate material layer to expose a first gate dielectric layer on the substrate surface, followed by doping to form a body region and a source region. During this doping process, since the gate material layer fills the trench above the inter-gate dielectric layer and the first gate dielectric layer covers the sidewalls of the trench above the gate dielectric layer and the substrate surface, dopant ions are effectively prevented from being implanted into the substrate from the trench sidewalls. Then, the remaining gate material layer is etched back to form the gate in the trench. Using this method, the dopant ion implantation depth fluctuation is significantly reduced, and the channel length uniformity is improved, thereby effectively improving the threshold voltage range and meeting product performance requirements.

[0054] This application also provides a semiconductor device, such as an SGT device, which is prepared by the above method and has the same beneficial effects as the semiconductor device manufacturing method.

[0055] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A semiconductor structure is provided, the semiconductor structure including a substrate, a trench extending from the surface of the substrate into the substrate is formed therein, a shielding gate layer filling a portion of the depth of the trench is formed therein, an inter-gate dielectric layer is formed on the shielding gate layer, and a first gate dielectric layer is formed on the sidewalls of the trench above the inter-gate dielectric layer and on the surface of the substrate, and a gate material layer is formed on the inter-gate dielectric layer, the gate material layer filling the trench and covering the first gate dielectric layer on the surface of the substrate; Remove the gate material layer on the surface of the substrate to expose the first gate dielectric layer on the surface of the substrate; In the substrate located on both sides of the trench, a body region and a source region are sequentially doped to form; The remaining gate material layer is etched back to a predetermined depth to form a gate in the trench, the top surface of the gate being lower than the surface of the substrate.

2. The manufacturing method as described in claim 1, characterized in that, The gate material layer on the substrate surface is removed using a chemical mechanical polishing process.

3. The manufacturing method as described in claim 1, characterized in that, At least two trenches are formed in the substrate, and the gates formed in the at least two different trenches have different thicknesses.

4. The manufacturing method as described in claim 1, characterized in that, A second gate dielectric layer is formed between the shielding gate layer and the substrate.

5. The manufacturing method as described in claim 1, characterized in that, The step of sequentially doping to form a body region and a source region in the substrate located on both sides of the trench includes: The substrates on both sides of the trench are first doped using an ion implantation process to form a bulk region of a predetermined depth, the bulk region extending from the surface of the substrate into the interior of the substrate; The body region is subjected to a second doping process using ion implantation to form a source region in the body region. The source region extends from the substrate surface into the interior of the body region, and the depth of the source region is less than the depth of the body region.

6. The manufacturing method as described in claim 5, characterized in that, The method further includes: After the first doping is performed, the substrate is subjected to a first annealing treatment; After the gate is formed, the substrate is subjected to a second annealing process.

7. The manufacturing method as described in claim 1, characterized in that, The doping ions forming the body region include ions of a first conductivity type, and the doping ions forming the source region include ions of a second conductivity type.

8. The manufacturing method as described in claim 1, characterized in that, The predetermined depth ranges from 100nm to 150nm.

9. The manufacturing method as described in claim 4, characterized in that, The inter-gate dielectric layer, the first gate dielectric layer, and the second gate dielectric layer may be made of the same or different materials.

10. A semiconductor device, characterized in that, It is prepared by the manufacturing method as described in any one of claims 1-9.

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