Preparation method of adjustable polycrystalline silicon band gap for TOPCon battery
By introducing an amorphous silicon oxide layer into the TOPCon cell, the problem of light energy loss caused by the doping concentration and thickness of the polycrystalline silicon layer is solved, resulting in higher cell performance and photoelectric conversion efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TRINA SOLAR CO LTD
- Filing Date
- 2024-11-19
- Publication Date
- 2026-05-19
AI Technical Summary
The doping concentration and thickness of the polycrystalline silicon layer in existing TOPCon cells lead to light energy loss and poor passivation, affecting the photoelectric conversion efficiency of the cells.
An amorphous silicon oxide layer is introduced between polycrystalline silicon layers as a diffusion barrier layer. By controlling the diffusion of phosphorus, the doping distribution is adjusted to form a wider band gap and a better passivation effect, thereby optimizing battery performance.
It improves the open-circuit voltage, short-circuit current density, and photoelectric conversion efficiency of TOPCon cells, and enhances passivation performance.
Smart Images
Figure CN122069809A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of solar cells, and more specifically, to a method for preparing tunable polycrystalline silicon bandgap for TOPCon cells. Background Technology
[0002] TOPCon (Tunnel Oxide Passivated Contact) solar cells are based on the selective carrier principle. The passivation contact structure consists of two parts: a silicon oxide layer and a doped polycrystalline silicon layer. This passivation structure effectively reduces surface recombination and metal-to-metal recombination, improving passivation and increasing the cell's open-circuit voltage. However, the doping concentration and thickness of the polycrystalline silicon layer exhibit strong parasitic absorption of long-wavelength light, causing energy loss and affecting the cell's photoelectric conversion efficiency. Conversely, an excessively thin polycrystalline silicon layer can negatively impact passivation, leading to a decrease in open-circuit voltage (Voc) and fill factor (FF).
[0003] Therefore, further optimization of polycrystalline silicon phosphorus doping technology is needed to better match light energy loss and passivation advantages. Summary of the Invention
[0004] This application aims to address at least one of the technical problems existing in the prior art, to at least some extent.
[0005] Therefore, in its first aspect, this application proposes a method for fabricating a TOPcon solar cell. According to an embodiment of this application, the method includes: forming a silicon oxide layer on the back side of a silicon wafer; depositing a first doped amorphous silicon layer on the side of the silicon oxide layer away from the silicon wafer; depositing an amorphous silicon oxide layer on the side of the first doped amorphous silicon layer away from the silicon oxide layer; depositing a second doped amorphous silicon layer on the side of the amorphous silicon oxide layer away from the first doped amorphous silicon layer; and annealing the silicon wafer containing the silicon oxide layer, the first doped amorphous silicon layer, the amorphous silicon oxide layer, and the second doped amorphous silicon layer to obtain the TOPcon solar cell. Thus, the method described in this application can form a silicon oxide layer with a wider bandgap and a polycrystalline silicon layer, which can improve light energy loss and passivation performance, thereby improving the open-circuit voltage, short-circuit current density, and photoelectric conversion efficiency of the TOPcon solar cell.
[0006] According to embodiments of this application, the method further includes at least one of the following additional technical features:
[0007] According to an embodiment of this application, the thickness of the amorphous silicon oxide layer is 0.8 nm to 1.2 nm. Therefore, by keeping the thickness of the amorphous silicon oxide layer within the above range, the diffusion of dopants such as phosphorus in the amorphous silicon layer can be controlled, the band gap of the polycrystalline silicon layer formed after annealing can be adjusted, and the photoelectric conversion efficiency, open-circuit voltage, and short-circuit current density of the battery can be further improved.
[0008] According to embodiments of this application, phosphorus is doped into both the first doped amorphous silicon layer and the second doped amorphous silicon layer. Therefore, phosphorus can improve the electrical conductivity of amorphous silicon.
[0009] According to an embodiment of this application, the thickness of the first doped amorphous silicon layer is 5 nm to 10 nm. Therefore, by keeping the thickness of the first doped amorphous silicon layer within this range, it is possible to reduce dangling bonds on the silicon wafer surface, lower the surface state density, reduce carrier surface recombination, and improve the open-circuit voltage of the battery.
[0010] According to an embodiment of this application, the thickness of the second doped amorphous silicon layer is 85 nm to 95 nm. Therefore, by keeping the thickness of the second doped amorphous silicon layer within this range, the bandgap width of the formed polycrystalline silicon can be influenced, thereby improving the photoelectric conversion efficiency of the battery.
[0011] According to an embodiment of this application, the doping concentration of the first doped amorphous silicon layer is 0.8 × 10⁻⁶. 19 ~1.2×10 19 atom / cm 3 Therefore, by keeping the doping concentration of the first doped amorphous silicon layer within the aforementioned range, it can be used to form a low-doped region of the battery, which helps to form a gradual doping distribution and optimize the battery performance.
[0012] According to an embodiment of this application, the doping concentration of the second doped amorphous silicon layer is 6.8 × 10⁻⁶. 20 ~7.2×10 20 atom / cm 3 Therefore, by keeping the doping concentration of the second doped amorphous silicon layer within the aforementioned range, it is possible to form a highly doped region in a solar cell, thereby affecting the bandgap width of the polycrystalline silicon layer and improving the photoelectric conversion efficiency of the cell.
[0013] According to an embodiment of this application, the thickness of the silicon oxide layer is 1.2 nm to 2.5 nm. Therefore, by keeping the thickness of the silicon oxide layer within this range, it facilitates the transport of electrons from the silicon substrate to the amorphous silicon layer via the tunneling effect, reduces electron-hole pair recombination at the interface, and improves current collection efficiency.
[0014] According to an embodiment of this application, the annealing temperature is 900°C to 920°C. Therefore, by keeping the annealing temperature within this range, crystallization can be promoted, which helps to transform the amorphous silicon layer into a polycrystalline silicon layer.
[0015] According to an embodiment of this application, the annealing process takes 23 to 27 minutes. Therefore, by keeping the annealing time within this range, it is ensured that the amorphous silicon layer is transformed into a polycrystalline silicon layer.
[0016] According to embodiments of this application, the deposition is performed by any one of plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or sputtering.
[0017] In a second aspect of this application, a TOPCon battery is proposed. According to an embodiment of this application, the battery is prepared using the method described in the first aspect. Thus, the TOPCon battery prepared by the method described in this application has a wider bandgap silicon oxide layer and a polycrystalline silicon layer, better passivation performance, and higher open-circuit voltage, short-circuit current density, and photoelectric conversion efficiency.
[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:
[0020] Figure 1 This is a flowchart of a method for preparing a TOPcon battery according to an embodiment of this application;
[0021] Figure 2 This is a schematic diagram of the structure of the TOPcon battery according to an embodiment of this application.
[0022] Figure reference numerals: 01: silicon wafer, 02: silicon oxide layer, 03: first doped polycrystalline silicon layer, 04: polycrystalline silicon oxide layer, 05: second doped polycrystalline silicon layer, 06: silicon nitride anti-reflection passivation layer, 07: silicon nitride anti-reflection passivation layer, 08: aluminum oxide passivation layer, 09: boron-expanded P+ region. Detailed Implementation
[0023] The embodiments of the technical solution of this application are described in detail below. The following embodiments are only used to illustrate the technical solution of this application more clearly, and are therefore only examples, and should not be used to limit the scope of protection of this application.
[0024] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0025] The "range" disclosed in this application is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of a particular range. Ranges defined in this way can include endpoints and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60-120 and 80-110 are listed for a specific parameter, it is also expected that ranges of 60-110 and 80-120 are also included. Furthermore, if minimum range values 1 and 2 are listed, and if maximum range values 3, 4, and 5 are listed, then the following ranges are all expected: 1-3, 1-4, 1-5, 2-3, 2-4, and 2-5. In this application, unless otherwise stated, the numerical range "ab" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers, and ranges defined in this way can include endpoints a and b. For example, the numerical range "0-5" indicates that all real numbers between "0-5" have been listed in this article; "0-5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is stated as an integer ≥2, it is equivalent to disclosing that the parameter is, for example, an integer such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.
[0026] In this document, the terms “comprising” or “including” are open-ended expressions, meaning that they include the contents specified in this application but do not exclude other contents.
[0027] Unless otherwise specified, all embodiments and optional embodiments of this application can be combined to form new technical solutions.
[0028] Unless otherwise specified, all technical features and optional technical features of this application may be combined to form new technical solutions.
[0029] Unless otherwise specified, all steps in this application may be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, the mention that the method may also include step (c) indicates that step (c) may be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.
[0030] In the field of solar cells, especially in the manufacturing process of TOPCon cells, there are several key issues that need to be addressed to improve cell performance and production efficiency. Current technologies typically employ methods such as adjusting the type and concentration of dopants, optimizing annealing processes, or using other types of barrier layers to optimize the electrical characteristics and photoelectric conversion efficiency of cells. However, these methods have some drawbacks, such as potentially uneven doping distribution, insufficient passivation, and a certain degree of parasitic absorption, all of which can affect the performance of solar cells.
[0031] To address these issues, this application proposes an innovative method: adding an amorphous silicon oxide layer between two amorphous silicon layers. This amorphous silicon oxide layer acts as a diffusion barrier, effectively limiting the diffusion of high-concentration dopants into the silicon substrate, thus achieving more precise control over the doping distribution. Simultaneously, it provides excellent passivation, improving the crystallization rate and quality of the upper amorphous silicon layer, and contributing to the formation of a superior polycrystalline silicon structure. Therefore, by precisely controlling the doping distribution and improving the passivation effect, not only are the open-circuit voltage, short-circuit current density, and fill factor of the solar cell improved, but the overall photoelectric conversion efficiency of the cell is also enhanced.
[0032] Preparation method of TOPcon battery
[0033] This application proposes a method for fabricating a TOPcon battery. According to embodiments of this application, refer to... Figure 1 The method includes:
[0034] S100: A silicon oxide layer is formed on the back side of the silicon wafer.
[0035] It should be noted that before forming the silicon oxide layer, a PN junction is formed by diffusion on the front side of the silicon wafer. The front side of the silicon wafer is the surface from which sunlight is incident, while the back side is opposite to the front side.
[0036] In some embodiments of this application, the silicon wafer can be either an N-type or a P-type silicon wafer, both of which are within the scope of protection of this application. To improve the efficiency of the solar cell, an N-type silicon wafer is preferred, and boron diffusion can be performed on the front side of the silicon wafer.
[0037] In some embodiments of this application, the thickness of the silicon oxide layer is 1.2 nm to 2.5 nm. For example, it can be 1.2 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.8 nm, 2 nm, 2.2 nm, 2.4 nm, 2.5 nm, or any range of the above values. Therefore, by keeping the thickness of the silicon oxide layer within the above range, it facilitates the transport of electrons from the silicon substrate to the amorphous silicon layer via the tunneling effect, reduces the recombination of electron-hole pairs at the interface, and improves current collection efficiency.
[0038] In some embodiments of this application, the silicon oxide layer is a tunneling oxide layer, and there are various ways to form it, which are not specifically limited in this application. For example, a tunneling oxide layer can be grown in the reaction of silane and oxidant using plasma-enhanced chemical vapor deposition; or, a tunneling oxide layer can be generated by oxidation using nitric acid solution, and so on.
[0039] S200: A first doped amorphous silicon layer is deposited on the side of the silicon oxide layer away from the silicon wafer.
[0040] In some embodiments of this application, when the silicon wafer is an N-type silicon wafer, phosphorus is doped into the first doped amorphous silicon layer. Therefore, phosphorus can improve the electrical conductivity of the amorphous silicon and create significant high and low electric fields.
[0041] In some embodiments of this application, the thickness of the first doped amorphous silicon layer is 5 nm to 10 nm. For example, it can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc., or it can be any range of the above values. Therefore, by making the thickness of the first doped amorphous silicon layer within the above range, the damage of phosphorus diffusion to the tunneling layer can be reduced, and the open-circuit voltage of the battery can be improved.
[0042] In some embodiments of this application, the doping concentration of the first doped amorphous silicon layer is 0.8 × 10⁻⁶. 19 ~1.2 19 atom / cm 3 For example, it could be 0.8 × 10⁻⁶. 19 atom / cm 3 0.9×10 19 atom / cm 3 1×10 19 atom / cm 3 1.1×10 19 atom / cm 31.2×10 19 atom / cm 3 The values can be any range of the values mentioned above. Therefore, by keeping the doping concentration of the first doped amorphous silicon layer within the aforementioned range, it is possible to form a low-doped region of the battery, which helps to create a gradual doping distribution and optimize battery performance.
[0043] S300: An amorphous silicon oxide layer is deposited on the side of the first doped amorphous silicon layer away from the silicon oxide layer.
[0044] In some embodiments of this application, the thickness of the amorphous silicon oxide layer is 0.8 nm to 1.2 nm. For example, it can be 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, 1.2 nm, or any range of the above values. Therefore, by keeping the thickness of the amorphous silicon oxide layer within the above range, on the one hand, it is possible to control the diffusion of dopants such as phosphorus in the second-doped amorphous silicon layer towards the first-doped amorphous silicon layer, optimizing the crystallization process and doping distribution of the upper amorphous silicon layer, widening the band gap of the polycrystalline silicon layer formed after annealing, and improving the open-circuit voltage of the battery; simultaneously, the widened band gap of the polycrystalline silicon layer helps to reduce parasitic light absorption caused by excessive polycrystalline silicon layer thickness, thereby improving the short-circuit current of the battery.
[0045] S400: A second doped amorphous silicon layer is deposited on the side of the amorphous silicon oxide layer away from the first doped amorphous silicon layer;
[0046] In some embodiments of this application, when the silicon wafer is an N-type silicon wafer, phosphorus is doped in the second doped amorphous silicon layer. Therefore, phosphorus can improve the conductivity of the amorphous silicon and create significant high and low electric fields.
[0047] In some embodiments of this application, the thickness of the second doped amorphous silicon layer is 85 nm to 95 nm. For example, it can be 85 nm, 86 nm, 88 nm, 90 nm, 92 nm, 94 nm, 95 nm, etc., or any range of the above values. Therefore, by making the thickness of the second doped amorphous silicon layer within the above range, the high and low electric fields of the formed N+ / N layer can be influenced, thereby improving the tunneling effect and the photoelectric conversion efficiency of the battery.
[0048] In some embodiments of this application, the doping concentration of the second doped amorphous silicon layer is 6.8 × 10⁻⁶. 20 ~7.2×10 20 atom / cm 3 For example, it could be 6.8 × 10⁻⁶. 20 atom / cm 3 6.9×10 20 atom / cm 3 7×10 20atom / cm 3 7.1×10 20 atom / cm 3 7.2×10 20 atom / cm 3 The values can be any range of the values mentioned above. Therefore, by keeping the doping concentration of the second doped amorphous silicon layer within the above range, it is possible to form a highly doped region in a solar cell, creating a high electric field in the N+ layer and improving the photoelectric conversion efficiency of the cell.
[0049] S500: Annealing treatment
[0050] The TOPcon solar cell is obtained by annealing a silicon wafer containing a silicon oxide layer, a first doped amorphous silicon layer, an amorphous silicon oxide layer, and a second doped amorphous silicon layer. After annealing, each of the doped amorphous silicon layers is converted into a doped polycrystalline silicon layer, and the doping concentration of each doped polycrystalline silicon layer gradually increases in the direction away from the silicon wafer. This is because the amorphous silicon oxide layer blocks the diffusion of phosphorus into the silicon wafer during annealing, thereby controlling the band gap of the polycrystalline silicon layer and improving the photoelectric conversion efficiency of the cell.
[0051] In some embodiments of this application, the annealing temperature is 900°C to 920°C. For example, it can be 900°C, 905°C, 910°C, 915°C, 920°C, or any range of the above values. Therefore, by keeping the annealing temperature within the above range, crystallization can be promoted, which helps to transform the amorphous silicon layer into a polycrystalline silicon layer.
[0052] In some embodiments of this application, the annealing time is 23 to 27 minutes. For example, it can be 23 minutes, 24 minutes, 25 minutes, 26 minutes, 27 minutes, or any range of the above values. Thus, by keeping the annealing time within the above range, it is ensured that the amorphous silicon layer is transformed into a polycrystalline silicon layer.
[0053] In some embodiments of this application, the deposition can be performed using any of the following methods: plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, sputtering, etc. This application does not specifically limit the deposition method; it can be selected according to experimental needs.
[0054] Plasma-enhanced chemical vapor deposition (PECVD) is a method for preparing semiconductor thin films and other material thin films by using glow discharge to ionize the substrate in a deposition chamber and then performing a chemical reaction deposition on the substrate. PECVD enhances the activity of the chemical vapor reactants through plasma activation, increasing the surface reaction rate, and significantly reduces the film deposition temperature through high-energy ions. This technique results in low deposition temperature, minimal impact on the structure and physical properties of the substrate, fast deposition rate, and good film thickness and composition uniformity.
[0055] Low-Pressure Chemical Vapor Deposition (LPCVD) is a widely used thin-film deposition technique in semiconductor processes. It forms solid-state thin films by subjecting a substrate (such as a silicon wafer) to a gaseous chemical reaction at low pressure (typically from atmospheric pressure to approximately 10 Torr). The LPCVD process requires relatively high temperatures (approximately between 500°C and 1100°C) to activate gas molecules and promote their chemical reaction on the substrate surface. This technique enables the formation of uniform thin films on silicon wafers, and due to the uniform diffusion of the gas at low pressure, the film quality and crystal structure are typically excellent, exhibiting low defect density.
[0056] Sputtering is a process that uses particles (ions, neutral atoms, or molecules) of a certain energy to bombard the substrate surface, causing atoms or molecules near the substrate surface to gain sufficient energy and eventually escape from the substrate surface. Sputtering can only be performed under specific vacuum conditions. This technology can deposit high-purity thin films because it does not rely on chemical reactions but rather transfers particles to the substrate surface through a physical process. Sputtering can provide good adhesion between the film and the substrate, and the film thickness can be precisely adjusted by controlling the sputtering time and gas flow rate.
[0057] A TOPCon battery
[0058] This application discloses a TOPCon battery. According to an embodiment of this application, the battery is prepared by the method described above. A schematic diagram of the TOPCon battery structure according to an embodiment of this application is shown below. Figure 2 The structure includes: a silicon wafer 01, on the back side of which are sequentially formed a silicon oxide layer 02, a first doped polycrystalline silicon layer 03, a polycrystalline silicon oxide layer 04, a second doped polycrystalline silicon layer 05, and a silicon nitride anti-reflection passivation layer 06. It should be noted that this application does not specifically limit the front structure of the silicon wafer. For example, the front side of the silicon wafer may sequentially form a silicon nitride anti-reflection passivation layer 07, an aluminum oxide passivation layer 08, and a boron-expanded P+ region 09.
[0059] The TOPCon cells prepared by the method described in this application have a wider bandgap silicon oxide layer and a polycrystalline silicon layer, better passivation performance, and higher open-circuit voltage, short-circuit current density, and photoelectric conversion efficiency.
[0060] The following will explain the solution of this application with reference to embodiments. Those skilled in the art will understand that the following embodiments are for illustrative purposes only and should not be considered as limiting the scope of this application. Where specific techniques or conditions are not specified in the embodiments, they are performed according to the techniques or conditions described in the literature in the art or according to the product instructions. Reagents or instruments whose manufacturers are not specified are all conventional products that can be obtained commercially.
[0061] Example 1
[0062] The fabrication of TOPCon batteries includes the following steps:
[0063] (1) Select an N-type silicon wafer that has been alkaline polished on the back side. The back side of the silicon wafer has a natural wet oxide layer.
[0064] (2) A 2.0 nm thick SiOx layer was prepared using PECVD technology;
[0065] (3) A first doped amorphous silicon layer was prepared on the SiOx thin film by depositing a phosphorus concentration of 1.0 × 10⁻⁶ using PECVD technology. 19 atom / cm 3 The first doped amorphous silicon layer has a thickness of 8 nm;
[0066] (4) Based on the first doped amorphous silicon layer, a 1.0 nm amorphous silicon oxide layer is prepared using PECVD technology;
[0067] (5) On the basis of the amorphous silicon oxide layer, a phosphorus concentration of 7.0×10⁻⁶ is deposited using PECVD technology. 20 atom / cm 3 A second doped amorphous silicon layer with a thickness of 90 nm;
[0068] (6) The subsequent process conditions of the battery cell are the same as those of the existing technology. The cell is annealed at 910℃ for 25 minutes, followed by RCA cleaning, front aluminum oxide passivation layer (AlOx) and silicon nitride anti-reflection passivation layer (SiNx) coating, back silicon nitride anti-reflection passivation layer (SiNx) coating, and finally screen printing to obtain the TOPCon battery.
[0069] Examples 2 to 21 and Comparative Example 1 were prepared according to the method described in Example 1, with differences shown in Table 1.
[0070] The difference between Comparative Example 1 and Example 1 is that Comparative Example 1 did not deposit an amorphous silicon oxide layer on the side of the first doped amorphous silicon layer away from the silicon oxide layer. The specific process is as follows:
[0071] (1) Select an N-type silicon wafer that has been alkaline polished on the back side. The back side of the silicon wafer has a natural wet oxide layer.
[0072] (2) A 2.0 nm thick SiOx layer was prepared using PECVD technology;
[0073] (3) A first doped amorphous silicon layer was prepared on the SiOx thin film by depositing a phosphorus concentration of 1.0 × 10⁻⁶ using PECVD technology. 19 atom / cm 3 The first doped amorphous silicon layer has a thickness of 8 nm;
[0074] (5) Based on the first doped amorphous silicon layer, a phosphorus concentration of 7.0 × 10⁻⁶ is deposited using PECVD technology. 20 atom / cm 3 A second doped amorphous silicon layer with a thickness of 90 nm;
[0075] (6) The subsequent process conditions of the battery cell are the same as those of the existing technology. The cell is annealed at 910℃ for 25 minutes, followed by RCA cleaning, front aluminum oxide passivation layer (AlOx) and silicon nitride anti-reflection passivation layer (SiNx) coating, back silicon nitride anti-reflection passivation layer (SiNx) coating, and finally screen printing to obtain the TOPCon battery.
[0076] Table 1
[0077]
[0078]
[0079] Performance testing
[0080] The batteries prepared in Examples 1-21 and Comparative Example 1 were subjected to performance sequencing. The open-circuit voltage, short-circuit current density, fill factor, and photoelectric conversion efficiency of each battery were detected. The specific process is as follows:
[0081] The conversion efficiency is calculated by measuring the IV relationship curve of a forward-biased solar cell.
[0082] Photoelectric conversion efficiency measurement: Eta=Uoc*Isc*FF / Pin / S;
[0083] Where Uoc is the open-circuit voltage, Isc is the short-circuit current, FF is the fill factor, Pin is the incident light power per unit area (W / m2), Pin standard light intensity refers to 1000 W / m2 under AM1.5 spectrum and 25°C test temperature, and S is the cell area.
[0084] The test results are shown in Table 2. Compared with the TOPCon cell without an amorphous silicon oxide layer in Comparative Example 1, the open-circuit voltage, short-circuit current density, fill factor and photoelectric conversion efficiency of the TOPCon cells prepared in Examples 1-21 are all improved.
[0085] Table 2
[0086]
[0087]
[0088] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0089] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. A method for preparing a TOPcon battery, characterized in that, include: A silicon oxide layer is formed on the back side of the silicon wafer; A first doped amorphous silicon layer is deposited on the side of the silicon oxide layer away from the silicon wafer; An amorphous silicon oxide layer is deposited on the side of the first doped amorphous silicon layer away from the silicon oxide layer; A second doped amorphous silicon layer is deposited on the side of the amorphous silicon oxide layer away from the first doped amorphous silicon layer; The TOPcon battery is obtained by annealing a silicon wafer containing a silicon oxide layer, a first doped amorphous silicon layer, an amorphous silicon oxide layer, and a second doped amorphous silicon layer.
2. The method according to claim 1, characterized in that, The thickness of the amorphous silicon oxide layer is 0.8 nm to 1.2 nm.
3. The method according to claim 2, characterized in that, Phosphorus is doped in both the first doped amorphous silicon layer and the second doped amorphous silicon layer.
4. The method according to claim 3, characterized in that, The thickness of the first doped amorphous silicon layer is 5 nm to 10 nm; And / or, the thickness of the second doped amorphous silicon layer is 85 nm to 95 nm.
5. The method according to claim 4, characterized in that, The doping concentration of the first doped amorphous silicon layer is 0.8 × 10⁻⁶. 19 ~1.2×10 19 atom / cm 3 .
6. The method according to claim 4, characterized in that, The doping concentration of the second doped amorphous silicon layer is 6.8 × 10⁻⁶. 20 ~7.2×10 20 atom / cm 3 .
7. The method according to claim 1, characterized in that, The thickness of the silicon oxide layer is 1.2 nm to 2.5 nm.
8. The method according to claim 1, characterized in that, The annealing temperature is 900℃~920℃; And / or, the annealing process takes 23 to 27 minutes.
9. The method according to claim 1, characterized in that, The deposition is performed by any one of plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or sputtering.
10. A TOPCon battery, characterized in that, The TOPCon battery is prepared using the method described in any one of claims 1 to 9.