Nitride epitaxial wafer and preparation method and application thereof
By introducing patterned microstructures into nitride epitaxial wafers, the surface damage and lattice mismatch problems caused by dry etching are solved, improving carrier recombination uniformity and luminous efficiency, and enhancing the brightness and efficiency of nitride light-emitting diodes.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU INST OF ADVANCED SEMICON CO LTD
- Filing Date
- 2024-11-19
- Publication Date
- 2026-05-19
AI Technical Summary
Existing nitride light-emitting diodes suffer from surface damage during the fabrication process due to dry etching, which affects luminous efficiency. Furthermore, the lattice mismatch between quantum wells and quantum barriers leads to high dislocation density and severe nonradiative recombination, impacting brightness and efficiency.
Patterned microstructures, including silicon nanopillars and metal nitride island protrusions, are introduced between the n-type nitride layer and the nitride luminescent layer to modulate compressive stress and improve carrier recombination uniformity and luminescent area.
By introducing patterned microstructures, the compressive stress in the nitride luminescent layer is compensated, thereby improving the uniformity of carrier recombination and the luminescent area, and enhancing the brightness and luminous efficiency of the nitride epitaxial wafer.
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Figure CN122069848A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology and relates to a nitride epitaxial wafer, its preparation method and application. Background Technology
[0002] Light-emitting diodes (LEDs) are a new type of optoelectronic device used in lighting, displays, and communications. They offer advantages such as long lifespan, low power consumption, small size, and high reliability. As LED technology continues to develop, its applications will become increasingly widespread. However, LEDs still suffer from low luminous intensity and efficiency, and further improving luminous intensity and efficiency remains the primary goal of LED technology development.
[0003] Micro-LEDs are composed of arrays of micron-sized semiconductor light-emitting units. Due to their advantages of small size, high resolution, low power consumption, and high reliability, Micro-LEDs are widely used in various fields such as visible light communication, large flat panel displays, virtual reality and wearable displays, television and lighting, optogenetics, and neural interface light sources. Currently, for Group III nitride Micro-LEDs, a combination of standard photolithography and dry etching is typically used for fabrication. However, the dry etching process inevitably causes surface damage to the Micro-LED chip, severely affecting its luminous efficiency. Simultaneously, because the nitride light-emitting layer requires heterogeneous structures as quantum wells and quantum barriers, the large lattice and thermal expansion mismatch between the quantum wells and quantum barriers leads to high dislocation density and stress in the nitride light-emitting layer, resulting in high nonradiative recombination and severely impacting the device's brightness and efficiency.
[0004] Based on the above research, there is a need to provide a nitride epitaxial wafer to effectively improve the brightness and luminous efficiency of nitride light-emitting diodes. Summary of the Invention
[0005] The purpose of this invention is to provide a nitride epitaxial wafer, its preparation method, and its application. The nitride epitaxial wafer introduces a patterned microstructure between the n-type nitride layer and the nitride luminescent layer, which can modulate and compensate for the compressive stress in the nitride luminescent layer, improve the uniformity of carrier recombination, and increase the luminescent area of the nitride luminescent layer, thereby improving the brightness and luminous efficiency of the nitride epitaxial wafer.
[0006] To achieve this objective, the present invention adopts the following technical solution:
[0007] In a first aspect, the present invention provides a nitride epitaxial wafer, the nitride epitaxial wafer comprising:
[0008] Substrate;
[0009] An n-type nitride layer is disposed on one side of the substrate;
[0010] At least one patterned microstructure is disposed on the side of the n-type nitride layer away from the substrate. The patterned microstructure includes a pillar and an island-shaped protrusion at the top of the pillar. The pillar includes an n-type nitride intercalation layer pillar and a silicon nanopillar. The n-type nitride intercalation layer pillar is disposed on the side of the n-type nitride layer away from the substrate, and the silicon nanopillar is disposed on the side of the n-type nitride intercalation layer pillar away from the n-type nitride layer. The island-shaped protrusion includes a metal nitride.
[0011] A nitride light-emitting layer is disposed on the side of the n-type nitride layer away from the substrate and covers the patterned microstructure;
[0012] A p-type nitride layer is disposed on the side of the nitride luminescent layer away from the n-type nitride layer and the patterned microstructure.
[0013] Preferably, the nitride epitaxial wafer further includes a doped nitride layer disposed between the n-type nitride layer and the nitride light-emitting layer, and the patterned microstructure is disposed on the side of the doped nitride layer away from the n-type nitride layer.
[0014] Preferably, the nitride epitaxial wafer further includes a metal nitride capping layer disposed between the doped nitride layer and the nitride luminescent layer, and covering the patterned microstructure.
[0015] Preferably, the metal nitride in the metal nitride capping layer and the metal nitride in the island-shaped protrusions both comprise AlN.
[0016] Preferably, the nitride luminescent layer includes at least one composite layer, the composite layer including a nitride quantum well layer and a nitride quantum barrier layer stacked sequentially, wherein, in the same composite layer, the nitride quantum barrier layer is located on the side closer to the p-type nitride layer.
[0017] In a second aspect, the present invention provides a method for preparing a nitride epitaxial wafer as described in the first aspect, the method comprising the following steps:
[0018] Provide substrate;
[0019] An n-type nitride layer and an n-type nitride insertion layer are sequentially grown on the surface of the substrate;
[0020] At least one metal island protrusion is grown on the surface of the n-type nitride insertion layer. Then, a metal nitride film is grown on the surface of the metal island protrusion. The metal nitride film and the n-type nitride insertion layer not covered by the metal island protrusion are then etched away, and an n-type nitride insertion layer pillar is obtained below the metal island protrusion.
[0021] Silicon nanopillars are grown between the metal island protrusions and the n-type nitride insert pillars. After the metal in the metal island protrusions is converted into metal nitrides, at least one patterned microstructure is obtained on the surface of the n-type nitride layer.
[0022] A nitride luminescent layer covering the patterned microstructure is grown on the surface of the n-type nitride layer;
[0023] A p-type nitride layer is grown on the surface of the nitride luminescent layer to obtain the nitride epitaxial wafer.
[0024] Preferably, an undoped nitride layer is grown between the n-type nitride layer and the n-type nitride insertion layer, and a silicon surface treatment is performed after obtaining the n-type nitride insertion layer pillar and before growing the silicon nanopillars.
[0025] Preferably, the conditions for the silicon surface treatment include sequential silicon thermal treatment and interrupted silicon thermal treatment;
[0026] Preferably, the temperature of the silicon heat treatment is 750-1100℃.
[0027] Preferably, a metal nitride capping layer covering the patterned microstructure is first grown on the surface of the n-type nitride layer, and then the nitride luminescent layer is grown on the surface of the metal nitride capping layer. Preferably, the n-type nitride insertion layer is grown at a temperature of 750-950°C.
[0028] Preferably, the metal island-shaped protrusions are grown under a first growth condition, the first growth condition including:
[0029] (i) Perform metal hot surface treatment and interrupt metal hot surface treatment sequentially.
[0030] (ii) After repeating step (i) 1-20 times, annealing is performed while maintaining the temperature.
[0031] Preferably, the silicon nanopillars are grown under a third growth condition, which includes repeating the following steps 10-100 times: sequentially performing Si thermal surface treatment and interrupting Si source surface treatment.
[0032] Preferably, the temperature of the Si thermal surface treatment is 700-1050℃.
[0033] Thirdly, the present invention provides an electronic device comprising a nitride epitaxial wafer as described in the first aspect.
[0034] Compared with the prior art, the present invention has the following beneficial effects:
[0035] This invention provides an embodiment of the invention by setting at least one patterned microstructure between the n-type nitride layer and the nitride luminescent layer. The patterned microstructure includes silicon nanopillars and island-shaped protrusions made of metal nitride. Therefore, Si nanomaterials can be introduced into the epitaxial layer. The large lattice constant of Si nanomaterials can be used to introduce tensile stress in the nitride luminescent layer to compensate for the compressive stress in the luminescent layer. This improves the incorporation of In in the nitride luminescent layer, enhances the uniformity of In distribution in the nitride luminescent layer, improves the uniformity of carrier recombination, and simultaneously increases the luminescent area and carriers of the nitride luminescent layer, thereby improving the brightness and luminous efficiency of the nitride epitaxial wafer. Attached Figure Description
[0036] Figure 1 This is a schematic diagram of the structure of the first nitride epitaxial wafer of the present invention;
[0037] Figure 2 This is a schematic diagram of the structure of the second type of nitride epitaxial wafer of the present invention;
[0038] Figure 3 This is a schematic diagram of the structure of the third type of nitride epitaxial wafer of the present invention;
[0039] Among them, 1-substrate, 2-n-type nitride layer, 3-patterned microstructure, 31-n-type nitride insertion pillar, 32-silicon nanopillar, 33-island protrusion, 4-nitride light-emitting layer, 5-p-type nitride layer, 6-doped nitride layer, 7-metal nitride capping layer. Detailed Implementation
[0040] The technical solution of the present invention will be further illustrated below through specific embodiments. Those skilled in the art should understand that the embodiments described are merely illustrative of the present invention and should not be construed as limiting the invention in any way.
[0041] This invention provides a method such as Figure 1 The nitride epitaxial wafer shown comprises:
[0042] Substrate 1;
[0043] An n-type nitride layer 2 is disposed on one side of the substrate 1;
[0044] At least one patterned microstructure 3 is disposed on the side of the n-type nitride layer 2 away from the substrate 1. The patterned microstructure 3 includes a pillar and an island-shaped protrusion 33 at the top of the pillar. The pillar includes an n-type nitride insertion layer pillar 31 and a silicon nanopillar 32. The n-type nitride insertion layer pillar 31 is disposed on the side of the n-type nitride layer 2 away from the substrate 1, and the silicon nanopillar 32 is disposed on the side of the n-type nitride insertion layer pillar 31 away from the n-type nitride layer 2. The island-shaped protrusion 33 includes a metal nitride.
[0045] A nitride light-emitting layer 4 is disposed on the side of the n-type nitride layer 2 away from the substrate 1 and covers the patterned microstructure 3;
[0046] The p-type nitride layer 5 is disposed on the side of the nitride luminescent layer 4 away from the n-type nitride layer 2 and the patterned microstructure 3.
[0047] A schematic diagram of the structure of the first nitride epitaxial wafer of the present invention is shown below. Figure 1 As shown, the structure includes a substrate 1, an n-type nitride layer 2, a nitride luminescent layer 4, and a p-type nitride layer 5 stacked sequentially. At least one patterned microstructure 3 is disposed between the n-type nitride layer 2 and the nitride luminescent layer 4. The patterned microstructure 3 is a pillar with island-shaped protrusions 33 on its top, and the nitride luminescent layer 4 covers the patterned microstructure 3. On one hand, the patterned microstructure 3 can modulate and compensate for the compressive stress in the nitride luminescent layer 4. Specifically, it utilizes the lattice mismatch between the silicon nanopillars 32 and the metal nitrides of the island-shaped protrusions 33 to introduce tensile stress in the epitaxial layer. This tensile stress greatly increases the incorporation of In in the nitride luminescent layer 4, significantly improving the uniformity of In distribution and thus greatly enhancing the uniformity of carrier recombination. On the other hand, the patterned microstructure 3 increases the luminescent area and carriers of the nitride luminescent layer 4, improving the brightness and luminous efficiency of the nitride epitaxial wafer.
[0048] In some embodiments, the substrate 1 is made of sapphire, which serves as a growth template.
[0049] In some embodiments, the thickness of the n-type nitride layer 2 is 2-5 μm, for example, it can be 2 μm, 3 μm, 4 μm or 5 μm, and the Si doping concentration is 1×10⁻⁶. 18 -5×10 19 cm -3 For example, it could be 1×10 18 cm -3 5×10 18 cm -3 1×10 19 cm -3 Or 5×10 19 cm -3 The material includes any one or a combination of at least two of GaN, AIN, AlGaN, InN, InGaN, AlInN, or AlGaInN.
[0050] In some embodiments, the height of the n-type nitride insertion pillar 31 is 10-50 nm, for example, it can be 10 nm, 20 nm, 30 nm, 40 nm or 50 nm, and the Si doping concentration is 5 × 10⁻⁶. 19-5×10 20 cm -3 For example, it could be 5×10 19 cm -3 1×10 20 cm -3 Or 5×10 20 cm -3 The material includes any one or a combination of at least two of GaN, AlN, AlGaN, InN, InGaN, AlInN, or AlGaInN; the n-type nitride insertion layer pillar 31 has a high Si doping concentration and its surface is distributed with high-density dislocation centers.
[0051] In some embodiments, the height of the silicon nanopillars 32 is 2-10 nm, for example, it can be 2 nm, 4 nm, 6 nm, 8 nm or 10 nm, but is not limited to the listed values, and other unlisted values within the range are also applicable.
[0052] In some embodiments, the thickness of the p-type nitride layer 5 is 20-200 nm, for example, it can be 20 nm, 50 nm, 100 nm, 150 nm or 200 nm, and the Si doping concentration is 1 × 10⁻⁶. 19 -5×10 20 cm -3 For example, it could be 1×10 19 cm -3 5×10 19 cm -3 1×10 20 cm -3 Or 5×10 20 cm -3 The material includes any one or a combination of at least two of GaN, AIN, AlGaN, InN, InGaN, AlInN, or AlGaInN.
[0053] Furthermore, the present invention provides a method such as Figure 2 The second type of nitride epitaxial wafer shown further includes a doped nitride layer 6 disposed between the n-type nitride layer 2 and the nitride light-emitting layer 4, and the patterned microstructure 3 is disposed on the side of the doped nitride layer 6 away from the n-type nitride layer 2.
[0054] The doped nitride layer 6 of the present invention can avoid the formation of free Si atoms as impurity defects in the region near the nitride light-emitting layer 4, which would cause light absorption. At the same time, it can reduce the series resistance between the n-type nitride layer 2 and the nitride light-emitting layer 4, reduce the working voltage of the epitaxial wafer, improve the uniformity of carrier injection, and improve the brightness and luminous efficiency of the epitaxial wafer.
[0055] In some embodiments, the thickness of the doped nitride layer 6 is 20-80 nm, for example, it can be 20 nm, 40 nm, 60 nm or 80 nm, wherein the doped nitride layer 6 is doped with silicon, and the material includes any one or a combination of at least two of GaN, AlGaN, InN, AlInN or AlGaInN.
[0056] Furthermore, the present invention provides a method such as Figure 3 The third type of nitride epitaxial wafer shown further includes a metal nitride capping layer 7 disposed between the doped nitride layer 6 and the nitride light-emitting layer 4, and covering the patterned microstructure 3.
[0057] The metal nitride capping layer 7 of the present invention can be uniformly nucleated on the patterned microstructure 3, covering the patterned microstructure 3, and providing a basis for the growth of the nitride light-emitting layer 4.
[0058] In some embodiments, the thickness of the metal nitride capping layer 7 is 2-10 nm, for example, it can be 2 nm, 4 nm, 6 nm, 8 nm or 10 nm, but is not limited to the listed values, and other unlisted values within the range are also applicable.
[0059] In some embodiments, the metal nitride in the metal nitride capping layer 7 and the metal nitride in the island protrusions 33 both comprise AlN.
[0060] Furthermore, the nitride luminescent layer 4 includes at least one composite layer, which includes a nitride quantum well layer and a nitride quantum barrier layer stacked sequentially, wherein, in the same composite layer, the nitride quantum barrier layer is located on the side closer to the p-type nitride layer 5.
[0061] The nitride luminescent layer 4 of the present invention includes a nitride quantum well layer and a nitride quantum barrier layer arranged in a periodic cycle. The nitride quantum barrier layer is located on the side close to the p-type nitride layer 5, while the nitride quantum well layer is located on the side close to the patterned microstructure 3. The patterned microstructure 3 makes it relatively easier for In atoms to be incorporated into the growth surface of the nitride quantum well layer under tensile stress conditions.
[0062] In some embodiments, the number of composite layers is 2-15, for example, 2, 4, 6, 7, 10, 12 or 15 layers, but not limited to the listed values, and other unlisted values within the range are also applicable.
[0063] In some embodiments, the thickness of the nitride quantum well layer is 1-5 nm, for example, it can be 1 nm, 2 nm, 3 nm, 4 nm or 5 nm, and the material includes any one or a combination of at least two of GaN, AlGaN, InN, InGaN, AlInN or AlGaInN.
[0064] In some embodiments, the thickness of the nitride quantum barrier layer is 6-25 nm, for example, it can be 6 nm, 10 nm, 15 nm, 20 nm or 25 nm, and the material includes any one or a combination of at least two of GaN, AlGaN, InN, AlInN or AlGaInN.
[0065] The present invention also provides a method for preparing the nitride epitaxial wafer, the method comprising the following steps:
[0066] Substrate 1 is provided;
[0067] An n-type nitride layer 2 and an n-type nitride insertion layer are sequentially grown on the surface of the substrate 1;
[0068] At least one metal island protrusion 33 is grown on the surface of the n-type nitride insertion layer, and then a metal nitride film is grown on the surface of the metal island protrusion 33. The metal nitride film and the n-type nitride insertion layer not covered by the metal island protrusion 33 are then etched away, and an n-type nitride insertion layer pillar 31 is obtained below the metal island protrusion 33.
[0069] Silicon nanopillars 32 are grown between the metal island protrusions 33 and the n-type nitride insert pillars 31. After the metal in the metal island protrusions 33 is converted into metal nitride, at least one patterned microstructure 3 is obtained on the surface of the n-type nitride layer 2.
[0070] A nitride light-emitting layer 4 covering the patterned microstructure 3 is grown on the surface of the n-type nitride layer 2;
[0071] A p-type nitride layer 5 is grown on the surface of the nitride luminescent layer 4 to obtain the nitride epitaxial wafer.
[0072] In this invention, after sequentially growing an n-type nitride layer 2 and an n-type nitride insertion layer on a substrate 1, at least one metal island-shaped protrusion 33 can be grown on the surface of the n-type nitride insertion layer, which has a high density of dislocation centers. Then, a metal nitride film is grown on the surface of the metal island-shaped protrusion 33, covering the metal island-shaped protrusion 33, in preparation for the next step of etching the n-type nitride insertion layer. Compared with the n-type nitride insertion layer, the metal-N in the metal nitride film has high stable bonding and a low etching rate during the etching process. The n-type nitride insertion layer has a high etching rate, and its high dislocation distribution further enhances the etching rate. Therefore, the n-type nitride insertion layer not covered by the metal island-shaped protrusion 33 can be etched away at a higher speed, and the metal nitride film can be etched away at a lower speed, thereby obtaining an n-type nitride insertion layer pillar 31 below the metal island-shaped protrusion 33.
[0073] Then, this invention utilizes the characteristic that silicon atoms dissolve and precipitate in micro / nano liquid metal structures and grow axially to form nanostructures, growing silicon nanopillars below the metal island-like protrusions. The specific principle is as follows: This invention introduces Si atoms onto the surface of the metal island-like protrusions. The Si atoms dissolve under heat treatment, and under the continuous treatment of Si atoms, Si forms a non-equilibrium diffusion growth on the surface of the metal island-like protrusions. On the one hand, with the heat treatment of Si, a high concentration of Si atoms accumulates on the surface of the liquid metal structure, creating a large concentration difference between the surface and the interior of the liquid metal structure, i.e., the surface has a high diffusion potential energy, causing Si atoms to continuously diffuse and precipitate crystals from the direction of high diffusion energy to low diffusion energy in the direction of the concentration difference. On the other hand, the precipitation of Si atoms from other positions on the surface requires a higher saturation, while the precipitation of solid Si nanopillars at the interface of the bottom of the liquid metal structure has the lowest diffusion energy, causing Si atoms to continuously diffuse in the direction of the concentration difference, precipitating from the bottom of the liquid metal, and finally forming silicon nanopillars at the bottom liquid-solid interface, rather than forming silicon nanopillars in other directions.
[0074] Below the metal island protrusion 33, i.e., between the metal island protrusion 33 and the n-type nitride insertion layer pillar 31, silicon nanopillars 32 are grown; then, after the metal in the metal island protrusion 33 is converted into metal nitride, at least one patterned microstructure 3 is obtained on the surface of the n-type nitride layer 2. Finally, a nitride light-emitting layer 4 and a p-type nitride layer 5 covering the patterned microstructure 3 are grown sequentially on the surface of the n-type nitride layer 2 to obtain the nitride epitaxial wafer.
[0075] Furthermore, an undoped nitride layer 6 is grown between the n-type nitride layer 2 and the n-type nitride insertion layer, and a silicon surface treatment is performed after obtaining the n-type nitride insertion layer pillar 31 and before growing the silicon nanopillar 32.
[0076] The doped nitride layer 6 of the present invention is prepared in situ from the undoped nitride layer 6. Specifically, silicon surface treatment is performed after the n-type nitride insertion layer pillar 31 and before the growth of silicon nanopillars 32, in conjunction with the silicon nanopillar preparation process. In addition, the silicon surface treatment will cause the metal island protrusions 33 to form a metal-Si eutectic structure inside, but the Si in the metal-Si eutectic structure will participate in the growth of silicon nanopillars 32 during the growth stage of silicon nanopillars 32.
[0077] In some embodiments, the undoped nitride layer 6 is grown at a temperature of 1050-1250°C, such as 1050°C, 1100°C, 1150°C, 1200°C or 1250°C, but is not limited to the listed values. Other unlisted values within the range are also applicable.
[0078] In some embodiments, the silicon surface treatment includes sequential silicon thermal treatment and interrupted silicon thermal treatment;
[0079] In some embodiments, the temperature of the silicon heat treatment is 750-1100°C, for example, 750°C, 850°C, 950°C, 1050°C or 1100°C, and the time is 120-300s, for example, 120s, 150s, 200s, 250s or 300s, but not limited to the listed values. Other unlisted values within the range are also applicable. This invention forms a Si deposition layer on a silicon surface treated at 750-1100℃. On one hand, silicon heat treatment forms Si deposition on the surface of the metal island protrusions and the undoped nitride layer. Interrupting the silicon heat treatment process promotes the formation of a metal microstructure aggregation center-Si eutectic structure in the metal island protrusions. Performing silicon surface treatment at a higher temperature than that for forming silicon nanopillars can improve the diffusion and dissolution of Si in the metal microstructure. On the other hand, Si diffuses into the undoped nitride layer to form an n-type doped nitride layer, avoiding the formation of free Si atoms as impurity defects in the region near the nitride luminescent layer, which would cause light absorption. At the same time, it reduces the series resistance between the n-type nitride layer and the nitride luminescent layer, reduces the operating voltage of the epitaxial wafer, improves the uniformity of carrier injection, and improves the brightness and luminous efficiency of the epitaxial wafer.
[0080] In some embodiments, the interruption time of the silicon thermal treatment is 100-600s, for example, it can be 100s, 300s, 500s or 600s, but is not limited to the listed values. Other unlisted values within the range are also applicable.
[0081] Furthermore, a metal nitride capping layer 7 covering the patterned microstructure 3 is first grown on the surface of the n-type nitride layer 2, and then the nitride light-emitting layer 4 is grown on the surface of the metal nitride capping layer 7.
[0082] This invention utilizes the poor migration activity of metal atoms to grow a metal nitride capping layer 7 covering the patterned microstructure 3, providing a basis for the growth of the nitride luminescent layer 4.
[0083] In some embodiments, the metal nitride capping layer 7 is grown at a temperature of 950-1100°C, for example, 950°C, 1000°C, 1050°C or 1100°C, but not limited to the listed values, and other unlisted values within the range are also applicable.
[0084] In some embodiments, the n-type nitride layer 2 is grown at a temperature of 1050-1250°C, for example, 1050°C, 1150°C, or 1250°C, and a pressure of 100-300 torr, for example, 100 torr, 200 torr, or 300 torr.
[0085] In some embodiments, the conditions for growing the nitride light-emitting layer 4 include repeating the following steps 2-15 times: sequentially growing a nitride quantum well layer and a nitride quantum barrier layer.
[0086] In some embodiments, the growth temperature of the nitride quantum well layer is 650-850°C, for example, 650°C, 750°C or 850°C, and the growth temperature of the nitride quantum barrier layer is 700-1000°C, for example, 700°C, 800°C, 900°C or 1000°C, but is not limited to the listed values. Other unlisted values within the range are also applicable.
[0087] In some embodiments, the p-type nitride layer 5 is grown at a temperature of 850-1050°C, for example, 850°C, 950°C, or 1050°C, but not limited to the listed values. Other unlisted values within the range are also applicable.
[0088] Furthermore, the n-type nitride insertion layer is grown at a temperature of 750-950°C, for example, 750°C, 850°C or 950°C, but not limited to the listed values. Other unlisted values within the range are also applicable.
[0089] This invention grows a highly doped n-type nitride insertion layer on the n-type nitride layer 2 at a relatively low growth temperature (the growth temperature of the n-type nitride layer 2 is higher than that of the n-type nitride insertion layer), resulting in a high density of dislocation centers distributed on the surface of the n-type nitride insertion layer.
[0090] In some embodiments, the metal island-shaped protrusion 33 is grown under a first growth condition, the first growth condition including:
[0091] (i) Perform metal hot surface treatment and interrupt metal hot surface treatment sequentially.
[0092] (ii) After repeating step (i) 1-20 times, annealing is performed while maintaining the temperature.
[0093] Under the first growth conditions of the present invention, a metal thermal surface treatment of 120-600s, such as Al thermal treatment, can be performed to form a metal deposition layer. More preferably, the metal thermal surface treatment (such as Al thermal treatment) and the metal thermal surface treatment are performed alternately and periodically, and finally annealing is performed, which can form metal island-shaped protrusions 33 on the surface of the n-type nitride insertion layer with a high density of dislocation centers.
[0094] In some embodiments, the temperature of the metal thermal surface treatment is 750-950°C, for example, 750°C, 850°C or 950°C, and the time is 10-30s, for example, 10s, 20s or 30s, but is not limited to the listed values. Other unlisted values within the range are also applicable.
[0095] In some embodiments, the interruption of the metal hot surface treatment is 5-10 seconds, for example, 5 seconds, 7 seconds, 9 seconds or 10 seconds, but is not limited to the listed values. Other unlisted values within the range are also applicable.
[0096] In some embodiments, the annealing time is 40-90s, for example, 40s, 50s, 60s, 70s, 80s or 90s, but not limited to the listed values. Other unlisted values within the range are also applicable.
[0097] In some embodiments, under a second growth condition, a metal nitride film is grown on the surface of the metal island protrusion 33. The second growth condition includes nitrogen heat treatment at a temperature of 900-1000°C, for example, 900°C, 950°C or 1000°C for 10-30 seconds, for example, 10 seconds, 20 seconds or 30 seconds, but is not limited to the listed values. Other unlisted values within the range are also applicable.
[0098] Under the second growth condition, the present invention performs insufficient nitriding on the metal island protrusion 33, and only nitriding is performed on the surface of the metal island protrusion 33, thereby forming a metal nitride film on the surface of the metal island protrusion 33.
[0099] In some embodiments, under etching conditions, the metal nitride film and the n-type nitride insertion layer not covered by the metal island protrusions 33 are etched away. The etching conditions include: processing at a temperature of 1050-1200°C in a reducing gas atmosphere, for example, 1050°C, 1100°C, 1150°C or 1200°C for 300-800s, for example, 300s, 500s, 700s or 800s, but not limited to the listed values. Other unlisted values within the range are also applicable.
[0100] In some embodiments, the reducing gas atmosphere includes H2.
[0101] In some embodiments, the silicon nanopillars 32 are grown under a third growth condition, the third growth condition comprising repeating the following steps 10-100 times: sequentially performing Si thermal surface treatment and interrupting Si source surface treatment.
[0102] In the process of growing silicon nanopillars 32, the present invention performs Si thermal surface treatment and interrupted Si source surface treatment in a periodic cycle. During the periodic cycle, Si atoms can be fully dissolved and continuously and uniformly precipitated on the surface of the metal island protrusions 33. On the one hand, a flat Si nanopillar structure is obtained, and on the other hand, the accumulation of freely moving Si atoms on the surface of the metal island protrusions 33 is prevented, thus avoiding the absorption of light directed toward the substrate 1 by the freely moving Si atoms as impurity atoms.
[0103] In some embodiments, the temperature of the Si thermal surface treatment is 700-1050℃, for example, 700℃, 80℃, 900℃, 1000℃ or 1050℃, and the time is 10-100s, for example, 10s, 30s, 50s, 70s, 90s or 100s, but not limited to the listed values. Other unlisted values within the range are also applicable.
[0104] The silicon nanopillars are formed at a relatively low temperature (compared to the silicon surface treatment process described above that forms a doped nitride layer from the undoped nitride layer) to promote the precipitation of Si atoms. This avoids the uneven precipitation of Si atoms caused by diffusion due to differences in Si atom concentration at high temperatures, thus improving the uniformity of Si atom precipitation.
[0105] In addition, since Si diffuses into the undoped nitride layer during the growth of Si nanopillars, the silicon surface treatment performed after the n-type nitride insertion layer pillars and before the growth of silicon nanopillars in this invention, as well as the two steps of growing silicon nanopillars, enable the undoped nitride layer to eventually form a doped nitride layer.
[0106] In some embodiments, the interruption time for the Si source surface treatment is 10-180s, for example, it can be 10s, 50s, 100s, 150s or 180s, but is not limited to the listed values. Other unlisted values within the range are also applicable.
[0107] In some embodiments, the conditions for converting the metal in the metal island protrusion 33 into a metal nitride include: nitrogen heat treatment at a temperature of 900-1050°C, for example, 900°C, 1000°C, or 1050°C, for 120-360 seconds, for example, 120 seconds, 150 seconds, 200 seconds, 250 seconds, 300 seconds, or 360 seconds, but not limited to the listed values; other unlisted values within the range are also applicable.
[0108] In some embodiments, the conditions for converting the metal in the metal island protrusion 33 into a metal nitride include: nitrogen heat treatment at a temperature of 900-1050°C, for example, 900°C, 1000°C or 1050°C for 120-360s, for example, 120s, 150s, 200s, 250s or 360s, but not limited to the listed values, and other unlisted values within the range are also applicable.
[0109] The present invention involves nitriding treatment, which transforms the metal in the metal island-shaped protrusions 33 into metal nitrides.
[0110] The technical solution of the present invention will be further illustrated below through embodiments.
[0111] Example 1
[0112] This embodiment provides a nitride epitaxial wafer, such as Figure 3 As shown, the nitride epitaxial wafer includes a substrate 1, an n-type nitride layer 2, a doped nitride layer 6, a metal nitride capping layer 7, a nitride light-emitting layer 4, and a p-type nitride layer 5 stacked sequentially, wherein a patterned microstructure 3 is disposed between the doped nitride layer 6 and the metal nitride capping layer 7.
[0113] The patterned microstructure 3 includes a pillar and an island-shaped protrusion 33 at the top of the pillar. The pillar includes an n-type nitride insertion layer pillar 31 and a silicon nanopillar 32. The n-type nitride insertion layer pillar 31 is disposed on the side of the doped nitride layer 6 away from the n-type nitride layer 2, and the silicon nanopillar 32 is disposed on the side of the n-type nitride insertion layer pillar 31 away from the doped nitride layer 6. The island-shaped protrusion 33 includes AlN.
[0114] The method for preparing the nitride epitaxial wafer includes the following steps:
[0115] S1: Provide a substrate for use as a template for epitaxial layer growth, wherein the substrate is made of sapphire.
[0116] S2: An n-type GaN layer with a thickness of 3 μm was grown on a GaN buffer layer at a temperature of 1150℃ and a pressure of 200 torr, wherein the Si doping concentration was 5 × 10⁻⁶. 18 cm -3 ;
[0117] S3: An undoped GaN layer with a thickness of 40 nm is grown on an n-type GaN layer at a temperature of 1250℃.
[0118] S4: An n-type GaN insertion layer with a thickness of 30 nm is grown on an undoped GaN layer at a temperature of 850℃, wherein the Si doping concentration is 5 × 10⁻⁶. 20 cm -3 ;
[0119] S5: Forming an Al metallic microstructure in the n-type GaN insertion layer, including steps S51 and S52:
[0120] S51: Repeat the alternation 10 times periodically. Steps S511-S512:
[0121] S511: The n-type GaN insertion layer is subjected to Al thermal surface treatment for 20s at a temperature of 850℃;
[0122] S512: Interrupt Al hot surface treatment for 8 seconds;
[0123] S52: Stop Al hot surface treatment and anneal for 60 seconds;
[0124] S6: Under a temperature of 950℃, perform N hot surface treatment for 20s to form an AlN thin layer on the surface of the Al metal microstructure.
[0125] S7: Surface etching is performed at 1150℃ under H2 reducing gas conditions for 500s;
[0126] S8: Perform surface heat treatment on Si at a temperature of 900℃, including the following steps:
[0127] S81: Perform Si heat treatment for 200 seconds;
[0128] S82: Interrupt Si heat treatment for 400 seconds;
[0129] S9: Growth of silicon nanopillars with a height of 6 nm at 800℃, including steps S91 and S92 repeated 50 times:
[0130] S91: Perform Si hot surface treatment for 50 seconds;
[0131] S92: Interrupt Si source surface treatment for 100 seconds;
[0132] S10: Under a temperature of 1000℃, perform N hot surface treatment for 250s to transform the Al metal microstructure into AlN island-shaped protrusions.
[0133] S11: An AlN capping layer with a thickness of 6 nm is grown at a temperature of 1000℃;
[0134] S12: Under a temperature of 800℃, the nitride quantum well layer and nitride quantum barrier layer grown in the periodic alternation steps S121-S122 serve as the nitride luminescent layer, and the cycle is repeated 8 times, including the following steps:
[0135] S121: An InGaN quantum well layer with a thickness of 3 nm was grown at a temperature of 750℃.
[0136] S122: A GaN quantum barrier layer with a thickness of 15 nm was grown at a temperature of 850℃;
[0137] S13: A 120 nm thick p-type GaN layer is grown on the nitride light-emitting layer at 900 °C, wherein the Si doping concentration is 5 × 10⁻⁶. 19 cm -3 .
[0138] Example 2
[0139] This embodiment provides a nitride epitaxial wafer, such as Figure 3 As shown, the nitride epitaxial wafer includes a substrate 1, an n-type nitride layer 2, a doped nitride layer 6, a metal nitride capping layer 7, a nitride light-emitting layer 4, and a p-type nitride layer 5 stacked sequentially, wherein a patterned microstructure 3 is disposed between the doped nitride layer 6 and the metal nitride capping layer 7.
[0140] The patterned microstructure 3 includes a pillar and an island-shaped protrusion 33 at the top of the pillar. The pillar includes an n-type nitride insertion layer pillar 31 and a silicon nanopillar 32. The n-type nitride insertion layer pillar 31 is disposed on the side of the doped nitride layer 6 away from the n-type nitride layer 2, and the silicon nanopillar 32 is disposed on the side of the n-type nitride insertion layer pillar 31 away from the doped nitride layer 6. The island-shaped protrusion 33 includes AlN.
[0141] The method for preparing the nitride epitaxial wafer includes the following steps:
[0142] S1: Provide a substrate for use as a template for epitaxial layer growth, wherein the substrate is made of sapphire.
[0143] S2: An n-type GaN layer with a thickness of 5 μm was grown on a GaN buffer layer at a temperature of 1250℃ and a pressure of 300 torr, wherein the Si doping concentration was 5 × 10⁻⁶. 19 cm -3 ;
[0144] S3: An undoped GaN layer with a thickness of 20 nm is grown on an n-type GaN layer at a temperature of 1050℃.
[0145] S4: An n-type GaN insertion layer with a thickness of 50 nm is grown on an undoped GaN layer at a temperature of 950℃, wherein the Si doping concentration is 1×10⁻⁶. 20 cm -3 ;
[0146] S5: Forming an Al metallic microstructure in the n-type GaN insertion layer, including steps S51 and S52:
[0147] S51: Repeat the alternating steps S511-S512 twice periodically:
[0148] S511: The n-type GaN insertion layer is subjected to Al thermal surface treatment for 30s at a temperature of 950℃;
[0149] S512: Interrupt Al hot surface treatment for 10 seconds;
[0150] S52: Stop Al hot surface treatment, anneal for 90 seconds;
[0151] S6: Under a temperature of 1000℃, perform N hot surface treatment for 10s to form an AlN thin layer on the surface of the Al metal microstructure;
[0152] S7: Surface etching is performed at 1200℃ under H2 reducing gas conditions for 300s;
[0153] S8: Perform surface heat treatment on Si at a temperature of 1100℃, including the following steps:
[0154] S81: Perform Si heat treatment for 300 seconds;
[0155] S82: Interrupt the Si heat treatment for 600s to form an n-type doped GaN layer from the undoped GaN layer;
[0156] S9: Growth of silicon nanopillars with a height of 10 nm at a temperature of 1050℃, including steps S91 and S92, which are repeated 100 times periodically.
[0157] S91: Perform Si hot surface treatment for 10 seconds;
[0158] S92: Interrupt the Si source surface treatment for 10 seconds;
[0159] S10: Under a temperature of 900℃, perform N hot surface treatment for 120s to transform the Al metal microstructure into AlN island-shaped protrusions.
[0160] S11: An AlN capping layer with a thickness of 2 nm was grown at a temperature of 950℃;
[0161] S12: The nitride quantum well layer and nitride quantum barrier layer grown in the periodic alternating steps S131-S132 serve as the nitride luminescent layer. This cycle is repeated twice, including the following steps:
[0162] S121: An InGaN quantum well layer with a thickness of 5 nm was grown at a temperature of 850℃.
[0163] S122: A GaN quantum barrier layer with a thickness of 25 nm is grown at a temperature of 1000℃;
[0164] S13: A 200 nm thick p-type GaN layer is grown on the nitride light-emitting layer at a temperature of 1050 °C, wherein the Si doping concentration is 5 × 10⁻⁶. 20 cm -3 .
[0165] Example 3
[0166] This embodiment provides a nitride epitaxial wafer, such as Figure 3 As shown, the nitride epitaxial wafer includes a substrate 1, an n-type nitride layer 2, a doped nitride layer 6, a metal nitride capping layer 7, a nitride light-emitting layer 4, and a p-type nitride layer 5 stacked sequentially, wherein a patterned microstructure 3 is disposed between the doped nitride layer 6 and the metal nitride capping layer 7.
[0167] The patterned microstructure 3 includes a pillar and an island-shaped protrusion 33 at the top of the pillar. The pillar includes an n-type nitride insertion layer pillar 31 and a silicon nanopillar 32. The n-type nitride insertion layer pillar 31 is disposed on the side of the doped nitride layer 6 away from the n-type nitride layer 2, and the silicon nanopillar 32 is disposed on the side of the n-type nitride insertion layer pillar 31 away from the doped nitride layer 6. The island-shaped protrusion 33 includes AlN.
[0168] The method for preparing the nitride epitaxial wafer includes the following steps:
[0169] S1: Provide a substrate for use as a template for epitaxial layer growth, wherein the substrate is made of sapphire.
[0170] S2: An n-type GaN layer with a thickness of 2 μm is grown on a GaN buffer layer at a temperature of 1050℃ and a pressure of 100 torr, wherein the Si doping concentration is 1×10⁻⁶. 18 cm -3 ;
[0171] S3: An undoped GaN layer with a thickness of 80 nm is grown on an n-type GaN layer at a temperature of 1250℃.
[0172] S4: An n-type GaN insertion layer with a thickness of 10 nm is grown on an undoped GaN layer at a temperature of 750℃, wherein the Si doping concentration is 5 × 10⁻⁶. 20 cm -3 ;
[0173] S5: Forming an Al metallic microstructure in the n-type GaN insertion layer, including steps S51 and S52:
[0174] S51: Repeat the alternation 1-20 times periodically. Steps S511-S512:
[0175] S511: The n-type GaN insertion layer is subjected to Al thermal surface treatment for 10s at a temperature of 750℃;
[0176] S512: Interrupt Al hot surface treatment for 5 seconds;
[0177] S52: Stop Al hot surface treatment and anneal for 40 seconds;
[0178] S6: Under a temperature of 900℃, perform N hot surface treatment for 30s to form an AlN thin layer on the surface of the Al metal microstructure;
[0179] S7: Surface etching is performed at 1050℃ under H2 reducing gas conditions for 800s;
[0180] S8: Perform surface heat treatment on Si at a temperature of 750℃, including the following steps:
[0181] S81: Perform Si heat treatment for 120 seconds;
[0182] S82: Interrupt the Si heat treatment for 100s to form an n-type doped GaN layer from the undoped GaN layer;
[0183] S9: Growth of silicon nanopillars with a height of 2 nm at a temperature of 700℃, including 10 cycles of steps S91 and S92:
[0184] S91: Perform Si hot surface treatment for 100s;
[0185] S92: Interrupt Si source surface treatment for 180 seconds;
[0186] S10: Under a temperature of 1050℃, N hot surface treatment is performed for 360s to transform the Al metal microstructure into AlN island-shaped protrusions.
[0187] S11: An AlN capping layer with a thickness of 10 nm is grown at a temperature of 1100℃;
[0188] S12: The nitride quantum well layer and nitride quantum barrier layer grown in the periodic alternating steps S121-S122 serve as the nitride luminescent layer, and the cycle is repeated 15 times, including the following steps:
[0189] S121: An InGaN quantum well layer with a thickness of 1 nm was grown at a temperature of 650℃.
[0190] S122: A GaN quantum barrier layer with a thickness of 6 nm was grown at a temperature of 700℃.
[0191] S13: A 20 nm thick p-type GaN layer is grown on the nitride light-emitting layer at 850 °C, wherein the Si doping concentration is 1 × 10⁻⁶. 19 cm -3 .
[0192] Example 4
[0193] This embodiment provides a nitride epitaxial wafer, which is the same as that in Embodiment 1 except that it does not include a doped nitride layer;
[0194] The preparation method of the nitride epitaxial wafer is the same as that in Example 1, except that step S4 is not performed.
[0195] Example 5
[0196] This embodiment provides a nitride epitaxial wafer, which is identical to that in Example 1 except that its preparation method does not include step S9, which changes the adaptability of the nitride epitaxial wafer.
[0197] Example 6
[0198] This embodiment provides a nitride epitaxial wafer, which is the same as that in Embodiment 1 except that it does not include a nitride capping layer;
[0199] The preparation method of the nitride epitaxial wafer is the same as that in Example 1, except that step S12 is not performed.
[0200] Comparative Example 1
[0201] This comparative example provides a nitride epitaxial wafer, which is the same as that in Example 1 except that it does not include a patterned microstructure;
[0202] The preparation method of the nitride epitaxial wafer is the same as that in Example 1, except that steps S6-S8 and S10-S11 are not performed.
[0203] Comparative Example 2
[0204] This comparative example provides a nitride epitaxial wafer, which is the same as that in Example 1 except that the patterned microstructure does not include silicon nanopillars;
[0205] The preparation method of the nitride epitaxial wafer is the same as that in Example 1, except that step S10 is not performed.
[0206] Comparative Example 3
[0207] This comparative example provides a nitride epitaxial wafer, which is the same as that in Example 1 except that the patterned microstructure does not include n-type nitride insert pillars;
[0208] The method for preparing the nitride epitaxial wafer is the same as in Example 1, except that steps S5, S7, and S8 are omitted and Al metal microstructures in S6 are prepared directly on the undoped GaN layer.
[0209] The nitride epitaxial wafers obtained in the above embodiments and comparative examples were subjected to performance testing. The wavelength uniformity (std / nm) and full width at half maximum (HW / nm) of the epitaxial wafers prepared in the above embodiments and comparative examples were tested by photoluminescence (PL). Then, Micro-LEDs were fabricated using the same preparation process and tested using an LED optoelectronic performance tester, including luminous intensity (Lop / mW) and voltage (VF / V) under a 2mA current injection condition, and antistatic discharge (ESD) yield and leakage current (IR) performance tests under a reverse breakdown voltage of 2000V and a reverse voltage of 7V.
[0210] The test results are shown in Table 1:
[0211] Table 1
[0212] WLD / nm std / nm HW / nm Lop / mW / 2mA VF / V / 2mA ESD / % IR / % Example 1 585.1 1.3 61.8 13.7 2.81 99.8 99.9 Example 2 585.4 1.4 61.8 13.5 2.83 99.9 99.9 Example 3 585.1 1.1 60.9 13.7 2.82 99.8 99.8 Example 4 585.2 1.6 61.1 11.1 2.82 89.7 81.9 Example 5 585.7 2.1 63.7 12.1 2.82 92.1 93.7 Example 6 585.4 2.6 65.9 12.4 2.86 94.3 92.3 Comparative Example 1 585.2 4.1 69.9 9.1 2.84 93.1 94.6 Comparative Example 2 585.6 3.7 67.7 10.2 2.85 92.2 91.2 Comparative Example 3 584.9 3.1 67.9 10.1 2.84 93.4 93.4
[0213] As shown in Table 1:
[0214] As can be seen from Example 1 and Comparative Example 1, the patterned microstructure of the present invention can improve the brightness and luminous efficiency of the nitride epitaxial wafer; as can be seen from Example 1 and Comparative Example 2, the introduction of silicon nanopillars in the patterned microstructure of the present invention can introduce tensile stress in the epitaxial layer, improve carrier recombination uniformity, etc., thereby improving the performance of the nitride epitaxial wafer; as can be seen from Example 1 and Comparative Example 3, the patterned microstructure of the present invention is grown on an n-type nitride insertion layer, and its surface has a high density of dislocation centers, which is conducive to the formation of a metallic microstructure, thereby facilitating the formation of the patterned microstructure and ensuring the effective functioning of the patterned microstructure; as can be seen from Example 1 and Example 4... The present invention preferably also includes an in-situ generated doped nitride layer, which can reduce the series resistance between the n-type nitride layer and the nitride luminescent layer, reduce the operating voltage of the epitaxial wafer, improve carrier injection uniformity, and increase the brightness and luminous efficiency of the epitaxial wafer. As can be seen from Examples 1 and 5, the silicon surface treatment performed after the n-type nitride insertion pillar and before the growth of the silicon nanopillar, and the two steps of growing the silicon nanopillar, enable the undoped nitride layer to eventually form a doped nitride layer. If the silicon surface treatment is not performed, it will affect the performance of the epitaxial wafer. As can be seen from Examples 1 and 6, the present invention preferably also includes a nitride capping layer, which provides a basis for the growth of the nitride luminescent layer.
[0215] In summary, this invention provides a nitride epitaxial wafer, its preparation method, and its application. The nitride epitaxial wafer introduces a patterned microstructure between the n-type nitride layer and the nitride luminescent layer, which can modulate and compensate for the compressive stress in the nitride luminescent layer, improve the uniformity of carrier recombination, and increase the luminescent area of the nitride luminescent layer, thereby improving the brightness and luminous efficiency of the nitride epitaxial wafer.
[0216] The above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention fall within the protection and disclosure scope of the present invention.
Claims
1. A nitride epitaxial wafer, characterized in that, The nitride epitaxial wafer comprises: Substrate; An n-type nitride layer is disposed on one side of the substrate; At least one patterned microstructure is disposed on the side of the n-type nitride layer away from the substrate. The patterned microstructure includes a pillar and an island-shaped protrusion at the top of the pillar. The pillar includes an n-type nitride intercalation layer pillar and a silicon nanopillar. The n-type nitride intercalation layer pillar is disposed on the side of the n-type nitride layer away from the substrate, and the silicon nanopillar is disposed on the side of the n-type nitride intercalation layer pillar away from the n-type nitride layer. The island-shaped protrusion includes a metal nitride. A nitride light-emitting layer is disposed on the side of the n-type nitride layer away from the substrate and covers the patterned microstructure; A p-type nitride layer is disposed on the side of the nitride luminescent layer away from the n-type nitride layer and the patterned microstructure.
2. The nitride epitaxial wafer according to claim 1, characterized in that, The nitride epitaxial wafer further includes a doped nitride layer disposed between the n-type nitride layer and the nitride light-emitting layer, and the patterned microstructure is disposed on the side of the doped nitride layer away from the n-type nitride layer; Preferably, the nitride epitaxial wafer further includes a metal nitride capping layer disposed between the doped nitride layer and the nitride emitting layer, and covering the patterned microstructure; Preferably, the metal nitride in the metal nitride capping layer and the metal nitride in the island-shaped protrusions both comprise aluminum nitride.
3. The nitride epitaxial wafer according to claim 1 or 2, characterized in that, The nitride luminescent layer includes at least one composite layer, which includes a nitride quantum well layer and a nitride quantum barrier layer stacked sequentially, wherein, in the same composite layer, the nitride quantum barrier layer is located on the side closer to the p-type nitride layer.
4. A method for preparing a nitride epitaxial wafer as described in any one of claims 1-3, characterized in that, The preparation method includes the following steps: Provide substrate; An n-type nitride layer and an n-type nitride insertion layer are sequentially grown on the surface of the substrate; At least one metal island protrusion is grown on the surface of the n-type nitride insertion layer. Then, a metal nitride film is grown on the surface of the metal island protrusion. The metal nitride film and the n-type nitride insertion layer not covered by the metal island protrusion are then etched away, and an n-type nitride insertion layer pillar is obtained below the metal island protrusion. Silicon nanopillars are grown between the metal island protrusions and the n-type nitride insert pillars. After the metal in the metal island protrusions is converted into metal nitrides, at least one patterned microstructure is obtained on the surface of the n-type nitride layer. A nitride luminescent layer covering the patterned microstructure is grown on the surface of the n-type nitride layer; A p-type nitride layer is grown on the surface of the nitride luminescent layer to obtain the nitride epitaxial wafer.
5. The preparation method according to claim 4, characterized in that, An undoped nitride layer is also grown between the n-type nitride layer and the n-type nitride insertion layer, and a silicon surface treatment is performed after obtaining the n-type nitride insertion layer pillars and before growing the silicon nanopillars.
6. The preparation method according to claim 5, characterized in that, The conditions for silicon surface treatment include sequential silicon thermal treatment and interrupted silicon thermal treatment; Preferably, the temperature of the silicon heat treatment is 750-1100℃.
7. The preparation method according to claim 4 or 5, characterized in that, First, a metal nitride capping layer covering the patterned microstructure is grown on the surface of the n-type nitride layer, and then the nitride light-emitting layer is grown on the surface of the metal nitride capping layer. Preferably, the n-type nitride insertion layer is grown at a temperature of 750-950°C.
8. The preparation method according to claim 4 or 5, characterized in that, Under a first growth condition, the metal island-shaped protrusion is grown, wherein the first growth condition includes: (i) Perform metal hot surface treatment and interrupt metal hot surface treatment sequentially. (ii) After repeating step (i) 1-20 times, annealing is performed while maintaining the temperature.
9. The preparation method according to claim 4 or 5, characterized in that, Under a third growth condition, the silicon nanopillars are grown, which includes repeating the following steps 10-100 times: sequentially performing Si thermal surface treatment and interrupting Si source surface treatment. Preferably, the temperature of the Si thermal surface treatment is 700-1050℃.
10. An electronic device, characterized in that, The electronic device includes a nitride epitaxial wafer as described in any one of claims 1-3.