Semiconductor structure

Abstract

The invention discloses a semiconductor structure. The semiconductor structure includes a first semiconductor stack, a tunneling junction structure and a second semiconductor stack. The first semiconductor stack comprises a first first type semiconductor layer, a first active region and a first second type semiconductor layer. The first active region has a plurality of first recesses. The first second type semiconductor layer conformally covers the first active region and has a plurality of second recesses corresponding to the plurality of first recesses. The tunneling junction structure conformally covers the first second type semiconductor layer and has a plurality of third recesses corresponding to the plurality of second recesses. The second semiconductor laminated layer is arranged on the tunneling junction structure and comprises a second first type semiconductor layer, a second active region and a second second type semiconductor layer which are sequentially stacked from bottom to top. The second first type semiconductor layer fills the plurality of third recesses.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more particularly to a semiconductor structure for a light-emitting diode. Background Technology

[0002] Light-emitting diodes (LEDs) are solid-state semiconductor devices with advantages such as low power consumption, low heat generation, long lifespan, shock resistance, small size, high response speed, and excellent photoelectric properties (such as stable emission wavelength). Therefore, LEDs are widely used in home appliances, indicator lights, and optoelectronic products. For high-voltage applications, dual-junction LEDs, which stack a tunneling junction layer between two LEDs, have been developed. However, current dual-junction LEDs still cannot fully meet the requirements of LED chips in all aspects. Summary of the Invention

[0003] In view of this, the present invention provides a semiconductor structure for a dual or multi-junction light-emitting diode, which can reduce the resistance value and operating voltage of the series resistor in the LED chip and is suitable for high-voltage applications.

[0004] According to some embodiments of the present invention, a semiconductor structure is provided, comprising a first semiconductor stack, a tunneling junction structure, and a second semiconductor stack. The first semiconductor stack includes a first type-1 semiconductor layer, a first active region, and a first type-2 semiconductor layer. The first active region is disposed on the first type-1 semiconductor layer and has a plurality of first recesses. The first type-2 semiconductor layer conformally covers the first active region and has a plurality of second recesses corresponding to the plurality of first recesses. The tunneling junction structure conformally covers the first type-2 semiconductor layer and has a plurality of third recesses corresponding to the plurality of second recesses. The second semiconductor stack is disposed on the tunneling junction structure and includes a second type-1 semiconductor layer, a second active region, and a second type-2 semiconductor layer. The second type-1 semiconductor layer fills the plurality of third recesses. The second active region is disposed on the second type-1 semiconductor layer. The second type-2 semiconductor layer is disposed on the second active region.

[0005] According to some embodiments of the present invention, a light-emitting device is provided, comprising the aforementioned semiconductor structure, a first electrode, and a second electrode. The first electrode is disposed on a first type semiconductor layer and electrically connected to a first semiconductor stack. The second electrode is electrically connected to a second semiconductor stack.

[0006] According to some embodiments of the present invention, a light-emitting package is provided, comprising a package substrate, a plurality of external electrodes, and at least one of the aforementioned light-emitting devices. The plurality of external electrodes are disposed on the package substrate. The light-emitting device is disposed on the package substrate and electrically connected to the external electrodes.

[0007] According to some embodiments of the present invention, a light-emitting system is provided, comprising a light-emitting device, a power supply module, and a control module. The light-emitting device includes at least one of the aforementioned light-emitting packages. The power supply module is connected to the light-emitting device. The control module is connected to the power supply module. The power supply module receives input voltage and control signals from the control module and provides drive signals to the light-emitting device.

[0008] According to some embodiments of the present invention, a light-emitting system is provided, comprising a light-emitting device, a power supply module, and a control module. The light-emitting device includes at least one of the aforementioned light-emitting apparatuses. The power supply module is connected to the light-emitting device. The control module is connected to the power supply module. The power supply module receives input voltage and control signals from the control module and provides drive signals to the light-emitting device. Attached Figure Description

[0009] Figure 1 These are cross-sectional schematic diagrams of semiconductor structures in some embodiments of the present invention;

[0010] Figure 2 These are cross-sectional schematic diagrams of the semiconductor structure in other embodiments of the present invention;

[0011] Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure in some other embodiments of the present invention;

[0012] Figure 4 These are cross-sectional schematic diagrams of the light-emitting device in some embodiments of the present invention;

[0013] Figure 5 This is a cross-sectional schematic diagram of the light-emitting device in some other embodiments of the present invention;

[0014] Figure 6 This is a cross-sectional schematic diagram of the light-emitting package in some embodiments of the present invention;

[0015] Figure 7 This is a cross-sectional schematic diagram of the light-emitting package in some other embodiments of the present invention;

[0016] Figure 8 These are schematic diagrams of light-emitting devices in some embodiments of the present invention;

[0017] Figure 9 This is a functional block diagram of the light-emitting system in some embodiments of the present invention.

[0018] Symbol explanation:

[0019] 1: Light-emitting device

[0020] 2: Light-emitting devices

[0021] 50: Packaging substrate

[0022] 53: Insulation section

[0023] 54: Encapsulation wall

[0024] 100, 100A, 100B: Semiconductor Structure

[0025] 101: Growth substrate

[0026] 103: Buffer Structure

[0027] 110: First semiconductor stack

[0028] 110S: Exposed Surface

[0029] 111: First Type I Semiconductor Layer

[0030] 113: First Active Zone

[0031] 115: Type I and Type II semiconductor layers

[0032] 119: Tunnel Joint Structure

[0033] 120: Second semiconductor stack

[0034] 121: Second Type I Semiconductor Layer

[0035] 123: Second Active Zone

[0036] 125: Second type II semiconductor layer

[0037] 129: Tunnel Joint Structure

[0038] 130: Third semiconductor stack

[0039] 131: Third Type I Semiconductor Layer

[0040] 133: Third Active Zone

[0041] 135: Third Type II Semiconductor Layer

[0042] 140: Shortest path

[0043] 200, 200a, 200c: Light-emitting devices

[0044] 201: Conductive substrate

[0045] 202: Substrate

[0046] 203: Bonding layer

[0047] 205: Barrier Layer

[0048] 207: Reflective layer

[0049] 210: First electrode

[0050] 220: Second electrode

[0051] 300, 300a, 300c: Light-emitting encapsulation

[0052] 301: Packaging substrate

[0053] 303, 304: External electrodes

[0054] 305, 327: Encapsulation wall

[0055] 307, 323: Conductors

[0056] 309: Wavelength conversion materials

[0057] 310, 329: Packaging materials

[0058] 321, 501: First terminal

[0059] 322, 502: Second terminal

[0060] 325: Chamber

[0061] 400: Lighting System

[0062] 410: Light-emitting device

[0063] 420: Power Module

[0064] 430: Control Module

[0065] d1: First depth

[0066] d2: Second depth

[0067] t1: First thickness

[0068] t2: Second thickness

[0069] t3: Third thickness

[0070] t4: Fourth thickness

[0071] A: Area

[0072] C1: First depression

[0073] C2: Second depression

[0074] C3: Third depression

[0075] C4: Fourth Depression

[0076] C5: Fifth Depression

[0077] C6: Sixth Depression

[0078] F: Normal direction Detailed Implementation

[0079] This invention relates to a semiconductor structure for a multi-junction light-emitting diode (LED), such as a two-junction or three-junction LED. The semiconductor structure includes a tunneling junction structure disposed between two semiconductor stacks. Furthermore, the tunneling junction structure conformally covers multiple recesses on the top surface of the lower semiconductor stack, allowing charge carriers injected from the upper semiconductor stack to enter the lower semiconductor stack via a shorter path. Therefore, the series resistance and operating voltage of an LED chip employing this semiconductor structure are reduced.

[0080] Figure 1 This is a schematic cross-sectional view of a semiconductor structure 100 according to some embodiments of the present invention. Figure 1 As shown, the semiconductor structure 100 includes a first semiconductor stack 110, a tunneling junction structure 119, and a second semiconductor stack 120, wherein the first semiconductor stack 110, the tunneling junction structure 119, and the second semiconductor stack 120 are stacked sequentially from bottom to top. In some embodiments, the first semiconductor stack 110 can be formed on a growth substrate 101 by epitaxial growth. The growth substrate 101 may include a sapphire (Al2O3) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a silicon (Si) substrate, or an aluminum nitride (AlN) substrate. In some embodiments, the growth substrate 101 can be a patterned substrate, that is, the surface of the growth substrate 101 forming the first semiconductor stack 110 may have a patterned structure.

[0081] In some embodiments, the processing method for epitaxial growth may include metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), physical vapor deposition (PVD), or liquid phase epitaxy (LPE). The following examples will be described using MOCVD epitaxial growth as a representative method.

[0082] The first semiconductor stack 110 includes a semiconductor light-emitting stack constituting a light-emitting element (e.g., a light-emitting diode or a laser). (See reference...) Figure 1The first semiconductor stack 110 includes a first type-1 semiconductor layer 111, a first active region 113, and a first type-2 semiconductor layer 115 stacked sequentially from bottom to top. In some embodiments, the first type-1 semiconductor layer may be a semiconductor layer including a first conductivity type (e.g., n-type), and the second type-2 semiconductor layer may be a semiconductor layer including a second conductivity type (e.g., p-type). By changing the physical and chemical composition of one or more layers (e.g., the first active region 113) in the first semiconductor stack 110, its emission wavelength can be adjusted. The first type-1 semiconductor layer 111, the first active region 113, and the first type-2 semiconductor layer 115 may be made of the same series of III-V group semiconductor materials, such as InGaN series materials, AlGaN series materials, or AlInGaN series materials. When the material of the first active region 113 is an InGaN series material, the first active region 113 may emit blue light with a wavelength between 400 nm and 490 nm, cyan light with a wavelength between 490 nm and 530 nm, or green light with a wavelength between 530 nm and 570 nm. When the material of the first active region 113 is an AlGaN series material or an AlInGaN series material, the first active region 113 can emit ultraviolet light with a wavelength between 250 nm and 400 nm. In some embodiments, the first active region 113 may include a single heterostructure, a double heterostructure, or a multiple quantum well structure. The first active region 113 may include multiple barrier layers and multiple well layers stacked on top of each other. In some embodiments, the material of the first active region 113 may be an intrinsically type (i-type) semiconductor, a p-type semiconductor, or an n-type semiconductor.

[0083] In some embodiments, the material of the first type semiconductor layer 111 includes Al. a Ga (1-a) N, where 0 ≤ a ≤ 1. The material of the first type-1 semiconductor layer 111 may be doped with a first conductivity type dopant. In some embodiments, the concentration of the first conductivity type dopant in the first type-1 semiconductor layer 111 is greater than 1 × 10⁻⁶. 18 / cm 3 For example, greater than 1×10 19 / cm 3 Or between 1×10 19 / cm 3 With 9×10 19 / cm 3 Between (including the two endpoints).

[0084] In some embodiments, the first semiconductor stack 110 may further include other layers located between the first first-type semiconductor layer 111 and the first active region 113. For example, to reduce lattice mismatch between the growth substrate 101 and the first active region 113, a buffer structure 103 may be formed between the growth substrate 101 and the first first-type semiconductor layer 111, and / or a stress relief structure (not shown) may be further formed between the first first-type semiconductor layer 111 and the first active region 113. Details of the buffer structure 103 will be described later. The stress relief structure may be a superlattice structure formed by stacking semiconductor layers of two different materials. These two semiconductor layers may be, for example, an indium gallium nitride (InGaN) layer and a gallium nitride (GaN) layer, or an aluminum gallium nitride (AlGaN) layer and a gallium nitride (GaN) layer. The stress relief structure may also be formed by a multilayer semiconductor stack with the same effect but different material compositions, such as a graded multilayer structure composed of group III-V elements. In order to reduce the operating voltage (Vf) and improve the anti-electrostatic discharge (Anti-ESD) capability of the first semiconductor stack 110, the first semiconductor stack 110 may include a low-doped layer between the first type semiconductor layer 111 and the stress relief structure to improve the current diffusion of the first type semiconductor layer 111 or to prevent the first semiconductor stack 110 from being damaged by voltage surges.

[0085] In some embodiments, the first semiconductor stack 110 may further include a hole blocking region in the stress-relieving structure (or between the stress-relieving structure and the active region 113). In some embodiments, the first semiconductor stack 110 may further include an electron blocking region (not shown) between the first active region 113 and the first second-type semiconductor layer 115. The hole blocking region and the electron blocking region prevent carriers (e.g., holes and electrons) from escaping from the first active region 113 without electron-hole recombination. The band gap of the electron blocking region is higher than that of the barrier layer in the first active region 113. The electron blocking region may include a single layer, multiple sublayers, or multiple alternating first and second sublayers. In some embodiments, multiple alternating first and second sublayers form a superlattice structure. In some embodiments, the electron blocking region may be doped or unintentionally doped. The electron blocking region includes a second conductivity type dopant, and the concentration of the second conductivity type dopant is greater than 1 × 10⁻⁶. 17 / cm 3 and / or no more than 1×10 21 / cm 3 In some embodiments, the electron blocking region includes a co-doped first conductivity type dopant and a second conductivity type dopant, wherein the concentration of the first conductivity type dopant is greater than 3 × 10⁻⁶. 17 / cm 3 and / or no more than 3×10 18 / cm3 The concentration of the second conductivity type dopant is greater than 2 × 10⁻⁶. 19 / cm 3 and / or no more than 1.5 × 10 20 / cm 3 The hole-blocking region includes a first conductivity type dopant, and the concentration of the first conductivity type dopant is greater than 1 × 10⁻⁶. 17 / cm 3 and / or no more than 1×10 21 / cm 3 Specifically, the concentration of the first conductivity type dopant in the hole blocking layer can be higher than the concentration of the dopant in the stress-relieving structure and the concentration of the dopant in the active region 113.

[0086] In some embodiments, the first and second type semiconductor layers 115 include Al g Ga (1-g) N, where 0 ≤ g ≤ 1. In some embodiments, the concentration of the second conductivity type dopant in the first and second type semiconductor layers 115 is greater than 1 × 10⁻⁶. 18 / cm 3 For example, greater than 1×10 19 / cm 3 In some embodiments, the first and second type semiconductor layer 115 includes a multilayer structure, such as a superlattice structure. The epitaxial quality of the first and second type semiconductor layer 115 can be improved by adjusting the concentration of dopants or the material composition gradient of the multilayer structure. In some embodiments, one or more layers other than the electron blocking region may be disposed between the first active region 113 and the first and second type semiconductor layer 115. For example, a diffusion prevention layer (not shown) may be disposed between the electron blocking region and the first active region 113. The diffusion prevention layer is used to prevent second conductivity type dopants in the first and second type semiconductor layer 115 or the electron blocking region from diffusing into the first active region 113, thereby avoiding degradation of the epitaxial quality or epitaxial efficiency of the first active region 113.

[0087] In some embodiments, a buffer structure 103 may be formed on the growth substrate 101 before forming the first semiconductor stack 110. The buffer structure 103 can reduce dislocations caused by lattice mismatch between the growth substrate 101 and the first semiconductor stack 110, thereby improving epitaxial quality. The buffer structure 103 may be a single-layer or multi-layer structure. In some embodiments, the buffer structure 103 includes Al i Ga (1-i)N, where 0 ≤ i ≤ 1. In some embodiments, the material of the buffer structure 103 includes GaN. In other embodiments, the material of the buffer structure 103 includes AlN. The method for forming the buffer structure 103 may be MOCVD, MBE, HVPE, or PVD. PVD includes sputtering or electron beam evaporation. When the buffer structure 103 includes multiple sublayers (not shown), the multiple sublayers may be the same material or different materials. In some embodiments, the buffer structure 103 includes two sublayers, wherein the first sublayer is formed by sputtering and the second sublayer is grown by MOCVD. In some embodiments, the buffer structure 103 further includes a third sublayer, wherein the third sublayer is grown by MOCVD, and the growth temperature of the second sublayer may be higher or lower than the growth temperature of the third sublayer. In some embodiments, the first, second, and third sublayers may include the same material (e.g., AlN) or a combination of different materials (e.g., AlN, GaN, and AlGaN). In other embodiments, the buffer structure 103 may be a PVD-AlN layer, wherein the PVD target used to form the PVD-AlN layer is made of aluminum nitride, or an aluminum metal target is used in a nitrogen-source environment to form the PVD-AlN layer in a reactive manner. In some embodiments, the buffer structure 103 may be undoped, i.e., not intentionally doped. In other embodiments, the buffer structure 103 may include a dopant, such as silicon, carbon, hydrogen, oxygen, or a combination thereof, and the concentration of this dopant in the buffer structure 103 is not less than 1 × 10⁻⁶. 17 / cm 3 .

[0088] Semiconductor structure 100 includes a second semiconductor stack 120 disposed on a first semiconductor stack 110. The second semiconductor stack 120 also includes a semiconductor light-emitting stack constituting a light-emitting element (e.g., a light-emitting diode or a laser). The second semiconductor stack 120 includes a second first-type semiconductor layer 121, a second active region 123, and a second second-type semiconductor layer 125 stacked sequentially from bottom to top. The emission wavelength of the second semiconductor stack 120 can be adjusted by changing the physical and chemical composition of one or more layers (e.g., the second active region 123). The second first-type semiconductor layer 121, the second active region 123, and the second second-type semiconductor layer 125 can be made of the same series of III-V group semiconductor materials, such as InGaN series materials, AlGaN series materials, or AlInGaN series materials. The second semiconductor stack 120 and the first semiconductor stack 110 can have similar layer structures. For example, details of the materials in the second first-type semiconductor layer 121, the second active region 123, and the second second-type semiconductor layer 125 can be found in the description of the first first-type semiconductor layer 111, the first active region 113, and the first second-type semiconductor layer 115, and will not be repeated here. Furthermore, similar to the first semiconductor stack 110, the second semiconductor stack 120 may include an electron blocking region and a stress relief structure. However, the second semiconductor stack 120 may not include a buffer structure.

[0089] Furthermore, the material of one or more layers in the first semiconductor stack 110 may be the same as or different from the material of one or more layers in the second semiconductor stack 120. In some embodiments, a contact layer may be formed on the second type semiconductor layer 125, wherein the contact layer includes a first conductivity type dopant (e.g., silicon) to form an ohmic contact with the electrode of the light-emitting device. The concentration of the second conductivity type dopant in the second type semiconductor layer 125 may be greater than or less than the concentration of the first conductivity type dopant in the contact layer 125.

[0090] The tunneling junction structure 119 sandwiched between the first semiconductor stack 110 and the second semiconductor stack 120 allows current to flow through the reverse-biased pn junction between the first second-type semiconductor layer 115 and the second first-type semiconductor layer 121. This is achieved by appropriately high-concentration doping to align the valence band and conduction band of adjacent layers, thereby allowing electrons and holes to tunnel bidirectionally through an extremely thin depletion region. In some embodiments, the tunneling junction structure 119 includes a highly concentrated doped second-type semiconductor layer (not shown) in direct contact with the first second-type semiconductor layer 115 and a highly concentrated doped first-type semiconductor layer (not shown) in direct contact with the second first-type semiconductor layer 121. In some embodiments, the tunneling junction structure 119 may include p+-GaN, n-InGaN, and n+-GaN stacked sequentially from bottom to top, or p+-AlGaN and n+-AlGaN, or p+-AlGaN, InGaN, and n+-AlGaN.

[0091] Refer again Figure 1 , Figure 1 An enlarged view of region A of semiconductor structure 100 is shown. A first active region 113 is disposed on a first first-type semiconductor layer 111 and has a plurality of first recesses C1. A portion of the first recesses C1 has an opening on the top surface of the first active region 113 and a bottom within the first active region 113. The first recesses C1 may include pits or trenches. In some embodiments, each pit may be V-shaped in a cross-sectional view and hexagonal in a top view. In some embodiments, each trench may be V-shaped in a cross-sectional view. The first recesses C1 may be formed by natural epitaxial growth or by etching a portion of the first active region 113. As the first active region 113 undergoes epitaxial growth, the opening size of the first recesses C1 gradually increases with the growth direction. In some embodiments, during the epitaxial growth of semiconductor structure 100, defects may occur in the stress-relief structure and / or the low-doped semiconductor layer (not shown) located between the stress-relief structure and the first first-type semiconductor layer 111, and their size gradually increases with subsequent epitaxial growth. Subsequent epitaxial layers will partially fill these defects, while unfilled defects will form the first depression C1. In some embodiments, a barrier layer and a well layer will fill these defects. The first depression C1 is formed after the last barrier layer or the last well layer has grown. The first depression C1 includes a V-shaped pit. The distribution density of the first depression C1 in the first active region 113 may be between 1 and 2 × 10⁻⁶. 8 / cm 2 In the cross-sectional view, the opening width of one of the multiple first recesses C1 can be between 240 and 280 nm.

[0092] Due to built-in physical constraints, most electrons and holes recombine near the first and second type semiconductor layers 115 in the first active region 113. In some embodiments, part or all of the well layer and part or all of the barrier layer in the defect have a sloped surface. The first recess C1 has a sloped surface, and the sloped surface is the top surface of the last barrier layer or the last well layer. The thickness of the barrier layer and the thickness of the well layer within the defect are smaller than their thickness on the plane outside the defect. For example, when the growth substrate is a sapphire substrate, the surface for epitaxial growth of the growth substrate includes a polar surface (e.g., a C-surface), and the sloped surface of the first recess C1 includes a semi-polar surface, thereby making it easier for holes to be injected into the first active region 113 via the sloped surface. Therefore, the injected current can be increased to improve the electron-hole recombination rate, thereby improving the luminous efficiency. In addition, the first recess C1 can improve current diffusion to enhance the anti-electrostatic discharge (Anti-ESD) capability of the first semiconductor stack 110.

[0093] A first and second type semiconductor layer 115 conformally covers the first active region 113 and has a plurality of second recesses C2 corresponding to a plurality of first recesses C1. In some embodiments, the first and second type semiconductor layer 115 has a top surface and a bottom surface, wherein the top surface and the bottom surface of the first and second type semiconductor layer 115 extend along the top surface of the first active region 113 and the inclined surface of the first recesses C1. The normal directions of the top surface and the bottom surface of the first and second type semiconductor layer 115 located on the inclined surface of the first recesses C1 are parallel to the normal direction F of the inclined surface of the first recesses C1. In other words, the first and second type semiconductor layer 115 does not fill the first recesses C1 completely. The second recesses C2 are the shapes that the first and second type semiconductor layer 115 presents after covering the first recesses C1. To achieve the above configuration, the thickness of the first and second type semiconductor layer 115 is less than the depth of the first recesses C1 below it. In some embodiments, the thickness of the second and second type semiconductor layer 125 may be greater than the thickness of the first and second type semiconductor layer 115. Furthermore, the tunneling junction structure 119 conformally covers the first and second type semiconductor layer 115 and has a plurality of third recesses C3 corresponding to a plurality of second recesses C2. In some embodiments, the tunneling junction structure 119 has a top surface and a bottom surface, wherein both the top and bottom surfaces of the tunneling junction structure 119 extend along the top surface of the first and second type semiconductor layer 115 and the inclined surface of the second recesses C2. The normal directions of the top and bottom surfaces of the tunneling junction structure 119 located on the inclined surface of the second recess C2 are parallel to the normal direction F of the inclined surface of the second recess C2. In other words, the tunneling junction structure 119 does not completely fill the second recesses C2. The third recess C3 is the shape presented after the tunneling junction structure 119 covers the second recesses C2. In some embodiments, the first recesses C1, the second recesses C2, and the third recesses C3 have the same shape. Figure 1 In a cross-sectional view, the first recess C1, the second recess C2, and the third recess C3 can all be V-shaped recesses. Each of the first recess C1, the second recess C2, and the third recess C3 can be a hexagonal pyramidal recess, with its bottom appearing pointed in the cross-sectional view. Furthermore, the second first-type semiconductor layer 121 can fill the third recess C3 and has a flat surface adjacent to the second active region 123.

[0094] In some embodiments, Figure 1In a first direction (e.g., the Z-axis direction), the first recess C1 has a first depth d1, and the first second-type semiconductor layer 115 has a first thickness t1 on the generally flat top surface of the first active region 113. The first second-type semiconductor layer 115 further has a second thickness t2 on the inclined surface of the first recess C1. In some embodiments, the first depth d1 is greater than the first thickness t1 and the second thickness t2, and the first thickness t1 is greater than the second thickness t2 (i.e., d1>t1>t2). The first second-type semiconductor layer 115 located in a portion of the first recess C1 provides a short path 140 for charge carriers (e.g., holes) to pass through and enter the first active region 113. In some embodiments, the first depth d1 is between 1000 angstroms (Å) and 3000 Å, for example, 2000 Å. In some embodiments, the first thickness t1 and the second thickness t2 of the first second-type semiconductor layer 115 are both less than 2000 Å, for example, between 400 Å and 2000 Å. Furthermore, in the first direction, the second recess C2 has a second depth d2, and the tunneling junction structure 119 has a third thickness t3 on the generally flat top surface of the first second-type semiconductor layer 115. The tunneling junction structure 119 further has a fourth thickness t4 on the inclined surface of the second recess C2. In some embodiments, the second depth d2 is greater than the third thickness t3, and the third thickness t3 is greater than the fourth thickness t4 (i.e., d2>t3>t4). The tunneling junction structure 119 located in a portion of the second recess C2 provides a short path 140 for charge carriers to pass through and enter the second first-type semiconductor layer 121. The tunneling junction structure 119 may include a junction that converts electrons into holes. In some embodiments, the third thickness t3 and the fourth thickness t4 of the tunneling junction structure 119 are both between 50 Å and 500 Å, for example, 200 Å. In some embodiments, the second depth d2 is between 1000 Å and 3000 Å, for example, 2000 Å. The third recess C3 is filled by the second first type semiconductor layer 121, and the thickness of the second first type semiconductor layer 121 is greater than the depth of the third recess C3.

[0095] Accordingly, the thinner second thickness t2 of the first and second type semiconductor layers 115 in the first recess C1 and the thinner fourth thickness t4 of the tunneling junction structure 119 in the second recess C2 can provide a short path 140 for charge carriers to pass through. Therefore, the series resistance (Rs) between the first semiconductor stack 110 and the second semiconductor stack 120 can be reduced, and the operating voltage (Vf) of the light-emitting device including the semiconductor structure 100 can also be reduced. Furthermore, the luminous efficiency of the light-emitting device can be improved.

[0096] In a comparative example, a first and second type semiconductor layer is formed on the first active region to fill the first recess, and the first and second type semiconductor layer has a certain thickness. Since the first recess in the comparative example is filled by the first and second type semiconductor layer, the upper surface of the first and second type semiconductor layer is flat, and the tunneling junction structure located on the first and second type semiconductor layer also has a flat upper surface. Therefore, the semiconductor structure in the comparative example does not have a second recess or a third recess.

[0097] In some embodiments, a first second-type semiconductor layer 115 is conformally formed on the top surface of the first active region 113 and in the first recess C1, and has a second recess C2. Furthermore, a tunneling junction structure 119 is conformally formed on the top surface of the first second-type semiconductor layer 115 and in the second recess C2, and has a third recess C3. Compared to a comparative example, the thinner portion of the first second-type semiconductor layer 115 in the first recess C1 and the thinner portion of the tunneling junction structure 119 in the second recess C2 can provide a shorter short path 140 for carriers injected from the second first-type semiconductor layer 121 and entering the first active region 113. Therefore, the series resistance (Rs) in the embodiments of the present invention is about 40% lower than that in the comparative example, and the operating voltage (Vf) in the embodiments of the present invention is about 35% lower than that in the comparative example. Furthermore, at the same operating voltage, the brightness of an LED chip using the semiconductor structure in the embodiments of the present invention can be increased by about 45% to 55% compared to two series-connected single-junction LED chips.

[0098] Figure 2 This is a cross-sectional schematic diagram of the semiconductor structure 100A according to other embodiments of the present invention. For example... Figure 2 As shown, semiconductor structure 100A and Figure 1 The semiconductor structure 100A is similar to the semiconductor structure 100A. The difference lies in that the second active region 123 of the semiconductor structure 100A further has a plurality of fourth recesses C4. In some embodiments, similar to the first recess C1, each fourth recess C4 may be V-shaped in cross-sectional view. The formation method and shape of the fourth recesses C4 are similar to the aforementioned recesses. In some embodiments, the fourth recesses C4 are induced by defects during the epitaxial growth of the second active region 123. The fourth recesses C4 may be hexagonal pyramidal recesses, and their bottoms are pointed in cross-sectional view. Each fourth recess C4 has an opening located on the top surface of the second active region 123, and its bottom is located inside the second active region 123. The opening size of the fourth recesses C4 gradually increases with the growth direction. The second type II semiconductor layer 125 fills the fourth recesses C4 and has a flat top surface or a roughened surface. The thickness of the second type II semiconductor layer 125 is greater than the thickness of the first type II semiconductor layer 115.

[0099] In some embodiments, the number of fourth recesses C4 is less than the number of first recesses C1. Figure 2 In a first direction (e.g., the Z-axis direction), the depth of any fourth recess C4 can be less than, equal to, or greater than the depth d1 of any first recess C1. Other functions and advantages of the fourth recess C4 can be found in the foregoing description of the first recess C1. Furthermore, Figure 2 Other feature details of the semiconductor structure 100A and region A can be found in the aforementioned section. Figure 1 The description of semiconductor structure 100 is omitted here.

[0100] Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure 100B according to some other embodiments of the present invention. For example... Figure 3 As shown, the semiconductor structure 100B further includes a third semiconductor stack 130 disposed on the second semiconductor stack 120 and an additional tunneling junction structure 129 disposed between the third semiconductor stack 130 and the second semiconductor stack 120. The third semiconductor stack 130 also includes a semiconductor light-emitting stack constituting a light-emitting element (e.g., a light-emitting diode or a laser). The third semiconductor stack 130 includes a third first-type semiconductor layer 131, a third active region 133, and a third second-type semiconductor layer 135 stacked sequentially from bottom to top. In some embodiments, the second second-type semiconductor layer 125 conformally covers the second active region 123 and has a plurality of fifth recesses C5 corresponding to a plurality of fourth recesses C4. Furthermore, the tunneling junction structure 129 conformally covers the second second-type semiconductor layer 125 and has a plurality of sixth recesses C6 corresponding to a plurality of fifth recesses C5. The third first-type semiconductor layer 131 fills the sixth recesses C6 and has a flat top surface adjacent to the third active region 133. In some embodiments, the thickness of the second type 2 semiconductor layer 125 is less than 2000 Å, and the thickness of the tunneling junction structure 129 is less than 500 Å. Figure 3 Other feature details of the semiconductor structure 100B and region A can be found in the foregoing. Figure 1 The description of the semiconductor structure 100 is omitted here. In some embodiments, the second active region 123 may not include the fourth recess C4. Accordingly, the second type II semiconductor layer 125 may not include the fifth recess C5, and the tunneling junction structure 129 may not include the sixth recess C6.

[0101] Figure 4 This is a cross-sectional schematic diagram of the light-emitting device 200 according to some embodiments of the present invention. For example... Figure 4 As shown, the light-emitting device 200 is a vertical LED chip. In some embodiments, the light-emitting device 200 may include a conductive substrate 201, a second electrode 220, and... Figure 1The semiconductor structure 100 shown includes a first semiconductor stack 110 and a second semiconductor stack 120. In other embodiments, the light-emitting device 200 may include... Figure 2 or Figure 3 The semiconductor structure is shown. The second electrode 220 and the semiconductor structure 100 are respectively disposed on opposite sides of the conductive substrate 201. In some embodiments, the first semiconductor stack 110 and the second semiconductor stack 120 originally grown on the growth substrate 101 can be transferred and bonded to the conductive substrate 201, and then the growth substrate 101 is removed to expose the surface of the second semiconductor stack 120. The second electrode 220 is disposed below the conductive substrate 201 and electrically connected to the second semiconductor stack 120. Furthermore, referring to… Figure 1 The first semiconductor stack 110 includes a plurality of first recesses C1. Each first recess C1 has an opening located on the top surface of the first active region 113. In some embodiments, the opening of the first recess C1 faces the conductive substrate 201.

[0102] In some embodiments, the light-emitting device 200 may further include a first electrode 210, a reflective layer 207, and a barrier layer 205. The reflective layer 207 and the barrier layer 205 are made of different metals. The first electrode 210 may be disposed on the top surface of the semiconductor structure 100. In some embodiments, the first electrode 210 is disposed on the surface of a first first-type semiconductor layer 111 and electrically connected to the first semiconductor stack 110. The reflective layer 207 may be disposed on the bottom surface of the semiconductor structure 100. The barrier layer 205 may be disposed below the reflective layer 207 and cover the reflective layer 207. In some embodiments, the reflective layer 207 is disposed between the barrier layer 205 and the second second-type semiconductor layer 125 of the second semiconductor stack 120.

[0103] In some embodiments, the light-emitting device 200 may further include a bonding layer 203 disposed between the conductive substrate 201 and the semiconductor structure 100. In some embodiments, the bonding layer 203 may connect the conductive substrate 201 and the second semiconductor stack 120. Furthermore, the bonding layer 203 is disposed between the barrier layer 205 and the conductive substrate 201, and the barrier layer 205 is disposed between the bonding layer 203 and the second semiconductor stack 120. In some embodiments, the barrier layer 205 is disposed between the bonding layer 203 and the reflective layer 207. The barrier layer 205 may prevent the material of the bonding layer 203 from diffusing into the reflective layer 207 during the fabrication process. The diffusing material of the bonding layer 203 may react with the reflective layer 207 to form compounds or alloys, thereby affecting the reflectivity and conductivity of the reflective layer 207.

[0104] In some embodiments, the reflective layer 207 may comprise a metallic material, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru), tungsten (W), rhodium (Rh), alloys of the above materials, or a multilayer stack. In some embodiments, the reflective layer 207 may comprise a multilayer structure (not shown). For example, the reflective layer 207 may be a multilayer structure consisting of a first metal layer, a second metal layer, and a third metal layer stacked sequentially. The first metal layer may comprise silver (Ag), the second metal layer may comprise titanium-tungsten (TiW), and the third metal layer may comprise platinum (Pt). The reflective layer 207 may form an ohmic contact with the second type II semiconductor layer 125.

[0105] In some embodiments, the barrier layer 205 may include a metallic material, such as aluminum (Al), chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), an alloy containing the above materials, or a multilayer stack. In some embodiments, when the barrier layer 205 is a metal stack, the barrier layer 205 may be composed of two or more layers of metals stacked alternately, such as Cr / Pt, Cr / Ti, Cr / TiW, Cr / W, Cr / Zn, Ti / Pt, Ti / W, Ti / TiW, Ti / Zn, Pt / TiW, Pt / W, Pt / Zn, TiW / W, TiW / Zn, or W / Zn.

[0106] Figure 5 This is a cross-sectional schematic diagram of the light-emitting device 200a according to other embodiments of the present invention. For example... Figure 5 As shown, the light-emitting device 200a is a side-mounted LED chip. In some embodiments, the light-emitting device 200a includes a carrier substrate 202 and a semiconductor structure 100 disposed on the carrier substrate 202. The carrier substrate 202 is used to support the semiconductor structure 100. In some embodiments, the carrier substrate 202 may be a growth substrate for epitaxial growth of the semiconductor structure 100. The carrier substrate 202 may be an insulating substrate. The carrier substrate 202 may be disposed below the first first-type semiconductor layer 111. In other embodiments, an insulating adhesive layer (not shown) is disposed between the semiconductor structure 100 and the carrier substrate 202, wherein the semiconductor structure 100 is first grown on an epitaxial substrate (not shown), and then mounted on the carrier substrate 202 through at least one transfer fabrication process. Depending on the number of transfer fabrication processes, the carrier substrate 202 may be disposed below the first semiconductor stack 110 or below the second semiconductor stack 120. (Refer to...) Figure 1The first semiconductor stack 110 includes a plurality of first recesses C1. Each first recess C1 has an opening on the top surface of the first active region 113. In some embodiments, the bottom of the first recess C1 is closer to the carrier substrate 202 than its opening. The first first type semiconductor layer 111 of the first semiconductor stack 110 has an exposed surface 110S not covered by the stacked structure, wherein the stacked structure includes the first active region 113, the first second type semiconductor layer 115, the tunneling junction structure 119, and the second semiconductor stack 120.

[0107] In some embodiments, the light-emitting device 200a may further include a first electrode 210 and a second electrode 220. The first electrode 210 is located on the exposed surface 110S and electrically connected to the first first-type semiconductor layer 111. The second electrode 220 is located on and electrically connected to the second second-type semiconductor layer 125 of the second semiconductor stack 120. In some embodiments, a transparent conductive layer (not shown) may be disposed between the second electrode 220 and the second second-type semiconductor layer 125.

[0108] In some embodiments, the carrier substrate 202 may be a patterned substrate, that is, the carrier substrate 202 has a patterned structure (not shown) on the surface where the first semiconductor stack 110 is located. Accordingly, light emitted from the semiconductor structure 100 can be refracted and / or reflected by the patterned structure of the carrier substrate 202, thereby enhancing the brightness of the light-emitting device 200a.

[0109] Figure 6 This is a cross-sectional schematic diagram of the light-emitting package 300 according to some embodiments of the present invention. Figure 6 As shown, the light-emitting package 300 may include a package wall 305, a package substrate 301, a plurality of external electrodes 303 and 304 disposed on the package substrate 301, and at least one Figure 4 The light-emitting device 200 (mounted on the encapsulation substrate 301, located within the encapsulation wall 305 and electrically connected to external electrodes 303 and 304) and the encapsulation material 310 including wavelength conversion material 309 (e.g., phosphor) encapsulate the light-emitting device 200. The external electrodes 303 and 304 are electrically insulated from each other and can be powered by a wire 307. Furthermore, the external electrodes 303 and 304 can reflect the light emitted by the light-emitting device 200 to improve light extraction efficiency and conduct heat from the light-emitting device 200 to the outside.

[0110] Figure 7 This is a cross-sectional schematic diagram of the light-emitting package 300a according to other embodiments of the present invention. For example... Figure 7As shown, the light-emitting package 300a includes a package wall 327, a first terminal 321 and a second terminal 322 connected to the package wall 327, a cavity 325 defined by the package wall 327, the first terminal 321 and the second terminal 322, and at least one Figure 5 The diagram shows a light-emitting device 200a, a wire 323, and an encapsulation material 329. In some embodiments, the sidewalls of the encapsulation wall 327 may include a reflective structure. In a chamber 325, a first terminal 321 and a second terminal 322 are spaced apart from each other. The light-emitting device 200a is disposed in the chamber 325 and located on at least one of the first terminal 321 and the second terminal 322. For example, the light-emitting device 200a may be disposed on the first terminal 321, and the first electrode 210 (e.g., ...) may be disposed on the first terminal 321. Figure 5 (as shown) and the second electrode 220 (as shown) Figure 5 (As shown) The first terminal 321 and the second terminal 322 are electrically connected via wires 323. An encapsulation material 329 is disposed in the chamber 325 and covers the light-emitting device 200a. In some embodiments, the encapsulation material 329 may be silicone or epoxy resin, and its structure may be single-layer or multi-layer. In some embodiments, the encapsulation material 329 may further include wavelength conversion materials (such as phosphors) and / or scattering materials to convert the wavelength of the light generated by the light-emitting device 200a.

[0111] Figure 8 This is a schematic diagram of the light-emitting device 2 according to some embodiments of the present invention. For example... Figure 8 As shown, the light-emitting device 1 can be Figure 5 The light-emitting device 200a shown is mounted in a flip-chip configuration on the first terminal 501 and the second terminal 502 of the packaging substrate 50. The first terminal 501 and the second terminal 502 are electrically insulated from each other by an insulating portion 53 comprising an insulating material. The primary light-collecting surface of the flip chip is the side of the growth substrate opposite to the surface where the electrode pads are formed. For example, Figure 5 In the light-emitting device 200a shown, the bottom surface of the substrate 202 is the main light-collecting surface. An encapsulation wall 54 may be provided around the light-emitting device 1. The encapsulation wall 54 may have a reflective inner surface to improve the light-collecting efficiency of the light-emitting device 2. In some embodiments, similar to the light-emitting package 300a, the light-emitting device 2 may include an encapsulation material, which is disposed in a cavity defined by the encapsulation wall 54 to cover the light-emitting device 1.

[0112] In some embodiments, Figure 6 The light-emitting package 300 shown Figure 7 The light-emitting package 300a shown and Figure 8 The light-emitting device 2 shown can be applied to backlight units, lighting units, display devices, indicators, lamps, streetlights, automotive lighting devices, automotive display devices, or smartwatches.

[0113] Figure 9 This is a functional block diagram of a light-emitting system 400 according to some embodiments of the present invention. For example... Figure 9 As shown, the light-emitting system 400 can be an automotive light-emitting system and includes a light-emitting device 410, a power module 420, and a control module 430. The power module 420 is connected to the light-emitting device 410. The control module 430 is connected to the power module 420. In some embodiments, the light-emitting device 410 includes a circuit board 412 and a plurality of light-emitting devices 200c disposed on the circuit board 412. The plurality of light-emitting devices 200c can be... Figure 4 The light-emitting device 200 shown or Figure 5 The light-emitting device 200a is shown. In some embodiments, the light-emitting device 410 includes a plurality of light-emitting packages 300c disposed on a circuit board 412. The plurality of light-emitting packages 300c may be... Figure 6 The light-emitting package 300 shown Figure 7 The light-emitting package 300a shown is or Figure 8 The light-emitting device 2 is shown. The light-emitting device 410 can be a vehicle's lighting device, display device, or backlight unit. The power module 420 can receive an input voltage and a control signal from the control module 430 and provide a drive signal to the light-emitting device 410.

[0114] Although the present invention has been disclosed above with reference to embodiments, some modifications or changes may be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims. The above embodiments can be combined or substituted with each other where appropriate, and are not limited to the specific embodiments described. For example, the relevant parameters of specific components or the connection relationship between specific components and other components disclosed in some embodiments can also be applied to other embodiments, and all fall within the scope of protection of the present invention.

Claims

1. A semiconductor structure comprising: The first semiconductor stack includes: First type-1 semiconductor layer; A first active region is disposed on the first type semiconductor layer and has a plurality of first recesses; and A first and a second type semiconductor layer conformally covers the first active region and has a plurality of second recesses corresponding to the plurality of first recesses; A tunneling interface structure conformally covers the first and second type semiconductor layers and has a plurality of third recesses corresponding to the plurality of second recesses; and A second semiconductor stack is disposed on the tunneling interface structure, the second semiconductor stack comprising: A second type-1 semiconductor layer fills the plurality of third recesses; The second active region is disposed on the second first-type semiconductor layer; and A second type II semiconductor layer is disposed on the second active region.

2. The semiconductor structure of claim 1, wherein the second first-type semiconductor layer has a flat surface adjacent to the second active region.

3. The semiconductor structure of claim 1, wherein the thickness of the first and second type semiconductor layers is less than 2000 angstroms (Å).

4. The semiconductor structure of claim 1, wherein the first active region includes a top surface, and each of the plurality of first recesses has an opening on the top surface and a bottom located within the first active region.

5. The semiconductor structure of claim 1, wherein one of the plurality of first recesses has a V-shape in a cross-sectional view.

6. The semiconductor structure of claim 1, wherein the thickness of the second type II semiconductor layer is greater than the thickness of the first type II semiconductor layer.

7. The semiconductor structure of claim 4, wherein the first second type semiconductor layer has a first thickness on the top surface of the first active region and a second thickness in one of the plurality of first recesses, the first depth of the plurality of first recesses is denoted as d1, the first thickness is denoted as t1, the second thickness is denoted as t2, and d1 > t1 > t2.

8. The semiconductor structure of claim 7, wherein the tunneling junction structure has a third thickness on the top surface of the first active region and a fourth thickness in one of the plurality of second recesses, the second depth of the plurality of second recesses is denoted as d2, the third thickness is denoted as t3, the fourth thickness is denoted as t4, and d2 > t3 > t4.

9. The semiconductor structure of claim 1, wherein the second active region has a plurality of fourth recesses.

10. The semiconductor structure of claim 9, wherein the number of the plurality of fourth recesses is less than the number of the plurality of first recesses.

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