Hall device and manufacturing method thereof

Abstract

The invention discloses a Hall device and a manufacturing method thereof. The device comprises a substrate and an isolation structure, and an active region pattern with a rotational symmetry structure is defined; a deep active region formed by diffusion of the side wall of the deep trench is arranged in the deep trench, and a connecting well region for guiding carriers to go deep, symmetrically distributed contact regions and a surface isolation region are arranged on the surface layer of the deep trench. According to the invention, an ultra-deep active region (15-25 [mu] m) is realized through a deep groove and a side wall diffusion process, and the sensitivity of the device is remarkably improved; x-direction and Y-direction magnetic fields can be monitored at the same time by using a rotational symmetric structure, and offset voltage is effectively eliminated in cooperation with a rotating current method, so that the problems of low sensitivity and difficulty in offset voltage correction caused by junction depth of an existing vertical Hall device are solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a Hall effect device and its manufacturing method. Background Technology

[0002] With the rapid development of the new energy vehicle industry, the market demand for sensing and monitoring chips is growing stronger. Magnetic field monitoring chips can convert changing magnetic field signals into electrical signals, thereby achieving precise monitoring of displacement and angle variables. This type of chip utilizes a non-contact magnetic field monitoring method, which has significant advantages over traditional contact monitoring methods, such as high reliability and durability. For example, the electronic gear shifting system commonly used in new energy vehicles is developed based on the magnetic field changes corresponding to different gear positions.

[0003] The design of the magnetic field monitoring chip is based on the Hall effect, which states that under the influence of an external magnetic field, charge carriers in a semiconductor are deflected and aggregated by the Lorentz force, thereby generating a voltage difference (Hall voltage). By monitoring the variable of the voltage difference, the magnetic field variable can be monitored.

[0004] Existing magnetic field monitoring devices are mainly divided into two categories: horizontal Hall devices and vertical Hall devices.

[0005] like Figure 1 The diagram illustrates a traditional horizontal Hall effect device for monitoring magnetic field strength. Horizontal Hall effect devices typically form a planar active region on the semiconductor surface, primarily sensitive to magnetic field components perpendicular to the device surface (i.e., the Z direction in the diagram). When monitoring magnetic field strength parallel to the device surface (i.e., the X or Y direction in the diagram) is required, the horizontal Hall effect device cannot directly respond. To achieve monitoring of magnetic fields in the X or Y directions, existing solutions usually require rotating the chip or package containing the horizontal Hall effect device by 90 degrees or employing extremely complex magnetic circuit guidance structures. This approach not only increases the complexity of system design in practical applications but also raises packaging and assembly costs.

[0006] To address the problem of detecting parallel magnetic fields, the industry has developed vertical Hall effect devices. For example... Figure 2 The diagram shows a vertical Hall effect device for monitoring the magnetic field strength in the Y direction. The current in a vertical Hall effect device flows primarily in a direction perpendicular to the semiconductor surface, thus enabling effective monitoring of magnetic field strength parallel to the surface (e.g., in the Y direction).

[0007] However, conventional vertical Hall devices face significant limitations in manufacturing processes. Existing technologies typically employ deep N-well (DNW) implantation to form the vertically oriented carrier-conducting region. Limited by the energy of the ion implantation equipment and the blocking effect of the photoresist, the junction depth of conventional DNWs is usually only 2–3 μm. This means that the path for current flow in the vertical direction is very short.

[0008] The current sensitivity formula for Hall effect devices is as follows: SIV = (G × rH) / (q × ND × d) in: SIV: Current Sensitivity G: Geometric factor q: Electronic charge d: Thickness of the charge carrier region ND: Doping concentration in the carrier region rH: Hall factor constant As shown in the formula above, the geometric factor G of a vertical Hall device is directly proportional to the depth of the carrier region. The greater the carrier depth, the greater the geometric factor G, and the higher the sensitivity SIV of the device.

[0009] In such Figure 2 In the conventional structure shown, the shallow depth of the DNW (only 2~3µm) results in a small geometric factor G, limiting the device's sensitivity. Furthermore, a high doping concentration is typically required to form the DNW through implantation, which leads to a decrease in carrier mobility, further reducing the device's sensitivity.

[0010] In summary, existing horizontal Hall effect devices cannot directly monitor parallel magnetic fields, while existing vertical Hall effect devices are limited by the shallow active region depth and low sensitivity caused by the DNW process. Therefore, how to design and manufacture a vertical Hall effect device with a deeper carrier region, higher sensitivity, effective guidance of vertical current, and excellent rotational symmetry to achieve low offset voltage is a key technical problem that urgently needs to be solved in the current field. Summary of the Invention

[0011] The present invention aims to solve the technical problems of existing vertical Hall devices, such as shallow active region depth and low sensitivity due to conventional deep-well (DNW) technology, and difficulty in effectively eliminating offset voltage due to insufficient structural symmetry.

[0012] To address the aforementioned technical problems, the present invention provides a Hall effect device, comprising: First conductivity type semiconductor substrate; An isolation structure is disposed in a semiconductor substrate of a first conductivity type and defines an independent active region pattern, the active region pattern having a rotationally symmetric structure; The second type of conductivity is the deep active region, located within the active region pattern defined by the isolation structure; Multiple connection well regions, of the second conductivity type, are spaced apart on the upper part of the deep active region of the second conductivity type and extend into the interior of the deep active region of the second conductivity type; Multiple second-conductivity contact areas are located on the top surface of the corresponding connection well area, and the multiple second-conductivity contact areas are symmetrically distributed according to the rotational symmetry structure; The first conductivity type surface isolation region is located on the surface of the second conductivity type deep active region and fills the space between adjacent second conductivity type contact regions.

[0013] Preferably, the isolation structure includes deep trenches, which are distributed in a closed ring shape to enclose the active region pattern.

[0014] Preferably, the deep active region of the second conductivity type is formed by overlapping the doped regions of the second conductivity type that diffuse inward from the sidewall of the deep trench.

[0015] Preferably, the depth of the deep trench is 15 μm to 25 μm.

[0016] Preferably, the rotationally symmetric structure is a cross-shaped structure, which has fourfold rotational symmetry, including a central intersection area and four arm areas extending outward from the central intersection area.

[0017] Preferably, the Hall device is configured to operate using a rotationally symmetric structure with a rotating current method to correct the offset voltage.

[0018] Preferably, the Hall device is configured to simultaneously monitor the magnetic field strength in the X direction and the magnetic field strength in the Y direction parallel to the device surface.

[0019] Preferably, the depth of the connection well region is greater than the depth of the second conductivity type contact region; the connection well region is configured to guide carriers to migrate from the second conductivity type contact region to the depth of the second conductivity type deep active region.

[0020] Preferably, the first conductivity type surface isolation region is configured to neutralize the second conductivity type charge carriers on the surface to suppress surface current.

[0021] Preferably, it further includes a metal silicide layer, which is formed only on the surface of the second conductivity type contact area.

[0022] Preferably, the deep trench is filled with a filling material, and an insulating layer is provided between the filling material and the inner wall of the deep trench.

[0023] Preferably, the filler material is polycrystalline silicon, which is configured to fill deep trenches to prevent stress-induced cracking and to serve as an electronic shielding layer.

[0024] Preferably, the insulating layer is a silicon dioxide layer.

[0025] The present invention also provides a method for manufacturing the Hall device as described above, comprising the following steps: Step 1: Provide a semiconductor substrate of the first conductivity type, form a hard mask layer on the surface of the semiconductor substrate of the first conductivity type, and form a deep trench through an etching process; Step 2: Perform tilted implantation of ions of the second conductivity type into the deep trench, and combine it with wafer rotation process to form implantation areas on the sidewalls and bottom of the deep trench; Step 3: Perform diffusion heat treatment to allow ions in the implantation region to diffuse and connect to form a deep active region of the second conductivity type, and form an insulating isolation layer on the inner wall of the deep trench; deposit filling material in the deep trench and perform preliminary planarization; Step 4: Remove the hard mask layer and perform planarization treatment on the surface of the first conductivity type semiconductor substrate again; Step 5: Form a second conductivity type contact region, a connection well region, and a first conductivity type surface isolation region on the surface of the deep active region of the second conductivity type; Step 6: Form metal silicide and metal leads.

[0026] Preferably, in step one, the hard mask layer is a multilayer structure, which includes a silicon oxide layer and a silicon nitride layer.

[0027] Preferably, in step one, the etching depth of the deep trench is 15µm to 25µm.

[0028] Preferably, in step two, the first conductivity type is P-type, and the first conductivity type semiconductor substrate is a P-type silicon substrate.

[0029] Preferably, in step two, the second conductivity type is N-type, and the second conductivity type ion is phosphorus ion.

[0030] Preferably, in step two, the tilting implantation and wafer rotation process are configured such that the spacing between adjacent implantation regions is S.

[0031] Preferably, in step three, the diffusion heat treatment is configured to make the value of the spacing S become 0, thereby causing the injection regions on both sides to overlap to form a deep active region of the second conductivity type.

[0032] Preferably, in step three, the insulating layer is a silicon dioxide layer.

[0033] Preferably, in step three, the filling material is polycrystalline silicon.

[0034] Preferably, in step three, polycrystalline silicon is used to fill deep trenches to prevent stress-induced cracking and to serve as an electronic shielding layer.

[0035] Preferably, in step three, the initial planarization is performed using a chemical mechanical polishing process.

[0036] Preferably, in step four, the hard mask layer is removed using a wet etching process.

[0037] Preferably, in step four, the planarization process is performed using a chemical mechanical polishing process.

[0038] Preferably, in step five, the steps of forming the second type of conductive contact region and the connection well region include: using the same photomask, performing ion implantation to form the second type of conductive contact region and high-energy ion implantation to form the connection well region, respectively.

[0039] Preferably, in step five, the step of forming the connection well region includes: performing ion implantation using an independent vertical Hall implantation mask, and adjusting the energy and dose of the ion implantation to meet the depth or resistance requirements of the connection well region.

[0040] Preferably, the depth of the connection well region is greater than the depth of the second conductivity type contact region.

[0041] Preferably, in step five, the first conductivity type surface isolation region is formed by ion implantation and covers the area except for the second conductivity type contact region.

[0042] Preferably, in step six, a metal silicide barrier layer photoresist is used so that the metal silicide is generated only on top of the second conductivity type contact area.

[0043] Preferably, in step one, the deep trench defines a cross-shaped structure on the surface of the first type of conductive semiconductor substrate.

[0044] Preferably, the cross-shaped structure has fourfold rotational symmetry, including a central intersection area and four arm areas extending outward from the central intersection area.

[0045] As described above, the Hall device and its manufacturing method of the present invention have the following beneficial effects: This invention employs a deep trench isolation structure and a sidewall tilting injection and diffusion process combined with wafer rotation. This allows for the fabrication of deep active regions with depths reaching approximately 20µm, significantly greater than that achieved by traditional DNW processes. This substantially increases the effective carrier region thickness of vertical Hall devices, thereby greatly improving the device's geometry factor and current sensitivity. The deep trenches physically limit the current path, reducing lateral leakage current. The use of a rotationally symmetric (e.g., cross-shaped) active region structure and symmetrically distributed contact areas enables the device to effectively eliminate offset voltage using a rotating current method and simultaneously monitor magnetic fields in both the X and Y directions. The design of the connection well region effectively guides current into the deep region, reducing series resistance. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of a horizontal Hall effect device used in the prior art to monitor the magnetic field strength in the Z direction. Figure 2 This is a schematic diagram of a vertical Hall effect device used in the prior art to monitor the magnetic field strength in the Y direction; Figure 3 The diagram shows a manufacturing process flow diagram of the Hall device and its manufacturing method according to the present invention. Figure 4 The diagram shows a schematic layout of a bidirectional magnetic field monitoring structure for the Hall device and its manufacturing method of the present invention. Figure 5 The diagram shows the working principle and current path of the vertical Hall device in the Hall device and its manufacturing method of the present invention. Figure 6 The diagram shown is a schematic diagram of the device portion of the Hall device and its manufacturing method according to the present invention. Figure 7 The diagram shows a cross-sectional structure of the Hall device and its manufacturing method of the present invention after forming a deep trench. Figure 8 The diagram shown is a cross-sectional view of the tilting injection step in the Hall device and its manufacturing method of the present invention. Figure 9 The diagram shows a cross-sectional structure of the Hall device and its manufacturing method of the present invention after deep trench filling and planarization. Figure 10 The diagram shows a cross-sectional structure of the Hall device and its manufacturing method of the present invention after the hard mask layer has been removed. Figure 11 The diagram shows a cross-sectional view of the Hall device and its manufacturing method according to the present invention, illustrating the formation of the device surface structure and metal interconnects. Figure 12 The diagram shows the layout of the device connection well region and the second conductivity type contact region of the Hall device and its manufacturing method according to the present invention. Detailed Implementation

[0047] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] like Figure 12 The diagram shown is a schematic layout of a Hall effect device according to an embodiment of this application; as shown... Figure 11 As shown, this device moves along... Figure 11 A schematic diagram of the cross-sectional structure along one arm of the structure.

[0049] This application provides a Hall device, including a first conductivity type semiconductor substrate 101.

[0050] In some embodiments, the first conductivity type semiconductor substrate may 101 comprise a bulk silicon substrate. Alternatively, the semiconductor substrate may comprise elemental semiconductors, such as diamond or germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide; alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, GaInP, GaInAs, GaInAsP, AlInAs, AlGaAs, AlGaInS, and combinations thereof. Furthermore, the semiconductor substrate may be a semiconductor-on-insulator (SOI) structure, a germanium-on-insulator (GOI) structure, or a silicon-on-insulator (SGOI) structure. The semiconductor substrate may also comprise a single or multiple epitaxial layers, which may be strained to enhance performance. Depending on design requirements, the semiconductor substrate may comprise various doped regions, such as P-type wells and / or N-type wells. Using these materials and structural configurations, carrier mobility can be effectively tuned, optimizing the response characteristics of the Hall device under different temperature and magnetic field environments.

[0051] The device in this embodiment also includes an isolation structure disposed in a first conductivity type semiconductor substrate 101, which defines an independent active region pattern, the active region pattern having a rotationally symmetric structure.

[0052] Rotationally symmetric structures can effectively work with chopper or rotating current techniques in circuits to counteract the piezoelectric resistance effect introduced by photolithography alignment errors or packaging stress, thereby significantly reducing the zero magnetic field offset voltage of the device.

[0053] In some embodiments, the isolation structure includes deep trenches distributed in a closed loop to enclose an active region pattern. For example... Figure 6 As shown, in the layout, the deep trench forms a closed loop through the filling material 107 and the insulating isolation layer 106, isolating the internal active region from the external substrate 101.

[0054] Deep trenches not only provide electrical isolation, but also restrict the lateral spread of current through physical morphology, confining the current within the active region channel in the vertical direction.

[0055] In some embodiments, the deep trench is filled with a filling material 107, and an insulating layer 106 is provided between the filling material 107 and the inner wall of the deep trench.

[0056] In some embodiments, the filler material 107 is polycrystalline silicon.

[0057] Alternatively, the filler material 107 may be selected from amorphous silicon, monocrystalline silicon, doped polycrystalline silicon (N-type or P-type), undoped polycrystalline silicon, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous carbon, spin-on glass (SOG), spin-on dielectric (SOD), low-k dielectric materials (e.g., fluorinated silicon glass FSG, carbon-doped silicon oxide CDO, Black Diamond, degel, aerogel), polymer materials (e.g., polyimide, benzocyclobutene BCB), or include metallic materials such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, and any combination or multilayer stacked structure of the above materials. Polycrystalline silicon filling provides good mechanical support, preventing deep trenches from collapsing or closing during subsequent thermal processes.

[0058] In some embodiments, polysilicon is configured to fill deep trenches to prevent stress-induced cracking and to serve as an electronic shielding layer.

[0059] By connecting polysilicon to a fixed potential, the modulation of the depletion layer width on the trench sidewalls by the external electric field can be shielded, thereby improving the stability of device performance.

[0060] In some embodiments, the insulating layer 106 is a silicon dioxide layer.

[0061] Alternatively, the insulating layer may comprise silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, lanthanum oxide, strontium titanate, barium titanate, and other high-k dielectric materials or combinations thereof. The insulating layer may be a growth layer formed by a thermal oxidation process or a deposition layer formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0062] In some embodiments, the depth of the deep trench is 15 μm to 25 μm.

[0063] This depth range (e.g., 20µm) is much larger than the depth of conventional DNW processes (2-3µm). According to the vertical Hall device sensitivity formula SIV=(G×rH) / (q×ND×d), the increase in the carrier region thickness d directly increases the geometric factor G, thereby significantly improving the current sensitivity SIV.

[0064] In some embodiments, the rotationally symmetric structure is a cross-shaped structure, such as... Figure 6 and Figure 12 As shown, the cross-shaped structure has fourfold rotational symmetry, including a central intersection area and four arm areas extending outward from the central intersection area.

[0065] Besides the cross shape, rotationally symmetric structures can also be square, rectangular (with double symmetry), octagonal, hexagonal, circular, plum blossom-shaped, windmill-shaped, or other polygonal composite structures with multiple rotational symmetries, to adapt to different packaging forms and magnetic field detection requirements.

[0066] In some embodiments, the Hall device is configured to operate using a rotationally symmetric structure with a rotating current method to correct offset voltage.

[0067] In some embodiments, the Hall device is configured to simultaneously monitor the magnetic field strength in the X direction and the magnetic field strength in the Y direction parallel to the device surface.

[0068] like Figure 4 The diagram illustrates the structure of the device for monitoring magnetic fields in the X and Y directions. The device includes a Vertical Hall device 1 (first vertical Hall device) extending along the X-axis and a Vertical Hall device 2 (second vertical Hall device) extending along the Y-axis. The first vertical Hall device monitors the magnetic field strength in the Y direction parallel to the surface, while the second vertical Hall device monitors the magnetic field strength in the X direction parallel to the surface. The cross-shaped layout allows the monitoring units in both directions to share a central area, achieving a compact 3D magnetic field sensing capability.

[0069] like Figure 4 and Figure 5 As shown, taking the first vertical Hall effect device for monitoring the magnetic field in the Y direction as an example, its working principle is as follows: A high voltage is applied to the central port H, and a low voltage is applied to the edge ports L1 and L2, thereby establishing a current field inside the device. Under the influence of the Y-direction magnetic field B, the vertically flowing electrons are deflected by the Lorentz force. Figure 5 As shown by the middle arrow, electrons are deflected and accumulate at induction port S2, while electrons become sparse at the opposite induction port S1. This uneven distribution of charge carriers generates a Hall voltage Vhall between ports S1 and S2. The specific value of Vhall reflects the magnetic field strength in the Y direction. Similarly, in Figure 4 The magnetic field strength in the X direction can be determined by measuring the voltage difference between ports S3 and S4. Figure 5 The vertical current path defined by the deep trench is clearly shown, and the depth of the path directly determines the effective distance at which electrons are subjected to the Lorentz force, proving the physical mechanism by which the deep trench structure of this application improves sensitivity.

[0070] The device also includes a second conductivity type deep active region 105 located within the active region pattern defined by the isolation structure.

[0071] In some embodiments, the second conductivity type deep active region 105 is formed by overlapping second conductivity type doped regions diffused inward from the sidewalls of the deep trench, such as... Figure 9 As shown, the diffusion zones on both sides of the trench walls merge at the center, forming a continuous active zone 105 that extends to the bottom.

[0072] Through sidewall diffusion, a conductive channel with uniform concentration distribution can be formed throughout the depth of the trench. This solves the problem that traditional top injection cannot maintain a high concentration at deep depths, while avoiding lattice damage caused by using excessive injection energy to achieve depth.

[0073] The device also includes multiple connection well regions 109, which are of the second conductivity type, spaced apart above the deep active region 105 of the second conductivity type, and extending into the interior of the deep active region 105 of the second conductivity type, such as... Figure 11 As shown.

[0074] The connection well region 109 acts as a low-resistance channel, effectively reducing the series resistance of current flowing from the surface contact region into the deep active region, thereby improving the device's driving capability and signal-to-noise ratio.

[0075] The device also includes a plurality of second conductivity type contact regions 108, which are located on the top surface of the corresponding connection well region 109, and the plurality of second conductivity type contact regions 108 are symmetrically distributed according to the rotational symmetry structure.

[0076] In some embodiments, the depth of the connection well region 109 is greater than the depth of the second conductivity type contact region 108; the connection well region 109 is configured to guide carriers to migrate from the second conductivity type contact region 108 to the depth of the second conductivity type deep active region 105.

[0077] In some embodiments, a plurality of second conductive type contact areas 108 are distributed in the central cross region and in each arm region.

[0078] like Figure 4 As shown, the contact area includes the H port located in the central crossover area, and the L1, L2, L3, and L4 ports located at the ends of the four arm areas, and the S1, S2, S3, and S4 ports located in the middle of the arm areas. This symmetrical distribution ensures that the input and output terminals can be flexibly switched in rotating current mode, thereby efficiently eliminating offset.

[0079] In some embodiments, a metal silicide layer 111 is also included, which is formed only on the surface of the second conductivity type contact region 108, such as... Figure 12 As shown.

[0080] Metal silicide materials can include titanium silicide, cobalt silicide, nickel silicide, platinum silicide, tungsten silicide, tantalum silicide, erbium silicide, palladium silicide, molybdenum silicide, ytterbium silicide, rhodium silicide, and their alloys or combinations. Forming metal silicides can reduce contact resistance and Joule heating.

[0081] The device also includes a first conductivity type surface isolation region 110, located on the surface of the second conductivity type deep active region 105, and filling the spaces between adjacent second conductivity type contact regions 108, such as... Figure 6 and Figure 12 As shown.

[0082] In some embodiments, the first conductivity type surface isolation region 110 is configured to neutralize the second conductivity type charge carriers on the surface.

[0083] In some embodiments, the first conductivity type surface isolation region 110 is formed by high concentration doping at the surface to suppress ineffective current components at the device surface.

[0084] Surfaces typically contain numerous interface state defects and dangling bonds, which can generate significant low-frequency noise when current flows through them. By using a high-concentration surface layer of the first conductivity type (e.g., P-type), charge carriers of the second conductivity type (e.g., N-type) can be pushed into the semiconductor interior, forcing the current to flow primarily in the bulk region, thereby reducing noise and improving detection accuracy.

[0085] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

[0086] P-type dopants can be selected from boron (B), boron difluoride (BF2), gallium (Ga), indium (In), or combinations thereof; N-type dopants can be selected from phosphorus (P), arsenic (As), antimony (Sb), nitrogen (N), bismuth (Bi), or combinations thereof. N-type charge carriers (electrons) typically have higher mobility than P-type charge carriers (holes), which helps to improve the sensitivity and response speed of Hall devices.

[0087] It should be noted that although this embodiment uses P-type as the first conductivity type and N-type as the second conductivity type as an example, those skilled in the art should understand that the conductivity types can be interchanged. That is, in alternative embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type. In this case, the substrate is an N-type semiconductor, the active region, the connection well region, and the contact region are P-type doped, and the surface isolation region is N-type doped. Although the sensitivity of a P-type channel Hall device may be slightly lower than that of an N-type channel device due to the lower hole mobility than electron mobility, its working principle is exactly the same and still falls within the protection scope of this application.

[0088] This application also provides a method for manufacturing a Hall effect device. For example... Figure 3 As shown, Figure 3 This is a schematic diagram of a manufacturing process provided for an embodiment of this application. The method includes steps one through six. Specifically, it includes the following steps: Step 1: Provide a first conductivity type semiconductor substrate 101, form a hard mask layer on the surface of the first conductivity type semiconductor substrate 101, and form deep trenches through an etching process. For example... Figure 7 As shown, the hard mask layer includes a first layer 102 and a second layer 103, and deep trenches are formed in the substrate 101 by photolithography and etching.

[0089] In some embodiments, in step one, the hard mask layer is a multilayer structure, which includes a silicon oxide layer and a silicon nitride layer.

[0090] Hard mask layers can be single-layer structures or include other materials such as silicon oxynitride, silicon carbide, amorphous carbon, spin-coated carbon, photoresist, or metal hard masks (such as titanium nitride and tantalum nitride). Multilayer structures (e.g., pad oxide layer plus silicon nitride layer) can reduce interfacial stress between the mask material and the silicon substrate.

[0091] In some embodiments, in step one, the etching depth of the deep trench is 15µm to 25µm.

[0092] Etching processes can include dry etching, such as reactive ion etching (RIE), inductively coupled plasma (ICP) etching, electron cyclotron resonance (ECR) etching, and especially deep reactive ion etching (DRIE) or Bosch processes, to obtain trench morphologies with high aspect ratios and vertical sidewalls.

[0093] In some embodiments, in step one, the deep trench defines a cross-shaped structure on the surface of the first conductivity type semiconductor substrate.

[0094] In some embodiments, the cross-shaped structure has fourfold rotational symmetry, including a central intersection area and four arm areas extending outward from the central intersection area.

[0095] Step 2: Tilt implantation of ions of the second conductivity type is performed on the deep trench, and combined with wafer rotation, implantation regions 104 are formed on the sidewalls and bottom of the deep trench, such as... Figure 8 As shown.

[0096] In some embodiments, in step two, the first conductivity type is P-type, and the first conductivity type semiconductor substrate is a P-type silicon substrate.

[0097] In some embodiments, in step two, the second conductivity type is N-type, and the second conductivity type ion is phosphorus ion.

[0098] Arsenic, antimony, or other N-type dopants can also be used at this time. Phosphorus ions were chosen because of their moderate diffusion coefficient, which makes it easy to achieve deep bonding through subsequent heat treatment.

[0099] In some embodiments, in step two, the tilting implantation and wafer rotation process is configured such that the spacing between adjacent implantation regions 104 is S.

[0100] Wafer rotation can be done in steps (e.g., 0 degrees, 90 degrees, 180 degrees, 270 degrees) or continuously to ensure that each sidewall of the trench receives a uniform dose.

[0101] Step 3: Perform diffusion heat treatment to allow ions in the implantation region 104 to diffuse and connect, forming a deep active region 105 of the second conductivity type, and form an insulating isolation layer 106 on the inner wall of the deep trench; deposit filling material 107 in the deep trench and perform preliminary planarization. Figure 9 As shown, the injection areas on both sides merge to form a continuous active area 105, the inner wall of the trench is oxidized to form an isolation layer 106, and a filling material 107 is deposited.

[0102] In some embodiments, in step three, the diffusion heat treatment is configured to make the value of the spacing S become 0, thereby causing the injection regions 104 on both sides to overlap to form a second conductivity type deep active region 105, such as... Figure 9 The diagram illustrates the transition state, showing that as the thermal process progresses, the spacing S gradually decreases until it disappears.

[0103] At this point, the originally separated injection regions diffuse laterally and "bridge" under thermal drive, forming a complete electrical encapsulation structure.

[0104] In some embodiments, in step three, the insulating layer 106 is a silicon dioxide layer generated by thermal oxidation during the diffusion heat treatment process.

[0105] This utilizes the diffusion thermal budget, eliminates the need for additional deposition steps, and results in a better interface quality for thermally grown oxide layers compared to deposited oxide layers.

[0106] In some embodiments, in step three, the insulating layer 106 is a silicon dioxide layer.

[0107] In some embodiments, in step three, the filler material 107 is polycrystalline silicon.

[0108] Polycrystalline silicon can be formed by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) to achieve good step coverage and trench filling effects.

[0109] In some embodiments, in step three, polysilicon is used to fill deep trenches to prevent stress-induced cracking and to serve as an electronic shielding layer.

[0110] In some embodiments, in step three, the initial planarization is performed using a chemical mechanical polishing process.

[0111] Chemical mechanical polishing (CMP) can remove excess filler material outside the trenches, stopping at the surface of a hard mask layer or substrate. Alternatively, planarization can be achieved using etch-back processes or combinations thereof.

[0112] Step 4: Remove the hard mask layers (102 and 103) and perform a second planarization process on the surface of the first conductivity type semiconductor substrate 101, such as... Figure 10 As shown, a smooth surface was obtained.

[0113] In some embodiments, step four involves removing the hard mask layer using a wet etching process.

[0114] For example, thermal phosphoric acid can be used to remove silicon nitride, while dilute hydrofluoric acid or buffered oxide etchant (BOE) can be used to remove silicon oxide. Dry etching can also be used to remove all or part of the hard mask layer.

[0115] In some embodiments, in step four, the planarization process employs a chemical mechanical polishing process to obtain a flat surface for subsequent photolithography processes.

[0116] Step 5: Form a second conductivity type contact region 108, a connection well region 109, and a first conductivity type surface isolation region 110 on the surface of the deep active region 105 of the second conductivity type, such as... Figure 11 As shown.

[0117] In some embodiments, step five, forming the second conductivity type contact region 108 and the connection well region 109, includes: using the same photomask, performing ion implantation to form the second conductivity type contact region 108 and high-energy ion implantation to form the connection well region 109, respectively.

[0118] This is known as a self-alignment process, which ensures that the contact area is precisely positioned above the connection well area.

[0119] In some embodiments, step five, forming the connection well region 109, includes: performing ion implantation using an independent vertical Hall implantation mask, and supplementing or replacing the photolithography process of the second conductivity type contact region 108 by individually adjusting the energy and dose of the ion implantation to meet the specific depth or resistance requirements of the connection well region 109.

[0120] While an independent mask strategy adds an extra photolithography step, it provides flexibility in the process window, allowing engineers to optimize the connection resistance independently.

[0121] In some embodiments, the depth of the connection well region 109 is greater than the depth of the second conductivity type contact region 108.

[0122] In some embodiments, in step five, the first conductivity type surface isolation region 110 is formed by ion implantation and covers the area other than the second conductivity type contact region 108.

[0123] Step Six: Forming metal silicides and metal leads. For example... Figure 11 As shown, a metal silicide 111 is formed and connected to other circuits via a metal wire (schematically 112).

[0124] In some embodiments, in step six, a metal silicide barrier layer photoresist is used such that the metal silicide 111 is generated only on top of the second conductivity type contact region 108.

[0125] This process, commonly known as SAB (Salicide Block), prevents the formation of silicides on non-contact areas (such as P-type surface isolation regions), thus avoiding short circuits between N- and P-regions via silicides. The steps for forming metal silicides may specifically include: depositing a layer of refractory metal, such as nickel, cobalt, titanium, platinum, erbium, palladium, or alloys thereof, on the surface of a semiconductor substrate. The deposition process can employ physical vapor deposition (PVD), such as DC magnetron sputtering or RF sputtering, or chemical vapor deposition (CVD) or atomic layer deposition (ALD). This is followed by a rapid thermal annealing (RTA) process, which reacts the deposited metal with the exposed silicon surface to form silicides. Subsequently, unreacted metal is removed using selective wet etching. Finally, a second annealing process may be performed to reduce the sheet resistance of the silicide and stabilize the phase structure.

[0126] In some embodiments, the metal lead includes a contact plug, a metal layer, and an interlayer dielectric layer (ILD).

[0127] In some embodiments, the interlayer dielectric layer may be formed of a low-k material to reduce parasitic capacitance and RC delay. The dielectric constant of the low-k material may be less than 3.0 or less than 2.5. The material of the interlayer dielectric layer may be selected from: silicon oxide, undoped silicon glass (USG), fluorine-doped silicon glass (FSG), silicon phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), spin-coated glass (SOG), carbon-doped silicon oxide (SiOC), black diamond, xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), polyimide, or multilayer combinations thereof. The interlayer dielectric layer may be formed by spin coating, chemical vapor deposition (CVD), high-density plasma CVD (HDP-CVD), or plasma-enhanced CVD (PECVD).

[0128] In some embodiments, the contact plug penetrates the interlayer dielectric layer and is electrically connected to the metal silicide. The steps of forming the contact plug include: etching contact holes in the interlayer dielectric layer; depositing a barrier / liner layer, including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof, to improve adhesion and prevent metal diffusion; subsequently depositing a conductive filler material, such as tungsten (W), copper (Cu), aluminum (Al), or an aluminum-copper alloy; and finally removing excess metal material by chemical mechanical polishing (CMP).

[0129] In some embodiments, the metal layer is formed on or embedded within an interlayer dielectric layer. When using an aluminum process, the metal layer comprises a sequentially deposited Ti / TiN / AlCu / TiN stack structure, patterned to form conductive lines via photolithography and reactive ion etching (RIE). When using a copper process, a single damascene or dual damascene process is employed. This includes: etching trenches or vias in the dielectric layer; depositing a diffusion barrier layer (such as Ta / TaN); depositing a copper seed layer; filling copper via electrochemical plating (ECP); and performing chemical mechanical polishing (CMP) planarization. The metal layer may comprise a multilayer interconnect structure, with layers isolated from each other by etch stop layers (such as silicon nitride or silicon carbide).

[0130] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0131] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A Hall effect device, characterized in that, include: First conductivity type semiconductor substrate; An isolation structure is disposed in the first conductivity type semiconductor substrate and defines an independent active region pattern, the active region pattern having a rotationally symmetric structure; The second conductivity type deep active region is located within the active region pattern defined by the isolation structure; Multiple connection well regions, of the second conductivity type, are spaced apart on the upper part of the deep active region of the second conductivity type and extend into the interior of the deep active region of the second conductivity type; Multiple second-conductivity contact areas are located on the top surface of the corresponding connection well area, and the multiple second-conductivity contact areas are symmetrically distributed according to the rotational symmetry structure; A first conductivity type surface isolation region is located on the surface of the second conductivity type deep active region and fills the space between adjacent second conductivity type contact regions.

2. The Hall device according to claim 1, characterized in that: The isolation structure includes deep trenches distributed in a closed loop to enclose the active region pattern.

3. The Hall device according to claim 2, characterized in that: The second conductivity type deep active region is formed by overlapping second conductivity type doped regions that diffuse inward from the sidewalls of the deep trench.

4. The Hall device according to claim 2, characterized in that: The depth of the deep trench is 15um to 25um.

5. The Hall device according to claim 1, characterized in that: The rotationally symmetric structure is a cross-shaped structure with fourfold rotational symmetry, including a central intersection area and four arm areas extending outward from the central intersection area.

6. The Hall device according to claim 1, characterized in that: The Hall device is configured to operate using the rotationally symmetric structure via a rotating current method to correct the offset voltage.

7. The Hall device according to claim 1, characterized in that: The Hall device is configured to simultaneously monitor the magnetic field strength in the X and Y directions parallel to the device surface.

8. The Hall device according to claim 1, characterized in that: The depth of the connection well region is greater than the depth of the second conductivity type contact region; the connection well region is configured to guide carriers to migrate from the second conductivity type contact region to the depth of the second conductivity type deep active region.

9. The Hall device according to claim 1, characterized in that: The first conductivity type surface isolation region is configured to neutralize the second conductivity type charge carriers on the surface to suppress surface current.

10. The Hall device according to claim 1, characterized in that: It also includes a metal silicide layer, which is formed only on the surface of the second type of conductive contact area.

11. The Hall device according to claim 8, characterized in that: The deep trench is filled with a filling material, and an insulating layer is provided between the filling material and the inner wall of the deep trench.

12. The Hall device according to claim 11, characterized in that: The filling material is polycrystalline silicon, which is configured to fill the deep trench to prevent stress-induced cracking and to serve as an electronic shielding layer.

13. The Hall device according to claim 11, characterized in that: The insulating layer is a silicon dioxide layer.

14. A method for manufacturing a Hall effect device, characterized in that, include: Step 1: Provide a semiconductor substrate of a first conductivity type, form a hard mask layer on the surface of the semiconductor substrate of the first conductivity type, and form the deep trench by etching process; Step 2: Perform tilted implantation of ions of the second conductivity type into the deep trench, and combine it with wafer rotation process to form implantation areas on the sidewalls and bottom of the deep trench; Step 3: Perform diffusion heat treatment to allow ions in the implantation region to diffuse and connect to form a deep active region of the second conductivity type, and form an insulating layer on the inner wall of the deep trench; Deposit filling material and perform preliminary planarization within the deep trench; Step 4: Remove the hard mask layer and perform planarization treatment on the surface of the first conductivity type semiconductor substrate again; Step 5: Form a second conductivity type contact region, the connection well region, and a first conductivity type surface isolation region on the surface of the deep active region of the second conductivity type; Step 6: Form metal silicide and metal leads.

15. The method for manufacturing a Hall device according to claim 14, characterized in that: In step one, the hard mask layer is a multilayer structure, which includes a silicon oxide layer and a silicon nitride layer.

16. The method for manufacturing a Hall device according to claim 14, characterized in that: In step one, the etching depth of the deep trench is 15um to 25um.

17. The method for manufacturing a Hall device according to claim 14, characterized in that: In step two, the first conductivity type is P-type, and the first conductivity type semiconductor substrate is a P-type silicon substrate.

18. The method for manufacturing a Hall device according to claim 14, characterized in that: In step two, the second conductivity type is N-type, and the second conductivity type ion is phosphorus ion.

19. The method for manufacturing a Hall device according to claim 14, characterized in that: In step two, the tilting implantation and wafer rotation process is configured such that the spacing between adjacent implantation regions is S.

20. The method for manufacturing a Hall device according to claim 18, characterized in that: In step three, the diffusion heat treatment is configured to make the value of the spacing S become 0, thereby causing the injection regions on both sides to overlap to form a deep active region of the second conductivity type.

21. The method for manufacturing a Hall device according to claim 14, characterized in that: In step three, the insulating layer is a silicon dioxide layer.

22. The method for manufacturing a Hall device according to claim 14, characterized in that: In step three, the filling material is polycrystalline silicon.

23. The method for manufacturing a Hall device according to claim 21, characterized in that: In step three, the polycrystalline silicon is used to fill the deep trench to prevent stress-induced cracking and to serve as an electronic shielding layer.

24. The method for manufacturing a Hall device according to claim 14, characterized in that: In step three, the initial planarization is performed using a chemical mechanical polishing process.

25. The method for manufacturing a Hall device according to claim 14, characterized in that: In step four, the hard mask layer is removed using a wet etching process.

26. The method for manufacturing a Hall device according to claim 14, characterized in that: In step four, the re-planarization process is performed using a chemical mechanical polishing process.

27. The method for manufacturing a Hall device according to claim 14, characterized in that: In step five, the steps of forming the second conductivity type contact region and the connection well region include: using the same photomask, performing ion implantation to form the second conductivity type contact region and high-energy ion implantation to form the connection well region, respectively.

28. The method for manufacturing a Hall device according to claim 14, characterized in that: In step five, the step of forming the connection well region includes: performing ion implantation using an independent vertical Hall implantation mask, and adjusting the energy and dose of the ion implantation to meet the depth or resistance requirements of the connection well region.

29. The method for manufacturing a Hall device according to claim 27 or 28, characterized in that: The depth of the connection well region is greater than the depth of the second type of conductive contact region.

30. The method for manufacturing a Hall device according to claim 14, characterized in that: In step five, the first conductive type surface isolation region is formed by ion implantation and covers the area other than the second conductive type contact region.

31. The method for manufacturing a Hall device according to claim 14, characterized in that: In step six, a metal silicide barrier layer photoresist is used so that the metal silicide is formed only on top of the second type of conductive contact area.

32. The method for manufacturing a Hall device according to claim 14, characterized in that: In step one, the deep trench defines a cross-shaped structure on the surface of the first type of conductive semiconductor substrate.

33. The method for manufacturing a Hall device according to claim 14, characterized in that: The cross-shaped structure has fourfold rotational symmetry, including a central intersection area and four arm areas extending outward from the central intersection area.

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