Source line resistance test key structure and monitoring method

Abstract

The invention provides a source line resistance test key structure and a monitoring method. The test key structure comprises a semiconductor substrate, an active region, a source line and a grid polycrystalline silicon structure. The key point is that the key size in the layout of the test key structure is determined according to a layout design rule of a memory cell array of a memory product related to the test key structure, for example, the distance between a grid polycrystalline silicon structure and a source line adopts the distance between two gate tubes in the memory cell array. The monitoring method comprises the following steps: providing the test key structure, applying a test signal, measuring an electrical response parameter, calculating to obtain a resistance value, and comparing the resistance value with a preset threshold value to monitor the process quality. By accurately simulating the real layout environment of the source line in the product, the problem that the resistance change of the source line cannot be effectively monitored by the existing common test structure is solved, the monitoring accuracy and sensitivity are remarkably improved, the failure risk such as weak programming can be effectively prevented, and the product yield is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a source line resistance test bond structure and monitoring method. Background Technology

[0002] In semiconductor memory technology, one-time programmable memory (OTP) is widely used due to its simple structure and low cost. Programming an OTP cell is typically achieved by applying a high programming voltage to a specific node of the memory cell, thereby altering its electrical characteristics to store information.

[0003] However, during the production of OTP products, a "weak programming" failure problem is frequently encountered, where the current of the programmed memory cell is insufficient, leading to read errors. Analysis revealed that excessively high resistance in the source line (SL) is a major cause of this weak programming failure.

[0004] Specifically, such as Figure 1 As shown, in a typical layout of an OTP memory cell array, a source line (SL) typically connects a row of multiple memory cells (e.g., Bit0 to Bit31) and is orthogonal to multiple word lines (WL). When programming a memory cell, the programming voltage (VPP) is typically applied from one or both ends of the source line. A portion of the programming current needs to flow through the source line to reach the target memory cell selected by the word line (e.g., Bit0 to Bit31). Figure 1 (As shown at point T). Due to the inherent resistance of the source line, the flow of current will inevitably cause a voltage drop.

[0005] Therefore, the farther a memory cell is from the programming voltage access point, the longer the source line path through which the programming current flows, the larger the accumulated resistance R, and the more significant the voltage drop experienced. This means that the actual programming voltage (Vt) ultimately applied to the target memory cell will be lower than the externally applied VPP, i.e., Vt = VPP - Iprogram * R. This voltage drop effect is particularly severe when the source line resistance is large, exhibiting a characteristic failure mode related to the physical layout. Figure 2 As shown, electrical test results will show that the performance parameters of the programmed unit (such as the unit current) exhibit a wave-like pattern with a period of 32 bits, high at both ends and low in the middle. This phenomenon is called the "by 32 phenomenon".

[0006] To address this issue and improve product programmability, the industry typically optimizes processes to reduce source line resistance, such as optimizing the formation process of silicides (e.g., adjusting the Co RTP temperature). Practice has proven that such process optimizations are effective. Figure 4As shown, after successful optimization, the average programming current of the OTP memory cell was significantly improved, and the previously observed "by 32 phenomenon" also disappeared, with the cell current showing good consistency across the entire source line.

[0007] However, a key technical challenge arises: how to effectively monitor the stability and effectiveness of the aforementioned process optimizations. Research has revealed that conventional WAT test structures, such as standard N-type or P-type active region (AA) resistance test structures (often denoted as RSN+ and RSP+), are insensitive to process tweaks aimed at improving source line resistance. For example, after the Salicide process has been clearly tuned and the "by 32" weak programming problem has been successfully resolved, such as... Figure 3 As shown, the RSN+ and RSP+ resistance values ​​monitored from the WAT data showed almost no meaningful changes, and their test values ​​remained stably distributed within the original specifications (SPEC). This indicates that this ordinary AA resistance test structure cannot accurately reflect the actual resistance changes of the source lines inside the OTP cell array, and therefore cannot be used as an effective monitoring method to warn or control weak programming risks related to source line resistance.

[0008] The reason for this is that the layout, pattern density, and surrounding environment of ordinary AA resistor test structures are significantly different from the source lines in real OTP memory cell arrays, resulting in inconsistent final electrical characteristics when they undergo the same process steps (such as Salicide formation).

[0009] Therefore, there is an urgent need to develop a new type of WAT test structure that can realistically simulate the actual layout environment and physical characteristics of the source line in OTP products, thereby achieving accurate and effective monitoring of the source line resistance. Summary of the Invention

[0010] The purpose of this invention is to overcome the shortcomings of the prior art and provide a test bond structure and corresponding monitoring method that can accurately and effectively monitor the source line resistance in memory products.

[0011] To address the technical problem mentioned in the background art that the ordinary WAT test structure cannot accurately reflect the source line resistance changes in memory products such as OTP, thus making it difficult to effectively monitor weak programming risks, this application provides a test key structure. This test key structure, by adopting key design rules consistent with the actual memory cell array in the layout design, enables its physical form and electrical characteristics to highly simulate the source line in real products, thereby solving the problems of insensitivity and inaccuracy of existing monitoring methods.

[0012] To achieve the above objectives, this application provides a source line resistance test bond structure, comprising:

[0013] Semiconductor substrate;

[0014] Active regions formed on semiconductor substrates;

[0015] Source lines formed on a semiconductor substrate, the source lines having connection terminals for measurement;

[0016] And a gate polysilicon structure disposed above or adjacent to the active region;

[0017] The key dimensions in the layout of the test key structure are determined according to the layout design rules of the memory cell array of the memory product related to the test key structure, so that the resistance characteristics of the source line in the test key structure can characterize the resistance characteristics of the source line in the memory cell array.

[0018] Preferably, the critical dimension includes the spacing between the gate polysilicon structure and the source line.

[0019] Preferably, the spacing between the gate polysilicon structure and the source line is determined by using the spacing between two select transistors in the memory cell array as a design rule.

[0020] Preferably, the memory product is a one-time programmable memory.

[0021] Preferably, a conductive layer is formed on the surface of the source line and / or the active region.

[0022] Preferably, the conductive layer is a metal silicide layer.

[0023] Preferably, the metal silicide layer is a cobalt silicide layer or a titanium silicide layer.

[0024] Preferably, it also includes test pads connected to both ends of the source line for performing electrical measurements on the source line via the test pads.

[0025] This application also provides a method for monitoring source line resistance, comprising the following steps:

[0026] Step 1: Provide a test key structure according to any of the preceding items;

[0027] Step 2: Apply a test signal to the source line through the connection terminal of the test bond structure and measure the corresponding electrical response parameters;

[0028] Step 3: Calculate the resistance value of the source wire based on the test signal and electrical response parameters;

[0029] Step 4: Compare the resistance value with a preset threshold to monitor the process quality of the source wire.

[0030] Preferably, in step two, applying the test signal means applying a test current, and measuring the corresponding electrical response parameters means measuring the voltage drop across the source line.

[0031] Preferably, in step four, the preset threshold is determined based on the upper limit of the source line resistance required for the memory product to avoid weak programming failures.

[0032] Preferably, when the measured resistance value is lower than a preset threshold, the process quality of the source wire is deemed to be qualified.

[0033] Preferably, the method is used to monitor the stability of metal silicide processes.

[0034] As described above, the source line resistance test bond structure and monitoring method of the present invention have the following beneficial effects:

[0035] The test key structure of this application simulates the layout environment of real devices, enabling its resistance measurements to accurately reflect the impact of process variations on product performance, significantly improving the accuracy and effectiveness of monitoring. The monitoring method based on this test key structure can detect process deviations early, providing a reliable technical means to prevent product failures such as weak programming, and contributing to improved product yield and reliability. Attached Figure Description

[0036] Figure 1 This is a partial layout diagram of an OTP memory cell array in the prior art, used to illustrate the physical cause of the weak programming phenomenon;

[0037] Figure 2 The electrical characteristic curves for the "by 32 phenomenon" occurring in existing technologies are shown.

[0038] Figure 3 This is a graph of WAT data monitored using a common AA resistor test structure in the existing technology.

[0039] Figure 4 The electrical characteristic curves showing the consistency of current in OTP cells after process improvement in the existing technology;

[0040] Figure 5 This is a top view of the layout of the test key structure in one embodiment of this application;

[0041] Figure 6 This is a cross-sectional schematic diagram of the test key structure in one embodiment of this application;

[0042] Figure 7 This is a schematic diagram of the main flow of a source line resistance monitoring method in one embodiment of this application. Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] This application provides a test bond structure for testing the resistance of the source line (SL), comprising:

[0045] A semiconductor substrate; an active area (AA) formed on the semiconductor substrate; a storage line (SL) formed on the semiconductor substrate, the SL having a connection terminal for measurement; and a gate polysilicon structure disposed above or adjacent to the AA; wherein, the key dimensions in the layout of the test bond structure are determined according to the layout design rules of the memory cell array of the memory product related to the test bond structure, so that the resistance characteristics of the SL in the test bond structure can characterize the resistance characteristics of the SL in the memory cell array. By adopting this design that is strongly correlated with the actual product layout rules, this test bond structure can accurately simulate the physical and electrical environment of the SL in the real memory cell array, thereby obtaining a resistance test value that is highly correlated with the actual performance of the product, solving the problem that existing ordinary test structures cannot effectively monitor process changes, and providing a reliable basis for monitoring process stability and improving product yield.

[0046] The test key structure of the embodiments of this application will now be described in more detail with reference to the accompanying drawings.

[0047] Figure 5 This is a top view of the layout of a test key structure in one embodiment of this application. Figure 5 As shown, the test bond structure includes an elongated AA, with two gate polysilicon (GPS) structures extending parallel to each other on both sides of the AA. The AA region located between the two GPS structures constitutes the SL to be tested in this invention. The two ends of the AA extend out of the GPS-covered area and form contact areas for subsequent connection to the test pads.

[0048] Figure 6 This is a cross-sectional schematic diagram of the test key structure in one embodiment of this application, which shows the relationship with... Figure 5 The corresponding structure is a cross-section perpendicular to the length of the gate polysilicon. For example... Figure 6As shown, two gate structures spaced a certain distance apart are formed on the substrate, and the AA surface between them is the SL region. A metal silicide layer can be formed on the SL surface to reduce resistance. The spacing between the two gate structures is defined as the critical dimension L. This dimension L is designed based on the spacing between two adjacent select gates (SG) in actual memory products (such as one-time programmable memory, OTP), thereby ensuring that the test bond structure can accurately simulate the real formation environment of the SL in the product.

[0049] In some embodiments, test bond structures are integrated into the dicing area of ​​a semiconductor wafer. Dicing grooves are non-functional areas located between individual dies on a wafer, used for dicing after manufacturing. Arranging test bond structures within the dicing grooves allows for monitoring of the uniformity of the entire wafer process without occupying valuable die functional area. Typically, multiple test bond structures are distributed across the wafer, such as at the center, edges, and representative locations in the four quadrants, to obtain statistical data reflecting variations in the entire wafer process.

[0050] In some embodiments, the formation method of the test bond structure is fabricated concurrently with the device of the functional area of ​​the memory product. This means that the test bond structure undergoes the exact same manufacturing process as the actual memory cell. Specifically, the formation method may include the following steps: First, a shallow trench isolation (STI) structure for defining the AA is formed on a semiconductor substrate using photolithography and etching processes. Subsequently, ion implantation is performed to form the well region and adjust the threshold voltage. Next, a gate polysilicon structure is formed by depositing a gate dielectric layer and a gate electrode layer (e.g., polysilicon), followed by photolithography and etching processes. Then, source / drain regions, i.e., SL regions, are formed by ion implantation. During this process, the presence of the gate polysilicon structure affects the distribution of implanted ions, thereby simulating the environment of a real cell. A key step is that after forming the sidewalls, metal deposition and one or more rapid thermal annealing (RTP) processes are performed to form a self-aligned metal silicide layer. Since the critical dimensions of the test bond structure (such as gate pitch) are consistent with the memory cell array, the thickness, phase, and resistivity of the metal silicide layer formed thereon can highly reproduce the SL conditions within the functional area. Finally, the SL in the test bond structure is connected to the test pads for wafer acceptance test (WAT) by forming interlayer dielectric (ILD), contact holes, and metal interconnects. Throughout the process, the test bond structure shares all photolithographic masks and process steps with the functional devices, thereby ensuring a high degree of consistency between its structure and electrical properties and the target monitored object.

[0051] Semiconductor substrates can be of various types, such as, but not limited to, bulk silicon substrates, silicon-on-insulator (SOI) substrates, or other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), or III-V group semiconductor materials such as gallium arsenide (GaAs). The specific choice depends on the integrated circuit process platform and application requirements.

[0052] AA is typically formed through a defined process, such as STI, which involves etching trenches into a semiconductor substrate and filling them with dielectric material to electrically isolate different devices or structures.

[0053] As a key patterning element in the test bond, the gate polysilicon structure can be made of heavily doped polysilicon or metal gate materials suitable for gate-before or gate-after processes, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and combinations thereof, to meet the process requirements of different technology nodes.

[0054] In some embodiments, a critical dimension includes the spacing between the gate polysilicon structure and the SL.

[0055] In some embodiments, the spacing between the gate polysilicon structure and the SL is determined using the spacing between two SGs in the memory cell array as a design rule. This specific design rule is one of the key aspects of this technical solution. In dense memory arrays, the spacing between adjacent gate structures significantly affects critical process steps such as sidewall formation and metal silicide growth. By accurately reproducing this spacing in the test bond structure, it can be ensured that the SL in the test bond undergoes almost identical local process effects during formation as the SL in the product, such as stress, etching load effects, and silicide growth environment, thereby enabling its resistance characteristics to truly represent the resistance characteristics of the SL in the product.

[0056] In some embodiments, the memory product is an OTP.

[0057] In some embodiments, a conductive layer is formed on the surface of SL and / or AA. The main function of this conductive layer is to reduce the sheet resistance of SL and AA, thereby reducing parasitic resistance and improving the driving capability and programming efficiency of the device.

[0058] In some embodiments, the conductive layer is a metal silicide layer. The metal silicide layer is typically formed by a self-aligned silicide process, which includes depositing a metal layer, performing one or more thermal annealing processes to react the metal with the underlying silicon to form a low-resistivity silicide phase, and finally removing the unreacted metal by wet etching.

[0059] In some embodiments, the metal silicide layer is a cobalt silicide (CoSi) layer or a titanium silicide (TiSi) layer. Besides CoSi and TiSi, the metal silicide layer can also be other materials, depending on the process node and performance requirements, such as nickel silicide (NiSi), platinum silicide (PtSi), or alloys thereof, which are widely used in more advanced process nodes and have lower resistivity and better thermal stability.

[0060] In some embodiments, test pads are also included, respectively connected to both ends of the SL, for performing electrical measurements on the SL through the test pads. This configuration supports efficient automated testing during the WAT stage using standard probe cards, enabling rapid acquisition of resistance data for multiple test bonds across the entire wafer, forming a wafer profile to evaluate process uniformity.

[0061] This application also provides a method for monitoring the SL resistor. Figure 7 The present application provides a flowchart illustrating a method for monitoring SL resistance according to an embodiment, including the following steps:

[0062] Step 1: Provide a test key structure according to any of the foregoing embodiments;

[0063] Step 2: Apply a test signal to the SL through the connection terminals of the test key structure and measure the corresponding electrical response parameters. This step is typically performed on the test key in the wafer dicing groove using automated test equipment (such as a probe station and semiconductor parameter analyzer). The probe precisely contacts the test pad of the test key to apply a signal and perform measurements.

[0064] In some embodiments, in step two, applying the test signal involves applying a known test current, and measuring the corresponding electrical response parameter involves measuring the voltage drop across SL. This is a classic four-wire or two-wire measurement principle based on Ohm's law. By applying a constant, appropriately sized current and accurately measuring the voltage across it, errors caused by contact resistance can be effectively eliminated, resulting in a more accurate resistance value.

[0065] Step 3: Calculate the resistance value of SL based on the test signal and electrical response parameters;

[0066] Step 4: Compare the resistance value with preset thresholds to monitor process quality. By comparing the real-time measured resistance value with preset upper and lower limits of engineering specifications, it can be determined whether the process is stable. Once the measured value exceeds the specification range or exhibits a specific drift trend, a process alarm can be triggered, prompting engineers to intervene and investigate. This allows for proactive prevention of potential product quality problems and avoids large-scale yield losses.

[0067] In some embodiments, in step four, the preset threshold is determined based on the upper limit of the SL resistor required to avoid weak programming failures in the memory product. This threshold is set based on rigorous experimental data and failure analysis. For example, by performing programming tests on chips with different SL resistor values, the critical resistance value that causes the "by 32 phenomenon" is found, and then a certain safety margin is added to this value to set a scientifically reasonable monitoring upper limit.

[0068] In some embodiments, when the measured resistance value is lower than a preset threshold, the process quality is deemed acceptable.

[0069] In some embodiments, this method can be specifically used to monitor the stability of metal silicide processes. For example, when the metal silicide layer in the test bond structure is CoSi, TiSi, or NiSi, this monitoring method can sensitively reflect the stability of key process parameters (such as metal deposition thickness, annealing temperature and time) for forming these different silicide layers. For instance, in the CoSi process, the RTP temperature and time are key parameters affecting the silicide phase and the final resistance. The SL resistance value monitored by this method can directly reflect minute fluctuations in the RTP process, exhibiting higher sensitivity compared to traditional test structures. Once a systematically high resistance value is detected, it can quickly pinpoint a potential problem with the RTP equipment, enabling timely equipment maintenance and process correction. Similarly, for the NiSi process, this method can also effectively monitor key process windows such as nickel metal thickness and oxygen content control during annealing, ensuring the consistency and reliability of the SL resistance.

[0070] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A source line resistance test bond structure, characterized in that, include: Semiconductor substrate; Active regions formed on the semiconductor substrate; A source line formed on the semiconductor substrate, the source line having a connection terminal for measurement; And a gate polysilicon structure disposed above or adjacent to the active region; The key dimensions in the layout of the test key structure are determined according to the layout design rules of the memory cell array of the memory product related to the test key structure, so that the resistance characteristics of the source lines in the test key structure can characterize the resistance characteristics of the source lines in the memory cell array.

2. The source line resistance test bond structure according to claim 1, characterized in that: The critical dimension includes the spacing between the gate polysilicon structure and the source line.

3. The source line resistance test bond structure according to claim 2, characterized in that: The spacing between the gate polysilicon structure and the source line is determined by using the spacing between two select transistors in the memory cell array as a design rule.

4. The source line resistance test bond structure according to claim 1, characterized in that: The memory product is a one-time programmable memory.

5. The source line resistance test key structure according to claim 1, characterized in that: A conductive layer is formed on the surface of the source line and / or the active region.

6. The source line resistance test bond structure according to claim 5, characterized in that: The conductive layer is a metal silicide layer.

7. The source line resistance test bond structure according to claim 6, characterized in that: The metal silicide layer is a cobalt silicide layer or a titanium silicide layer.

8. The source line resistance test bond structure according to claim 1, characterized in that: It also includes test pads connected to both ends of the source line for performing electrical measurements on the source line through the test pads.

9. A method for monitoring source line resistance, characterized in that, include: Step 1: Provide a test key structure according to any one of claims 1 to 8; Step 2: Apply a test signal to the source line through the connection terminal of the test key structure and measure the corresponding electrical response parameters; Step 3: Calculate the resistance value of the source wire based on the test signal and the electrical response parameters; Step 4: Compare the resistance value with a preset threshold to monitor the process quality of the source wire.

10. The method for monitoring source line resistance according to claim 9, characterized in that: In step two, the applied test signal is the applied test current, and the measured electrical response parameter is the measured voltage drop across the source line.

11. The method for monitoring source line resistance according to claim 9 or 10, characterized in that: In step four, the preset threshold is determined based on the upper limit of the source line resistance required to avoid weak programming failures in the memory product.

12. The method for monitoring source line resistance according to claim 11, characterized in that: When the measured resistance value is lower than the preset threshold, the process quality of the source wire is deemed to be qualified.

13. The method for monitoring source line resistance according to claim 9, characterized in that: The method is used to monitor the stability of metal silicide processes.

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