Preparation method of semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure, and relates to the technical field of semiconductors. The preparation method of the semiconductor structure comprises the steps of providing a semiconductor initial structure; forming a patterned first photoresist layer on the surface of the semiconductor initial structure, taking the patterned first photoresist layer as a mask, performing first etching treatment on the second mask layer and the first mask layer in sequence, and forming a groove in the first mask layer; forming a side wall on the side wall of the groove; a third mask layer and a patterned second photoresist layer are sequentially stacked on the surface of the first mask layer, the patterned second photoresist layer comprises at least one photoresist strip, and the photoresist strip at least partially exposes the surface of the third mask layer corresponding to the groove; and taking the patterned second photoresist layer as a mask, and performing second etching treatment on the third mask layer, the first mask layer and the polycrystalline silicon layer in sequence to obtain the semiconductor structure. According to the preparation method, the etching precision and the manufacturing process window during the first etching treatment can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Technology

[0002] With the continuous evolution of semiconductor integrated circuit technology, the demand for integrating more functional devices within a limited area of ​​a chip is constantly increasing. The critical dimension (CD) of semiconductor devices is continuously shrinking, which places higher demands on the ability of photolithography processes to achieve finer linewidth patterns. However, due to the wavelength of photolithography light sources gradually approaching their physical limits, and the critical dimension of devices also approaching the resolution limits of the exposure system, unlimited miniaturization is difficult to achieve. To further improve device integration, dual patterning techniques are often used. However, the etching precision of dual patterning techniques is difficult to control. Summary of the Invention

[0003] This invention provides a method for fabricating semiconductor structures to improve the etching accuracy of dual patterning techniques.

[0004] The present invention provides a method for fabricating a semiconductor structure, comprising:

[0005] A semiconductor initial structure is provided, the semiconductor initial structure comprising a substrate, a polysilicon layer, a first mask layer and a second mask layer stacked sequentially; A patterned first photoresist layer is formed on the surface of the second mask layer. Using the patterned first photoresist layer as a mask, the second mask layer and the first mask layer are sequentially etched to form a groove on the first mask layer. Remove the patterned first photoresist layer and the second mask layer to form a sidewall on the sidewall of the groove; A third mask layer and a patterned second photoresist layer are sequentially stacked on the surface of the first mask layer. The patterned second photoresist layer includes at least one photoresist strip, which at least partially exposes the surface of the third mask layer corresponding to the groove. Using the patterned second photoresist layer as a mask, the third mask layer, the first mask layer, and the polysilicon layer are sequentially subjected to a second etching process to obtain the semiconductor structure.

[0006] In one embodiment of the present invention, a sidewall is formed on the sidewall of the groove, comprising: A sidewall material is deposited within the groove, the sidewall material covering the first mask layer and the groove; Remove the sidewall material in the horizontal direction to form the sidewall on the sidewall of the groove.

[0007] In one embodiment of the present invention, when removing the sidewall material in the horizontal direction and forming the sidewall on the sidewall of the groove, dry etching or wet etching is used.

[0008] In one embodiment of the present invention, when forming the sidewall on the sidewall of the groove, the process includes multiple depositions of the sidewall material and removal of the sidewall material in the horizontal direction.

[0009] In one embodiment of the present invention, the first mask layer includes a nitride layer and an oxide layer, wherein the nitride layer is formed on the surface of the polysilicon layer and the oxide layer is formed on the surface of the nitride layer.

[0010] In one embodiment of the present invention, the second mask layer includes a first organic dielectric layer and a first silicon-oxygen hard mask intermediate layer structure layer, wherein the first organic dielectric layer is formed on the surface of the first mask layer and the first silicon-oxygen hard mask intermediate layer structure layer is formed on the surface of the first organic dielectric layer.

[0011] In one embodiment of the present invention, the third mask layer includes a second organic dielectric layer and a second silicon-oxygen hard mask intermediate layer structure layer, wherein the second organic dielectric layer is formed on the surface of the first mask layer and the second silicon-oxygen hard mask intermediate layer structure layer is formed on the surface of the second organic dielectric layer.

[0012] In one embodiment of the present invention, the substrate includes a substrate and a dielectric layer formed on the surface of the substrate, the dielectric layer including a high dielectric constant material layer and a protective layer formed on the high dielectric constant material layer.

[0013] In one embodiment of the present invention, after the first etching process, the preparation method further includes a first cleaning process for the initial semiconductor structure.

[0014] In one embodiment of the present invention, after the second etching process, the preparation method further includes a second cleaning process for the initial semiconductor structure.

[0015] The beneficial effects of this invention are as follows: The method for fabricating a semiconductor structure proposed in this invention involves sequentially etching a second mask layer and a first mask layer using a patterned first photoresist layer as a mask. A groove is formed on the first mask layer, and a sidewall is formed on the sidewall of the groove. A third mask layer and a patterned second photoresist layer are formed on the surface of the first mask layer and the sidewall. Using the patterned second photoresist layer as a mask, a second etching process is sequentially performed on the third mask layer, the first mask layer, and the polysilicon layer. An unexpected effect of this invention is that by forming a sidewall on the sidewall of the groove, the opening of the groove can be prevented from further expanding during the second etching process. This not only improves etching accuracy but also increases the process window during the first etching process. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] In the attached diagram: Figure 1 This is a flowchart illustrating the fabrication process of a semiconductor structure according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the initial semiconductor structure provided in one embodiment of the present invention; Figure 3 for Figure 2 A top view of the first photoresist layer forming the pattern; Figure 4 for Figure 3 The AA-directed face diagram; Figure 5 This is a top view schematic diagram of the groove formation provided in one embodiment of the present invention; Figure 6 yes Figure 5 A cross-sectional view along the BB direction; Figure 7 This is a top view schematic diagram of the formation of sidewall material provided in one embodiment of the present invention; Figure 8 yes Figure 7 A cross-sectional view along the CC direction; Figure 9 This is a top view schematic diagram of the formation of a sidewall provided in one embodiment of the present invention; Figure 10 yes Figure 9 A cross-sectional view along the DD direction; Figure 11 This is a top view schematic diagram of the formation of a third mask layer and a patterned second photoresist layer provided in one embodiment of the present invention; Figure 12 yes Figure 11 EE-direction cross-sectional view; Figure 13 This is a top view schematic diagram of the second etching process provided in one embodiment of the present invention; Figure 14 yes Figure 13 A cross-sectional view along the FF direction.

[0018] The attached figures are labeled as follows: 10. Semiconductor initial structure; 100. Substrate; 110. Substrate; 120. Dielectric layer; 200. Polysilicon layer; 300. First mask layer; 310. Groove; 320. Sidewall; 321. Sidewall material; 330. Nitride layer; 340. Oxide layer; 400. Second mask layer; 410. First organic dielectric layer; 420. First silicon-oxygen hard mask intermediate layer structure layer; 500. Patterned first photoresist layer; 600. Third mask layer; 610. Second organic dielectric layer; 620. Second silicon-oxygen hard mask intermediate layer structure layer; 700. Patterned second photoresist layer; 710. Photoresist strip. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0020] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0021] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0022] In this document, when referring to numerical ranges, unless otherwise specified, the distribution of selectable values ​​within a numerical range is considered continuous, including the two endpoints of the range (i.e., the minimum and maximum values), and every value between these two endpoints. When multiple numerical ranges are provided to describe a feature or property, these numerical ranges can be combined.

[0023] In existing technologies, the dual patterning etching process for polysilicon at the 28nm technology node includes two process paths: Cut First and Cut Last. For the Cut First process, a first-stage patterning defines the cut opening, and a second-stage patterning further forms the line end. However, in actual manufacturing, the sidewalls of the cut opening defined in the first-stage patterning undergo additional etching during the second-stage patterning process, resulting in enlargement. This enlargement effect is difficult to control precisely. This process defect directly leads to an abnormally large critical dimension of the final line end, accompanied by significant degradation in dimensional uniformity. Therefore, this invention provides a semiconductor structure fabrication method that prevents the cut opening defined in the first-stage patterning from further enlarging during the second etching process, thereby improving the accuracy and dimensional stability of the final line end.

[0024] Please see Figures 1 to 14 As shown, the present invention provides a method for preparing a semiconductor structure, comprising the following steps: S1, providing such Figure 2 The semiconductor initial structure 10 shown includes a substrate 100, a polysilicon layer 200, a first mask layer 300, and a second mask layer 400 stacked sequentially. S2, such as Figures 3 to 6 As shown, a patterned first photoresist layer 500 is formed on the surface of the second mask layer 400. Using the patterned first photoresist layer 500 as a mask, the second mask layer 400 and the first mask layer 300 are sequentially etched to form a groove 310 on the first mask layer 300. S3, such as Figures 7 to 10 As shown, the patterned first photoresist layer 500 and second mask layer 400 are removed, and a sidewall 320 is formed on the sidewall of the groove 310. S4, such as Figure 11 and Figure 12 As shown, a third mask layer 600 and a patterned second photoresist layer 700 are sequentially stacked on the surface of the first mask layer 300. The patterned second photoresist layer 700 includes at least one photoresist strip 710, and the photoresist strip 710 at least partially exposes the surface of the third mask layer 600 corresponding to the groove 310. S5, such as Figure 13 and Figure 14As shown, using the patterned second photoresist layer 700 as a mask, the third mask layer 600, the first mask layer 300, and the polysilicon layer 200 are sequentially etched to obtain the following... Figure 13 and Figure 14 The semiconductor structure shown.

[0025] Please see Figure 2 As shown, in step S1 of the present invention, the substrate 100 includes a substrate 110 and a dielectric layer 120 formed on the surface of the substrate 110. Exemplarily, the dielectric layer 120 includes a high-dielectric-constant material layer and a protective layer formed on the high-dielectric-constant material layer. In other embodiments, the substrate 100 may also include other structures, which can be flexibly adjusted according to requirements. The substrate 110 can be any material suitable for forming a semiconductor structure, such as undoped single-crystal silicon, impurity-doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. The present invention does not limit the specific material and thickness of the substrate 110, and the substrate 110 can be a P-doped semiconductor substrate or an N-doped semiconductor substrate; the doping type of the impurity can be flexibly set according to the semiconductor structure to be formed. In this embodiment, the substrate 110 is, for example, a silicon substrate.

[0026] In one embodiment, the substrate 100 is fabricated on the basis of the substrate 110, and the fabrication method of the substrate 100 is as follows: Please see Figure 2As shown, in one embodiment of the present invention, a dielectric layer 120 is formed on a substrate 110. Specifically, a high-dielectric-constant material layer is first formed on the surface of the substrate 110. This high-dielectric-constant material layer effectively protects the surface of the substrate 110, preventing the silicon atoms on the surface of the substrate 110 from being eroded or damaged during subsequent process steps. This maintains the integrity and cleanliness of the substrate 110 surface, ensuring a stable and high-quality silicon-dielectric interface can be formed during the subsequent growth of the gate dielectric layer. This, in turn, ensures that key electrical characteristics such as carrier mobility and threshold voltage in the device channel region meet design requirements. Simultaneously, the high-dielectric-constant material layer, as a occupant structure for the gate dielectric region, can reserve the necessary thickness space for the subsequent gate dielectric layer, ensuring that the thickness consistency and interface state of the gate dielectric meet device design specifications and electrical performance indicators during subsequent gate dielectric replacement. The high-dielectric-constant material layer can be, for example, an HfO2-based material. Its high-dielectric-constant characteristics can effectively reduce gate leakage current and improve the switching characteristics and long-term operational reliability of the device after subsequent true gate replacement. The high dielectric constant material layer is, for example, an HfO2 layer, or it is deposited on the surface of substrate 110 by atomic layer deposition (ALD). By alternately introducing Hf source (such as tetrakis(dimethylamino)hafnium) and O source (such as ozone), atomic-level deposition is performed on the surface of substrate 110 to ensure the uniformity of the thickness of the high dielectric constant material layer, the step coverage and the interface quality, so as to meet the device design requirements.

[0027] After forming a high dielectric constant material layer, a protective layer is formed on the surface of the high dielectric constant material layer. The material of the protective layer is, for example, titanium nitride (TiN), and it is formed, for example, by physical vapor deposition (PVD) or chemical vapor deposition (CVD). Exemplarily, the protective layer is prepared by physical vapor deposition, using a Ti target as the sputtering source, and in an inert gas atmosphere (such as Ar), Ti atoms are deposited on the surface of the high dielectric constant material layer by plasma sputtering, while N2 or NH3 is introduced to react and form a dense and uniform TiN layer. The thickness of the protective layer is controlled by controlling the deposition time so that the thickness and resistivity of the protective layer meet the process requirements. Due to the excellent etching selectivity between the titanium nitride layer and the high-k dielectric material layer and substrate 110, as well as its good mechanical strength, the critical gate dimensions (especially the gate length CD) can be precisely defined during the gate etching process. This ensures that the gate line morphology is regular and the dimensional accuracy meets the device design requirements, effectively avoiding process defects such as over-etching, under-etching, line deformation, or collapse during the etching process. Simultaneously, it provides protection against damage to the underlying high-k dielectric material layer and the interface between the substrate 110 and the high-k dielectric material layer caused by plasma, high-temperature environments, and chemical reagents during subsequent source / drain etching, source / drain epitaxial growth, and high-temperature annealing processes. This maintains the structural integrity and interface stability of the high-k dielectric material layer, ensuring the smooth implementation of subsequent true gate replacement processes. Furthermore, TiN material possesses excellent selective etching characteristics, allowing for complete removal through specific wet or dry etching processes without damaging the high-k dielectric material layer and substrate 110. This facilitates the complete removal of the dummy gate, creating favorable conditions for subsequent metal gate deposition and filling.

[0028] In some embodiments, before forming the dielectric layer 120 on the substrate 110, a cleaning process is further included for the substrate 110. By cleaning the substrate 110, impurities present on the surface of the substrate 110 can be removed, preventing impurities from affecting subsequent processes and thus ensuring device performance. For example, a cleaning solution can be used to clean the substrate 110, or a gas such as nitrogen can be used to purge the substrate 110 to achieve cleaning.

[0029] Please see Figure 2As shown, in one embodiment of the present invention, after forming a protective layer, a polycrystalline silicon layer 200 is formed on the surface of the protective layer. In this embodiment, the polycrystalline silicon layer 200 is deposited, for example, by any one of the processes such as low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or plasma-enhanced chemical vapor deposition. For example, the polycrystalline silicon layer 200 is deposited by low-pressure chemical vapor deposition, and the reaction gas includes silane (SiH4) or disilane (Si2H6). During the formation of the polycrystalline silicon layer 200, in order to improve the uniformity of the formed polycrystalline silicon layer 200, N2 can also be added to the reaction gas, and the thickness of the polycrystalline silicon layer 200 can be controlled by adjusting the reaction time.

[0030] Please see Figure 2 As shown, in one embodiment of the present invention, after forming a polysilicon layer 200, a first mask layer 300 is formed on the surface of the polysilicon layer 200. Exemplarily, the first mask layer 300 includes a nitride layer 330 and an oxide layer 340. The nitride layer 330 is formed on the surface of the polysilicon layer 200, and the oxide layer 340 is formed on the surface of the nitride layer 330. The nitride layer 330 can be prepared by any one of low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma-enhanced chemical vapor deposition. Exemplarily, when preparing the nitride layer 330 using a low-pressure chemical vapor deposition process, silicon nitride can be generated by reacting ammonia with dichlorosilane. The oxide layer 340 can be made of materials such as silicon dioxide, and the oxide layer 340 can be formed using a deposition process, such as at least one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

[0031] Please see Figure 2As shown, in one embodiment of the present invention, after forming the oxide layer 340, a second mask layer 400 is formed on the surface of the oxide layer 340. Exemplarily, the second mask layer 400 includes a first organic dielectric layer (ODL) 410 and a first silicon-oxygen-based hard mask (SHB) intermediate layer structure layer 420. The first organic dielectric layer 410 is formed on the surface of the oxide layer 340, and the first silicon-oxygen-based hard mask intermediate layer structure layer 420 is formed on the surface of the first organic dielectric layer 410. When forming the first organic dielectric layer 410, an organic dielectric material is coated on the surface of the oxide layer 340, and then the coated organic dielectric material is baked to form the first organic dielectric layer 410 on the surface of the oxide layer 340. The baking process can make the first organic dielectric layer 410 more dense, have better plasma resistance, reduce the lateral etching rate of the first organic dielectric layer 410, and reduce the outward expansion of the opening of the first organic dielectric layer 410. When the first mask layer 300 below the first organic dielectric layer 410 is subsequently etched to form the groove 310, it is beneficial to reduce the outward expansion of the opening of the groove 310, effectively control the opening size of the groove 310, and improve the etching accuracy of the groove 310. The first organic dielectric layer 410 is, for example, a carbon coating (Spin-On-Carbon, SOC), which is a polymer with high carbon content. In some embodiments, in order to improve the flatness of the first organic dielectric layer 410, the surface of the first organic dielectric layer 410 is planarized by a chemical mechanical polishing (CMP) process. After the first organic dielectric layer 410 is formed, a first silicon-oxygenated hard mask intermediate layer structure layer 420 is formed on the surface of the first organic dielectric layer 410. The first silicon-oxygenated hard mask intermediate layer structure layer 420 is formed, for example, by any one of the processes such as physical vapor deposition, spin coating, and plasma-enhanced chemical vapor deposition. The material of the first silicon-oxygenated hard mask intermediate layer structure layer 420 is, for example, a silicon-containing organic polymer or polysilane.

[0032] Please see Figure 3 and Figure 4 As shown, in step S2 of the present invention, after forming the first silicon-oxygen hard mask intermediate layer structure layer 420, a patterned first photoresist layer 500 is formed on the surface of the first silicon-oxygen hard mask intermediate layer structure layer 420. Specifically, a first photoresist material is coated on the surface of the first silicon-oxygen hard mask intermediate layer structure layer 420. The type of the first photoresist material is not limited; it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, a photolithography process such as mask exposure and development is performed to form a patterned first photoresist layer 500. The patterned first photoresist layer 500 exposes the surface of the first silicon-oxygen hard mask intermediate layer structure layer 420 corresponding to the groove 310. Figure 4 The uncovered area of ​​the first photoresist layer 500 in the patterned middle layer).

[0033] Please see Figure 5 and Figure 6 As shown, in one embodiment of the present invention, using a patterned first photoresist layer 500 as a mask, a first etching process is performed sequentially on a second mask layer 400 and a first mask layer 300 to form a groove 310 on the first mask layer 300. In this embodiment, the groove 310 is formed within an oxide layer 340, and the depth of the groove 310 is, for example, less than the thickness of the oxide layer 340 consumed during the second etching process, to ensure that the sidewalls 320 are removed during the second etching process. The opening of the groove 310 corresponds to the notch etching area of ​​the subsequent polysilicon layer 200.

[0034] For example, dry etching is used to sequentially etch the second mask layer 400 and the first mask layer 300. Using a patterned first photoresist layer 500 as a mask, sequentially etching the second mask layer 400 and the first mask layer 300 enables the sequential transfer of patterns on the patterned first photoresist layer 500. The critical dimensions of the openings in the patterned first organic dielectric layer 410 remain the same as the critical dimensions of the openings in the patterned first photoresist layer 500, corresponding to the opening pattern of the groove 310 in the first mask layer 300. The multilayer film structure, formed by the patterned first photoresist layer 500, the first silicon-oxygen hard mask intermediate layer structure 420, and the first organic dielectric layer 410, is transferred to the first mask layer 300. The multilayer film structure sequentially transfers patterns and dimensions, improving the resolution and fidelity of the opening pattern. Precise control of the critical dimensions of the opening pattern corresponding to the groove 310 is achieved, thus enabling precise control of the critical dimensions of the opening of the groove 310. After the first etching process, the fabrication method further includes a first cleaning process for the initial semiconductor structure 10 to remove etching byproducts.

[0035] Please see Figures 7 to 10As shown, in step S3 of the present invention, after forming the groove 310, the patterned first photoresist layer 500, the first silicon-oxygen hard mask intermediate layer structure layer 420, and the first organic dielectric layer 410 are removed sequentially, forming a sidewall 320 on the sidewall of the groove 310. Specifically, when forming the sidewall 320 on the sidewall of the groove 310, a sidewall material 321 is first deposited in the groove 310, covering the surface of the first mask layer 300 and the surface of the groove 310. Then, the horizontal sidewall material 321 is removed, forming the sidewall 320 on the sidewall of the groove 310. The sidewall 320 is flush with the surface of the oxide layer 340, for example. The sidewall material 321 can be deposited using any one of the following processes: low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma-enhanced chemical vapor deposition. In this embodiment, the sidewall material 321 is deposited, for example, by atmospheric pressure chemical vapor deposition. The sidewall material 321 is, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), etc. In this embodiment, the sidewall material 321 is, for example, silicon nitride. To improve the accuracy of the sidewall 320, the sidewall 320 can be formed on the sidewall of the groove 310 by repeating the deposition-etching steps. For example, sidewall material 321 is deposited covering the surface of the first mask layer 300 and the surface of the groove 310. The horizontal sidewall material 321 is removed, forming a first sub-sidewall in the groove 310. The sidewall material 321 is deposited repeatedly, covering the surface of the first mask layer 300, the surface of the groove 310, and the surface of the first sub-sidewall. The horizontal sidewall material 321 is removed, forming a second sub-sidewall on the surface of the first sub-sidewall. This process is repeated until the thickness of the sidewall 320 reaches the desired thickness. The thickness of the sidewall 320 can be adjusted according to actual needs, ensuring that it is removed precisely at the end of the second etching process. Since the sidewalls 320 are consumed simultaneously during the second etching process, there is no need to consider the removal of the sidewalls 320 separately. When removing the horizontal sidewall material 321, methods such as dry etching, wet etching, or a combination of both can be used. In this embodiment, dry etching is used to remove the horizontal sidewall material 321.

[0036] Please see Figure 11 and Figure 12As shown, in step S4 of the present invention, after forming a sidewall 320 on the sidewall of the groove 310, a third mask layer 600 is formed on the surface of the first mask layer 300 and the surface of the sidewall 320. Exemplarily, the third mask layer 600 includes a second organic dielectric layer 610 and a second silicon-oxygen hard mask intermediate layer structure layer 620. The second organic dielectric layer 610 is formed on the surfaces of the first mask layer 300 and the sidewall 320, filling the groove 310. The second silicon-oxygen hard mask intermediate layer structure layer 620 is formed on the surface of the second organic dielectric layer 610. When forming the second organic dielectric layer 610, an organic dielectric material is coated on the surface of the oxide layer 340, and then the coated organic dielectric material is baked to form the second organic dielectric layer 610 on the surface of the oxide layer 340. Baking can make the second organic dielectric layer 610 denser and improve its plasma resistance, reducing the lateral etching rate of the second organic dielectric layer 610. This effectively improves the etching accuracy when etching the first mask layer 300 and polysilicon layer 200 below the patterned second organic dielectric layer 610. The second organic dielectric layer 610 is, for example, a carbon coating (Spin-On-Carbon, SOC), which is a polymer with high carbon content. In some embodiments, to improve the flatness of the second organic dielectric layer 610, the surface of the second organic dielectric layer 610 is planarized by a chemical mechanical polishing (CMP) process. After forming the second organic dielectric layer 610, a second silicon-oxygenated hard mask intermediate layer structure layer 620 is formed on the surface of the second organic dielectric layer 610. The second silicon-oxygenated hard mask intermediate layer structure layer 620 is formed, for example, by any one of the processes such as physical vapor deposition, spin coating, and plasma-enhanced chemical vapor deposition. The material of the second siloxane hard mask intermediate layer 620 is, for example, a silicon-containing organic polymer or a polysilane.

[0037] Please see Figure 11 and Figure 12As shown, in one embodiment of the present invention, after forming the second silicon-oxygen hard mask intermediate layer structure layer 620, a patterned second photoresist layer 700 is formed on the surface of the second silicon-oxygen hard mask intermediate layer structure layer 620. Specifically, a second photoresist material is coated on the surface of the second silicon-oxygen hard mask intermediate layer structure layer 620. The type of second photoresist material is not limited; it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, the patterned second photoresist layer 700 is formed by photolithography processes such as mask exposure and development. The patterned second photoresist layer 700 includes at least one photoresist strip 710. This application does not limit the number of photoresist strips 710 and can set them according to actual needs. When there are multiple photoresist strips 710, the multiple photoresist strips 710 are arranged in parallel and spaced apart, and the patterned second photoresist layer 700 corresponds to the linear etching region on the polysilicon layer 200. The photoresist strip 710 at least partially exposes the surface of the third mask layer 600 corresponding to the groove 310, that is, the photoresist strip 710 partially exposes the surface of the third mask layer 600 corresponding to the groove 310, or the photoresist strip 710 fully exposes the surface of the third mask layer 600 corresponding to the groove 310. For example, in this embodiment, the photoresist strip 710, for example, partially exposes the surface of the third mask layer 600 corresponding to the groove 310; or, for example, the photoresist strip 710 extends along the width direction of the groove 310, the width of the photoresist strip 710 is less than the length of the groove 310, and both sides of the photoresist strip 710 expose the sidewalls of the groove 310. Figure 11 The structure between the two rectangular frames is the side wall 320.

[0038] Please see Figure 13 and Figure 14As shown, in step S5 of this invention, after forming the patterned second photoresist layer 700, the patterned second photoresist layer 700 is used as a mask to sequentially perform a second etching process on the third mask layer 600, the first mask layer 300, and the polysilicon layer 200. Specifically, using the patterned second photoresist layer 700 as a mask, the pattern of the patterned second photoresist layer 700 is transferred to the second mask layer 400 through the third mask layer 600. When the linear etching depth on the polysilicon layer 200 is the same as the notch etching depth corresponding to the groove 310, the patterned second photoresist layer 700, the second silicon-oxygen hard mask intermediate layer structure layer 620, and the second organic dielectric layer 610 are sequentially removed to expose the linear etching region and the notch etching region of the polysilicon layer 200. The selectivity of the etching gas is adjusted, and the polysilicon layer 200 is etched further. In this embodiment, the second etching process extends to the surface of the substrate 110. During the second etching process, the sidewalls 320 can protect the sidewalls of the oxide layer 340, preventing the opening of the groove 310 from further expanding during the second etching process. This not only helps to improve etching accuracy but also helps to increase the process window during the first etching process. After the second etching process, the fabrication method also includes a second cleaning process for the initial semiconductor structure 10 to remove etching byproducts.

[0039] In summary, the semiconductor structure fabrication method proposed in this invention involves sequentially etching a second mask layer and a first mask layer using a patterned first photoresist layer as a mask. A groove is formed on the first mask layer, and sidewalls are formed on the sidewalls of the groove. A third mask layer and a patterned second photoresist layer are formed on the surfaces of the first mask layer and the sidewalls. A second etching process is then performed sequentially on the third mask layer, the first mask layer, and the polysilicon layer using the patterned second photoresist layer as a mask. An unexpected benefit of this invention is that by forming sidewalls on the sidewalls of the groove, the opening of the groove can be prevented from further expanding during the second etching process. This not only improves etching accuracy but also increases the process window during the first etching process.

[0040] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor initial structure is provided, the semiconductor initial structure comprising a substrate, a polysilicon layer, a first mask layer and a second mask layer stacked sequentially; A patterned first photoresist layer is formed on the surface of the second mask layer. Using the patterned first photoresist layer as a mask, the second mask layer and the first mask layer are sequentially etched to form a groove on the first mask layer. Remove the patterned first photoresist layer and the second mask layer to form a sidewall on the sidewall of the groove; A third mask layer and a patterned second photoresist layer are sequentially stacked on the surface of the first mask layer. The patterned second photoresist layer includes at least one photoresist strip, which at least partially exposes the surface of the third mask layer corresponding to the groove. Using the patterned second photoresist layer as a mask, the third mask layer, the first mask layer, and the polysilicon layer are sequentially subjected to a second etching process to obtain the semiconductor structure.

2. The preparation method according to claim 1, characterized in that, A sidewall is formed on the sidewall of the groove, comprising: A sidewall material is deposited within the groove, the sidewall material covering the first mask layer and the groove; Remove the sidewall material in the horizontal direction to form the sidewall on the sidewall of the groove.

3. The preparation method according to claim 2, characterized in that, When removing the sidewall material in the horizontal direction to form a sidewall on the sidewall of the groove, dry etching or wet etching is used.

4. The preparation method according to claim 2, characterized in that, When forming the sidewall on the sidewall of the groove, the process includes multiple depositions of the sidewall material and removal of the sidewall material in the horizontal direction.

5. The preparation method according to claim 1, characterized in that, The first mask layer includes a nitride layer and an oxide layer, wherein the nitride layer is formed on the surface of the polysilicon layer and the oxide layer is formed on the surface of the nitride layer.

6. The preparation method according to claim 1, characterized in that, The second mask layer includes a first organic dielectric layer and a first silicon-oxygen hard mask intermediate layer structure layer, wherein the first organic dielectric layer is formed on the surface of the first mask layer and the first silicon-oxygen hard mask intermediate layer structure layer is formed on the surface of the first organic dielectric layer.

7. The preparation method according to claim 1, characterized in that, The third mask layer includes a second organic dielectric layer and a second silicon-oxygen hard mask intermediate layer structure layer, wherein the second organic dielectric layer is formed on the surface of the first mask layer and the second silicon-oxygen hard mask intermediate layer structure layer is formed on the surface of the second organic dielectric layer.

8. The preparation method according to claim 1, characterized in that, The substrate includes a substrate and a dielectric layer formed on the surface of the substrate, the dielectric layer including a high dielectric constant material layer and a protective layer formed on the high dielectric constant material layer.

9. The preparation method according to claim 1, characterized in that, After the first etching process, the fabrication method further includes a first cleaning process for the initial semiconductor structure.

10. The preparation method according to claim 1, characterized in that, After the second etching process, the fabrication method further includes a second cleaning process for the initial semiconductor structure.

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