Surge peak sampling circuit

Abstract

The surge peak sampling circuit comprises a voltage division circuit, a main circuit and a sampler, the two ends of the voltage division circuit are connected with the positive electrode and the negative electrode of a power source, the voltage division output end is connected to the input end of the main circuit, and the output end of the main circuit is connected to the sampler. The main circuit comprises a first comparator, a second comparator, an energy storage capacitor, a first diode, an eighth resistor and a tenth resistor, the inverting input end of the first comparator is connected to the voltage division output end of the voltage division circuit, the non-inverting input end of the first comparator is connected to the output end of the second comparator through the tenth resistor, and the output end of the first comparator is connected to the positive electrode of the first diode; the negative electrode of the first diode is connected to the first end of the eighth resistor and the positive phase input end of the second comparator, the second end of the eighth resistor is connected to the first end of the first capacitor, the second end of the first capacitor is grounded, the negative phase input end of the second comparator is connected to the output end of the second comparator, and the output end of the second comparator is connected to the sampler. Compared with the prior art, the surge protection circuit has the advantages that a common high-speed sampling chip can be used for capturing the peak voltage of the surge, and the like.

Description

Technical Field

[0001] This invention relates to the field of surge protection, and in particular to a surge peak sampling circuit. Background Technology

[0002] While traditional surge protectors also have surge detection capabilities, most only detect the presence of a surge. For example, Chinese patent CN105990824A discloses a surge protection circuit, including a first voltage divider circuit composed of resistors and capacitors, a rectifier circuit for rectifying mains power, and a control circuit for surge protection. The control circuit includes a first comparator. The input terminal of the first voltage divider circuit is connected to the output terminal of the rectifier circuit, and the output terminal of the first voltage divider circuit is connected to the first input terminal of the first comparator. The second input terminal of the first comparator is connected to a preset first standard power supply. When the mains voltage is less than the first preset value, if a positive surge exists, the voltage at the output terminal of the first voltage divider circuit is greater than the voltage of the first standard power supply; if no positive surge exists, the voltage at the output terminal of the first voltage divider circuit is less than the voltage of the first standard power supply. The control circuit performs surge protection control based on the output level of the first comparator.

[0003] However, surge protection circuits, including the aforementioned Chinese patent CN105990824A, do not have the ability to detect surge peak values.

[0004] In response, some existing technologies attempt to use high-speed sampling chips to sample peak voltages, but these existing technologies generally suffer from the following drawbacks:

[0005] 1. The peak voltage exists for a very short time. If the peak voltage needs to be sampled accurately, the sampling chip needs to have an extremely fast sampling speed. Conventional high-speed sampling chips cannot meet this requirement. Chips that can meet this requirement are monopolized by a few or even a single company, resulting in extremely high costs.

[0006] 2. During high-speed sampling, the sampling chip receives sampling points of each phase in a single surge waveform. Although a threshold is set in software to filter out values ​​below the safe threshold, the voltage value of the surge is generally much higher than this threshold. Therefore, the voltage of most sampling points in one cycle will exceed this threshold, and the sampling chip will collect a large amount of data, which puts a lot of pressure on the subsequent data processing and also increases the overall cost.

[0007] 3. The overall circuit design is relatively complex and the size is relatively large. Summary of the Invention

[0008] The purpose of this invention is to provide a sampling circuit for surge peak values.

[0009] The objective of this invention can be achieved through the following technical solutions:

[0010] A surge peak sampling circuit includes a voltage divider circuit, a main circuit, and a sampler. The two ends of the voltage divider circuit are connected to the positive and negative terminals of a power supply, and the voltage divider output terminal is connected to the input terminal of the main circuit. The output terminal of the main circuit is connected to the sampler. The main circuit includes a first comparator, a second comparator, an energy storage capacitor, a first diode, an eighth resistor, and a tenth resistor. The inverting input terminal of the first comparator is connected to the voltage divider output terminal of the voltage divider circuit, and the non-inverting input terminal is connected to the output terminal of the second comparator through the tenth resistor. The output terminal is connected to the anode of the first diode. The cathode of the first diode is connected to the first terminal of the eighth resistor and the non-inverting input terminal of the second comparator. The second terminal of the eighth resistor is connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is grounded. The inverting input terminal of the second comparator is connected to the output terminal of the second comparator, and the output terminal of the second comparator is connected to the sampler.

[0011] The main circuit also includes a second diode, the positive terminal of which is connected to the inverting input terminal of the first comparator, and the negative terminal of which is connected to the output terminal of the first comparator.

[0012] The main circuit also includes a ninth resistor and a reset transistor. The ninth resistor is grounded through the collector and emitter of the reset transistor, and the base of the reset transistor is used to receive a reset signal.

[0013] The reset transistor is an NPN transistor, with its collector connected to the ninth resistor and its emitter grounded.

[0014] The main circuit also includes an eleventh resistor, one end of which is connected to the output of the second comparator and the other end is grounded.

[0015] The voltage divider circuit includes a first voltage divider module, a second voltage divider module, and a third voltage divider module connected in series. The connection between the first voltage divider module and the second voltage divider module serves as the first voltage divider output terminal, and the connection between the second voltage divider module and the third voltage divider module serves as the second voltage divider output terminal.

[0016] The first voltage divider module includes a first resistor, a second resistor, and a third resistor connected in series.

[0017] The second voltage divider module includes a fourth resistor, a fifth resistor, and a sixth resistor connected in series.

[0018] The voltage divider circuit further includes a first clamping diode and a second clamping diode. The positive terminal of the first clamping diode is connected to the negative terminal of the power supply, and the negative terminal is connected to the positive terminal of the second clamping diode, as well as the connection point of the fifth resistor and the sixth resistor. The negative terminal of the second clamping diode is connected to the positive terminal of the first DC power supply.

[0019] The third voltage divider module includes a seventh resistor.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. Rectification is achieved through an active rectifier composed of a first comparator and a first diode. Based on the first and second comparators and combined with a first capacitor, peak voltage can be latched while non-peak voltage is filtered. On the one hand, by latching, the existence time of peak voltage is extended, thereby reducing the requirements of the sampling chip of the back-end sampler, so that ordinary high-speed sampling chips can also achieve accurate acquisition of peak voltage. On the other hand, a large number of non-peak voltages can be filtered, and when multiple surges exist at the same time, non-maximum peak voltages can be filtered to avoid the sampler receiving a large amount of invalid data, thereby reducing the overall cost. In addition, the overall circuit design has fewer components and a smaller size.

[0022] 2. The second diode acts as a clamping device to prevent the first comparator from entering the saturation region and shorten the transition time of the detection circuit from the hold state to the tracking state.

[0023] 3. By designing the ninth resistor and the reset transistor, the peak voltage held on the first capacitor can be discharged, thereby achieving a reset.

[0024] 4. By designing a two-stage voltage divider output, the measurement range can be increased without changing the withstand voltage capability.

[0025] 5. By setting a first clamping diode and a second clamping diode, if the voltage between the fifth resistor and the sixth resistor exceeds the reference voltage, it will be clamped to the reference voltage by the first clamping diode and the second clamping diode, thereby protecting the core circuit. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of the present invention;

[0027] Figure 2 This is a schematic diagram of a voltage divider circuit;

[0028] Figure 3 A schematic diagram of the main circuit section;

[0029] The circuit consists of: 1. Voltage divider circuit; 2. Main circuit; 3. Sampler; U1. First comparator; U2. Second comparator; E. First DC power supply; D1. First diode; D2. Second diode; D3. First clamping diode; D4. Second clamping diode; C1. First capacitor; R1. First resistor; R2. Second resistor; R3. Third resistor; R4. Fourth resistor; R5. Fifth resistor; R6. Sixth resistor; R7. Seventh resistor; R8. Eighth resistor; R9. Ninth resistor; R10. Tenth resistor; R11. Eleventh resistor; Q1. Reset transistor. Detailed Implementation

[0030] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0031] A surge peak sampling circuit, such as Figure 1 As shown, it includes a voltage divider circuit 1, a main circuit 2, and a sampler 3, as follows: Figure 2 As shown, the two ends of voltage divider circuit 1 are connected to the positive and negative terminals of the power supply, the output terminal of voltage divider circuit 1 is connected to the input terminal of main circuit 2, and the output terminal of main circuit 2 is connected to sampler 3, as shown. Figure 3 As shown, the main circuit 2 includes a first comparator U1, a second comparator U2, an energy storage capacitor, a first diode D1, an eighth resistor R8, and a tenth resistor R10. The inverting input of the first comparator U1 is connected to the voltage divider output of the voltage divider circuit 1, and the non-inverting input is connected to the output of the second comparator U2 through the tenth resistor R10. The output is connected to the positive terminal of the first diode D1. The negative terminal of the first diode D1 is connected to the first terminal of the eighth resistor R8 and the non-inverting input of the second comparator U2. The second terminal of the eighth resistor R8 is connected to the first terminal of the first capacitor C1, and the second terminal of the first capacitor C1 is grounded. The inverting input of the second comparator U2 is connected to the output of the second comparator U2, and the output of the second comparator U2 is connected to the sampler 3.

[0032] Rectification is achieved through an active rectifier composed of the first comparator U1 and the first diode D1. Based on the first comparator U1 and the second comparator U2, and combined with the first capacitor C1, the peak voltage can be latched while filtering non-peak voltages. On the one hand, by latching, the existence time of the peak voltage is extended, thereby reducing the requirements of the sampling chip of the back-end sampler 3, so that ordinary high-speed sampling chips can also achieve accurate acquisition of peak voltage. On the other hand, a large number of non-peak voltages can be filtered, and when multiple surges exist at the same time, non-maximum peak voltages can be filtered to avoid the sampler 3 receiving a large amount of invalid data, thereby reducing the overall cost. In addition, the overall circuit design has fewer components and a smaller size.

[0033] In addition, the main circuit 2 also includes a second diode D2. The positive terminal of the second diode D2 is connected to the inverting input terminal of the first comparator U1, and the negative terminal is connected to the output terminal of the first comparator U1. The second diode D2 acts as a clamp to prevent the first comparator U1 from entering the saturation region and shorten the transition time of the detection circuit from the holding state to the tracking state.

[0034] In most embodiments, the main circuit 2 also includes a ninth resistor R9 and a reset transistor Q1. The ninth resistor R9 is grounded through the collector and emitter of the reset transistor Q1, and the base of the reset transistor Q1 is used to receive the reset signal. By designing the ninth resistor R9 and the reset transistor Q1, the peak voltage held on the first capacitor C1 can be discharged, thereby realizing the reset.

[0035] In this embodiment, the reset transistor Q1 is an NPN transistor, with its collector connected to the ninth resistor R9 and its emitter grounded.

[0036] In addition, the main circuit 2 also includes an eleventh resistor R11, one end of which is connected to the output of the second comparator U2, and the other end is grounded.

[0037] like Figure 2 As shown, the voltage divider circuit 1 includes a first voltage divider module, a second voltage divider module, and a third voltage divider module connected in series. The connection between the first voltage divider module and the second voltage divider module serves as the first voltage divider output terminal, and the connection between the second voltage divider module and the third voltage divider module serves as the second voltage divider output terminal. By designing a two-stage voltage divider output, the measurement range can be increased without changing the withstand voltage capability.

[0038] The first voltage divider module includes a first resistor R1, a second resistor R2, and a third resistor R3 connected in series.

[0039] The second voltage divider module includes a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6 connected in series.

[0040] The voltage divider circuit 1 also includes a first clamping diode D3 and a second clamping diode D4. The positive terminal of the first clamping diode D3 is connected to the negative terminal of the power supply, and the negative terminal is connected to the positive terminal of the second clamping diode D4, as well as the connection point of the fifth resistor R5 and the sixth resistor R6. The negative terminal of the second clamping diode D4 is connected to the positive terminal of the first DC power supply E. By setting the first clamping diode D3 and the second clamping diode D4, if the voltage between the fifth resistor R5 and the sixth resistor R6 exceeds the reference voltage, it will be clamped to the reference voltage by the first clamping diode D3 and the second clamping diode D4, thereby protecting the core circuit.

[0041] In this embodiment, the third voltage divider module includes a seventh resistor R7.

[0042] In this embodiment, the voltage division ratios of the two voltage divider output terminals are 100:1 and 1000:1, respectively. Specifically, when there is a power surge, the first comparator U1 and the first diode D1 form an active rectifier to track the input voltage; the first capacitor C1 is used to store the peak value of the input voltage, and the second comparator U2 is used as a voltage follower to output the peak voltage.

[0043] Since the inverting input of the second comparator U2 is connected to the output, and the non-inverting input is connected to the first capacitor C1 via the eighth resistor R8, the second comparator U2 can compare the voltage of the first capacitor C1 with the output voltage to achieve tracking. Combined with the eighth resistor R8, the charge on the first capacitor C1 is slowly released, thus reducing the sampling rate requirement of the subsequent sampler 3.

[0044] In addition, the non-inverting input of the first comparator U1 receives the surge input, and the directional input is connected to the output of the second comparator U2 via the tenth resistor R10. This allows for the filtering of non-peak data. When the surge input voltage is less than the output of the second comparator, i.e., when it is a non-peak, the output of the first comparator U1 is 0 and it does not output to the subsequent stage, thus no longer outputting invalid non-peak data and reducing the invalid data received by the sampler 3.

[0045] In this embodiment, the core component of the sampler 3 can be a high-speed ADC. In addition, this application can also superimpose the data processing of the prior art. After the sampler 3 receives the data, it can filter some data that are lower than the pre-configured threshold voltage, thereby ignoring normal data. Finally, the peak voltage sampled by the sampler 3 can be multiplied by the corresponding multiplier to obtain the peak voltage of the surge.

[0046] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A surge peak sampling circuit, comprising a voltage divider circuit, a main circuit, and a sampler, wherein the two ends of the voltage divider circuit are connected to the positive and negative terminals of a power supply, the voltage divider output terminal is connected to the input terminal of the main circuit, and the output terminal of the main circuit is connected to the sampler, characterized in that, The main circuit includes a first comparator, a second comparator, an energy storage capacitor, a first diode, an eighth resistor, and a tenth resistor. The inverting input of the first comparator is connected to the voltage divider output of the voltage divider circuit. The non-inverting input is connected to the output of the second comparator through the tenth resistor. The output is connected to the anode of the first diode. The cathode of the first diode is connected to the first terminal of the eighth resistor and the non-inverting input of the second comparator. The second terminal of the eighth resistor is connected to the first terminal of the first capacitor. The second terminal of the first capacitor is grounded. The inverting input of the second comparator is connected to the output of the second comparator. The output of the second comparator is connected to a sampler.

2. The surge peak sampling circuit according to claim 1, characterized in that, The main circuit also includes a second diode, the positive terminal of which is connected to the inverting input terminal of the first comparator, and the negative terminal of which is connected to the output terminal of the first comparator.

3. The surge peak sampling circuit according to claim 1, characterized in that, The main circuit also includes a ninth resistor and a reset transistor. The ninth resistor is grounded through the collector and emitter of the reset transistor, and the base of the reset transistor is used to receive a reset signal.

4. The surge peak sampling circuit according to claim 3, characterized in that, The reset transistor is an NPN transistor, with its collector connected to the ninth resistor and its emitter grounded.

5. The surge peak sampling circuit according to claim 1, characterized in that, The main circuit also includes an eleventh resistor, one end of which is connected to the output of the second comparator and the other end is grounded.

6. The surge peak sampling circuit according to claim 1, characterized in that, The voltage divider circuit includes a first voltage divider module, a second voltage divider module, and a third voltage divider module connected in series. The connection between the first voltage divider module and the second voltage divider module serves as the first voltage divider output terminal, and the connection between the second voltage divider module and the third voltage divider module serves as the second voltage divider output terminal.

7. The surge peak sampling circuit according to claim 6, characterized in that, The first voltage divider module includes a first resistor, a second resistor, and a third resistor connected in series.

8. The surge peak sampling circuit according to claim 6, characterized in that, The second voltage divider module includes a fourth resistor, a fifth resistor, and a sixth resistor connected in series.

9. A surge peak sampling circuit according to claim 8, characterized in that, The voltage divider circuit further includes a first clamping diode and a second clamping diode. The positive terminal of the first clamping diode is connected to the negative terminal of the power supply, and the negative terminal is connected to the positive terminal of the second clamping diode, as well as the connection point of the fifth resistor and the sixth resistor. The negative terminal of the second clamping diode is connected to the positive terminal of the first DC power supply.

10. A surge peak sampling circuit according to claim 6, characterized in that, The third voltage divider module includes a seventh resistor.

Images