Power module manufacturing method for reducing voltage overshoot

Abstract

A power inverter may include a plurality of direct current (DC) bus bars. Each of the plurality of DC bus bars has a terminal end and a die attachment region. The power inverter may also include a plurality of power switch dies. Each of the plurality of power switch dies is secured to the die attachment area at one of the plurality of die positions. One of a plurality of die positions for each of the plurality of power switch dies is selected to minimize drain-source voltage overshoot of each of the plurality of power switch dies during switching.

Description

Technical Field

[0001] This disclosure relates to methods for manufacturing systems and apparatuses for power conversion. Background Technology

[0002] To convert power in vehicle applications, power modules can be used. A power module is a self-contained power electronic device that typically includes semiconductor switches configured to be controllable to perform power conversion tasks, such as direct current (DC) to alternating current (AC) conversion, AC to DC conversion, DC to DC conversion, etc. In some examples, the power module is configured as a half-bridge with four semiconductor devices, thus allowing DC to AC conversion. Multiple power modules can be used in series to provide multiphase AC power to a load, such as a vehicle's traction motor.

[0003] While current methods for manufacturing power conversion devices have achieved their intended purpose, a new and improved manufacturing method for power modules of power inverters is still needed to mitigate voltage overshoot. Summary of the Invention

[0004] Depending on several aspects, a power inverter may include multiple direct current (DC) buses. Each of the multiple DC buses has terminal ends and a die attachment area. The power inverter may also include multiple power switch dies. Each of the multiple power switch dies is fixed to the die attachment area at one of a plurality of die locations. One of the plurality of die locations for each of the multiple power switch dies is selected to minimize drain-source voltage overshoot for each of the multiple power switch dies during switching.

[0005] In another aspect of this disclosure, one of the plurality of die positions for each of the plurality of power switch dies is selected at least in part based on the parasitic inductance of each of the plurality of die positions. The parasitic inductance of each of the plurality of die positions is the parasitic inductance between each of the plurality of die positions and a terminal end of one of the plurality of DC busbars.

[0006] In another aspect of this disclosure, the parasitic inductance of each of the plurality of die locations varies directly with the bus length between each of the plurality of die locations and the terminal end.

[0007] In another aspect of this disclosure, one of a plurality of die positions for each of the plurality of power switch dies is selected based at least in part on the threshold voltage of each of the plurality of power switch dies.

[0008] In another aspect of this disclosure, a first power switch die among a plurality of power switch dies is fixed at a first die position among a plurality of die positions. The first power switch die has a first threshold voltage and the first die position has a first parasitic inductance. A second power switch die among a plurality of power switch dies is fixed at a second die position among a plurality of die positions. The second power switch die has a second threshold voltage and the second die position has a second parasitic inductance. The second threshold voltage is greater than the first threshold voltage, and the second parasitic inductance is greater than the first parasitic inductance.

[0009] In another aspect of this disclosure, the plurality of DC busbars includes a positive DC busbar. The positive DC busbar has a positive terminal end and a positive die attachment region. The plurality of DC busbars also includes a negative DC busbar. The negative DC busbar has a negative terminal end and a negative die attachment region. The plurality of power switch dies includes a plurality of high-side power switch dies. Each of the plurality of high-side power switch dies is fixed to the positive die attachment region of the positive DC busbar at one of the plurality of high-side die locations. The plurality of power switch dies also includes a plurality of low-side power switch dies. Each of the plurality of low-side power switch dies is fixed to the negative die attachment region of the negative DC busbar at one of the plurality of low-side die locations.

[0010] In another aspect of this disclosure, the second die location is one of a plurality of high-side die locations.

[0011] In another aspect of this disclosure, one of a plurality of die positions for each of the plurality of power switch dies is selected at least in part based on the material type of each of the plurality of power switch dies.

[0012] In another aspect of this disclosure, a third power switch die of the plurality of power switch dies is fixed at a first die position of the plurality of die positions. The third power switch die has a first material type and the first die position has a first parasitic inductance. A fourth power switch die of the plurality of power switch dies is fixed at a second die position of the plurality of die positions. The fourth power switch die has a second material type and the second die position has a second parasitic inductance. The second parasitic inductance is greater than the first parasitic inductance.

[0013] In another aspect of this disclosure, the first material type is silicon carbide and the second material type is silicon.

[0014] According to several aspects, a method for manufacturing a power inverter is provided. The method may include securing a plurality of direct current (DC) buses to a dielectric substrate. Each of the plurality of DC buses has a terminal end and a die attachment region. The method may further include securing a plurality of power switch dies to the plurality of DC buses. Each of the plurality of power switch dies is secured to the die attachment region at one of a plurality of die locations. One of the plurality of die locations for each of the plurality of power switch dies is selected to minimize drain-source voltage overshoot of each of the plurality of power switch dies during switching.

[0015] In another aspect of this disclosure, fixing the plurality of power switch dies may further include selecting one of the plurality of die positions for each of the plurality of power switch dies based at least in part on the parasitic inductance of each of the plurality of die positions. The parasitic inductance of each of the plurality of die positions is the parasitic inductance between each of the plurality of die positions and a terminal end of one of the plurality of DC busbars.

[0016] In another aspect of this disclosure, selecting one of the plurality of die positions for each of the plurality of power switch dies may further include selecting one of the plurality of die positions for each of the plurality of power switch dies based at least in part on the threshold voltage of each of the plurality of power switch dies.

[0017] In another aspect of this disclosure, fixing the plurality of power switch dies may further include fixing a first power switch die among the plurality of power switch dies at a first die position among the plurality of die positions. The first power switch die has a first threshold voltage and the first die position has a first parasitic inductance. Fixing the plurality of power switch dies may further include fixing a second power switch die among the plurality of power switch dies at a second die position among the plurality of die positions. The second power switch die has a second threshold voltage and the second die position has a second parasitic inductance. The second threshold voltage is greater than the first threshold voltage, and the second parasitic inductance is greater than the first parasitic inductance.

[0018] In another aspect of this disclosure, fixing the plurality of DC busbars may further include fixing a positive DC busbar to a dielectric substrate. The positive DC busbar has a positive terminal end and a positive die attachment region. The positive terminal end is electrically connected to a DC positive terminal. Fixing the plurality of DC busbars may further include fixing a plurality of power switch dies, which may further include fixing a plurality of high-side power switch dies at one of a plurality of high-side die positions to the positive die attachment region. A second die position is one of the plurality of high-side die positions.

[0019] In another aspect of this disclosure, selecting one of the plurality of die positions for each of the plurality of power switch dies may further include selecting one of the plurality of die positions for each of the plurality of power switch dies based at least in part on the material type of each of the plurality of power switch dies.

[0020] In another aspect of this disclosure, fixing the plurality of power switch dies may further include fixing a third power switch die of the plurality of power switch dies at a first die position of the plurality of die positions. The third power switch die is of silicon carbide material type and the first die position has a first parasitic inductance. Fixing the plurality of power switch dies may further include fixing a fourth power switch die of the plurality of power switch dies at a second die position of the plurality of die positions. The fourth power switch die is of silicon material type and the second die position has a second parasitic inductance. The second parasitic inductance is greater than the first parasitic inductance.

[0021] According to several aspects, a power inverter for a vehicle is provided. The power inverter may include a plurality of direct current (DC) buses. Each of the plurality of DC buses has a terminal end and a die attachment region. The power inverter may also include a plurality of power switch dies. Each of the plurality of power switch dies is fixed to the die attachment region at one of a plurality of die locations. One of the plurality of die locations for each of the plurality of power switch dies is selected to minimize drain-source voltage overshoot of each of the plurality of power switch dies during switching. The plurality of die locations for each of the plurality of power switch dies is selected at least in part based on the parasitic inductance of each of the plurality of die locations. The parasitic inductance of each of the plurality of die locations is the parasitic inductance between each of the plurality of die locations and a terminal end of one of the plurality of DC buses.

[0022] In another aspect of this disclosure, a first power switch die among a plurality of power switch dies is fixed at a first die position among a plurality of die positions. The first power switch die has a first threshold voltage and the first die position has a first parasitic inductance. A second power switch die among a plurality of power switch dies is fixed at a second die position among a plurality of die positions. The second power switch die has a second threshold voltage and the second die position has a second parasitic inductance. The second threshold voltage is greater than the first threshold voltage, and the second parasitic inductance is greater than the first parasitic inductance.

[0023] In another aspect of this disclosure, a third power switch die of the plurality of power switch dies is fixed at a first die position of the plurality of die positions. The third power switch die has a first material type and the first die position has a first parasitic inductance. A fourth power switch die of the plurality of power switch dies is fixed at a second die position of the plurality of die positions. The fourth power switch die has a second material type and the second die position has a second parasitic inductance. The second parasitic inductance is greater than the first parasitic inductance.

[0024] Further areas of application will become apparent from the description provided herein. It should be understood that these descriptions and specific examples are for illustrative purposes only and are not intended to limit the scope of this disclosure. Attached Figure Description

[0025] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure in any way.

[0026] Figure 1 This is a schematic diagram of an electrical system for a vehicle according to an exemplary embodiment;

[0027] Figure 2 This is a schematic diagram of a power inverter for a power system according to an exemplary embodiment;

[0028] Figure 3A This is a schematic diagram of the first power module of a power inverter according to an exemplary embodiment;

[0029] Figure 3B This is a schematic diagram of the second power module of a power inverter according to an exemplary embodiment; and

[0030] Figure 4 This is a flowchart of a method for manufacturing a power inverter according to an exemplary embodiment. Detailed Implementation

[0031] The following description is merely exemplary in nature and is not intended to limit this disclosure, its application, or its uses.

[0032] In various aspects of this disclosure, when manufacturing power electronic devices (e.g., power inverters for vehicles), it is advantageous to utilize components with known electrical characteristics within acceptable ranges. However, due to manufacturing variations, the electrical characteristics within a batch of components may differ. This disclosure provides a novel and improved method for manufacturing a power inverter for vehicles, allowing for the use of components with varying electrical characteristics to minimize voltage overshoot.

[0033] refer to Figure 1The electrical system of the vehicle is shown and is generally indicated by reference numeral 10. System 10 is shown together with an exemplary vehicle 12. Although a passenger vehicle is shown, it should be understood that vehicle 12 can be any type of vehicle without departing from the scope of this disclosure. System 10 generally includes a controller 14, a rechargeable energy storage system (RESS) 16, a traction motor 18, and a power inverter 20.

[0034] Controller 14 is used to control RESS 16, traction motor 18, and power inverter 20. Controller 14 includes at least one processor 22 and a non-transitory computer-readable storage device or medium 24. Processor 22 may be a custom or commercially available processor, central processing unit (CPU), graphics processing unit (GPU), an auxiliary processor among several processors associated with controller 14, a semiconductor-based microprocessor (in the form of a microchip or chipset), a macroprocessor, a combination thereof, or generally a device for executing instructions.

[0035] Computer-readable storage device or medium 24 may include volatile and non-volatile storage devices such as read-only memory (ROM), random access memory (RAM), and keep-alive memory (KAM). KAM is persistent or non-volatile memory that can be used to store various operational variables when the processor 22 is powered off. Computer-readable storage device or medium 24 may be implemented using multiple storage devices, such as PROM (programmable read-only memory), EPROM (electrical PROM), EEPROM (electrically erasable PROM), flash memory, or other electrical, magnetic, optical, or combined storage devices capable of storing data, some of which represents executable instructions used by controller 14 to control various systems of vehicle 12. Controller 14 may also consist of multiple controllers that are electrically in communication with each other.

[0036] Controller 14 communicates electrically with RESS 16, traction motor 18, and power inverter 20. Controller 14 may also interconnect with additional systems and / or controllers of vehicle 12, allowing controller 14 to access data such as the speed, acceleration, braking, and steering angle of vehicle 12. In exemplary embodiments, networks such as CAN networks, FLEXRAY networks, local area networks (e.g., WiFi, Ethernet, etc.), and Serial Peripheral Interface (SPI) networks are used. It should be understood that various additional wired and wireless technologies and communication protocols used for communicating with controller 14 are within the scope of this disclosure. It should also be understood that, within the scope of this disclosure, electrical communication also includes the transfer of power and / or energy between electrical devices (e.g., using wired and / or wireless power transmission technologies).

[0037] RESS16 stores and provides electrical energy in the form of direct current (DC) energy to propel vehicle 12. In an exemplary embodiment, RESS16 includes multiple battery cells (e.g., lithium-ion battery cells) connected in series and / or parallel to provide increased voltage and / or current carrying capacity. In a non-limiting example, the multiple battery cells are housed in a housing configured to protect the multiple battery cells from mechanical vibration, water intrusion, and dust intrusion. The housing is also configured to provide temperature regulation (e.g., using a liquid cooling system, resistance heating system, etc.).

[0038] In an exemplary embodiment, RESS 16 also includes a battery management system (BMS) in electrical communication with controller 14, configured to monitor battery characteristics such as state of charge (SOC), state of health (SOH), temperature, etc., and transmit these battery characteristics to controller 14. In a non-limiting example, the BMS includes a BMS controller in electrical communication with a plurality of BMS sensors disposed within the housing of RESS 16. In another non-limiting example, the BMS also includes one or more electronic switches (e.g., relays, contactors, semiconductor-based switches, etc.) that are operable in response to commands received from the BMS controller and / or controller 14 to interrupt current flowing through the plurality of battery cells of RESS 16. In an exemplary embodiment, RESS 16 provides a DC voltage between a positive output terminal and a negative output terminal. The positive and negative output terminals are electrically connected to power inverter 20, as will be discussed in more detail below.

[0039] Traction motor 18 is used to convert electrical energy from RESS 16 into mechanical energy (i.e., rotational energy) to propel vehicle 12. In an exemplary embodiment, traction motor 18 is a three-phase alternating current (AC) induction motor capable of converting AC energy into mechanical energy. In a non-limiting example, traction motor 18 includes a stator having multiple stator windings and a rotor rotatably disposed within the stator having multiple rotor windings. The stator windings are excited by three-phase AC current supplied by power inverter 20 to generate a rotating stator magnetic field. The rotating stator magnetic field induces current in the rotor windings, which in turn generate a rotor magnetic field that interacts with the rotating stator magnetic field, causing the rotor to rotate. The amplitude, frequency, and / or relative phase shift of the excitation of each of the three phases of the stator windings control the speed, direction, and / or torque of traction motor 18. Controller 14 is in electrical communication with traction motor 18 for monitoring and / or controlling traction motor 18, for example, measuring the temperature, rotational speed, etc. of traction motor 18.

[0040] Power inverter 20 is used to convert the direct current (DC) energy supplied by RESS 16 into three-phase alternating current (AC) energy for use by traction motor 18. In an exemplary embodiment, power inverter 20 includes multiple power semiconductor devices, such as insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), etc., configured to convert DC to three-phase AC. In a non-limiting example, power inverter 20 operates by switching multiple power semiconductor devices in a certain mode to generate an AC sinusoidal output for each of the three phases. This mode can be adjusted to change the amplitude, frequency, and / or relative phase shift of each of the three phases in order to control the speed, direction, and / or torque of traction motor 18 based on signals from controller 14. Power inverter 20 includes a DC positive terminal 26a and a DC negative terminal 26b electrically connected to RESS 16. Power inverter 20 also includes a first AC terminal 28a, a second AC terminal 28b, and a third AC terminal 28c electrically connected to traction motor 18. The power inverter 20 is in electrical communication with the controller 14, enabling the controller 14 to enable, disable, and otherwise regulate the operation of the power inverter 20. It should be understood that various types of inverters, including, for example, multilevel inverters, are within the scope of this disclosure.

[0041] refer to Figure 2 The diagram shows a power inverter 20. In an exemplary embodiment, the power inverter 20 includes a heat sink 30 and a plurality of power modules 32.

[0042] The radiator 30 is used to remove heat from the plurality of power modules 32 during operation of the power inverter 20. In an exemplary embodiment, the radiator 30 includes a cooling plate having one or more internal liquid-tight channels for conveying coolant through the radiator 30. The radiator 30 also includes a coolant inlet 34a and a coolant outlet 34b, at which coolant enters the radiator 30 and at the coolant outlet 34b exits the radiator 30. In a non-limiting example, after exiting the radiator 30 through the coolant outlet 34b, the coolant flows through a cooler to release the heat absorbed from the plurality of power modules 32.

[0043] Multiple power modules 32 are independent modules used to convert direct current to alternating current. In a non-limiting example, such as Figure 2 As shown, the power inverter 20 includes a first power module 32a, a second power module 32b, and a third power module 32c. It should be understood that the power inverter 20 may include any number of power modules without departing from the scope of this disclosure. In an exemplary embodiment, multiple power modules 32 are fixed to the heat sink 30 using, for example, thermal compounds, thermal adhesives, etc.

[0044] refer to Figure 3AA schematic diagram of the first power module 32a is shown. It should be understood that the following disclosure also applies to any number of additional power modules of the power inverter 20, including, for example, the second power module 32b and the third power module 32c. In an exemplary embodiment, the first power module 32a includes a positive DC busbar 36a, a negative DC busbar 36b, an AC busbar 38 fixed to a dielectric substrate 40 (e.g., directly bonded to a copper substrate), and a plurality of power switch dies 42.

[0045] The positive DC busbar 36a includes a positive terminal end 44a and a positive die attachment region 46a. The positive terminal end 44a is electrically connected to the DC positive terminal 26a. The positive die attachment region 46a is used for electrical connection of multiple high-side power switch dies (described below) at multiple high-side die positions 48a via the current-carrying terminals (e.g., drain or source terminals) of each of the multiple high-side power switch dies.

[0046] The negative DC busbar 36b includes a negative terminal end 44b and a negative die attachment region 46b. The negative terminal end 44b is electrically connected to the DC negative terminal 26b. The negative die attachment region 46b is used for electrical connection of multiple low-side power switch dies (described below) at multiple low-side die locations 48b via the current-carrying terminals (e.g., drain or source terminals) of each of the multiple low-side power switch dies.

[0047] The positive terminal end 44a and the negative terminal end 44b are also collectively referred to herein as terminal ends. The positive die attachment area 46a and the negative die attachment area 46b are also collectively referred to herein as die attachment areas. The multiple high-side die positions 48a and the multiple low-side die positions 48b are also collectively referred to herein as multiple die positions. The positive DC bus bar 36a and the negative DC bus bar 36b are also collectively referred to herein as multiple DC bus bars.

[0048] AC busbar 38 electrically connects the current-carrying terminals (e.g., drain or source terminals) of each of the plurality of power switch dies 42 to the first AC terminal 28a. The plurality of power switch dies 42 includes a first power switch die 42a, a second power switch die 42b, a third power switch die 42c, and a fourth power switch die 42d. It should be understood that each of the plurality of power modules 32 may include any number of power switch dies.

[0049] Each of the plurality of power switch dies 42 includes one or more semiconductor devices, such as transistors, thyristors, triacs, gate turn-off thyristors (GTOs), insulated-gate bipolar transistors (IGBTs), MOSFETs, silicon controlled rectifiers (SCRs), etc. The first power switch die 42a is connected to the DC negative terminal 26b at a first die position 50a in the negative die attachment region 46b. The second power switch die 42b is connected to the DC positive terminal 26a at a second die position 50b in the positive die attachment region 46a.

[0050] The third power switch die 42c is connected to the DC negative terminal 26b at the third die position 50c in the negative die attachment region 46b. The fourth power switch die 42d is connected to the DC positive terminal 26a at the fourth die position 50d in the positive die attachment region 46a. The second power switch die 42b and the fourth power switch die 42d are connected to the DC positive terminal 26a, and are therefore referred to as multiple high-side power switch dies. The first power switch die 42a and the third power switch die 42c are connected to the DC negative terminal 26b, and are therefore referred to as multiple low-side power switch dies.

[0051] In an exemplary embodiment, each of the plurality of power switch dies 42 is characterized by a plurality of electrical characteristics. In a non-limiting example, the plurality of electrical characteristics include at least: a threshold voltage and a material type. The threshold voltage is the minimum gate-source voltage required to create a conductive path between the source and drain terminals. The material type is a semiconductor material used to create the power switch die, such as silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), etc.

[0052] Within the scope of this disclosure, drain-source voltage overshoot is defined as a transient spike in the voltage between the drain and source terminals that exceeds the nominal operating voltage of the power switch die. Over time, drain-source voltage overshoot can lead to device performance degradation or failure.

[0053] Both threshold voltage and material type affect drain-source voltage overshoot in power switch dies. In a non-limiting example, a lower threshold voltage allows the power switch die to turn on with a smaller gate drive voltage, resulting in faster switching times. Furthermore, wide-bandgap materials such as silicon carbide (SiC) and gallium nitride (GaN) can handle higher voltages and faster switching speeds compared to silicon (Si). However, due to the higher rate of change of voltage and current, faster switching increases the likelihood of overshoot, causing voltage spikes in inductive elements or parasitic inductance.

[0054] Furthermore, the electrical design and topology of the multiple power modules 32, including the arrangement of the multiple power switch dies 42, also affect the drain-source voltage overshoot of the multiple power switch dies 42. In a non-limiting example, the parasitic inductance between each of the multiple die locations and the terminal end of one of the multiple DC busbars affects the drain-source voltage overshoot of the multiple power switch dies 42. Larger parasitic inductance tends to increase the likelihood and severity of drain-source voltage overshoot.

[0055] In a non-limiting example, multiple power switch dies 42 are supplied in batches for use in the manufacturing process of multiple power modules 32. Therefore, the electrical characteristics of the multiple power switch dies 42 can vary.

[0056] To ensure the proper operation of the plurality of power modules 32 of the power inverter 20, predetermined thresholds are defined. In an exemplary embodiment, the predetermined voltage overshoot threshold is defined as the maximum permissible drain-source voltage overshoot for any individual power switch die. This disclosure provides a novel and improved method of manufacturing for the plurality of power modules 32 to minimize drain-source voltage overshoot for each of the plurality of power switch dies 42 during switching.

[0057] refer to Figure 3B A schematic diagram of the second power module 32a is shown. It should be understood that the following disclosure also applies to any number of additional power modules of the power inverter 20, including, for example, the second power module 32b and the third power module 32c. References to the first power module 32a and... Figure 3A The disclosed information also applies to the second power module 32b and Figure 3B .exist Figure 3B In an exemplary embodiment, multiple DC busbars, AC busbars 38, and multiple power switch chips 42 are arranged horizontally, rather than as... Figure 3A The layout is vertical. It should be understood that... Figure 3A and Figure 3B The arrangement of the plurality of DC busbars, AC busbars 38 and the plurality of power switch dies 42 shown is merely exemplary in nature, and any arrangement or orientation of the plurality of DC busbars, AC busbars 38 and the plurality of power switch dies 42 is within the scope of this disclosure.

[0058] also, Figure 3BAn exemplary embodiment includes a fifth power switch die 42e and a sixth power switch die 42f. The fifth power switch die 42e is connected to the DC negative terminal 26b at a fifth die position 50e in the negative die attachment region 46b. The sixth power switch die 42f is connected to the DC positive terminal 26a at a sixth die position 50f in the positive die attachment region 46a. The second power switch die 42b, the fourth power switch die 42d, and the sixth power switch die 42f are connected to the DC positive terminal 26a and are therefore referred to as a plurality of high-side power switch dies. The first power switch die 42a, the third power switch die 42c, and the fifth power switch die 42e are connected to the DC negative terminal 26b and are therefore referred to as a plurality of low-side power switch dies. It should be understood that any arrangement, orientation, and number of the plurality of DC busbars, AC busbars 38, and the plurality of power switch dies 42 are within the scope of this disclosure.

[0059] refer to Figure 4 A flowchart of a method 100 for manufacturing a power inverter is shown. Method 100 begins at block 102 and proceeds to block 104. At block 104, a plurality of DC busbars (i.e., positive DC busbar 36a and negative DC busbar 36b) and AC busbar 38 are fixed to a dielectric substrate 40. After block 104, method 100 proceeds to block 106.

[0060] At block 106, the parasitic inductance of each of the plurality of die locations (i.e., the plurality of high-side die locations 48a and the plurality of low-side die locations 48b) is determined. In another exemplary embodiment, the inherent parasitic inductance of each of the plurality of power switch dies 42 is determined. Within the scope of this disclosure, the parasitic inductance of each of the plurality of die locations is the parasitic inductance between each of the plurality of die locations and a terminal end of one of the plurality of DC busbars. For example, the parasitic inductance of one of the plurality of high-side die locations 48a is measured between one of the plurality of high-side die locations 48a and the positive terminal end 44a. The parasitic inductance of one of the plurality of low-side die locations 48b is measured between one of the plurality of low-side die locations 48b and the negative terminal end 44b. Within the scope of this disclosure, the inherent parasitic inductance of each of the plurality of power switch dies 42 is influenced by the material properties and manufacturing processes of each of the plurality of power switch dies 42.

[0061] In a non-limiting example, the parasitic inductance of each of the plurality of die locations varies directly with the bus length between each of the plurality of die locations and the terminal end. Therefore, the longer the bus length, the greater the parasitic inductance. In an exemplary embodiment, the parasitic inductance of each of the plurality of die locations is determined at least in part based on the bus length. In a non-limiting example, the parasitic inductance of the first die location 50a is determined at least in part based on the length of the first bus between the first die location 50a and the negative terminal end 44b. The parasitic inductance of the second die location 50b is determined at least in part based on the length of the second bus between the second die location 50b and the positive terminal end 44a.

[0062] exist Figure 3A In the example shown, because the length of the first busbar between the first die position 50a and the negative terminal end 44b is less than the length of the second busbar between the second die position 50b and the positive terminal end 44a, the parasitic inductance of the second die position 50b is greater than the parasitic inductance of the first die position 50a. Figure 3B In the example shown, because the length of the fifth bus between the fifth die position 50e and the negative terminal end 44b is less than both the lengths of the first and third buses between the third die position 50c and the negative terminal end 44b, the parasitic inductance of the fifth die position 50e is less than both the parasitic inductance of the first die position 50a and the parasitic inductance of the third die position 50c. Furthermore, because the length of the sixth bus between the sixth die position 50f and the positive terminal end 44a is less than both the lengths of the second and fourth buses between the fourth die position 50d and the positive terminal end 44a, the parasitic inductance of the sixth die position 50f is less than both the parasitic inductance of the second die position 50b and the parasitic inductance of the fourth die position 50d. After block 106, method 100 proceeds to block 108.

[0063] At block 108, multiple electrical characteristics of each of the plurality of power switch dies 42 are determined. In an exemplary embodiment, the multiple electrical characteristics include at least one of the following: threshold voltage and material type. In a non-limiting example, the multiple electrical characteristics are determined by performing electrical tests on each of the plurality of power switch dies 42 (e.g., measuring voltage and current during switching and on-state current flow). In another non-limiting example, the multiple electrical characteristics of each of the plurality of power switch dies 42 are provided by the manufacturer of each of the plurality of power switch dies 42. After block 108, method 100 proceeds to block 110.

[0064] At block 110, a plurality of power switch dies 42 are secured to a plurality of DC busbars at least in part based on the parasitic inductance of each of the plurality of die locations to minimize drain-source voltage overshoot of each of the plurality of power switch dies 42 during switching. In an exemplary embodiment, one of the plurality of die locations for each of the plurality of power switch dies 42 is selected at least in part based on the parasitic inductance of each of the plurality of die locations determined at block 106 and the threshold voltage of each of the plurality of power switch dies 42 determined at block 108. Dies with relatively high threshold voltages are placed at die locations with relatively high parasitic inductance to balance the effects of switching speed and inductance on voltage overshoot, such that the drain-source voltage overshoot of each of the plurality of power switch dies 42 is less than or equal to a predetermined voltage overshoot threshold. In another exemplary embodiment, dies with similar threshold voltages (i.e., within a predetermined range, e.g., ±5%) are grouped together and fixed adjacent to each other and / or fixed on the same power module to minimize voltage overshoot and / or load current mismatch due to switching mismatch. Furthermore, dies with similar on-resistances are grouped together and fixed adjacent to each other and / or fixed on the same power module to minimize load current mismatch.

[0065] In the non-restrictive example, for Figure 3A In the illustrated embodiment, a first power switch die 42a is fixed at a first die position 50a. The first power switch die 42a has a first threshold voltage and the first die position 50a has a first parasitic inductance. A third power switch die 42c is fixed at a third die position 50c. The third power switch die 42c has a third threshold voltage and the third die position 50c has a third parasitic inductance. The third threshold voltage (i.e., the threshold voltage of the third power switch die 42c) is greater than the first threshold voltage (i.e., the threshold voltage of the first power switch die 42a) and the third parasitic inductance (i.e., the parasitic inductance of the third die position 50c) is greater than the first parasitic inductance (i.e., the parasitic inductance of the first die position 50a), as evidenced by the longer busbar length of the third die position 50c compared to the first die position 50a.

[0066] In the non-restrictive example, for Figure 3BIn the illustrated embodiment, a fifth power switch die 42e is fixed at a fifth die position 50e. The fifth power switch die 42e has a fifth threshold voltage and a fifth parasitic inductance at the fifth die position 50e. A first power switch die 42a is fixed at a first die position 50a, and a third power switch die 42c is fixed at a third die position 50c. The first power switch die 42a has a first threshold voltage and a first parasitic inductance at the first die position 50a. The third power switch die 42c has a third threshold voltage and a third parasitic inductance at the third die position 50c. The first and third threshold voltages are greater than the fifth threshold voltage. The first and third parasitic inductances are greater than the fifth parasitic inductance, as evidenced by the longer busbar lengths at the first die position 50a and the third die position 50c compared to the fifth die position 50e.

[0067] In another non-restrictive example, for Figure 3A In the illustrated embodiment, a first power switch die 42a is fixed at a first die position 50a. The first power switch die 42a has a first threshold voltage and the first die position 50a has a first parasitic inductance. A second power switch die 42b is fixed at a second die position 50b (i.e., the second power switch die 42b is fixed at one of a plurality of high-side die positions 48a). The second power switch die 42b has a second threshold voltage and the second die position 50b has a second parasitic inductance. The second threshold voltage (i.e., the threshold voltage of the second power switch die 42b) is greater than the first threshold voltage (i.e., the threshold voltage of the first power switch die 42a) and the second parasitic inductance (i.e., the parasitic inductance of the second die position 50b) is greater than the first parasitic inductance (i.e., the parasitic inductance of the first die position 50a), as evidenced by the longer busbar length of the second die position 50b compared to the first die position 50a.

[0068] In another exemplary embodiment, one of the plurality of die positions for each of the plurality of power switch dies 42 is selected at least in part based on the parasitic inductance of each of the plurality of die positions determined at block 106 and the material type of each of the plurality of power switch dies 42 determined at block 108. In a non-limiting example, a die with a faster switching material type is placed at a die position with relatively low parasitic inductance to balance the effects of switching speed, reverse recovery, and inductance on voltage overshoot, such that the drain-source voltage overshoot of each of the plurality of power switch dies 42 is less than or equal to a predetermined voltage overshoot threshold.

[0069] In the non-restrictive example, for Figure 3AIn the illustrated embodiment, a third power switch die 42c is fixed at a third die position 50c. The third power switch die 42c has a first material type and the third die position 50c has a third parasitic inductance. A fourth power switch die 42d is fixed at a fourth die position 50d. The fourth power switch die 42d has a second material type and the fourth die position 50d has a fourth parasitic inductance. The second material type (i.e., the material of the fourth power switch die 42d) is silicon (Si). The first material type (i.e., the material type of the third power switch die 42c) is silicon carbide (SiC). The fourth parasitic inductance (i.e., the parasitic inductance of the fourth die position 50d) is greater than the third parasitic inductance (i.e., the parasitic inductance of the third die position 50c), as evidenced by the longer busbar length of the fourth die position 50d compared to the third die position 50c.

[0070] In the non-restrictive example, for Figure 3B In the illustrated embodiment, a fifth power switch die 42e is fixed at a fifth die position 50e. The fifth power switch die 42e has a fifth material type and a fifth parasitic inductance at the fifth die position 50e. A first power switch die 42a is fixed at a first die position 50a, and a third power switch die 42c is fixed at a third die position 50c. The first power switch die 42a has a first material type and a first parasitic inductance at the first die position 50a. The third power switch die 42c has a third material type and a third parasitic inductance at the third die position 50c. Both the first and third material types are silicon (Si). The fifth material type is silicon carbide (SiC). The first and third parasitic inductances are greater than the fifth parasitic inductance, as evidenced by the longer busbar lengths at the first die position 50a and the third die position 50c compared to the fifth die position 50e.

[0071] After selecting one of a plurality of die positions for each of the plurality of power switch dies 42, the plurality of power switch dies 42 are secured to the dielectric substrate 40. Electrical connections between components are established using a plurality of conductors (e.g., busbars, bonding wires, bonding clips, bonding tapes, etc.). Control terminals for connecting the gate terminals (not shown) of each of the plurality of power switch dies 42 to a gate driver (not shown) and / or to an inverter controller (not shown) and / or to a controller 14 are implemented as pins extending orthogonally from the dielectric substrate 40 and electrically connected to the gate terminals using bonding wires. Following block 110, method 100 proceeds to block 112.

[0072] At block 112, the first power module 32a is secured to the heat sink 30. It should be understood that method 100 may also include additional steps, such as electrical connections of components, testing of components, enclosure of components, encapsulation or conformal coating, quality assurance, etc. After block 112, method 100 proceeds to the standby state at block 114.

[0073] In an exemplary embodiment, method 100 is repeatedly restarted at block 102 to generate a plurality of power modules 32 (e.g., a second power module 32b and a third power module 32c) and each of the plurality of power modules 32 is attached to a heat sink 30 to complete the assembly of the power inverter 20.

[0074] The method 100 of this disclosure provides several advantages. By manufacturing the power inverter 20 according to method 100, voltage overshoot is mitigated, and the performance, lifespan, and reliability of the power inverter 20 are improved. The description in this disclosure is merely exemplary in nature, and variations thereof that do not depart from the spirit and scope of this disclosure are intended to fall within its scope. These variations should not be considered as departing from the spirit and scope of this disclosure.

Claims

1. A power inverter, comprising: Multiple DC busbars, each of which has a terminal end and a die attachment area; as well as A plurality of power switch dies, wherein each of the plurality of power switch dies is fixed to the die attachment region at one of a plurality of die locations, wherein one of the plurality of die locations for each of the plurality of power switch dies is selected to minimize drain-source voltage overshoot of each of the plurality of power switch dies during switching.

2. The power inverter according to claim 1, wherein, One of the plurality of die positions for each of the plurality of power switch dies is selected at least in part based on the parasitic inductance of each of the plurality of die positions, wherein the parasitic inductance of each of the plurality of die positions is the parasitic inductance between each of the plurality of die positions and the terminal end of one of the plurality of DC busbars.

3. The power inverter according to claim 2, wherein, The parasitic inductance of each of the plurality of die locations varies directly with the bus length between each of the plurality of die locations and the terminal end.

4. The power inverter according to claim 2, wherein, One of the plurality of die positions for each of the plurality of power switch dies is selected based at least in part on the threshold voltage of each of the plurality of power switch dies.

5. The power inverter according to claim 4, wherein: The first power switch die among the plurality of power switch dies is fixed at a first die position among the plurality of die positions, wherein the first power switch die has a first threshold voltage and the first die position has a first parasitic inductance; and The second power switch die among the plurality of power switch dies is fixed at the second die position among the plurality of die positions, wherein the second power switch die has a second threshold voltage and the second die position has a second parasitic inductance, wherein the second threshold voltage is greater than the first threshold voltage and the second parasitic inductance is greater than the first parasitic inductance.

6. The power inverter according to claim 5, wherein: The plurality of DC busbars include: A positive DC busbar, wherein the positive DC busbar has a positive terminal end and a positive die attachment area; and A negative DC busbar, wherein the negative DC busbar has a negative terminal end and a negative die attachment area; and The plurality of power switch chips include: A plurality of high-side power switch dies, wherein each of the plurality of high-side power switch dies is fixed at one of the plurality of high-side die locations to the positive die attachment region of the positive DC busbar; and A plurality of low-side power switch dies, wherein each of the plurality of low-side power switch dies is fixed at one of the plurality of low-side die locations to the negative die attachment region of the negative DC busbar.

7. The power inverter according to claim 6, wherein, The second die position is one of the plurality of high-side die positions.

8. The power inverter according to claim 2, wherein, One of the plurality of die positions for each of the plurality of power switch dies is selected at least in part based on the material type of each of the plurality of power switch dies.

9. The power inverter according to claim 8, wherein: The third power switch die among the plurality of power switch dies is fixed at the first die position among the plurality of die positions, wherein the third power switch die has a first material type and the first die position has a first parasitic inductance; and The fourth power switch die among the plurality of power switch dies is fixed at the second die position among the plurality of die positions, wherein the fourth power switch die has a second material type and the second die position has a second parasitic inductance, and wherein the second parasitic inductance is greater than the first parasitic inductance.

10. The power inverter according to claim 9, wherein, The first material type is silicon carbide and the second material type is silicon.

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