Semiconductor device, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system. The semiconductor device comprises a plurality of semiconductor main bodies; the plurality of semiconductor main bodies are separated by a first dielectric layer; the conductive structures are positioned at one end of the semiconductor main body along the first direction and are coupled with the semiconductor main body; the first direction is the extension direction of the semiconductor main body; the conductive structure at least comprises metal silicide layers extending in the first direction, and the multiple metal silicide layers are separated through the first dielectric layers.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for manufacturing the same, and a memory system. Background Technology

[0002] Semiconductor devices, such as Dynamic Random Access Memory (DRAM), are among the most important storage components in electronic systems. They typically employ a 1T1C structure, consisting of a transistor and a capacitor, as a single storage cell. This 1T1C structure allows DRAM to achieve high integration density and low cost, giving it an irreplaceable position in computer storage devices. With the rapid development of semiconductor technology, DRAM is rapidly evolving towards higher density and higher quality. Summary of the Invention

[0003] This disclosure presents a semiconductor device, a method for fabricating the same, and a memory system.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, the semiconductor device comprising: a plurality of semiconductor bodies; the plurality of semiconductor bodies being separated by a first dielectric layer; a plurality of conductive structures, the conductive structures being located at one end of a semiconductor body along a first direction and coupled to the semiconductor body; the first direction being the extension direction of the semiconductor body; the conductive structures comprising at least a metal silicide layer extending along the first direction, the plurality of metal silicide layers being separated by the first dielectric layer.

[0005] In one alternative embodiment, the conductive structure further includes a conductive layer located on the side of the metal silicide layer away from the semiconductor body; the semiconductor device further includes a second dielectric layer located between the plurality of conductive layers; the second dielectric layer is made of a different material than the first dielectric layer.

[0006] In one alternative embodiment, in a first direction, the metal silicide layer has a first surface and a second surface, the first surface being farther away from the semiconductor body relative to the second surface; the second dielectric layer includes a third surface and a fourth surface, the third surface being closer to the first dielectric layer relative to the fourth surface; the first surface is located between the third surface and the semiconductor body.

[0007] In one alternative implementation, the size of the first surface is greater than or equal to the size of the second surface in a second direction perpendicular to the first direction.

[0008] In one alternative embodiment, a portion of the conductive layer is formed in a first dielectric layer, and another portion of the conductive layer is formed in a second dielectric layer.

[0009] In one alternative embodiment, the conductive layer has a fifth surface in contact with the metal silicide layer, the contact area between the metal silicide layer and the conductive layer being equal to the surface area of ​​the fifth surface.

[0010] In one alternative embodiment, the semiconductor device further includes a third dielectric layer located between the first dielectric layer and the second dielectric layer; the surface of the third dielectric layer adjacent to the metal silicide layer is higher than the first surface.

[0011] In one alternative embodiment, a portion of the conductive layer is formed in a third dielectric layer, and another portion of the conductive layer is formed in a second dielectric layer.

[0012] In one alternative implementation, the metal element in the metal silicide layer includes tungsten, nickel, cobalt, or titanium.

[0013] In one alternative implementation, the semiconductor body has a source and a drain at opposite ends along a first direction; one of the source and drain is coupled to a metal silicide layer; and the other of the source and drain is coupled to a corresponding bit line.

[0014] In one alternative implementation, the system further includes a plurality of storage capacitors, each of which is coupled to the semiconductor body via a conductive structure.

[0015] In one alternative implementation, the metal silicide layer is in contact with the semiconductor body, and the conductive layer is in contact with the storage capacitor.

[0016] In a second aspect, embodiments of this disclosure provide a method for fabricating a semiconductor device, the method comprising: forming a plurality of conductive structures, each conductive structure including at least a metal silicide layer; forming a plurality of semiconductor bodies extending along a first direction, the plurality of semiconductor bodies being separated by a first dielectric layer; the semiconductor bodies being located on one side of the conductive structures along the first direction and connected to the metal silicide layer; the plurality of metal silicide layers being separated by the first dielectric layer.

[0017] In one optional embodiment, forming a semiconductor body and a conductive structure includes: forming a plurality of initial semiconductor bodies; separating the plurality of initial semiconductor bodies by a first dielectric layer; removing a portion of the first dielectric layer along a first direction, exposing a portion of the initial semiconductor bodies as a first initial semiconductor body, and the remaining portion of the initial semiconductor bodies as a second initial semiconductor body; the dimension of the first initial semiconductor body in a cross-section perpendicular to the first direction is less than or equal to the dimension of the second initial semiconductor body in a cross-section perpendicular to the first direction; etching away the first initial semiconductor body and a portion of the second initial semiconductor body, the remaining portion of the second initial semiconductor body as a third initial semiconductor body; and forming a metal silicide layer using the third initial semiconductor body.

[0018] In one alternative implementation, the surface of the remaining first dielectric layer is higher than the surface of the third initial semiconductor body.

[0019] In one alternative embodiment, after removing a portion of the first dielectric layer along the first direction, the method further includes: forming a third dielectric layer covering the first initial semiconductor body; forming a second dielectric layer covering the third dielectric layer; and removing a portion of the second dielectric layer to expose a portion of the first initial semiconductor body.

[0020] In one alternative embodiment, etching away the first initial semiconductor body and a portion of the second initial semiconductor body includes: etching away a portion of the third dielectric layer, the first initial semiconductor body, and a portion of the second initial semiconductor body to form a plurality of first trenches in the remaining first dielectric layer and the first dielectric layer.

[0021] In one alternative embodiment, forming a metal silicide layer using a third initial semiconductor body includes: metallizing at least a portion of the third initial semiconductor body through a first trench to form a metal silicide layer; and forming a semiconductor body from the remaining third initial semiconductor body after metallization.

[0022] In one alternative embodiment, forming a conductive structure further includes forming a conductive layer within a first trench, the conductive layer being connected to a metal silicide layer.

[0023] In one alternative implementation, the metal element in the metal silicide layer includes tungsten, nickel, cobalt, or titanium.

[0024] In one alternative implementation, the method further includes forming a storage capacitor coupled to a conductive structure, the storage capacitor being coupled to a semiconductor body via the conductive structure.

[0025] Thirdly, embodiments of this disclosure provide a memory system, including: a semiconductor device as described in any of the first aspects; and a memory controller connected to the semiconductor device and used to control the semiconductor device.

[0026] This disclosure provides a semiconductor device, a method for fabricating the same, and a memory system. The semiconductor device includes: multiple semiconductor bodies; multiple semiconductor bodies separated by a first dielectric layer; multiple conductive structures located at one end of a semiconductor body along a first direction and coupled to the semiconductor body; the first direction being the extension direction of the semiconductor body; and each conductive structure including at least a metal silicide layer extending along the first direction, with the multiple metal silicide layers separated by the first dielectric layer. In this disclosure, the metal silicide layer and the semiconductor body in the conductive structure are located in the same dielectric, meaning that the metal silicide layer in this disclosure is formed using an initial semiconductor body located in the first dielectric layer. This allows the cross-sectional dimension of the metal silicide layer perpendicular to the first direction to be the maximum cross-sectional dimension of the initial semiconductor body perpendicular to the first direction, thereby increasing the cross-sectional dimension of the metal silicide layer perpendicular to the first direction to a certain extent. Attached Figure Description

[0027] Figure 1 A schematic diagram of the structure of a semiconductor device provided in this disclosure embodiment. Figure 1 ;

[0028] Figure 2 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0029] Figures 3a to 3d A cross-sectional schematic diagram of the process of forming an initial semiconductor body provided in an embodiment of this disclosure;

[0030] Figures 4a to 4g A cross-sectional schematic diagram of the process of forming a conductive structure and a semiconductor body provided in an embodiment of this disclosure;

[0031] Figure 5 A schematic diagram of the structure of a semiconductor device provided in this disclosure embodiment. Figure 2 ;

[0032] Figure 6 A schematic diagram of an exemplary system with a memory system provided in the embodiments of this disclosure;

[0033] Figure 7 A schematic diagram of an exemplary memory device provided for embodiments of this disclosure. Detailed Implementation

[0034] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0035] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0036] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0037] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0041] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements of dynamic random access memory for ions and leakage current, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.

[0042] In some embodiments of this disclosure, whether planar transistors or buried transistors, the dynamic random access memory is composed of multiple memory cells. Each memory cell consists of a transistor and a capacitor controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0043] The following is combined Figure 1 One architecture of dynamic random access memory is described in detail. In the introduction... Figure 1 Before illustrating the semiconductor device, we first define the various directions that may be used in the following description. The extension direction of the semiconductor body is defined as the first direction (i.e., the Z-axis direction). In a plane perpendicular to the Z-axis direction, we define the intersecting second direction (i.e., the X-axis direction) and the third direction (i.e., the Y-axis direction). In some embodiments, the X-axis direction, the Y-axis direction, and the Z-axis direction can be mutually perpendicular.

[0044] A cross-sectional view of a semiconductor device 100 including a vertical transistor is provided in this embodiment of the disclosure; as shown... Figure 1 As shown, the semiconductor device 100 includes a second semiconductor structure 102 and a first semiconductor structure 104 stacked on top of the second semiconductor structure 102 along the Z-axis direction. The second semiconductor structure 102 and the first semiconductor structure 104 are connected via a bonding interface 106. The second semiconductor structure 102 and the first semiconductor structure 104 can be connected by methods such as hybrid bonding. In some embodiments, the first semiconductor structure 104 can be bonded to the top of the second semiconductor structure 102 in a face-to-face manner at the bonding interface 106. The second semiconductor structure 102 may include a first substrate 1010, a peripheral circuit 1012 located on one side of the first substrate 1010, and a first interconnect layer 1016 located on the side of the peripheral circuit 1012 away from the first substrate 1010. The first interconnect layer 1016 is used to transmit electrical signals of the peripheral circuit 1012. The peripheral circuit 1012 may include a plurality of transistors 1014. In some embodiments, trench isolation (such as shallow trench isolation (STI)) and doped regions (such as the well, source and drain of transistor 1014) may also be formed on or in the first substrate 1010.

[0045] The second semiconductor structure 102 may further include a first bonding layer 1018 located at the bonding interface 106 and on the side of the first interconnect layer 1016 away from the peripheral circuit 1012. The first bonding layer 1018 may include a plurality of first bonding contacts 1019 and a dielectric material electrically isolating the first bonding contacts 1019. The first bonding contacts 1019 in the first bonding layer 1018 and the surrounding dielectric material can be used for mixed bonding. Conversely, the first semiconductor structure 104 may also include a second bonding layer 1020 located at the bonding interface 106 and on the side of the first bonding layer 1018 away from the first interconnect layer 1016. The second bonding layer 1020 may include a plurality of second bonding contacts 1021 and a dielectric material electrically isolating the second bonding contacts 1021. The second bonding contacts 1021 in the second bonding layer 1020 and the surrounding dielectric material can be used for mixed bonding. Here, the second bonding contact 1021 contacts the first bonding contact 1019 at the bonding interface 106.

[0046] In some embodiments, the peripheral circuitry 1012 may further include word lines (WL) and word line drivers / row decoders coupled to the second interconnect layer 1022 via second bonding contacts 1021 in the second bonding layer 1020, first bonding contacts 1019 in the first bonding layer 1018, and the first interconnect layer 1016. In other embodiments, the peripheral circuitry 1012 may further include bit lines 1023 (BL) and bit line drivers / column decoders coupled to the second interconnect layer 1022 via second bonding contacts 1021 in the second bonding layer 1020, first bonding contacts 1019 in the first bonding layer 1018, and the first interconnect layer 1016. Here, the second interconnect layer 1022 includes bit lines 1023 above the second bonding layer 1020, and the bit lines 1023 are used to transmit electrical signals. In other embodiments, the stacked second semiconductor structure 102 and the first semiconductor structure 104 may not be connected by bonding, but rather integrated on the same substrate (only the first substrate, no second substrate), and directly connected through one or more interconnect layers between the second semiconductor structure 102 and the first semiconductor structure 104. In this case, the second semiconductor structure 102 does not have the first bonding layer 1018 and the first bonding contact 1019; the first semiconductor structure 104 does not have the second bonding layer 1020 and the second bonding contact 1019; and the bonding interface 106 between the second semiconductor structure 102 and the first semiconductor structure 104 also does not exist.

[0047] refer to Figure 1The first semiconductor structure 104 further includes a memory cell array located on the second interconnect layer 1022. The memory cell array may include a plurality of memory cells 1024 arranged in an array along the X-axis and Y-axis directions, a second substrate 1048 located on the memory cells 1024, and a third interconnect layer 1050 located on the second substrate 1048. Figure 1 The cross section of the dynamic random access memory 100 can be cut along the bit line direction (X-axis direction), and a bit line 1023 in the second interconnect layer 1022 extending in the X-axis direction can be coupled to a column of memory cells 1024.

[0048] Here, each memory cell 1024 may include a vertical transistor 1026 and a capacitor structure 1028 coupled to the vertical transistor 1026; the vertical transistor 1026 includes a semiconductor body 1030 extending vertically (in the Z-axis direction) and a gate structure 1036 contacting at least a portion of the side surface of the semiconductor body 1030 in the bit line direction (X-axis direction); in other embodiments, the gate structure may also completely surround the semiconductor body, partially surround the semiconductor body, or be located on two opposite sides of the semiconductor body, etc., which will not be elaborated here. Here, the gate structure 1036 includes a gate electrode 1034 and a gate dielectric 1032 located between the gate electrode 1034 and the semiconductor body 1030 in the bit line direction (X-axis direction). In some embodiments, the gate dielectric 1032 is adjacent to one side surface of the semiconductor body 1030, and the gate electrode 1034 is adjacent to the gate dielectric 1032.

[0049] In some embodiments, the semiconductor body 1030 has two ends (upper end and lower end) in the vertical direction (Z-axis direction), and one end (e.g. Figure 1 The lower end of the semiconductor body 1030 extends in the vertical direction (Z-axis direction) beyond the gate dielectric 1032 into the interlayer dielectric (ILD) layer, while the other end of the semiconductor body 1030 (such as...) Figure 1 The upper end of the semiconductor body 1030 is flush with the corresponding end of the gate dielectric 1032. In other embodiments, both ends (upper and lower) of the semiconductor body 1030 extend in the vertical direction (Z-axis direction) beyond the gate electrode 1034 into the ILD layer. In other words, the semiconductor body 1030 may have a larger vertical dimension than the vertical dimension (e.g., depth in the Z-axis direction) of the gate electrode 1034, and neither the upper nor lower end of the semiconductor body 1030 is flush with the corresponding end of the gate electrode 1034. This avoids short circuits between the bit line 1023 and the word line / gate electrode 1034 or between the word line / gate electrode 1034 and the capacitor structure 1028.

[0050] The vertical transistor 1026 may further include a source 1038 and a drain 1040 respectively disposed at both ends (upper and lower ends) of the semiconductor body 1030 in the vertical direction (Z-axis direction). (The positions of the source and drain can be interchanged; here and below, the upper end is the source 1038 and the lower end is the drain 1040 as an example.) In some embodiments, the source 1038 is coupled to the capacitor 1028, and the drain 1040 is coupled to the bit line 1023.

[0051] Since the gate electrode can be part of a word line or extend as a word line in the word line direction, the first semiconductor structure 104 of the dynamic random access memory 100 can also include multiple word lines, each extending in the word line direction (Y-axis direction). Here, each word line 1034 can be coupled to a row of memory cells 1024.

[0052] Vertical transistor 1026 extends vertically through and contacts word line 1034, and its drain 1040 at its lower end contacts bit line 1023. Therefore, due to the vertical arrangement of vertical transistor 1026, word line 1034 and bit line 1023 can be arranged in different planes in the vertical direction, simplifying the wiring of word line 1034 and bit line 1023. Here, vertical transistor 1026 can be arranged in a mirror-symmetric manner to increase the density of memory cells 1024 in the bit line direction (X-axis direction). Two adjacent vertical transistors 1026 in the bit line direction are mirror-symmetric with respect to the first isolation structure 1060; that is, the first semiconductor structure 104 may include a plurality of first isolation structures 1060, each extending parallel to word line 1034 in the word line direction (Y-axis direction) and disposed between semiconductor bodies 1030 of two adjacent rows of vertical transistor 1026. In some embodiments, the rows of vertical transistors 1026 separated by the first isolation structure 1060 are mirror-symmetrical to each other with respect to the first isolation structure 1060. It should be understood that the first isolation structure 1060 may include air gaps, each air gap being laterally disposed between adjacent semiconductor bodies 1030. The first semiconductor structure 104 also includes a plurality of second isolation structures 1062, each second isolation structure 1062 extending parallel to the word line 1034 in the word line direction (Y-axis direction) and disposed between the word lines 1034 of two adjacent rows of vertical transistors 1026. It should be understood that the dimensions of the second isolation structure 1062 and word line 1034 in the bit line direction (X-axis direction) may be the same as or different from the dimensions of the first isolation structure 1060 in the bit line direction (X-axis direction). When the dimensions of the two in the bit line direction (X-axis direction) are different, the spacing between the multiple semiconductor bodies 1030 arranged along the bit line direction (X-axis direction) is different, that is, the multiple semiconductor bodies 1030 arranged along the bit line direction (X-axis direction) are not uniformly arranged.

[0053] like Figure 1 As shown, the capacitor structure 1028 is located above and in contact with the source 1038 (i.e., the upper end of the semiconductor body 1030) of the vertical transistor 1026. The capacitor structure 1028 can be a vertical capacitor.

[0054] In some embodiments, a conductive structure 1064 is formed between the capacitor structure 1028 and the vertical transistor 1026 to reduce contact resistance. For example... Figure 1 As shown, the first semiconductor structure 104 may further include a capacitor contact 1047 that contacts a common plate of the second electrode for coupling the second electrode of the capacitor structure 1028 to the peripheral circuit 1012 or directly to ground. In some embodiments, the ILD layer forming the capacitor structure 1028 has the same dielectric material, such as silicon oxide, as the two ILD layers into which the semiconductor body 1030 extends. The construction of the capacitor structure 1028 may include any suitable structure and construction, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-planar capacitor.

[0055] like Figure 1 As shown, the vertical transistor 1026 extends vertically through and contacts the word line 1034. The drain 1040 at its lower end contacts the bit line 1023, and the source 1038 at its upper end contacts the capacitor structure 1028. That is, due to the vertical arrangement of the vertical transistor 1026, the bit line 1023 and the capacitor structure 1028 can be arranged in different planes in the vertical direction and coupled vertically to opposite ends of the vertical transistor 1026 of the memory cell 1024. In some embodiments, the bit line 1023 and the capacitor structure 1028 are arranged on opposite sides of the vertical transistor 1026 in the vertical direction. Compared to conventional memory cells where the bit line and capacitor structure are arranged on the same side of a planar transistor, this simplifies the wiring of the bit line 1023 and reduces the coupling capacitance between the bit line 1023 and the capacitor structure 1028.

[0056] In some embodiments, the vertical transistor 1026 is vertically disposed between the capacitor structure 1028 and the bonding interface 106. That is, the vertical transistor 1026 can be arranged closer to the peripheral circuitry 1012 and the bonding interface 106 of the second semiconductor structure 102 than the capacitor structure 1028. Since the bit line 1023 and the capacitor structure 1028 are coupled to opposite ends of the vertical transistor 1026, the bit line 1023 (as part of the second interconnect layer 1022) is vertically disposed between the vertical transistor 1026 and the bonding interface 106 to reduce interconnect wiring distance and complexity.

[0057] In some embodiments, the first semiconductor structure 104 further includes a second substrate 1048 disposed above the memory cell 1024, and a third interconnect layer 1050 with pads leading out above the memory cell 1024. The third interconnect layer 1050 with pads leading out may include interconnects in one or more ILD layers, such as contact pads 1054.

[0058] In some embodiments, the first semiconductor structure 104 further includes one or more contacts 1052 extending through a portion of the third interconnect layer 1050 and a second substrate 1048 to couple the pads out of the third interconnect layer 1050 to the memory cell 1024 and the second interconnect layer 1022. Thus, the peripheral circuitry 1012 can be coupled to the memory cell 1024 via the first interconnect layer 1016 and the second interconnect layer 1022, as well as the second bonding layer 1020 and the first bonding layer 1018, and the peripheral circuitry 1012 and the memory cell 1024 can be coupled to external circuitry via the contacts 1052 and the pads out of the third interconnect layer 1050.

[0059] As mentioned above, in order to reduce the contact resistance between the capacitor structure 1028 and the vertical transistor 1026, a conductive structure 1064 is provided between the capacitor structure 1028 and the vertical transistor 1026.

[0060] This disclosure provides a method for fabricating a semiconductor device. (See also...) Figure 2 , Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure; the method includes:

[0061] Step S201: Form multiple conductive structures, each conductive structure including at least a metal silicide layer;

[0062] Step S202: Form a plurality of semiconductor bodies, the semiconductor bodies extending along a first direction, and the plurality of semiconductor bodies being separated by a first dielectric layer; the semiconductor bodies are located on one side of the conductive structure along the first direction and are connected to the metal silicide layer; the plurality of metal silicide layers are separated by the first dielectric layer.

[0063] It should be understood that Figure 2 The steps shown are not exclusive, and other steps may be performed before, after, or between any step in the shown manufacturing method; Figure 2 The steps shown can be adjusted in order according to actual needs.

[0064] It should be noted that a semiconductor device may include a conductive structure, a semiconductor body and a storage capacitor, or multiple conductive structures, multiple semiconductor bodies and multiple storage capacitors. Here and below, the example of a semiconductor device including multiple conductive structures, multiple semiconductor bodies and multiple storage capacitors is used.

[0065] As mentioned earlier, there can be various relative positions between the gate structure and the semiconductor body in a semiconductor device, and different relative positions correspond to different specific fabrication methods. In this embodiment of the present disclosure, two gate structures corresponding to two adjacent semiconductor bodies are respectively arranged back-to-back. Figure 1 The example shown is a back-to-back arrangement. Based on this, a semiconductor device may include multiple conductive structures, multiple semiconductor bodies, and multiple memory structures arranged in an array along the X-axis and Y-axis directions. However, it should be understood that the following methods for forming semiconductor structures are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0066] There are various methods for forming conductive structures and semiconductor bodies. Several methods are illustrated by way of example in the embodiments of this disclosure. The formation process of multiple conductive structures and multiple semiconductor bodies will be described in detail below with reference to the accompanying drawings.

[0067] In some embodiments, forming a conductive structure and a semiconductor body includes:

[0068] Multiple initial semiconductor bodies are formed; the multiple initial semiconductor bodies are separated by a first dielectric layer;

[0069] A portion of the first dielectric layer is removed along the first direction, exposing a portion of the initial semiconductor body, which is the first initial semiconductor body, and the remaining portion of the initial semiconductor body is the second initial semiconductor body; the dimension of the first initial semiconductor body in a cross-section perpendicular to the first direction is less than or equal to the dimension of the second initial semiconductor body in a cross-section perpendicular to the first direction.

[0070] Etching removes the first initial semiconductor body and part of the second initial semiconductor body, and the remaining part of the second initial semiconductor body becomes the third initial semiconductor body;

[0071] A metal silicide layer is formed using a third initial semiconductor substrate.

[0072] Figures 3a to 3d This is a cross-sectional schematic diagram illustrating the process of forming an initial semiconductor body according to an embodiment of this disclosure. It should be noted that... Figure 3c for Figure 3b A schematic cross-sectional view along the AA' direction is shown below; the formation process of the initial semiconductor body is described in detail below with reference to the accompanying drawings.

[0073] refer to Figure 3aA substrate 300 is provided, the material of which may be a semiconductor material, such as silicon; more specifically, the material of the substrate 300 may be monocrystalline silicon.

[0074] refer to Figure 3b , Figure 3c A plurality of initial semiconductor bodies 310 arranged in an array are formed in a substrate 300. In some embodiments, the formation of the initial semiconductor bodies 310 may include: first forming a plurality of trenches extending along the X-axis in the substrate 300, filling the trenches with an insulating material (such as silicon oxide), and then forming a plurality of trenches extending along the Y-axis in the substrate 300, wherein the trenches extending along the Y-axis are adjusted according to the relative position between the gate structure and the initial semiconductor bodies. Figure 3b The diagram shows that when two gate structures corresponding to two adjacent initial semiconductor bodies are arranged back to back, the trenches extending along the Y-axis include alternately arranged trenches of different sizes. The remaining insulating material that was previously used to fill the trenches is removed, thus forming an array of initial semiconductor bodies 310.

[0075] It should be noted that, Figure 3c The shape of the cross section of the initial semiconductor body along the X and Y axes shown is square. This shape is only for example and is not intended to limit the shape of the initial semiconductor body in this cross section. The shape of the initial semiconductor body in this cross section may also include circles, ellipses, and approximate shapes of these shapes.

[0076] In other embodiments, the formation of the initial semiconductor body 310 may also include: first forming a plurality of trenches extending along the Y-axis in the substrate 300, filling the trenches with an insulating material (such as silicon oxide), and then forming a plurality of trenches extending along the X-axis in the substrate 300.

[0077] In some specific embodiments, trenches along the X-axis and / or Y-axis can be formed by photolithography (here and hereinafter, this can be understood as lithography-etching (LE)). Methods for filling the trenches with insulating material include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0078] Next, refer to Figure 3d Based on the requirements of subsequent semiconductor device manufacturing processes, a first isolation structure 320 and a second isolation structure 330 are formed in trenches extending along the Y-axis direction. It can be understood that the first isolation structure 320 here is similar to... Figure 1The first isolation structure 1060 serves a similar function to the second isolation structure 330. Figure 1 The role of the second isolation structure 1062 in the middle.

[0079] In some embodiments, such as Figure 3d As shown, the first isolation structure 320 may include an isolation layer 321 and a first dielectric layer 322 surrounding the isolation layer 321, wherein the isolation layer 321 may include an air gap, such as air; the material of the first dielectric layer 322 includes, but is not limited to, silicon oxide. In other embodiments, the first isolation structure 320 may also include a conductive material layer and a protective layer (…). Figure 3d (Not shown in the diagram), the conductive material layer can provide good electrostatic shielding. However, it should be noted that when the first isolation structure 320 includes a conductive material layer, the protective layer must surround the conductive material layer to prevent the conductive material layer from contacting the initial semiconductor substrate. In some specific embodiments, the methods for forming the first isolation structure 320 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD) processes.

[0080] In some embodiments, such as Figure 3d As shown, the second isolation structure 330 may include a gate structure 331 and a first dielectric layer 322 surrounding the gate structure 331. The gate structure 331 may include a gate electrode and a gate dielectric. Optionally, the gate structure 331 may further include a barrier layer located between the gate electrode and the gate dielectric. The material of the gate electrode may include, but is not limited to, tungsten; the material of the gate dielectric may include, but is not limited to, silicon oxide; and the material of the barrier layer may include, but is not limited to, titanium nitride.

[0081] In some specific embodiments, the method for forming the gate structure 331 in the second isolation structure 330 includes, but is not limited to, deposition, etching and other processes; the method for forming the first dielectric layer 322 in the second isolation structure 330 includes, but is not limited to, deposition, etching, CMP and other processes.

[0082] It should be noted that, from the appendix Figure 3a The cross-sectional diagrams shown later in the diagrams are all intermediate stages of the manufacturing process. Some of the structural features shown in the diagrams may not be the final product form of the semiconductor device. For example, the lower ends of the word lines (gate electrodes) shown in the diagram are connected together, while in the final product of the semiconductor device, the lower ends of the word lines (gate electrodes) are disconnected, forming a back-to-back structure.

[0083] Figures 4a to 4gThis is a cross-sectional schematic diagram illustrating the process of forming a conductive structure and a semiconductor substrate, as provided in an embodiment of this disclosure. It should be noted that... Figures 4a to 4g The illustrated structure is Figure 3d A magnified view of the structure within the dashed box.

[0084] refer to Figure 4a Multiple initial semiconductor bodies 310 extending along the Z-axis are formed; the multiple initial semiconductor bodies 310 are separated by a first dielectric layer 322. The specific formation method of the initial semiconductor bodies 310 can be referred to the foregoing. Figures 3a to 3d The example given is shown in the text.

[0085] refer to Figure 4b A portion of the first dielectric layer 322 is removed along the first direction, exposing a portion of the initial semiconductor body as the first initial semiconductor body 311, and the remaining portion of the initial semiconductor body as the second initial semiconductor body 312; a third dielectric layer 341 is formed covering the first initial semiconductor body 311.

[0086] In some embodiments, the size of the first initial semiconductor body 311 in a cross section perpendicular to the first direction is less than or equal to the size of the second initial semiconductor body 312 in a cross section perpendicular to the first direction.

[0087] In some embodiments, the dimension of the cross section of the first initial semiconductor body 311 at the end near the second initial semiconductor body 312 in the direction perpendicular to the Z-axis is greater than the dimension of the cross section of the first initial semiconductor body 311 at the end away from the second initial semiconductor body 312 in the direction perpendicular to the Z-axis.

[0088] refer to Figure 4c This forms a second dielectric layer 342 covering the third dielectric layer 341.

[0089] In some specific embodiments, the methods for forming the second dielectric layer 342 include, but are not limited to, processes such as PVD and CVD.

[0090] refer to Figure 4d The second dielectric layer 342 is partially removed, exposing a portion of the third dielectric layer 341. In some specific embodiments, the method for removing a portion of the second dielectric layer 342 includes, but is not limited to, dry etching.

[0091] refer to Figure 4e The third dielectric layer 341, the first initial semiconductor body 311, and a portion of the second initial semiconductor body 312 are etched away to form a plurality of first trenches 350 in the remaining second dielectric layer 342 and the first dielectric layer 322. Here, the remaining portion of the second initial semiconductor body 312 is the third initial semiconductor body 313.

[0092] In some embodiments, the etching selectivity ratios of the third dielectric layer 341 and the second dielectric layer 342 are different. Exemplarily, the material of the second dielectric layer 342 may include one or more of nitrides, such as silicon nitride, silicon oxynitride, or high-dielectric materials; the material of the third dielectric layer 341 may include oxides, such as silicon oxide.

[0093] In some embodiments, the material of the second dielectric layer 342 is different from the material of the first dielectric layer 322. For example, the material of the second dielectric layer 342 is silicon nitride or silicon boron nitride, and the material of the first dielectric layer 322 is silicon oxide.

[0094] In some embodiments, the material of the third dielectric layer 341 may be the same as the material of the first dielectric layer 322.

[0095] In some embodiments, reference Figure 4e The third initial semiconductor body 313 has an upper surface S2, which is lower than the surface of the remaining third dielectric layer 341 perpendicular to the first direction.

[0096] In some embodiments, the surface of the remaining first dielectric layer 322 is higher than the upper surface S2 of the third initial semiconductor body 313. In other words, the etching depth of the initial semiconductor body extends into the remaining first dielectric layer 322, thereby the subsequently formed metal silicide layer is formed using the initial semiconductor body located in the remaining first dielectric layer 322. Since the initial semiconductor body located in the remaining first dielectric layer 322 has not undergone etching or other processing operations, its morphology is unaffected, thus retaining its initial dimensions. That is, the dimension of the third initial semiconductor body 313 in the cross-section perpendicular to the first direction is also greater than or equal to the dimension of the first initial semiconductor body in the cross-section perpendicular to the first direction.

[0097] refer to Figure 4f A metal silicide layer 351 is formed using the third initial semiconductor substrate 313; the remaining third initial semiconductor substrate after metallization is formed into a semiconductor substrate 1030.

[0098] In some embodiments, the metal elements in the metal silicide layer 351 include, but are not limited to, tungsten, nickel, cobalt, or titanium.

[0099] As previously described, since the third initial semiconductor body 313 located in the remaining first dielectric layer 322 has not undergone etching or other processing operations, its morphology remains unaffected, thus retaining its initial dimensions. Therefore, compared to the metal silicide layer formed using the first initial semiconductor body, the metal silicide layer formed using the third initial semiconductor body 313 has a larger cross-sectional dimension perpendicular to the first direction. Based on this, without adding any additional process steps, in this embodiment of the disclosure, the metal silicide layer formed using the third initial semiconductor body 313 is such that the cross-sectional dimension of the metal silicide layer perpendicular to the first direction is the maximum cross-sectional dimension of the initial semiconductor body perpendicular to the first direction.

[0100] Compared to forming a metal silicide layer using a first initial semiconductor substrate, forming a metal silicide layer using a third initial semiconductor substrate allows for a larger metal silicide layer, thereby increasing the connection window between the metal silicide layer and the conductive layer, and also reducing contact resistance. Furthermore, forming a metal silicide layer using a third initial semiconductor substrate eliminates the need for an additional mask layer, which helps reduce manufacturing costs.

[0101] In some specific embodiments, forming a metal silicide layer 361 using a third initial semiconductor body 313 includes: metallizing at least a portion of the third initial semiconductor body 313 through a first trench 350 to form a metal silicide layer 361; and forming a semiconductor body 1030 from the remaining third initial semiconductor body after metallization.

[0102] In some embodiments, the sum of the lengths of the metal silicide layer 361 and the semiconductor body 1030 along the first direction is equal to the length of the third initial semiconductor body 313 along the first direction.

[0103] In some specific embodiments, forming a metal silicide layer 361 includes: forming an exposed surface covering the third initial semiconductor body 313 (including...) Figure 4e The initial metal layer of the second surface (S2) of the third initial semiconductor body 313 exposed in the middle; the third initial semiconductor body 313 with the initial metal layer formed is annealed to form a metal silicide layer 361.

[0104] It should be noted that the metallization process mainly takes place in semiconductor materials covered by the initial metal layer. It does not take place in non-semiconductor materials covered by the initial metal layer, such as oxide or nitride materials. Therefore, after the metal silicide layer is formed, it is generally necessary to remove the excess initial metal layer covering the non-semiconductor material.

[0105] In some embodiments, in a first direction, the metal silicide layer 361 has a first surface S3 and a second surface S4, the size of the first surface S3 being greater than or equal to the size of the second surface S4. The second surface S4 of the metal silicide layer 361 is in contact with the semiconductor body 1030, and the first surface S3 of the metal silicide layer 361 is farther from the semiconductor body 1030 relative to the second surface S4.

[0106] In some embodiments, the second dielectric layer 342 includes a third surface and a fourth surface, with the third surface closer to the first dielectric layer 322 than the fourth surface. The first surface S3 is located between the third surface and the semiconductor body 1030.

[0107] In some embodiments, the second dielectric layer 342 includes a third surface and a fourth surface, the third surface being in contact with the third dielectric layer 341, and the fourth surface being away from the third dielectric layer 341 relative to the third surface. The first surface S3 is located between the third surface and the second surface S4.

[0108] It is understandable that the first surface S3 of the metal silicide layer 361 and the upper surface S2 of the third initial semiconductor body 313 are on the same horizontal plane. In other words, the first surface S3 of the metal silicide layer 361 is... Figure 4e The upper surface S2 of the third initial semiconductor body 313. Thus, the surface of the remaining first dielectric layer 322 is higher than the first surface S3 of the metal silicide layer 361.

[0109] In some embodiments, in a second direction perpendicular to the first direction, the size of the first surface S3 is equal to the size of the second surface S4.

[0110] In some embodiments, the surface area of ​​the first surface S3 is equal to the surface area of ​​the second surface S4.

[0111] In some embodiments, the size of the metal silicide layer 361 can be further increased by thickening the third initial semiconductor body 313, such that the size of the first surface S3 of the metal silicide layer 361 is larger than the size of the second surface S4. Thickening the third initial semiconductor body 313 includes, but is not limited to: widening the first trench, forming a thickened semiconductor layer in the widened first trench, and metallizing the thickened semiconductor layer to form a metal silicide layer. The size of the thickened semiconductor layer in the second direction is larger than the size of the third initial semiconductor body in the second direction.

[0112] In some embodiments, a metal silicide layer 361 is formed in a first dielectric layer 322. Since the metal silicide layer 361 is formed using an initial semiconductor substrate (i.e., a third initial semiconductor substrate) located in the remaining first dielectric layer 322 in this embodiment, the metal silicide layer 361 is formed in the first dielectric layer 322. In other words, multiple metal silicide layers 361 are separated by the first dielectric layer 322.

[0113] It is understood that a portion of the third initial semiconductor body 313 is used to form the metal silicide layer 361, while another portion of the third initial semiconductor body 313 is used to form the semiconductor body 1030. Because the third initial semiconductor body 313 is formed in a single step from bottom to top, and the metal silicide layer 361 is used to form the conductive structure, the conductive structure and the semiconductor body 1030 share the same third initial semiconductor body 313. Therefore, the conductive structure and the semiconductor body 1030 can directly achieve self-alignment, eliminating the need for a mask layer. Thus, in this embodiment, the alignment between the conductive structure and the semiconductor body is self-aligned, offering high alignment accuracy and reducing manufacturing difficulty. Furthermore, the absence of a mask layer saves on manufacturing steps and reduces the manufacturing cost of the semiconductor device.

[0114] Here, self-alignment can be understood as the alignment of the geometric centers of the conductive structure and the semiconductor body 1030; or, the overlap of the orthographic projections of the conductive structure and the semiconductor body 1030 in a cross section perpendicular to the first direction. It should be noted that minor deviations in the geometric centers of the two due to manufacturing errors or other reasons, or minor dimensional changes (overall thickening or thinning) of the third initial semiconductor body 313 before and after metallization, are all within the scope of protection of this application.

[0115] In some embodiments, before forming the metal silicide layer 361, the method further includes removing a third dielectric layer 341 located inside the first trench 350. In some specific embodiments, the method for removing the third dielectric layer 341 located inside the first trench 350 includes, but is not limited to, dry etching.

[0116] In some embodiments, removing the third dielectric layer 341 located inside the first trench 350 is equivalent to widening the first trench 350 (from...). Figures 4e to 4f This increases the size of the conductive layer that will be formed in the first trench 350, thereby improving the connection window between the conductive layer and the storage capacitor.

[0117] It should be noted that when removing the third dielectric layer 341 located inside the first trench 350, the etching rate when etching the third dielectric layer 341 in contact with the second dielectric layer 342 is greater than the etching rate when etching the third dielectric layer 341 in contact with the first dielectric layer 322. That is, the etching rate of the third dielectric layer 341 decreases when etching to the boundary between the third dielectric layer 341 and the first dielectric layer 322. Since the etching rate is greater in the early stage (the stage of etching the third dielectric layer 341 in contact with the second dielectric layer 342) than in the later stage (the stage of etching the third dielectric layer 341 in contact with the first dielectric layer 322), after etching away the third dielectric layer 341 located inside the first trench 350, the first trench 350 becomes... Figure 4f The groove shown is wider at the top and narrower at the bottom.

[0118] refer to Figure 4g A conductive layer 362 is formed in the first trench 350, and the conductive layer 362 is connected to the metal silicide layer 361.

[0119] Here, the conductive layer 362 and the metal silicide layer 361 constitute the conductive structure 360.

[0120] In some embodiments, a portion of the conductive layer 362 is formed in the first dielectric layer 322, and another portion of the conductive layer 362 is formed in the second dielectric layer 342.

[0121] In some embodiments, the conductive layer 362 has a fifth surface S1 that contacts the metal silicide layer 361, and the contact area between the metal silicide layer 361 and the conductive layer 362 is equal to the surface area of ​​the fifth surface S1. It should be noted that minor deviations between the contact area between the metal silicide layer 361 and the conductive layer 362 and the surface area of ​​the fifth surface S1 due to manufacturing errors or process parameters are also within the scope of protection of this disclosure. Here, the contact area between the metal silicide layer 361 and the conductive layer 362 is the surface area of ​​the first surface S3 of the metal silicide layer 361. That is, the first surface S3 and the first surface S1 of the metal silicide layer 361 have the same dimensions.

[0122] In some embodiments, the conductive layer 362 includes a first conductive layer, the material of which includes, but is not limited to, titanium or titanium nitride, and the method of forming the conductive layer 362 includes, but is not limited to, processes such as PVD, CVD, and ALD.

[0123] In other embodiments, conductive layer 362 further includes a second conductive layer. The second conductive layer is located on the side of the first conductive layer away from the metal silicide layer 361. In some specific embodiments, the material of the second conductive layer includes, but is not limited to, tungsten or copper.

[0124] In some embodiments, the conductive layer 362 is located on the side of the metal silicide layer 361 away from the semiconductor body 1030; the contact area between the metal silicide layer 361 and the conductive layer 362 is greater than or equal to the contact area between the metal silicide layer 361 and the semiconductor body 1030.

[0125] The conductive layer 362 also has a sixth surface S5 located away from the metal silicide layer 361. Here, since the padding layer 341 located inside the first trench 350 was removed before the conductive layer 362 was formed, the top dimension of the conductive layer 362 was increased to a certain extent, that is, the size of the sixth surface S5 of the conductive layer 362 is larger than the size of the fifth surface S1. This improves the connection window between the conductive structure and the storage capacitor, and can also further reduce the contact resistance.

[0126] It should be noted that since the conductive structure shares the same semiconductor pillar as the semiconductor body used to form the vertical transistor, doping of the transistor's source and drain, whether performed before or after metallization, will leave dopant ions in the conductive structure. Based on this, the semiconductor body extends along the first direction; the conductive structure contains dopant ions, and the type of these dopant ions is the same as the doping type of the dopant ions at opposite ends of the semiconductor body along the first direction.

[0127] This completes the fabrication of the conductive structure and the semiconductor body. Next, we will introduce the fabrication of other structures of the semiconductor device.

[0128] In some embodiments, a memory structure is formed on the side of the conductive structure away from the semiconductor body on both sides along the first direction; the method for forming the memory structure is relatively mature and will not be described in detail here.

[0129] In some specific embodiments, the storage structure includes a storage capacitor; forming the storage structure includes: forming a storage capacitor coupled to the conductive structure, the storage capacitor being coupled to the semiconductor body through the conductive structure.

[0130] In some embodiments, the storage capacitor includes a cup-shaped capacitor (CUP), a cylindrical capacitor (CYL), or a pillar-shaped capacitor (PIL). The shape of the storage capacitor can be selected according to actual needs, and this disclosure does not limit it.

[0131] In some embodiments, the method further includes: forming word lines on at least one side of the semiconductor body; and forming bit lines on the surface of the semiconductor body that is away from the conductive structure among two surfaces disposed opposite each other along the first direction.

[0132] Here, word lines can extend along a third direction, and bit lines can extend along a second direction.

[0133] In some embodiments, forming word lines on at least one side of a semiconductor body includes: forming word lines located on one side of the semiconductor body; forming word lines located on two opposite sides of the semiconductor body; and forming word lines surrounding the side of the semiconductor body.

[0134] It is understood that the conductive structure in this embodiment can be applied to different word line (gate structure) scenarios. For example, the conductive structure in this embodiment can be applied to a scenario where two word line structures corresponding to two adjacent semiconductor bodies are arranged back-to-back. The accompanying drawings in this embodiment illustrate a back-to-back arrangement scenario.

[0135] In some specific embodiments, two adjacent semiconductor bodies form a semiconductor body group, and the two semiconductor bodies in a semiconductor body group are separated by a first isolation structure (i.e. Figure 3d The first isolation structure 320) separates adjacent semiconductor body groups; the second isolation structure separates adjacent semiconductor body groups. Figure 3d The final form corresponding to the second isolation structure 330 (the lower end of the gate electrode is disconnected); forming a word line on at least one side of the semiconductor body includes: forming the word line on one side away from the first isolation structure on each of the two sides of the corresponding semiconductor body in the semiconductor body group.

[0136] In this embodiment of the disclosure, by cleverly utilizing the initial semiconductor body, self-alignment between the conductive structure and the semiconductor body can be achieved. This increases the alignment accuracy between the first part of the conductive structure and the semiconductor body, reduces the alignment difficulty between the two, improves the reliability of the semiconductor device, saves manufacturing time and cost, and increases process speed and efficiency. On the other hand, the metal silicide layer, as the material of the conductive structure between the semiconductor body and the memory structure, has a low resistivity, which can achieve better electrical connection between the semiconductor body and the memory structure, and improve the reliability of the semiconductor device.

[0137] Figure 5 A schematic diagram of the structure of a semiconductor device provided in this disclosure embodiment. Figure 2 ;like Figure 5 As shown, the semiconductor device 100 includes a plurality of semiconductor bodies 1030; the plurality of semiconductor bodies 1030 are separated by a first dielectric layer; a plurality of conductive structures 360 are located at one end of a semiconductor body 1030 along a first direction and coupled to the semiconductor body 1030; the first direction is the extension direction of the semiconductor body 1030; the conductive structure 360 ​​includes at least a metal silicide layer 361 extending along the first direction, and the metal silicide layers 361 are separated by the first dielectric layer.

[0138] In some embodiments, the conductive structure 360 ​​further includes a conductive layer 362 located on the side of the metal silicide layer 361 away from the semiconductor body 1030; the semiconductor device further includes a second dielectric layer 342 located between the plurality of conductive layers 362; the second dielectric layer 342 is made of a different material than the first dielectric layer.

[0139] In some embodiments, a plurality of metal silicide layers 361 and a plurality of semiconductor bodies 1030 are located in the same dielectric layer (first dielectric layer).

[0140] In some embodiments, in a first direction, the metal silicide layer 361 has a first surface and a second surface, the first surface being away from the semiconductor body 1030 relative to the second surface; the second dielectric layer 342 includes a third surface and a fourth surface, the third surface being close to the first dielectric layer relative to the fourth surface; the first surface is located between the third surface and the semiconductor body 1030.

[0141] In some embodiments, in a second direction perpendicular to the first direction, the size of the first surface is greater than or equal to the size of the second surface.

[0142] In some embodiments, a portion of the conductive layer 362 is formed in the first dielectric layer, and another portion of the conductive layer 362 is formed in the second dielectric layer 342.

[0143] In some embodiments, the conductive layer 362 has a fifth surface that contacts the metal silicide layer 361, and the contact area between the metal silicide layer 361 and the conductive layer 362 is less than or equal to the surface area of ​​the fifth surface.

[0144] In some embodiments, the semiconductor device further includes a third dielectric layer located between the first dielectric layer and the second dielectric layer 342; the surface of the third dielectric layer near the metal silicide layer 361 is higher than the first surface.

[0145] In some embodiments, a portion of the conductive layer 362 is formed in the third dielectric layer, and another portion of the conductive layer 362 is formed in the second dielectric layer 342.

[0146] In some embodiments, the metal element in the metal silicide layer includes nickel, cobalt, or titanium.

[0147] In some embodiments, the semiconductor body 1030 has a source 1038 and a drain 1040 at opposite ends along a first direction; one of the source 1038 and the drain 1040 is coupled to a metal silicide layer 361; the other of the source 1038 and the drain 1040 is coupled to a corresponding bit line 1023.

[0148] In some embodiments, the system further includes a plurality of storage capacitors 1028, each of which is coupled to the semiconductor body 1030 via a conductive structure 360.

[0149] In some embodiments, the metal silicide layer 361 is in contact with the semiconductor body 1030, and the conductive layer 362 is in contact with the storage capacitor 1028.

[0150] It should be noted that, Figure 5 Other structures shown in the image can be referenced. Figure 1 To understand it.

[0151] Compared to forming a metal silicide layer using a first initial semiconductor substrate, the metal silicide layer formed using a third initial semiconductor substrate in this embodiment can achieve a larger metal silicide layer. This increases the connection window between the metal silicide layer and the conductive layer, and also reduces contact resistance. Furthermore, forming the metal silicide layer using a third initial semiconductor substrate eliminates the need for an additional mask layer, thus reducing manufacturing costs. Finally, the metal silicide layer, as the material for the conductive structure between the semiconductor substrate and the storage capacitor, has low resistivity, enabling better electrical connection between the semiconductor substrate and the storage capacitor and improving the reliability of the semiconductor device.

[0152] This disclosure provides another memory system, including: a semiconductor device as described in the above embodiments; and a memory controller connected to the semiconductor device and used to control the semiconductor device.

[0153] In some embodiments, the semiconductor device is a memory device, specifically a DRAM memory device.

[0154] Figure 6 A block diagram of an exemplary system 600 having a memory device according to some aspects of this disclosure is shown. System 600 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 6As shown, system 600 may include a host 608 and a memory system 602, the memory system 602 having one or more memory devices 604 and a memory controller 606. The host 608 may be a processor of an electronic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)). The host 608 may be configured to send data to or receive data from the memory device 604. The memory controller 606 is coupled to the memory device 604 and the host 608 and is configured to control the memory device 604. The memory controller 606 may manage the data stored in the memory device 604 and communicate with the host 608.

[0155] The memory controller 606 can be configured to control the operation of the memory device 604, such as read, erase, write, and refresh operations. In some embodiments, the memory controller 606 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 604. The memory controller 606 can also perform any other suitable functions, such as formatting the memory device 604. The memory controller 606 can communicate with external devices (e.g., host 608) according to a specific communication protocol.

[0156] In some specific embodiments, one or more memory devices 604 and memory controller 606 can be integrated into various types of storage devices. For example, multiple memory devices 604 can be integrated into a memory module; the memory controller 606 can be integrated into the northbridge of the motherboard or directly into the CPU. In other words, the memory system 602 can be implemented and packaged into different types of terminal electronic products.

[0157] Figure 7 This is a schematic diagram of an exemplary DRAM memory device according to an embodiment of the present disclosure; Figure 7 The right side shows the circuitry of a memory cell in a DRAM. Each DRAM chip 604 (Die) includes a semiconductor structure 701 with memory cells and peripheral circuitry 702. Each memory cell includes a transistor T and a capacitor C. The primary function of the memory cell is to represent a binary bit (1 or 0) by the amount of charge stored in the capacitor. The memory cells are arranged in an array, which can be viewed as a typical mesh structure. The memory array uses rows and columns to specify addresses. By specifying the intersection of rows and columns (by specifying the row and column addresses of the DRAM), the memory controller can independently access each memory cell in the DRAM chip and perform read or write operations on the stored data.

[0158] In some embodiments, the semiconductor structure 701 includes multiple memory banks, each memory bank is divided into multiple memory groups, each memory group may include multiple memory blocks, each memory block includes multiple rows of memory cells and multiple columns of memory cells, each row of memory cells is coupled to a corresponding word line, and each column of memory cells is coupled to a corresponding bit line; the peripheral circuit 702 includes a series of complementary metal-oxide-semiconductor (CMOS) control circuits; for example, this series of CMOS control circuits includes: control circuits corresponding to each memory block, such as sensing amplifier circuits (SA) and word-line driver circuits (WLD); control circuits corresponding to each memory bank, such as row decoders, column decoders, etc.; and control circuits corresponding to all memory banks, such as command buffers, command decoders, address buffers, data buffers, mode registers, etc.

[0159] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0160] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0161] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Multiple semiconductor bodies; the multiple semiconductor bodies are separated by a first dielectric layer; Multiple conductive structures are located at one end of the semiconductor body along a first direction and coupled to the semiconductor body; the first direction is the extension direction of the semiconductor body; The conductive structure includes at least a metal silicide layer extending along the first direction, and the plurality of metal silicide layers are separated by the first dielectric layer.

2. The semiconductor device according to claim 1, characterized in that, The conductive structure further includes a conductive layer located on the side of the metal silicide layer away from the semiconductor body; The semiconductor device further includes a second dielectric layer located between the plurality of conductive layers; the second dielectric layer and the first dielectric layer are made of different materials.

3. The semiconductor device according to claim 2, characterized in that, In the first direction, the metal silicide layer has a first surface and a second surface, the first surface being away from the semiconductor body relative to the second surface; the second dielectric layer includes a third surface and a fourth surface, the third surface being close to the first dielectric layer relative to the fourth surface; The first surface is located between the third surface and the semiconductor body.

4. The semiconductor device according to claim 3, characterized in that, In a second direction perpendicular to the first direction, the size of the first surface is greater than or equal to the size of the second surface.

5. The semiconductor device according to claim 2, characterized in that, A portion of the conductive layer is formed in the first dielectric layer, and another portion of the conductive layer is formed in the second dielectric layer.

6. The semiconductor device according to claim 2, characterized in that, The conductive layer has a fifth surface that contacts the metal silicide layer, and the contact area between the metal silicide layer and the conductive layer is equal to the surface area of ​​the fifth surface.

7. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes a third dielectric layer located between the first dielectric layer and the second dielectric layer; The surface of the third dielectric layer near the metal silicide layer is higher than the first surface.

8. The semiconductor device according to claim 7, characterized in that... A portion of the conductive layer is formed in the third dielectric layer, and another portion of the conductive layer is formed in the second dielectric layer.

9. The semiconductor device according to claim 1, characterized in that, The metal element in the metal silicide layer includes tungsten, nickel, cobalt, or titanium.

10. The semiconductor device according to claim 1, characterized in that, The semiconductor body has a source and a drain at opposite ends along the first direction; one of the source and the drain is coupled to the metal silicide layer; the other of the source and the drain is coupled to a corresponding bit line.

11. The semiconductor device according to claim 1, characterized in that, Also includes: Multiple storage capacitors, each of which is coupled to the semiconductor body through the conductive structure.

12. The semiconductor device according to claim 11, characterized in that, The metal silicide layer is in contact with the semiconductor body, and the conductive layer is in contact with the storage capacitor.

13. A method for fabricating a semiconductor device, characterized in that, The method includes: Multiple conductive structures are formed, wherein each conductive structure includes at least a metal silicide layer; Multiple semiconductor bodies are formed, the semiconductor bodies extending along the first direction, and the multiple semiconductor bodies are separated by a first dielectric layer; the semiconductor bodies are located on one side of the conductive structure along the first direction and are connected to the metal silicide layer; The plurality of metal silicide layers are separated by the first dielectric layer.

14. The method according to claim 13, characterized in that, Forming the semiconductor body and the conductive structure includes: Multiple initial semiconductor bodies are formed; the multiple initial semiconductor bodies are separated by the first dielectric layer; A portion of the first dielectric layer is removed along the first direction, exposing a portion of the initial semiconductor body, which is designated as the first initial semiconductor body, and the remaining portion of the initial semiconductor body is designated as the second initial semiconductor body; the dimension of the first initial semiconductor body in a cross-section perpendicular to the first direction is less than or equal to the dimension of the second initial semiconductor body in a cross-section perpendicular to the first direction. The first initial semiconductor body and a portion of the second initial semiconductor body are etched away, and the remaining portion of the second initial semiconductor body becomes the third initial semiconductor body. The metal silicide layer is formed using the third initial semiconductor substrate.

15. The method according to claim 14, characterized in that, The surface of the remaining first dielectric layer is higher than the surface of the third initial semiconductor body.

16. The method according to claim 14, characterized in that, After removing a portion of the first dielectric layer along the first direction, the method further includes: A third dielectric layer is formed covering the first initial semiconductor body; A second dielectric layer is formed covering the third dielectric layer; Remove a portion of the second dielectric layer to expose a portion of the first initial semiconductor body.

17. The method according to claim 16, characterized in that, The etching process removes the first initial semiconductor body and a portion of the second initial semiconductor body, including: Etching removes portions of the third dielectric layer, the first initial semiconductor body, and a portion of the second initial semiconductor body to form a plurality of first trenches in the remaining second dielectric layer and the first dielectric layer.

18. The method according to claim 17, characterized in that, Forming the metal silicide layer using the third initial semiconductor substrate includes: At least a portion of the third initial semiconductor body is metallized through the first trench to form a metal silicide layer; the remaining third initial semiconductor body after metallization forms the semiconductor body.

19. The method according to claim 18, characterized in that, Forming the conductive structure further includes: A conductive layer is formed in the first trench, and the conductive layer is connected to the metal silicide layer.

20. The method according to claim 13, characterized in that, The metal element in the metal silicide layer includes tungsten, nickel, cobalt, or titanium.

21. The method according to claim 13, characterized in that, The method further includes: A storage capacitor is formed coupled to the conductive structure, and the storage capacitor is coupled to the semiconductor body through the conductive structure.

22. A memory system, characterized in that, include: The semiconductor device as described in any one of claims 1-12; as well as, A memory controller, connected to the semiconductor device, and used to control the semiconductor device.

Images