Memory device and method of manufacturing the same

Abstract

A memory device includes: a first substrate including a cell region and a peripheral region disposed around the cell region; a memory cell array disposed in the cell region of the first substrate; a second substrate disposed on the memory cell array; peripheral transistors disposed on the second substrate and connected to the memory cell array; a first insulating layer disposed in the trench in the peripheral region of the first substrate, and including a high density plasma oxide; and a second insulating layer on the first insulating layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2024-0165843, filed on November 20, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure generally relate to semiconductor technology, and more specifically, to a memory device and a method of manufacturing the same. Background Technology

[0004] Memory devices have garnered attention as crucial components in the electronics industry due to their characteristics such as miniaturization, versatility, and typically low manufacturing costs. With the rapid development of the electronics industry, memory devices are becoming increasingly highly integrated. Higher integration necessitates reducing wiring linewidth and / or the size of the memory cells included within the device. However, this has become increasingly challenging and requires new structures, materials, and technologies for further improvement.

[0005] One method for enabling higher integration of memory devices includes a process in which a wafer in which memory cells can be disposed and a wafer in which peripheral circuitry can be disposed are separately manufactured, and then the two wafers are bonded together to manufacture the memory device. However, using wafer bonding to manufacture memory devices requires more efficient placement of various components and circuitry within the memory device. Summary of the Invention

[0006] Various embodiments of this disclosure aim to provide a memory device, including bonding two semiconductor structures together in a manner capable of preventing memory cell degradation, and a method of manufacturing a semiconductor device. In embodiments of this disclosure, a memory device may include: a first substrate including cell regions and peripheral regions disposed around the cell regions; a memory cell array disposed in the cell regions of the first substrate; a second substrate disposed on the memory cell array; peripheral transistors disposed on the second substrate and connected to the memory cell array; a first insulating layer disposed in trenches located in the peripheral regions of the first substrate and comprising high-density plasma oxide; and a second insulating layer on the first insulating layer.

[0007] In embodiments of this disclosure, a storage device may include: a first substrate; a memory cell array disposed on the first substrate; a first insulating layer disposed in a trench in the first substrate, surrounding a region where the memory cell array is disposed and comprising high-density plasma oxide; and a second insulating layer covering the upper surface of the first insulating layer.

[0008] In embodiments of this disclosure, a memory device is provided, the memory device including a first semiconductor structure and a second semiconductor structure bonded to the first semiconductor structure, wherein the first semiconductor structure includes: a first substrate including cell regions and peripheral regions surrounding the cell regions; a memory cell array disposed in the cell regions of the first substrate; a first insulating layer disposed in the peripheral regions of the first substrate; and a second insulating layer covering the upper surface of the first insulating layer, wherein the second semiconductor structure includes: a second substrate; and peripheral transistors disposed on the second substrate and connected to the memory cell array, wherein at least one of the peripheral transistors overlaps with the cell regions.

[0009] In embodiments of this disclosure, a method for manufacturing a memory device is provided, the memory device including a first semiconductor structure having a memory cell array and a second semiconductor structure having peripheral transistors. The method may include: forming a trench in a peripheral region of a first substrate including a cell region and a peripheral region surrounding the cell region; forming a first insulating layer including a high-density plasma oxide in the trench; forming a memory cell array in the cell region of the first substrate; and forming peripheral transistors on the memory cell array for connection to the memory cell array.

[0010] According to embodiments of this disclosure, degradation of storage cells can be prevented. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0012] Figure 2 This is a view illustrating the circuit configuration of a storage device according to an embodiment of the present disclosure.

[0013] Figure 3 This is a view showing the planar structure of a storage device according to an embodiment of the present disclosure.

[0014] Figure 4 This is a view illustrating an example of the cross-sectional structure of a storage device according to an embodiment of the present disclosure.

[0015] Figure 5 It is shown Figure 4 A view of the storage device shown.

[0016] Figure 6 This is a view showing another cross-sectional structure of the storage device according to an embodiment of the present disclosure.

[0017] Figure 7 It is shown Figure 6 A view of the storage device shown.

[0018] Figure 8 and Figure 9 It is shown Figure 6 Views of other embodiments of the storage device shown.

[0019] Figure 10 This is a view showing another cross-sectional structure of a storage device according to an embodiment of the present disclosure.

[0020] Figure 11 It is shown Figure 10 A view of an embodiment of the storage device shown. Detailed Implementation

[0021] Embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the technical concepts disclosed in this disclosure. Embodiments based on these technical concepts can be implemented in various forms, and the scope of this disclosure is not limited to the embodiments described herein.

[0022] Crosshairs in all figures illustrate corresponding or similar areas between figures, rather than indicating material associated with the areas.

[0023] When one element is identified as “connected” or “coupled” to another element, these elements can be directly connected or coupled, or connected or coupled through an intermediate element between the elements. When two elements are identified as “directly connected” or “directly coupled”, one element is directly connected or directly coupled to the other element, and there is no intermediate element between the two elements.

[0024] When a component is identified as "on another component", "above another component", "below another component" or "under another component", these components can be in direct contact with each other, or an intermediate component can be disposed between these components.

[0025] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “under,” “below,” “above,” “on,” “side,” “upper,” “topmost,” “lower,” “bottommost,” “front,” “back,” “left,” “right,” “column,” “row,” and “horizontal,” as well as other terms that suggest relative spatial relationships or orientations, are used for the purpose of description or reference to the accompanying drawings only and are not intended to be limiting. Other spatial relationships or orientations not shown in the drawings or described in the specification are possible within the scope of this disclosure.

[0026] Terms such as "first" and "second" are used to distinguish various elements, rather than to imply the size, order, priority, number, or importance of the elements. For example, in one embodiment, a first element may be referred to as a second element, while in another embodiment, a second element may be referred to as a first element.

[0027] In the specification, when an element included in an embodiment is described in the singular, the element can be interpreted as including a plurality of elements that perform the same or similar functions.

[0028] In the accompanying drawings, three directions parallel to the upper surface of the substrate are defined as the first direction FD, the second direction SD, and the third direction TD, respectively, and a direction projecting vertically from the upper surface of the substrate is defined as the fourth direction VD. The first direction FD and the second direction SD may be substantially perpendicular to each other. The fourth direction VD is a direction perpendicular to the first direction FD, the second direction SD, and the third direction TD. In the following description, the term "vertical" or "vertical direction" will be used to have substantially the same meaning as the fourth direction VD. In the accompanying drawings, the direction indicated by the arrow and the direction opposite to it represent the same direction.

[0029] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0030] The storage device 100 may include a storage cell array 110, a sense amplifier (SA) 120, a row decoder 130, a column decoder 140, an input / output (I / O) circuit 150, and control logic 160.

[0031] The storage cell array 110 includes multiple storage cells, which can be used, for example, to store data.

[0032] Sensing amplifier 120 is connected to a plurality of memory cells included in memory cell array 110. In operation, sensing amplifier 120 can detect (sensor) and amplify signals (e.g., small voltage changes) when reading data stored in a memory cell or writing data to a memory cell. For example, when writing data, i.e., during a write operation, sensing amplifier 120 can amplify the signal received from input / output circuitry 150 and provide the amplified signal to the memory cells in memory cell array 110 to ensure that data is accurately written and stored. During a read operation, when reading data, sensing amplifier 120 can sense the data stored in the memory cells, amplify the signal for the sensed data, and provide the amplified signal to input / output circuitry 150.

[0033] The row decoder 130 can select the corresponding word line in the memory cell array 110 based on a specified row address. The row decoder 130 can generate a word line drive signal to drive the selected word line.

[0034] The column decoder 140 can decode the column address to activate the column select signal and select multiple bit lines based on a column select signal.

[0035] When a write operation is performed, the input / output circuit 150 can write input data to the memory cell. When a read operation is performed, the input / output circuit 150 can sense, amplify, and output the data loaded on the input / output lines.

[0036] Control logic 160 can control the peripheral circuits of storage device 100 according to received commands. These peripheral circuits include row decoder 130 and column decoder 140.

[0037] The above reference Figure 1 The components 110, 120, 130, 140, 150, and 160 of the described storage device 100 illustrate only one example of a possible configuration of the storage device. Many variations of the storage device can be implemented, including embodiments in which one or more of the aforementioned components may be omitted. Alternatively, in some embodiments of the storage device, one or more of the aforementioned components may be integrated with another component. Depending on the circumstances, the storage device 100 may also include at least one component in addition to the aforementioned components.

[0038] Figure 2 This is a view illustrating the circuit configuration of a storage device according to an embodiment of the present disclosure.

[0039] refer to Figure 2The storage device 100 may include a storage cell array 110, word lines WL, bit lines BL, storage cells MC, a first sense amplifier 120a, a second sense amplifier 120b, a first sub-word line driver 210a, and a second sub-word line driver 210b.

[0040] Each of the bit line BL and word line WL connects to a plurality of memory cells MC in the memory cell array 110. The bit line BL and word line WL intersect each other. The memory cells MC can be positioned at the points where the bit line BL and word line WL intersect each other. The bit line BL and word line WL intersect at each memory cell MC, creating a grid-like structure.

[0041] Bit lines BL can be connected to either the first sense amplifier 120a or the second sense amplifier 120b. Two adjacent bit lines BL can be connected to the first sense amplifier 120a and the second sense amplifier 120b, respectively. For example, a bit line BL connected to the first sense amplifier 120a can be positioned between bit lines BL connected to the second sense amplifier 120b. A bit line BL connected to the first sense amplifier 120a can be adjacent to a bit line BL connected to the second sense amplifier 120b.

[0042] The word line WL can be connected to either the first sub-word line driver 210a or the second sub-word line driver 210b. Each of the first sub-word line driver 210a and the second sub-word line driver 210b can be connected from... Figure 1 The line decoder 130 shown receives the signals required to drive word lines WL and can drive word lines WL selected from among the word lines WL. Two adjacent word lines WL can be connected to a first sub-word line driver 210a and a second sub-word line driver 210b, respectively. For example, a word line WL connected to the first sub-word line driver 210a can be positioned between word lines WL connected to the second sub-word line driver 210b. A word line WL connected to the first sub-word line driver 210a can be adjacent to a word line WL connected to the second sub-word line driver 210b.

[0043] Figure 3 This is a view showing the planar structure of a storage device according to an embodiment of the present disclosure.

[0044] refer to Figure 3 The storage device 100 may include a cell region CR and a peripheral region PR. The cell region CR is where a cell is provided with a peripheral region PR. Figure 1 and Figure 2 The area of ​​the memory cell array 110 shown is an outer region PR, which is a region in which peripheral circuitry for transmitting various voltages or signals to the memory cells disposed in the cell region CR is provided. The outer region PR is disposed around the cell region CR. In an embodiment, the outer region PR may surround the cell region CR.

[0045] The storage device 100 may include bit lines BL, word lines WL, and active regions 310.

[0046] Active regions 310 may be spaced apart from each other in a first direction FD and a second direction SD. Active regions 310 may extend in a third direction TD. Bit lines BL and word lines WL may be configured to intersect active regions 310. Bit lines BL extend in the second direction SD. Word lines WL extend in the first direction FD. Bit lines BL and word lines WL may be configured to overlap with cell regions CR. In one embodiment, at least some of the bit lines BL may extend along the second direction SD to a peripheral region PR. In one embodiment, at least some of the word lines WL may extend along the first direction FD to a peripheral region PR.

[0047] Figure 3 The diagram illustrates one bit line BL and one word line WL that can be set in a single cell region CR, but this is for ease of description. For example, the number of bit lines BL and word lines WL set in cell region CR can be greater than one. Bit lines BL and word lines WL can be set in all cell regions CR.

[0048] The first insulating layer 300 can be disposed in the peripheral region PR. The first insulating layer 300 can be disposed between adjacent cell regions CR. In one embodiment, the first insulating layer 300 can surround the cell region CR.

[0049] Figure 4 This is a view showing the cross-sectional structure of a storage device according to an embodiment of the present disclosure.

[0050] refer to Figure 4 The memory device 100 may include a first semiconductor structure S1 and a second semiconductor structure S2 disposed on the first semiconductor structure. The first semiconductor structure S1 and the second semiconductor structure S2 may be fabricated on different wafers. In embodiments, the processes for fabricating the first semiconductor structure S1 may be performed separately from the processes for fabricating the second semiconductor structure S2. The second semiconductor structure S2 may be bonded to the upper surface of the first semiconductor structure S1. The boundary between the first semiconductor structure S1 and the second semiconductor structure S2 may be referred to as a bonding interface.

[0051] The first semiconductor structure S1 may include a first substrate 410, a memory cell array 110, a memory cell MC, a first insulating layer 300, and a first interlayer insulating layer 430.

[0052] In the cell region CR, a memory cell array 110, including memory cells MC, can be disposed on a first substrate 410. In the peripheral region PR, a first insulating layer 300 is disposed in the first substrate 410. In one embodiment, the first insulating layer 300 may surround the region where the memory cell array 110 is disposed. A first interlayer insulating layer 430 is disposed on the memory cell array 110.

[0053] A second semiconductor structure S2 is disposed on the first semiconductor structure S1. The second semiconductor structure S2 may include a second substrate 420, a first sub-word line driver 210a, and a second interlayer insulating layer 440.

[0054] A first sub-word line driver 210a may be disposed on a second substrate 420. In one embodiment, the first sub-word line driver 210a may be disposed in a peripheral region PR. The first sub-word line driver 210a may include a first peripheral transistor TR1. The first peripheral transistor TR1 may constitute the first sub-word line driver 210a. A second interlayer insulating layer 440 may be disposed on the second substrate 420 and the first sub-word line driver 210a. Although it is shown that the first sub-word line driver 210a may be disposed on the second substrate 420, this is provided by way of example only. That is, the second sub-word line driver 210b (see Figure 2 It can be set on the second substrate 420.

[0055] The memory cell MC can be electrically connected to the first peripheral transistor TR1. For example, a memory cell MC can be connected to a word line WL, and can be electrically connected to the first peripheral transistor TR1 through the word line WL.

[0056] Figure 5 It is shown Figure 4 A detailed view of the storage device shown.

[0057] refer to Figure 5 The memory device 100 may include a first semiconductor structure S1, a second semiconductor structure S2 disposed on the first semiconductor structure S1, and word line connection contacts 560 extending within the first semiconductor structure S1 and the second semiconductor structure S2. The first semiconductor structure S1 may include a first substrate 410, an isolation layer 501, a gate structure 510, a third insulating layer 505, a bit line contact 506, a bit line BL, a lower contact plug 508, an upper contact plug 509, a landing pad 518, a capacitor 530, a support layer 550, a fourth insulating layer 521, a first contact 581, a first wiring 591, an inner insulating layer 502, a first insulating layer 300, a second insulating layer 503, and a first interlayer insulating layer 430.

[0058] The first substrate 410 may include a semiconductor substrate, such as a silicon wafer or an SOI (silicon-on-insulator) wafer. The first substrate 410 may include a III-V group semiconductor substrate, such as a compound semiconductor substrate like gallium arsenide (GaAs). The first substrate 410 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof.

[0059] The first substrate 410 may include at least one isolation layer 501 in the cell region CR and the peripheral region PR. The isolation layer 501 may be formed using a trench isolation technique such as shallow trench isolation (STI). The isolation layer 501 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or combinations thereof.

[0060] In the cell region CR, the gate structure 510 can be buried in the first substrate 410. The gate structure 510 may include a word line WL, a gate capping layer 512, and a gate insulating layer 513. The upper surface of the word line WL may be located at a level lower than the upper surface of the first substrate 410. The word line WL may be a buried gate or a buried word line. The gate capping layer 512 may be disposed on the word line WL. The gate insulating layer 513 may surround the side surface of the word line WL, the side surface of the gate capping layer 512, and the bottom surface of the word line WL.

[0061] The word line WL may include a conductive material, such as a metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof. The gate capping layer 512 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. The gate insulating layer 513 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof.

[0062] The third insulating layer 505, bit line contact 506, and contact plugs 508 and 509 can be disposed on the first substrate 410.

[0063] In the cell region CR, a bit line BL can be disposed on the bit line contact 506. The bit line BL can extend in a direction perpendicular to the word line WL. The bit line BL may not contact the contact plugs 508 and 509. An insulating layer may be additionally disposed between the bit line BL and the contact plugs 508 and 509. A landing pad 518 and a fourth insulating layer 521 may be disposed on the upper contact plug 509. The landing pad 518 may overlap with the contact plug 509 in the vertical direction VD.

[0064] Bit line contacts 506, bit line BL, contact plugs 508 and 509, and landing pad 518 may include conductive materials such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.

[0065] The lower electrode 531, dielectric layer 532, upper electrode 533, and support layer 550 can be disposed on the fourth insulating layer 521 and landing pad 518. The lower electrode 531, dielectric layer 532, and upper electrode 533 can constitute the capacitor 530 of the memory cell.

[0066] The lower electrode 531 may overlap with the landing pad 518 in the vertical direction VD. A support layer 550 may be disposed on the side surface of the lower electrode 531. The support layer 550 surrounds the side surface of the lower electrode 531. The support layer 550 disposed on the side surface of one lower electrode 531 may be separable from the support layer 550 disposed on the side surface of the other lower electrode 531.

[0067] The dielectric layer 532 can be configured to cover the surface of the lower electrode 531 and the surface of the support layer 550. The upper electrode 533 can be disposed on the dielectric layer 532. The upper surface of the upper electrode 533 can be located at a higher level than the upper surface of the lower electrode 531.

[0068] The lower electrode 531 and the upper electrode 533 may include conductive materials such as metals, metal oxides, metal nitrides, metal silicides, polycrystalline silicon, conductive carbon, or combinations thereof. The support layer 550 may include, but is not limited to, silicon nitride or silicon nitride carbon. The dielectric layer 532 may include a high-k dielectric, silicon oxide, silicon nitride, or combinations thereof.

[0069] A first interlayer insulating layer 430 may be disposed on the upper electrode 533. A first contact 581 may pass through the first interlayer insulating layer 430 and may be connected to the upper electrode 533. A first wiring 591 may be disposed on the first contact 581.

[0070] In the peripheral region PR, the first substrate 410 includes at least one trench TRE. An inner insulating layer 502, a first insulating layer 300, and a second insulating layer 503 may be disposed in the trench TRE. In one embodiment, the inner insulating layer 502, the first insulating layer 300, and the second insulating layer 503 may surround the region where the memory cell array 110 is disposed. The inner insulating layer 502 may be disposed on the side and bottom surfaces of the trench TRE. The inner insulating layer 502 may include an oxide.

[0071] A first insulating layer 300 may be disposed on the inner liner insulating layer 502. The first insulating layer 300 may fill the interior of the trench TRE. The first insulating layer 300 may include hydrogen. The first insulating layer 300 may be a layer with a higher hydrogen supply capacity than other layers. The first insulating layer 300 may include an oxide with a high hydrogen content. In one embodiment, the first insulating layer 300 may include a high-density plasma (HDP) oxide.

[0072] A second insulating layer 503 may be disposed on the first insulating layer 300. The second insulating layer 503 may cover the entire upper surface of the first insulating layer 300. In one embodiment, the upper surface of the second insulating layer 503 may be formed to be substantially the same plane as the upper surface of the first substrate 410. In one embodiment, the second insulating layer 503 may comprise silicon nitride.

[0073] Word lines WL can be disposed on the second insulating layer 503. In one embodiment, word lines WL can be located on the upper surface of the first substrate 410 in at least a portion of the peripheral region PR. Additionally, in one embodiment, word lines WL can extend into the peripheral region PR along a first direction FD. Furthermore, in one embodiment, word lines WL can overlap with the first insulating layer 300.

[0074] A word line connection contact 560 and a first interlayer insulating layer 430 may be disposed on the word line WL. The word line connection contact 560 penetrates the first interlayer insulating layer 430 and connects to the word line WL. The word line connection contact 560 contacts the upper surface of the word line WL and extends in the vertical direction VD. The word line connection contact 560 may include a conductive material, such as a metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof.

[0075] The second semiconductor structure S2 can be disposed on the first semiconductor structure S1. The second semiconductor structure S2 may include a second substrate 420, a second interlayer insulating layer 440, a second contact 582, a third contact 583, a second wiring 592, a third wiring 593, a first peripheral transistor TR1, and a source contact 574 and a drain contact 575.

[0076] The second substrate 420 may be disposed on the first semiconductor structure S1. In one embodiment, the second substrate 420 may comprise the same material as the material forming the first substrate 410.

[0077] In the cell region CR, a second contact 582 is provided that penetrates the second substrate 420. The second contact 582 penetrates the second substrate 420 in the vertical direction VD and contacts the upper surface of the first wiring 591.

[0078] The second wiring 592 is connected to the second contact 582. The third contact 583 can be disposed on the second wiring 592. The third wiring 593 is connected to the third contact 583. A second interlayer insulating layer 440 covering the second contact 582, the second wiring 592, the third contact 583, and the third wiring 593 can be disposed on the second substrate 420.

[0079] In the peripheral region PR, the word line connection contact 560 penetrates the second substrate 420. The word line connection contact 560 penetrates the second substrate 420 and contacts the lower surface of the second wiring 592.

[0080] The first peripheral transistor TR1 can be disposed on the second substrate 420. The first peripheral transistor TR1 includes a gate electrode 570, a gate insulating layer 571, a source region 572, and a drain region 573. The first peripheral transistor TR1 is... Figure 4 The transistors included in the first sub-word line driver 210a shown. In an embodiment, the first peripheral transistor TR1 may be disposed in the peripheral region PR.

[0081] Source contact 574 is connected to source region 572 and second wiring 592. Drain contact 575 is connected to drain region 573 and second wiring 592.

[0082] The first peripheral transistor TR1 can be connected to a word line WL via a drain contact 575 connected to the drain region 573, a second wiring 592 connected to the drain contact 575, and a word line connection contact 560 connected to the second wiring 592.

[0083] Figure 6 This is a view showing another cross-sectional structure of the storage device according to an embodiment of the present disclosure.

[0084] refer to Figure 6 The memory device 100 may include a first semiconductor structure S1 and a second semiconductor structure S2 disposed on the first semiconductor structure. The first semiconductor structure S1 may include a first substrate 410, a memory cell array 110, memory cells MC, a first insulating layer 300, and a first interlayer insulating layer 430. The second semiconductor structure S2 may be disposed on the first semiconductor structure S1. The second semiconductor structure S2 may include a second substrate 420, a first sensing amplifier 120a, and a second interlayer insulating layer 440.

[0085] A first sensing amplifier 120a may be disposed on a second substrate 420. The first sensing amplifier 120a may be disposed in a cell region CR and a peripheral region PR. In one embodiment, the first sensing amplifier 120a may overlap with the cell region CR. The first sensing amplifier 120a includes a second peripheral transistor TR2. The second peripheral transistor TR2 is a transistor constituting the first sensing amplifier 120a. In one embodiment, the second peripheral transistor TR2 may be disposed in the peripheral region PR. A second interlayer insulating layer 440 may be disposed on the second substrate 420 and the first sensing amplifier 120a. Although it is shown that the first sensing amplifier 120a may be disposed on the second substrate 420, this is only an example. That is, the second sensing amplifier 120b (see...) Figure 2 It can be set on the second substrate 420.

[0086] The memory cell MC can be electrically connected to the second peripheral transistor TR2. For example, a memory cell MC can be connected to a bit line BL, and can be electrically connected to the second peripheral transistor TR2 through that bit line BL.

[0087] Figure 7 It is shown Figure 6 A view of the storage device shown.

[0088] refer to Figure 7 The storage device 100 may include a first semiconductor structure S1, a second semiconductor structure S2, and a bit line connection contact 760.

[0089] The first semiconductor structure S1 may include a first substrate 410, an isolation layer 501, a gate structure 510, a third insulating layer 505, a bit line contact 506, a bit line BL, a lower contact plug 508, an upper contact plug 509, a landing pad 518, a capacitor 530, a support layer 550, a fourth insulating layer 521, a first contact 581, a first wiring 591, an inner insulating layer 502, a first insulating layer 300, a second insulating layer 503, and a first interlayer insulating layer 430.

[0090] In the peripheral region PR, bit line BL can be disposed on the second insulating layer 503. Bit line BL can be located at the same height as bit line BL located in cell region CR. Bit line BL can be spaced apart from the upper surface of the first substrate 410 in the vertical direction VD. In one embodiment, bit line BL can extend into the peripheral region PR along the second direction SD. In one embodiment, bit line BL can overlap with the first insulating layer 300.

[0091] Bit line connection contact 760 and first interlayer insulation layer 430 can be disposed on bit line BL. Bit line connection contact 760 penetrates first interlayer insulation layer 430 and is connected to bit line BL. Bit line connection contact 760 contacts the upper surface of bit line BL and extends in the vertical direction VD. Bit line connection contact 760 may include conductive material, such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or combinations thereof.

[0092] The second semiconductor structure S2 can be disposed on the first semiconductor structure S1. The second semiconductor structure S2 may include a second substrate 420, a second interlayer insulating layer 440, a second contact 582, a third contact 583, a second wiring 592, a third wiring 593, a second peripheral transistor TR2, and a source contact 774 and a drain contact 775.

[0093] The second peripheral transistor TR2 can be disposed on the second substrate 420. The second peripheral transistor TR2 includes a gate electrode 770, a gate insulating layer 771, a source region 772, and a drain region 773. Figure 6 The transistors included in the first sensing amplifier 120a shown. In one embodiment, a second peripheral transistor TR2 may be disposed in the peripheral region PR.

[0094] Source contact 774 is connected to source region 772 and second wiring 592. Drain contact 775 is connected to drain region 773 and second wiring 592.

[0095] The second peripheral transistor TR2 can be connected to a bit line BL via a drain contact 775 connected to the drain region 773, a second wiring 592 connected to the drain contact 775, and a bit line connection contact 760 connected to the second wiring 592.

[0096] Figure 8 and Figure 9 It is shown Figure 6 Views of other embodiments of the storage device shown.

[0097] refer to Figure 8 The storage device 100 may include a first semiconductor structure S1 and a second semiconductor structure S2 disposed on the first semiconductor structure. The second semiconductor structure S2 may be coupled to the first semiconductor structure S1 via a suitable operable connection.

[0098] The first semiconductor structure S1 may include a first substrate 410, an isolation layer 501, a gate structure 510, a third insulating layer 505, a bit line contact 506, a bit line BL, a lower contact plug 508, an upper contact plug 509, a landing pad 518, a capacitor 530, a support layer 550, a fourth insulating layer 521, a first contact 581, an inner insulating layer 502, a first insulating layer 300, a second insulating layer 503, a first interlayer insulating layer 430, a first bonding insulating layer 811, a first bonding pad 821, and a bit line connection contact 860.

[0099] The second semiconductor structure S2 may include a second substrate 420, a second interlayer insulating layer 440, a second contact 870, a second wiring 592, a second peripheral transistor TR2, a source contact 774 and a drain contact 775, a second bonding insulating layer 812, and a second bonding pad 822.

[0100] In the cell region CR, a first bonding insulating layer 811 and a first bonding pad 821 may be disposed on a first contact 581 and a first interlayer insulating layer 430. A second bonding insulating layer 812 and a second bonding pad 822 may be disposed on the first bonding insulating layer 811 and the first bonding pad 821, respectively. The second bonding pad 822 may overlap with the first bonding pad 821. The second bonding pad 822 may completely overlap with the first bonding pad 821 in the stacking direction of the first semiconductor structure S1 and the second semiconductor structure S2. The second bonding pad 822 may be bonded to the upper surface of the first bonding pad 821. The second bonding insulating layer 812 may be bonded to the upper surface of the first bonding insulating layer 811. A second contact 870 is connected to the second bonding pad 822. The first bonding pad 821 and the second bonding pad 822 may include conductive materials, such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof.

[0101] In the peripheral region PR, the bit line connection contact 860 extends in the vertical direction VD and contacts the bit line BL. The bit line connection contact 860 can be connected to the corresponding first bonding pad 821.

[0102] In the peripheral region PR, the second bonding pad 822 is bonded to the first bonding pad 821. The second contact 870 is connected to the second bonding pad 822.

[0103] The second peripheral transistor TR2 can be connected to a bit line BL via a drain contact 775 connected to the drain region 773, a second wiring 592 connected to the drain contact 775, a second contact 870 connected to the second wiring 592, a second bonding pad 822 connected to the second contact 870, a first bonding pad 821 connected to the second contact 870, and a bit line connection contact 860.

[0104] refer to Figure 9 The first semiconductor structure S1 of the memory device 100 may include a first substrate 410, an isolation layer 501, a gate structure 510, a third insulating layer 505, a bit line contact 506, a bit line BL, a lower contact plug 508, an upper contact plug 509, a landing pad 518, a capacitor 530, a support layer 550, a fourth insulating layer 521, a first contact 581, a first wiring 591, a first insulating layer 900, a second insulating layer 903, and a first interlayer insulating layer 430.

[0105] In the peripheral region PR, the first substrate 410 includes at least one trench TRE. A first insulating layer 900 and a second insulating layer 903 may be disposed in the trench TRE. In one embodiment, the first insulating layer 900 and the second insulating layer 903 may surround the region where the memory cell array 110 is disposed.

[0106] The first insulating layer 900 may be configured to fill the interior of the trench TRE. The side and bottom surfaces of the first insulating layer 900 may contact the first substrate 410. The first insulating layer 900 comprises hydrogen. The first insulating layer 900 may be a layer with a higher hydrogen supply capacity than other layers. The first insulating layer 900 may comprise an oxide with a high hydrogen content. In one embodiment, the first insulating layer 900 may comprise a high-density plasma (HDP) oxide.

[0107] A second insulating layer 903 may be disposed on the first insulating layer 900. The second insulating layer 903 may cover the entire upper surface of the first insulating layer 900. The side surfaces of the second insulating layer 903 may contact the first substrate 410. In one embodiment, the upper surface of the second insulating layer 903 may be formed to be substantially the same plane as the upper surface of the first substrate 410. In one embodiment, the second insulating layer 903 may comprise silicon nitride.

[0108] Figure 10 This is a view showing another cross-sectional structure of a storage device according to an embodiment of the present disclosure.

[0109] refer to Figure 10 The memory device 100 may include a first semiconductor structure S1 and a second semiconductor structure S2 disposed on the first semiconductor structure. The first semiconductor structure S1 may include a first substrate 410, a memory cell array 110, memory cells MC, a first insulating layer 300, and a first interlayer insulating layer 430. The second semiconductor structure S2 may be disposed on the first semiconductor structure S1. The second semiconductor structure S2 may include a second substrate 420, a first sensing amplifier 120a, and a second interlayer insulating layer 440.

[0110] The first sensing amplifier 120a includes a third peripheral transistor TR3. The third peripheral transistor TR3 is a transistor constituting the first sensing amplifier 120a. In one embodiment, the third peripheral transistor TR3 may be the same as the one referenced above. Figure 6 The second peripheral transistor TR2 is a different transistor. In one embodiment, the third peripheral transistor TR3 can be disposed in the cell region CR.

[0111] The memory cell MC can be electrically connected to the third peripheral transistor TR3. For example, a memory cell MC can be connected to a bit line BL, and can be electrically connected to the third peripheral transistor TR3 through that bit line BL.

[0112] Figure 11 It is shown Figure 10 A view of the storage device shown.

[0113] refer to Figure 11 The storage device 100 may include a first semiconductor structure S1, a second semiconductor structure S2, and a bit line connection contact 760.

[0114] The first semiconductor structure S1 may include a first substrate 410, an isolation layer 501, a gate structure 510, a third insulating layer 505, a bit line contact 506, a bit line BL, a lower contact plug 508, an upper contact plug 509, a landing pad 518, a capacitor 530, a support layer 550, a fourth insulating layer 521, a first contact 581, a first wiring 591, an inner insulating layer 502, a first insulating layer 300, a second insulating layer 503, and a first interlayer insulating layer 430.

[0115] The second semiconductor structure S2 can be disposed on the first semiconductor structure S1. The second semiconductor structure S2 may include a second substrate 420, a second interlayer insulating layer 440, a second contact 582, a third contact 583, a second wiring 592, a third wiring 593, a third peripheral transistor TR3, and a source contact 1174 and a drain contact 1175.

[0116] The third peripheral transistor TR3 can be disposed on the second substrate 420. The third peripheral transistor TR3 includes a gate electrode 1170, a gate insulating layer 1171, a source region 1172, and a drain region 1173. Figure 10 The first sensing amplifier 120a shown includes transistors. In one embodiment, a third peripheral transistor TR3 may be disposed in the cell region CR. In one embodiment, the third peripheral transistor TR3 may overlap with the memory cell array 110.

[0117] Source contact 1174 is connected to source region 1172 and second wiring 592. Drain contact 1175 is connected to drain region 1173 and second wiring 592.

[0118] The third peripheral transistor TR3 can be connected to a bit line BL via a drain contact 1175 connected to the drain region 1173, a second wiring 592 connected to the drain contact 1175, and a bit line connection contact 760 connected to the second wiring 592.

[0119] Refer again Figure 5 and Figure 7 The memory device 100 may include a first semiconductor structure S1 and a second semiconductor structure S2 bonded to the first semiconductor structure S1. The first semiconductor structure S1 includes a first substrate 410 and a first insulating layer 300. The second semiconductor structure S2 may include a second substrate 420, a first peripheral transistor TR1, and a second peripheral transistor TR2. The first insulating layer 300 may be disposed within the first substrate 410 in the peripheral region PR. The first insulating layer 300 may include high-density plasma oxide. The first peripheral transistor TR1 and the second peripheral transistor TR2 may be disposed on the second substrate 420. The first peripheral transistor TR1 is a transistor constituting a first sub-word line driver 210a. The second peripheral transistor TR2 is a transistor constituting a first sense amplifier 120a.

[0120] According to an embodiment of the present disclosure, when the first sensing amplifier 120a and the first sub-word line driver 210a can be disposed on the second substrate 420 of the second semiconductor structure S2, the first insulating layer 300 can be disposed in the first substrate 410 of the first semiconductor structure S1.

[0121] In the manufacturing process of memory devices, when the first substrate 410 is damaged, lattice defects such as silicon dangling bonds may appear in the first substrate 410. Because silicon dangling bonds can act as traps that impede the movement of charge carriers, they must be removed, and a passivation process can be performed for this purpose. Passivation is a process that supplies hydrogen to the substrate, and through passivation, hydrogen (H) can permeate into the first substrate 410 to form Si-H bond structures, thereby reducing silicon dangling bonds. Therefore, for effective passivation, good hydrogen permeation into the first substrate 410 is important.

[0122] When a first insulating layer 300 with a high hydrogen content is located on a capacitor 530, in order for the hydrogen contained in the first insulating layer 300 to permeate into the first substrate 410, the hydrogen must pass through a plurality of layers present between the first substrate 410 and the first insulating layer 300. At least some of the layers present between the first substrate 410 and the first insulating layer 300 absorb hydrogen, and therefore, the efficiency of hydrogen supply to the first substrate 410 is reduced. In addition, because hydrogen moves through the capacitor 530, the capacitor 530 may deteriorate.

[0123] On the other hand, when the first insulating layer 300 is disposed in the first substrate 410, hydrogen contained in the first insulating layer 300 can directly permeate into the first substrate 410 without passing through other layers, thus improving hydrogen supply capability. Therefore, degradation of the memory cells due to silicon dangling bonds can be reduced. Furthermore, because the first insulating layer 300 is disposed in the first substrate 410, hydrogen may not pass through the capacitor 530. Therefore, degradation that may occur when hydrogen passes through the capacitor 530 can be prevented.

[0124] In embodiments of this disclosure, a method for manufacturing a memory device is provided, the memory device including a first semiconductor structure having a memory cell array and a second semiconductor structure having peripheral transistors. The method may include: forming a trench in a peripheral region of a first substrate including a cell region and a peripheral region surrounding the cell region; forming a first insulating layer including a high-density plasma oxide in the trench; forming a memory cell array in the cell region of the first substrate; and forming peripheral transistors on the memory cell array for connection to the memory cell array.

[0125] In embodiments of this disclosure, a method for manufacturing a storage device may include forming a second insulating layer on the first insulating layer after forming a first insulating layer.

[0126] In embodiments of this disclosure, the second semiconductor structure further includes a second substrate, wherein a peripheral transistor is formed on the second substrate.

[0127] In embodiments of this disclosure, a method for manufacturing a memory device may include bonding a second semiconductor structure to a first semiconductor structure.

[0128] While detailed embodiments have been disclosed in this disclosure, those skilled in the art will understand that various modifications, additions, and substitutions related to these embodiments are possible without departing from the scope and technical concept of this disclosure. Therefore, the scope of this disclosure should not be limited to the foregoing embodiments. All changes within the meaning and scope of equivalents of the claims are included within its scope. Furthermore, these embodiments may be combined to form additional embodiments.

Claims

1. A storage device, comprising: A first substrate, the first substrate including a cell region and a peripheral region disposed around the cell region; A memory cell array, wherein the memory cell array is disposed in the cell region of the first substrate; A second substrate is disposed on the memory cell array; A peripheral transistor is disposed on the second substrate and connected to the memory cell array; A first insulating layer is disposed in a trench located in the peripheral region of the first substrate and comprises a high-density plasma oxide. as well as A second insulating layer is placed on top of the first insulating layer.

2. The storage device according to claim 1, wherein, The second insulating layer covers the upper surface of the first insulating layer.

3. The storage device according to claim 1, wherein, The upper surface of the second insulating layer forms a plane that is substantially the same as the upper surface of the first substrate.

4. The storage device according to claim 1, wherein, The second insulating layer comprises silicon nitride.

5. The storage device according to claim 1, wherein, At least one of the peripheral transistors overlaps with the cell region.

6. The storage device according to claim 1, wherein, The peripheral transistors constitute a sub-word line driver or a sense amplifier.

7. The storage device according to claim 6, further comprising: Bit line; as well as Bit line connection contact member, the bit line connection contact member contacting the upper surface of the bit line and extending in a direction perpendicular to the upper surface of the bit line to penetrate the second substrate. The peripheral transistor constitutes the sensing amplifier and is electrically connected to the bit line via the bit line connection contact.

8. The storage device according to claim 7, wherein, The bit line connection contact overlaps with the first insulating layer.

9. The storage device according to claim 6, further comprising: Word lines; as well as A word line connection contact is provided, which contacts the upper surface of the word line and extends in a direction perpendicular to the upper surface of the word line to penetrate the second substrate. The peripheral transistors constitute the sub-word line driver and are electrically connected to the word line via the word line connection contacts.

10. A storage device comprising: First substrate; A memory cell array, wherein the memory cell array is disposed on the first substrate; A first insulating layer is disposed in a trench in the first substrate, surrounds the region where the memory cell array is disposed, and comprises a high-density plasma oxide. as well as A second insulating layer covers the upper surface of the first insulating layer.

11. The storage device according to claim 10, wherein, The upper surface of the second insulating layer forms a plane that is substantially the same as the upper surface of the first substrate.

12. The storage device according to claim 10, wherein, The second insulating layer comprises silicon nitride.

13. The storage device according to claim 10, further comprising: Peripheral transistors are disposed on and connected to the memory cell array.

14. The storage device according to claim 13, wherein, The peripheral transistors constitute a sub-word line driver or a sense amplifier.

15. The storage device according to claim 13, wherein, At least one of the peripheral transistors overlaps with the region where the memory cell array is disposed.

16. A memory device comprising a first semiconductor structure and a second semiconductor structure bonded to the first semiconductor structure. in, The first semiconductor structure includes: A first substrate, the first substrate including a cell region and a peripheral region surrounding the cell region; A memory cell array, wherein the memory cell array is disposed in the cell region of the first substrate; A first insulating layer is disposed in the peripheral region of the first substrate; and A second insulating layer covers the upper surface of the first insulating layer. The second semiconductor structure includes: Second substrate; and Peripheral transistors, which are disposed on the second substrate and connected to the memory cell array, and Wherein, at least one of the peripheral transistors overlaps with the unit region.

17. The storage device according to claim 16, wherein, At least one of the peripheral transistors overlaps with the peripheral region on the second substrate.

18. The storage device according to claim 16, wherein, The first insulating layer comprises high-density plasma oxide.

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