Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the semiconductor device comprises a plurality of storage units which are located at different layers and are distributed in a stacking manner in a direction perpendicular to a substrate; the storage unit comprises a transistor; the transistor comprises a first electrode, a second electrode, a semiconductor layer located between the first electrode and the second electrode, a contact layer, a gate insulation layer and a gate electrode. The semiconductor layer, the contact layer, the gate insulation layer and the gate electrode are distributed in sequence. The semiconductor device is high in storage density, and the transistor is good and stable in performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device. The semiconductor device has high storage density and the transistors have good and stable performance.

[0006] This application provides a semiconductor device comprising: a plurality of memory cells stacked on different layers in a direction perpendicular to a substrate; each memory cell comprising a transistor; each transistor comprising a first electrode, a second electrode, a semiconductor layer, a contact layer, a gate insulating layer, and a gate electrode located between the first electrode and the second electrode; the semiconductor layer, the contact layer, the gate insulating layer, and the gate electrode being sequentially distributed; the semiconductor layer extending in a direction perpendicular to the substrate.

[0007] In some embodiments of this application, the material of the contact layer is tungsten or indium tin oxide.

[0008] In some embodiments of this application, the thickness of the contact layer is 2 nm to 10 nm.

[0009] In some embodiments of this application, the semiconductor layers of a plurality of memory cells stacked along a direction perpendicular to the substrate are spaced apart and disconnected; and / or, The contact layers of the plurality of memory cells stacked along a direction perpendicular to the substrate are spaced apart and disconnected; and / or, The gate insulating layer of the plurality of memory cells stacked along a direction perpendicular to the substrate is a single-piece structure; and / or, The gate electrodes of the plurality of memory cells stacked in a direction perpendicular to the substrate are of a single structure.

[0010] In some embodiments of this application, the semiconductor layer at least partially surrounds the gate electrode.

[0011] In some embodiments of this application, the semiconductor device further includes: A word line extends in a direction perpendicular to the substrate and passes through transistors of a plurality of memory cells stacked in a direction perpendicular to the substrate; the gate electrodes of the plurality of memory cells stacked in a direction perpendicular to the substrate are located in different regions of the word line; Bit lines are located on one side of the semiconductor layer and extend along a column direction parallel to the substrate; the first electrodes of a plurality of memory cells spaced apart along the column direction are connected to the same bit line.

[0012] In some embodiments of this application, the storage unit further includes a capacitor; the capacitor includes a first capacitor electrode, a second capacitor electrode, and a dielectric layer located between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode and the second electrode located in the same storage unit are an integral structure.

[0013] This application also provides a method for manufacturing a semiconductor device, the method comprising: Multiple first insulating layers and multiple second insulating layers are sequentially and alternately formed on a substrate to obtain a stacked structure; The stacked structure is etched along the direction toward the substrate to form transistor holes that penetrate the stacked structure; A semiconductor layer, a contact layer, a gate insulating layer, and a word line are sequentially formed in the transistor hole; Remove the semiconductor layer and the contact layer located on the sidewall of the first insulating layer of the transistor hole.

[0014] In some embodiments of this application, the manufacturing method further includes: after obtaining the stacked structure, but before forming the transistor via; A first capacitor electrode and a bit line of a capacitor are formed on both sides of the transistor hole, which are distributed in a row direction parallel to the substrate. The first capacitor electrode and the bit line are located between two adjacent first insulating layers that are stacked in a direction perpendicular to the substrate. A plurality of first capacitor electrodes are stacked and spaced apart in a direction perpendicular to the substrate. A plurality of bit lines extend in a column direction parallel to the substrate. The row direction intersects the column direction.

[0015] In some embodiments of this application, the first capacitor electrode is formed on one side of the transistor aperture distributed along the row direction, including: On one side of the transistor holes distributed along the row direction, the stacked structure is etched along the direction toward the substrate to form a plurality of capacitor holes penetrating the stacked structure; the plurality of capacitor holes are spaced apart along the column direction; The exposed second insulating layer is etched inside the capacitor hole, and a first groove extending in a direction away from the capacitor hole is formed on the sidewall of the capacitor hole. A first capacitor electrode and a first sacrificial layer are sequentially formed in the first groove; An etching barrier layer and the first sacrificial layer are sequentially formed inside the capacitor hole.

[0016] In some embodiments of this application, the bit line is formed on the other side of the transistor aperture along the row direction, including: On the other side of the transistor holes distributed along the row direction, the stacked structure is etched along the direction toward the substrate to form a trench that penetrates the stacked structure and extends along the column direction parallel to the substrate; The second insulating layer on both sides is etched within the trench, and bit line grooves extending in a direction away from the trench are formed on the sidewalls of the trench; the bit line grooves extend in the column direction. The bit line is formed within the bit line groove; The etching barrier layer and the first sacrificial layer are formed sequentially within the trench.

[0017] In some embodiments of this application, etching the stacked structure along a direction toward the substrate to form a transistor hole through the stacked structure includes: Between the first capacitor electrode and the bit line, the stacked structure is etched along the direction toward the substrate to form a transistor hole that penetrates the stacked structure; the first capacitor electrode and the bit line are exposed on both sides of the transistor hole, respectively. The first insulating layer exposed inside the transistor hole is etched to expand the transistor hole toward the capacitor hole and the trench. The expanded transistor hole exposes the etching barrier layer on the sidewall of the capacitor hole and the etching barrier layer on the sidewall of the trench. Multiple second sacrificial layers are formed at intervals on the inner wall of the expanded transistor hole; the second sacrificial layers expose the first capacitor electrode and the bit line, and the second sacrificial layers cover the etch barrier layer on the sidewall of the capacitor hole and the etch barrier layer on the sidewall of the trench.

[0018] In some embodiments of this application, removing the semiconductor layer and the contact layer located on the sidewall of the first insulating layer from the transistor hole includes: Remove the first sacrificial layer inside the capacitor hole to expose the etching barrier layer on the inner wall of the capacitor hole; Remove the etching barrier layer on the inner wall of the capacitor hole to expose the second sacrificial layer; At least a portion of the second sacrificial layer is removed to expose at least a portion of the semiconductor layer located on the sidewall of the first insulating layer of the transistor aperture; At least the semiconductor layer and the contact layer between two adjacent first capacitor electrodes stacked in a direction perpendicular to the substrate are removed, and the semiconductor layer and the contact layer are disconnected in a direction perpendicular to the substrate.

[0019] In some embodiments of this application, removing the semiconductor layer and the contact layer located on the sidewall of the first insulating layer from the transistor hole includes: Remove the first sacrificial layer within the trench to expose the etching barrier layer on the inner wall of the trench; Remove the etching barrier layer on the inner wall of the trench to expose the second sacrificial layer; At least a portion of the second sacrificial layer is removed to expose at least a portion of the semiconductor layer located on the sidewall of the first insulating layer of the transistor aperture; At least the semiconductor layer and the contact layer between two adjacent bit lines stacked in a direction perpendicular to the substrate are removed, and the semiconductor layer and the contact layer are disconnected in a direction perpendicular to the substrate.

[0020] In some embodiments of this application, the same etching process is used to remove the capacitor hole and the first sacrificial layer in the trench; The same etching process is used to remove the etching barrier layer on the inner wall of the capacitor hole and the trench; The second sacrificial layer is removed from the capacitor holes and the trenches using the same etching process; The semiconductor layer and the contact layer on the sidewall of the first insulating layer of the transistor hole are removed from the capacitor hole and the trench using the same etching process.

[0021] This application also provides an electronic device, which includes the semiconductor device described above, or includes a semiconductor device obtained by the semiconductor device manufacturing method described above.

[0022] The semiconductor device in this application embodiment sets the semiconductor layer to extend in a direction perpendicular to the substrate to form a vertical transistor structure, which can reduce the occupied area of ​​the memory cell, thereby increasing the storage density and improving the performance and stability of the transistor.

[0023] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0024] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0025] Figure 1 This is a schematic diagram of a longitudinal section of a semiconductor device in accordance with an exemplary embodiment of this application, perpendicular to the substrate. Figure 2 A process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application; Figure 3 A schematic longitudinal section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a transistor hole, is shown in the figure. Figure 4 A schematic longitudinal section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming an expanded transistor hole, is shown in a cross section perpendicular to the substrate. Figure 5 A schematic longitudinal section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of a second sacrificial layer, is shown in a cross section perpendicular to the substrate. Figure 6 This is a schematic longitudinal section view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after word lines have been formed; Figure 7 A schematic longitudinal section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the removal of the first sacrificial layer, is shown in a cross section perpendicular to the substrate. Figure 8 This is a schematic diagram of a longitudinal section perpendicular to the substrate, illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application after removing parasitic MOS.

[0026] The meanings of the symbols in the attached diagram are as follows: 10-Substrate; 11-First insulating layer; 12-Second insulating layer; 13-First sacrificial layer; 14-Second sacrificial layer; 15-Etch barrier layer; 20-Transistor; 21-First electrode; 22-Second electrode; 23-Semiconductor layer; 24-Contact layer; 25-Gate insulating layer; 26-Gate electrode; 31-First capacitor electrode; K1-Capacitor hole; K2-Transistor hole; T1-First groove; T2-Trench; T3-Bit line groove. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0028] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values ​​shown in the drawings.

[0029] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing can be adjusted according to actual needs.

[0030] The ordinal numbers such as "first" and "second" in this application are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0031] In this application, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the application is not limited to the terms described in the disclosure and may be appropriately replaced as appropriate.

[0032] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0033] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0034] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.

[0035] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0036] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0037] In this application, "film" and "layer" can be interchanged. For example, "semiconductor layer" can sometimes be replaced with "semiconductor film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0038] The phrase "A and B are arranged in the same layer" in this application refers to A and B being distributed on the same horizontal plane, or although not on the same horizontal plane, both being in different areas of the same supporting surface. One embodiment involves A and B being formed simultaneously on the same film layer using the same patterning process.

[0039] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.

[0040] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functional circuits are already distributed. The devices involved in the inventive construction of the embodiments of this application are disposed on the main surface of the support structure.

[0041] In this application, the spacing distribution can be understood as a separate distribution, which can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors is modified to achieve insulation, thereby realizing the electrical spacing between the two channels.

[0042] This application provides a semiconductor device.

[0043] Figure 1 This is a schematic diagram of a longitudinal section of a semiconductor device in a section perpendicular to the substrate, which is an exemplary embodiment of this application.

[0044] like Figure 1 As shown, the semiconductor device includes: a plurality of memory cells stacked in different layers along a direction perpendicular to the substrate 10; each memory cell includes a transistor 20; the transistor 20 includes a first electrode 21, a second electrode 22, a semiconductor layer 23, a contact layer 24, a gate insulating layer 25, and a gate electrode 26 located between the first electrode 21 and the second electrode 22; the semiconductor layer 23, the contact layer 24, the gate insulating layer 25, and the gate electrode 26 are sequentially distributed; the semiconductor layer 23 extends along a direction perpendicular to the substrate 10.

[0045] The semiconductor device in this application embodiment sets the semiconductor layer to extend in a direction perpendicular to the substrate to form a vertical transistor structure, which can reduce the occupied area of ​​the memory cell, thereby increasing the storage density and improving the performance and stability of the transistor.

[0046] In some embodiments of this application, the contact layer is made of tungsten (W) or indium tin oxide (e.g., ITO). In other exemplary embodiments of this application, other metals or conductive materials may also be used.

[0047] Direct contact between IGZO and other metal-oxide-semiconductor (MOS) layers and the gate insulating layer can lead to the accumulation of metals such as In in the MOS layer, causing instability in IGZO and other MOS materials. Furthermore, the limitation of oxygen vacancies in the channel restricts the regulation capability of the gate electrode work function. When indium tin oxide (InTiO2) is used to form the contact layer, the tin in InTiO2 can form Sn-O bonds with oxygen in the MOS layer, thereby improving the stability of the MOS material; moreover, it helps to increase the carrier concentration, thus improving the effective mobility of the transistor.

[0048] When tungsten is used to form the contact layer, the contact resistance between the semiconductor layer and the gate insulating layer can be reduced.

[0049] In some embodiments of this application, the thickness of the contact layer is from 2 nm to 10 nm. For example, the thickness of the contact layer can be 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm.

[0050] In some embodiments of this application, such as Figure 1 As shown, the semiconductor layers 23 of the plurality of memory cells stacked in a direction perpendicular to the substrate 10 are spaced apart and disconnected.

[0051] In some embodiments of this application, such as Figure 1 As shown, the contact layers 24 of the plurality of memory cells stacked in a direction perpendicular to the substrate 10 are spaced apart and disconnected.

[0052] In some embodiments of this application, such as Figure 1 As shown, the gate insulating layer 25 of the plurality of memory cells stacked along a direction perpendicular to the substrate 10 is a single structure.

[0053] In some embodiments of this application, such as Figure 1 As shown, the gate electrodes 26 of the plurality of memory cells stacked in a direction perpendicular to the substrate 10 are an integral structure.

[0054] In some embodiments of this application, such as Figure 1 As shown, the semiconductor layer 23 at least partially surrounds the gate electrode 26.

[0055] In some embodiments of this application, such as Figure 1 As shown, the semiconductor device further includes: a word line WL, which extends in a direction perpendicular to the substrate 10 and passes through transistors 20 of a plurality of memory cells stacked in a direction perpendicular to the substrate 10; gate electrodes 26 of the plurality of memory cells stacked in a direction perpendicular to the substrate 10 are located in different regions of the word line WL.

[0056] In some embodiments of this application, such as Figure 1 As shown, the semiconductor device further includes: a bit line BL, which is located on one side of the semiconductor layer 23 and extends along a column direction parallel to the substrate 10; and the first electrodes 21 of a plurality of memory cells spaced apart along the column direction are connected to the same bit line BL.

[0057] In some embodiments of this application, the semiconductor device can be a 3D memory, such as a 3D DRAM. The 3D memory can be a 1T1C or 2T1C structure, or a 2T0C structure (containing a read transistor and a write transistor).

[0058] In some embodiments of this application, the storage unit further includes a capacitor; the capacitor includes a first capacitor electrode 31, a second capacitor electrode, and a dielectric layer located between the first capacitor electrode 31 and the second capacitor electrode; the first capacitor electrode 31 and the second electrode 22 located in the same storage unit are an integral structure.

[0059] In this application, the semiconductor layer can be understood as a semiconductor material, and its shape and structure are not emphasized, but only its function is emphasized.

[0060] For example, the material of the semiconductor layer can be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it can be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0061] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0062] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0063] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0064] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0065] In some embodiments of this application, the material of the bit line can be selected from any one or more of other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The bit line can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0066] In some embodiments of this application, the materials of the gate electrode and the word line can be any one or more of the following different types of materials: For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals. It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials. Of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; and other materials that exhibit conductivity, etc.

[0067] In some embodiments of this application, the gate insulating layer may comprise one or more Low-K and / or High-K dielectric materials, or comprise two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of this application will be illustrated below by way of example.

[0068] Low-K materials, such as silicon oxide.

[0069] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, they may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0070] In some embodiments of this application, the dielectric layer may be made of silicon oxide or a high-K dielectric material. High-K materials, in some embodiments, may include any one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0071] This application also provides a method for manufacturing a semiconductor device. The semiconductor device described above can be obtained by this manufacturing method.

[0072] Figure 2 This is a process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application.

[0073] like Figure 2 As shown, the manufacturing method includes: Multiple first insulating layers and multiple second insulating layers are sequentially and alternately formed on a substrate to obtain a stacked structure; The stacked structure is etched along the direction toward the substrate to form transistor holes that penetrate the stacked structure; A semiconductor layer, a contact layer, a gate insulating layer, and a word line are sequentially formed in the transistor hole; Remove the semiconductor layer and the contact layer located on the sidewall of the first insulating layer of the transistor hole.

[0074] In some embodiments of this application, the manufacturing method further includes: after obtaining the stacked structure, but before forming the transistor via; A first capacitor electrode and a bit line of a capacitor are formed on both sides of the transistor hole, which are distributed in a row direction parallel to the substrate. The first capacitor electrode and the bit line are located between two adjacent first insulating layers that are stacked in a direction perpendicular to the substrate. A plurality of first capacitor electrodes are stacked and spaced apart in a direction perpendicular to the substrate. A plurality of bit lines extend in a column direction parallel to the substrate. The row direction intersects the column direction.

[0075] In some embodiments of this application, the first capacitor electrode is formed on one side of the transistor aperture distributed along the row direction, including: On one side of the transistor holes distributed along the row direction, the stacked structure is etched along the direction toward the substrate to form a plurality of capacitor holes penetrating the stacked structure; the plurality of capacitor holes are spaced apart along the column direction; The exposed second insulating layer is etched inside the capacitor hole, and a first groove extending in a direction away from the capacitor hole is formed on the sidewall of the capacitor hole. A first capacitor electrode and a first sacrificial layer are sequentially formed in the first groove; An etching barrier layer and the first sacrificial layer are sequentially formed inside the capacitor hole.

[0076] In some embodiments of this application, the bit line is formed on the other side of the transistor aperture along the row direction, including: On the other side of the transistor holes distributed along the row direction, the stacked structure is etched along the direction toward the substrate to form a trench that penetrates the stacked structure and extends along the column direction parallel to the substrate; The second insulating layer on both sides is etched within the trench, and bit line grooves extending in a direction away from the trench are formed on the sidewalls of the trench; the bit line grooves extend in the column direction. The bit line is formed within the bit line groove; The etching barrier layer and the first sacrificial layer are formed sequentially within the trench.

[0077] In some embodiments of this application, etching the stacked structure along a direction toward the substrate to form a transistor hole through the stacked structure includes: Between the first capacitor electrode and the bit line, the stacked structure is etched along the direction toward the substrate to form a transistor hole that penetrates the stacked structure; the first capacitor electrode and the bit line are exposed on both sides of the transistor hole, respectively. The first insulating layer exposed inside the transistor hole is etched to expand the transistor hole toward the capacitor hole and the trench. The expanded transistor hole exposes the etching barrier layer on the sidewall of the capacitor hole and the etching barrier layer on the sidewall of the trench. Multiple second sacrificial layers are formed at intervals on the inner wall of the expanded transistor hole; the second sacrificial layers expose the first capacitor electrode and the bit line, and the second sacrificial layers cover the etch barrier layer on the sidewall of the capacitor hole and the etch barrier layer on the sidewall of the trench.

[0078] In some embodiments of this application, removing the semiconductor layer and the contact layer located on the sidewall of the first insulating layer from the transistor hole includes: Remove the first sacrificial layer inside the capacitor hole to expose the etching barrier layer on the inner wall of the capacitor hole; Remove the etching barrier layer on the inner wall of the capacitor hole to expose the second sacrificial layer; At least a portion of the second sacrificial layer is removed to expose at least a portion of the semiconductor layer located on the sidewall of the first insulating layer of the transistor aperture; At least the semiconductor layer and the contact layer between two adjacent first capacitor electrodes stacked in a direction perpendicular to the substrate are removed, and the semiconductor layer and the contact layer are disconnected in a direction perpendicular to the substrate.

[0079] In some embodiments of this application, removing the semiconductor layer and the contact layer located on the sidewall of the first insulating layer from the transistor hole includes: Remove the first sacrificial layer within the trench to expose the etching barrier layer on the inner wall of the trench; Remove the etching barrier layer on the inner wall of the trench to expose the second sacrificial layer; At least a portion of the second sacrificial layer is removed to expose at least a portion of the semiconductor layer located on the sidewall of the first insulating layer of the transistor aperture; At least the semiconductor layer and the contact layer between two adjacent bit lines stacked in a direction perpendicular to the substrate are removed, and the semiconductor layer and the contact layer are disconnected in a direction perpendicular to the substrate.

[0080] In some embodiments of this application, the same etching process is used to remove the capacitor hole and the first sacrificial layer in the trench; The same etching process is used to remove the etching barrier layer on the inner wall of the capacitor hole and the trench; The second sacrificial layer is removed from the capacitor holes and the trenches using the same etching process; The semiconductor layer and the contact layer on the sidewall of the first insulating layer of the transistor hole are removed from the capacitor hole and the trench using the same etching process.

[0081] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0082] like Figures 3 to 8 As shown, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.

[0083] S10: A plurality of first insulating layers 11 and a plurality of second insulating layers 12 are sequentially and alternately deposited on the substrate 10 to obtain a stacked structure formed by alternating stacking of a plurality of first insulating layers 11 and a plurality of second insulating layers 12.

[0084] In some embodiments of this application, the materials forming the first insulating layer and the second insulating layer can be low-K dielectric materials, i.e., dielectric materials with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing films. For example, the material of the first insulating layer can be silicon oxide, and the material of the second insulating layer can be silicon nitride.

[0085] S20: A plurality of first capacitor electrodes 31 are formed in the stacked structure, which are stacked and spaced apart along a direction perpendicular to the substrate 10.

[0086] For example, step S20 may include steps S21 to S24 described below.

[0087] S21: The stacked structure is etched along the direction toward the substrate 10 to form a plurality of capacitor holes K1 through the stacked structure; the plurality of capacitor holes K1 are distributed at intervals along the row and column directions parallel to the substrate; in the extension direction of the capacitor holes K1, the capacitor holes K1 alternately expose the first insulating layer 11 and the second insulating layer 12.

[0088] S22: Etch the exposed second insulating layer 12 inside the capacitor hole K1 to form a first groove T1 extending in a direction away from the capacitor hole K1 on the sidewall of the capacitor hole K1; the first groove T1 can be annular and completely surrounds the entire circumferential sidewall of the capacitor hole K1.

[0089] S23: A ring-shaped first capacitor electrode 31 is deposited on the inner wall of the first groove T1, and the first sacrificial layer 13 is filled in the first groove T1.

[0090] For example, step S23 may include: S231: An electrode layer and a first sacrificial layer 13 are sequentially deposited on the inner walls of the first groove T1 and the capacitor hole K1; S232: Etch away the first sacrificial layer 13 on the sidewall of capacitor hole K1 to expose the electrode layer on the sidewall of capacitor hole K1. S233: Etch away the electrode layer on the sidewall of the capacitor hole K1, leaving only the electrode layer on the inner wall of the first groove T1, so that the electrode layer is broken in the direction perpendicular to the substrate 10; the remaining electrode layers are distributed at intervals in the direction perpendicular to the substrate 10, i.e., the first capacitor electrode 31.

[0091] Multiple first capacitor electrodes 31 are stacked and spaced apart along a direction perpendicular to the substrate 10. Each first capacitor electrode 31 can be annular, and its cross-sectional profile in a longitudinal section perpendicular to the substrate is as follows: Figure 3 As shown.

[0092] S24: Deposit an etching barrier layer 15 on the inner wall of the capacitor hole K1, and fill the capacitor hole K1 with a first sacrificial layer 13.

[0093] S30: Multiple bit lines BL are formed in the stacked structure, stacked and spaced apart along a direction perpendicular to the substrate 10.

[0094] For example, step S30 may include steps S31 to S34 described below.

[0095] S31: On one side of the capacitor hole K1 distributed along the row direction, the stacked structure is etched in the direction toward the substrate 10 to form a trench T2 that penetrates the stacked structure and extends along the column direction; in the direction toward the substrate 10, the trench T2 alternately exposes the first insulating layer 11 and the second insulating layer 12.

[0096] When forming trench T2, a position for a transistor needs to be reserved between capacitor hole K1 and trench T2.

[0097] S32: The second insulating layer 12 on both sides is etched in the trench T2 to form a plurality of bit line grooves T3 extending in a direction away from the trench T2 on the sidewall of the trench T2; the bit line grooves T3 extend in the column direction.

[0098] Multiple bit line grooves T3 are spaced apart on both sides of the trench T2 and are stacked and spaced apart in a direction perpendicular to the substrate 10.

[0099] S33: A bit line BL is formed within the bit line slot T3.

[0100] Bit lines BL extend along the column direction. Multiple bit lines BL are spaced apart on both sides of the trench T2 and are stacked and spaced apart in a direction perpendicular to the substrate 10.

[0101] S34: Deposit an etching barrier layer 15 on the inner wall of the trench T2 and fill the trench T2 with a first sacrificial layer 13; S35: A mask layer is formed on the surface of substrate 10 to cover capacitor hole K1 and communication T2.

[0102] For example, the material of the mask layer can be the same as the material of the second insulating layer, for example, both can be silicon nitride.

[0103] S40: The stacked structure is etched along the direction toward the substrate 10 to form a transistor hole K2 through the stacked structure.

[0104] For example, step S40 may include steps S41 to S43.

[0105] S41: Between capacitor hole K1 and trench T2, the stacked structure is etched along the direction towards substrate 10 to form transistor hole K2 penetrating the stacked structure, as shown. Figure 3 As shown.

[0106] The first capacitor electrode 31 and the bit line BL are exposed on both sides of the transistor hole K2, respectively.

[0107] S42: Laterally etch the exposed first insulating layer 11 within the transistor hole K2, expanding the transistor hole K2 toward the capacitor hole K1 and the trench T2. The expanded transistor hole K2 exposes the etching barrier layer 15 on the sidewall of the capacitor hole K1 and the etching barrier layer 15 on the sidewall of the trench T2. Figure 4 As shown.

[0108] S43: Multiple second sacrificial layers 14 are formed at intervals on the inner wall of the expanded transistor hole K2; the second sacrificial layers 14 expose the first capacitor electrode 31 and the bit line BL, and the second sacrificial layers 14 cover the etch barrier layer 15 on the sidewall of the capacitor hole K1 and the etch barrier layer 15 on the sidewall of the trench T2, such as Figure 5 As shown.

[0109] For example, a second sacrificial layer 14 can be formed on the entire inner wall of the expanded transistor hole K2 first, and then the second sacrificial layer 14 covering the first capacitor electrode 31 and the bit line BL can be removed.

[0110] S50: A semiconductor layer 23, a contact layer 24, and a gate insulating layer 25 are sequentially deposited on the inner wall of the transistor hole K2, and the word line WL is filled into the transistor hole K2, as shown. Figure 6 As shown.

[0111] S60: Remove the semiconductor layer 23 and contact layer 24 located on the sidewall of the first insulating layer 11 from the transistor hole K2.

[0112] For example, step S60 may include steps S61 to S64.

[0113] S61: The first sacrificial layer 13 in the capacitor hole K1 and trench T2 is removed by etching, exposing the etching barrier layer 15 on the inner wall of the capacitor hole K1 and trench T2, such as Figure 7 As shown.

[0114] For example, a wet etching process can be used to remove the first sacrificial layer 13 (polysilicon material) in the capacitor hole K1 and trench T2, and the etching reagent used can be diluted ammonia or TMAH.

[0115] S62: The etching barrier layer 15 on the inner wall of capacitor hole K1 and trench T2 is removed by etching, exposing the second sacrificial layer 14.

[0116] For example, the etching barrier layer 15 (silicon nitride material) on the inner wall of capacitor hole K1 and trench T2 can be removed by dry etching or wet etching process. The etching reagent used in wet etching can be phosphoric acid HPO.

[0117] S63: By etching away the entire annular second sacrificial layer 14, the annular semiconductor layer 23 located on the sidewall of the first insulating layer 11 of the transistor hole K2 is exposed, as shown. Figure 8 As shown.

[0118] For example, a wet etching process can be used to remove the etching barrier layer 15 (silicon nitride material) on the inner wall of capacitor hole K1 and trench T2. The etching reagent used can be diluted ammonia or TMAH.

[0119] S64: The annular semiconductor layer 23 and contact layer 24 located on the sidewall of the first insulating layer 11 are removed by etching, i.e., the parasitic MOS is removed, to obtain the following... Figure 1 The semiconductor device shown.

[0120] For example, a wet etching process can be used to remove the semiconductor layer 23 of the MOS region, and the etching reagent used can be HCl or acetic acid.

[0121] For example, the contact layer 24 of the MOS region can be removed by a wet etching process, and the etching reagent used can be diluted SC1 reagent or hydrochloric acid HCl.

[0122] This application also provides an electronic device, which includes the semiconductor device described above, or includes a semiconductor device obtained by the semiconductor device manufacturing method described above.

[0123] In some embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0124] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Multiple memory cells are stacked in different layers along a direction perpendicular to the substrate; each memory cell includes a transistor; each transistor includes a first electrode, a second electrode, a semiconductor layer, a contact layer, a gate insulating layer, and a gate electrode located between the first electrode and the second electrode; the semiconductor layer, the contact layer, the gate insulating layer, and the gate electrode are distributed sequentially; the semiconductor layer extends along a direction perpendicular to the substrate.

2. The semiconductor device according to claim 1, characterized in that, The contact layer is made of tungsten or indium tin oxide.

3. The semiconductor device according to claim 1, characterized in that, The thickness of the contact layer is 2 nm to 10 nm.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor layers of the plurality of memory cells stacked in a direction perpendicular to the substrate are spaced apart and disconnected; And / or, The contact layers of the plurality of memory cells stacked in a direction perpendicular to the substrate are spaced apart and disconnected; And / or, The gate insulating layer of the plurality of memory cells stacked along a direction perpendicular to the substrate is a single-piece structure; and / or, The gate electrodes of the plurality of memory cells stacked in a direction perpendicular to the substrate are of a single structure.

5. The semiconductor device according to claim 4, characterized in that, The semiconductor layer at least partially surrounds the gate electrode.

6. The semiconductor device according to claim 4, characterized in that, Also includes: Word lines, which extend in a direction perpendicular to the substrate and pass through transistors of a plurality of memory cells stacked in a direction perpendicular to the substrate; The gate electrodes of the plurality of memory cells stacked along a direction perpendicular to the substrate are located in different regions of the word line; Bit lines are located on one side of the semiconductor layer and extend along a column direction parallel to the substrate; the first electrodes of a plurality of memory cells spaced apart along the column direction are connected to the same bit line.

7. The semiconductor device according to claim 4, characterized in that, The storage unit further includes a capacitor; the capacitor includes a first capacitor electrode, a second capacitor electrode, and a dielectric layer located between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode and the second electrode located in the same storage unit are an integral structure.

8. A method for manufacturing a semiconductor device, characterized in that, include: Multiple first insulating layers and multiple second insulating layers are sequentially and alternately formed on a substrate to obtain a stacked structure; The stacked structure is etched along the direction toward the substrate to form transistor holes that penetrate the stacked structure; A semiconductor layer, a contact layer, a gate insulating layer, and a word line are sequentially formed in the transistor hole; Remove the semiconductor layer and the contact layer located on the sidewall of the first insulating layer of the transistor hole.

9. The manufacturing method according to claim 8, characterized in that, Also includes: After obtaining the stacked structure and before forming the transistor aperture; A first capacitor electrode and a bit line of a capacitor are formed on both sides of the transistor hole, which are distributed in a row direction parallel to the substrate; the first capacitor electrode and the bit line are both located between two adjacent first insulating layers that are stacked and distributed in a direction perpendicular to the substrate; a plurality of first capacitor electrodes are stacked and spaced apart in a direction perpendicular to the substrate. The multiple bit lines extend along a column direction parallel to the substrate; the row direction intersects the column direction.

10. The manufacturing method according to claim 9, characterized in that, The first capacitor electrode is formed on one side of the transistor aperture distributed along the row direction, including: On one side of the transistor holes distributed along the row direction, the stacked structure is etched along the direction toward the substrate to form a plurality of capacitor holes penetrating the stacked structure; the plurality of capacitor holes are spaced apart along the column direction; The exposed second insulating layer is etched inside the capacitor hole, and a first groove extending in a direction away from the capacitor hole is formed on the sidewall of the capacitor hole. A first capacitor electrode and a first sacrificial layer are sequentially formed in the first groove; An etching barrier layer and the first sacrificial layer are sequentially formed inside the capacitor hole.

11. The manufacturing method according to claim 10, characterized in that, The bit line is formed on the other side of the transistor aperture along the row direction, including: On the other side of the transistor holes distributed along the row direction, the stacked structure is etched along the direction toward the substrate to form a trench that penetrates the stacked structure and extends along the column direction parallel to the substrate; The second insulating layer on both sides is etched within the trench, and bit line grooves extending in a direction away from the trench are formed on the sidewalls of the trench; the bit line grooves extend in the column direction. The bit line is formed within the bit line groove; The etching barrier layer and the first sacrificial layer are formed sequentially within the trench.

12. The manufacturing method according to claim 11, characterized in that, The etching of the stacked structure along the direction toward the substrate to form a transistor hole through the stacked structure includes: Between the first capacitor electrode and the bit line, the stacked structure is etched along the direction toward the substrate to form a transistor hole that penetrates the stacked structure; the first capacitor electrode and the bit line are exposed on both sides of the transistor hole, respectively. The first insulating layer exposed inside the transistor hole is etched to expand the transistor hole toward the capacitor hole and the trench. The expanded transistor hole exposes the etching barrier layer on the sidewall of the capacitor hole and the etching barrier layer on the sidewall of the trench. Multiple second sacrificial layers are formed at intervals on the inner wall of the expanded transistor hole; the second sacrificial layers expose the first capacitor electrode and the bit line, and the second sacrificial layers cover the etch barrier layer on the sidewall of the capacitor hole and the etch barrier layer on the sidewall of the trench.

13. The manufacturing method according to claim 12, characterized in that, The removal of the semiconductor layer and the contact layer located on the sidewall of the first insulating layer from the transistor hole includes: Remove the first sacrificial layer inside the capacitor hole to expose the etching barrier layer on the inner wall of the capacitor hole; Remove the etching barrier layer on the inner wall of the capacitor hole to expose the second sacrificial layer; At least a portion of the second sacrificial layer is removed to expose at least a portion of the semiconductor layer located on the sidewall of the first insulating layer of the transistor aperture; At least the semiconductor layer and the contact layer between two adjacent first capacitor electrodes stacked in a direction perpendicular to the substrate are removed, and the semiconductor layer and the contact layer are disconnected in a direction perpendicular to the substrate.

14. The manufacturing method according to claim 13, characterized in that, The removal of the semiconductor layer and the contact layer located on the sidewall of the first insulating layer from the transistor hole includes: Remove the first sacrificial layer within the trench to expose the etching barrier layer on the inner wall of the trench; Remove the etching barrier layer on the inner wall of the trench to expose the second sacrificial layer; At least a portion of the second sacrificial layer is removed to expose at least a portion of the semiconductor layer located on the sidewall of the first insulating layer of the transistor aperture; At least the semiconductor layer and the contact layer between two adjacent bit lines stacked in a direction perpendicular to the substrate are removed, and the semiconductor layer and the contact layer are disconnected in a direction perpendicular to the substrate.

15. The manufacturing method according to claim 13 or 14, characterized in that, The same etching process is used to remove the first sacrificial layer in the capacitor hole and the trench; The same etching process is used to remove the etching barrier layer on the inner wall of the capacitor hole and the trench; The second sacrificial layer is removed from the capacitor holes and the trenches using the same etching process; The semiconductor layer and the contact layer on the sidewall of the first insulating layer of the transistor hole are removed from the capacitor hole and the trench using the same etching process.

16. An electronic device, characterized in that, It includes the semiconductor device according to any one of claims 1 to 7, or it includes the semiconductor device obtained by the manufacturing method of the semiconductor device according to any one of claims 8 to 15.

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