Semiconductor structure

Abstract

A semiconductor structure includes a first die, a second die, and a first via. The first die includes a first substrate, a first interconnect structure having a first conductive pad, and a first bonding layer on the first conductive pad. The second die includes a second bonding layer bonded to the first bonding layer, a second substrate on the second bonding layer, and a second interconnect structure. The first via passes through the second die and the first bonding layer and is coupled to the first conductive pad. The first via includes a first portion having a first width, and a second portion coupled to the first portion and having a second width different from the first width, where the first portion is surrounded by the first bonding layer and adjacent to the second interconnect structure, and the second portion is surrounded by the second substrate.

Description

Technical Field

[0001] This disclosure claims priority to U.S. Patent Application No. 18 / 951,912 (i.e., priority date "November 19, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor structure and a method for manufacturing the semiconductor structure. More particularly, this disclosure relates to a semiconductor structure having through-silicon vias and a method for manufacturing the semiconductor structure including forming the through-silicon vias. Background Technology

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication of semiconductor components involves sequentially depositing various material layers on a semiconductor wafer and using lithography and etching processes to pattern the material layers to form microelectronic components, including transistors, diodes, resistors, and / or capacitors, on or within the semiconductor wafer.

[0004] The semiconductor industry continuously improves the integration density of microelectronic components by constantly shrinking the smallest feature size, allowing more components to be integrated within a given area. To facilitate the formation and integration of components of different sizes, smaller package structures with smaller footprints are being developed to encapsulate semiconductor devices. However, such formation and integration can increase the complexity of the manufacturing process. Therefore, improvements are desired to address these issues.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of the "prior art" in this case. Summary of the Invention

[0006] The purpose of this disclosure is to provide a semiconductor structure to solve at least one of the above-mentioned problems.

[0007] One aspect of this disclosure provides a semiconductor structure. The semiconductor structure includes a first die, a second die, and a first via. The first die includes a first substrate, a first dielectric layer on the first substrate, a first interconnect structure disposed within the first dielectric layer and having a first conductive pad, and a first bonding layer on the first dielectric layer, wherein the first dielectric layer at least partially exposes the first conductive pad. The second die includes a second bonding layer bonded to the first bonding layer, a second substrate on the second bonding layer, and a second interconnect structure between the second bonding layer and the second substrate. The first via penetrates the second die and the first bonding layer and is coupled to the first conductive pad.

[0008] The first via includes a first portion having a first width, and a second portion coupled to the first portion and having a second width, the second width being different from the first width, wherein the first portion is surrounded by the first bonding layer and adjacent to the second interconnect structure, and the second portion is surrounded by the second substrate.

[0009] Another aspect of this disclosure provides a semiconductor structure. The semiconductor structure includes a first die, a second die, a third die, a first via, and a second via. The first die includes a first substrate, a first interconnect structure disposed on the first substrate and having a first conductive pad, and a first bonding layer on the first conductive pad. The second die includes a second bonding layer bonded to the first bonding layer, a second substrate on the second bonding layer, and a second interconnect structure between the second bonding layer and the second substrate. The third die includes a third bonding layer bonded to the second die, a third substrate on the third bonding layer, and a third interconnect structure between the third bonding layer and the third substrate. The first via penetrates the second die and enters the first die. The second via penetrates the third die and is electrically connected to the first via. The second grain is disposed between the first grain and the third grain. The first guide hole has a tapered cross-sectional structure. A first contact surface area of ​​the first guide hole contacts a second contact surface area of ​​the second guide hole, and the size of the first contact surface area is different from the size of the second contact surface area.

[0010] Another aspect of this disclosure provides a method for manufacturing a semiconductor structure. The method includes the steps of forming a first die, forming a second die, and bonding the second die to the first die. The formation of the first die includes providing a first substrate and a first dielectric layer on the first substrate, forming a first interconnect structure having a first conductive pad within the first dielectric layer, and disposing a first bonding layer on the first dielectric layer that contacts the first conductive pad.

[0011] The formation of the second grain includes providing a second substrate and a second dielectric layer on the second substrate, forming a second interconnect structure having a second conductive pad in the second dielectric layer, and providing a second bonding layer on the second dielectric layer that contacts the second conductive pad.

[0012] The method further includes bonding a first bonding layer to the second bonding layer to bond the first die to the second die; removing a portion of the second die and a portion of the first bonding layer to form a first opening, wherein the first opening exposes the first conductive pad, and the first opening includes a first portion having a first width and surrounded by the first die and a second portion having a second width different from the first width; and disposing a first conductive material within the first opening to form a first via. The first via includes a first portion having the first width and a second portion coupled to the first portion and having the second width.

[0013] In summary, the process involves bonding a first die to a second die via fusion bonding, and then extending a through-silicon via (TSV) in the second die into the first die and electrically coupling it to a conductive pad in the first die. A dielectric-to-dielectric interface is formed between the first and second dies. The aforementioned TSV has a tapered profile, and no release layer (temporary layer) is required between the first and second dies. This eliminates several processes (e.g., release processes, flip-flop processes, and microbump bonding processes) and reduces the thickness of the semiconductor structure, thereby increasing its density (the product's z-axis height). Therefore, costs are reduced while ensuring good electrical properties and reliability of the high-density semiconductor structure.

[0014] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0015] This disclosure will be more fully understood by referring to the embodiments and claims, and it should also be understood that this disclosure relates to the reference numerals in the drawings, which refer to similar elements throughout the disclosure.

[0016] Figure 1 This is a schematic cross-sectional view of a first semiconductor structure according to some embodiments of the present disclosure.

[0017] Figure 2 For along Figure 1 The top cross-sectional view of various embodiments of the first and second vias of the first semiconductor structure is shown along the center line A-A'.

[0018] Figure 3 For along Figure 1 The top cross-sectional view of various embodiments of the first and second vias of the first semiconductor structure is shown along the center line A-A'.

[0019] Figure 4 For along Figure 1 The top cross-sectional view of various embodiments of the first and second vias of the first semiconductor structure is shown along the center line A-A'.

[0020] Figure 5 This is a schematic cross-sectional view of a second semiconductor structure according to some embodiments of the present disclosure.

[0021] Figure 6 This is a flowchart of a method for manufacturing a display semiconductor structure according to some embodiments of the present disclosure.

[0022] Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figures 9 to 12 , Figure 13A , Figure 13B and Figures 14 to 23 This diagram shows a cross-sectional view of an intermediate stage in the formation of a semiconductor structure according to some embodiments of the present disclosure.

[0023] The attached figures are labeled as follows:

[0024] 100: First semiconductor structure

[0025] 100i: Intermediate Structure

[0026] 101: First grain

[0027] 101a: First basement

[0028] 101b: First interconnect layer

[0029] 101c: First dielectric layer

[0030] 101d: First interconnect structure

[0031] 101e: First pad portion

[0032] 101f: First guide hole section

[0033] 101g: First conductive pad

[0034] 101h: First bonding layer

[0035] 101j: Third guide hole

[0036] 101k: First Electronic Component

[0037] 101l: First passivation layer

[0038] 102: Second grain

[0039] 102a: Second substrate

[0040] 102b: Second Interconnect Layer

[0041] 102c: Second dielectric layer

[0042] 102d: Second interconnect structure

[0043] 102e: Second pad portion

[0044] 102f: Second guide hole section

[0045] 102g: Second conductive pad

[0046] 102h: Fourth bonding layer

[0047] 102j: Second bonding layer

[0048] 102k: Second electronic component

[0049] 102l: Second passivation layer

[0050] 103: Third grain

[0051] 103a: Third basement

[0052] 103b: Third Interconnect Layer

[0053] 103c: Third dielectric layer

[0054] 103d: Third interconnect structure

[0055] 103e: Third pad portion

[0056] 103f: Third guide hole section

[0057] 103g: Third conductive pad

[0058] 103h: Fifth bonding layer

[0059] 103j: Third bonding layer

[0060] 103k: Third electronic component

[0061] 103l: Third passivation layer

[0062] 103x: Interface

[0063] 104: Conductive bump

[0064] 105: Molded parts

[0065] 106: First guide hole

[0066] 106': First conductive material

[0067] 106a: Part 1

[0068] 106b: Part Two

[0069] 106c: Barrier layer

[0070] 106i: Interface

[0071] 106o: First opening

[0072] 106s: Stepped structure

[0073] 106x: First contact surface area

[0074] 107: Second guide hole

[0075] 107': Second conductive material

[0076] 107a: Part 1

[0077] 107b: Part Two

[0078] 107c: Barrier Layer

[0079] 107i: Interface

[0080] 107o: Second opening

[0081] 107s: Stepped structure

[0082] 107x: Second contact surface area

[0083] 108: Supporting base

[0084] 200: Second semiconductor structure

[0085] 201: Intermediary Layer

[0086] A1: First cross-sectional area

[0087] A2: Second section area

[0088] A3: Third Sectional Region

[0089] A4: Fourth Sectional Area

[0090] S300: Method

[0091] S301: Steps

[0092] S302: Steps

[0093] S303: Steps

[0094] S304: Steps

[0095] S305: Steps

[0096] S306: Steps

[0097] S307: Steps

[0098] S308: Steps

[0099] S309: Steps

[0100] S310: Steps

[0101] S311: Steps

[0102] W1: First width

[0103] W2: Second width

[0104] W3: First width

[0105] W4: Second width Detailed Implementation

[0106] The embodiments or examples of this disclosure illustrated in the accompanying drawings are now described using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any substitutions or modifications to the described embodiments, and any further application of the principles described herein, should be considered as common to those skilled in the art to which this disclosure pertains. Reference numerals may be repeated in the embodiments, but even if they share the same reference numerals, it does not necessarily mean that one or more features of one embodiment are applicable to another embodiment.

[0107] It should be understood that although terms such as first, second, third, etc., are used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another. Therefore, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section without departing from the teachings of the present invention.

[0108] The terminology used herein is for describing specific exemplary embodiments only and is not intended to limit the concept of the invention. Unless expressly indicated herein, the singular forms “a” and “the” as used herein may also include the plural forms. It should be understood that when the word “comprising” is used in this specification, it indicates the presence of the stated feature, integer, step, operation, element, or component, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0109] Figure 1 This is a schematic cross-sectional view of a first semiconductor structure 100 according to some embodiments of the present disclosure. In some embodiments, the first semiconductor structure 100 is part of a die, a package, or an element. In some embodiments, the first semiconductor structure 100 is a die, a package, or an element. In some embodiments, the first semiconductor structure 100 is a bonding structure.

[0110] In some embodiments, the first semiconductor structure 100 includes a first die 101 and a second die 102 stacked on the first die 101. In some embodiments, the first die 101 and the second die 102 include any of various known types of semiconductor elements, such as accelerated processing units (APUs), memory, dynamic random-access memory (DRAM), NAND flash memory, central processing units (CPUs), graphics processing units (GPUs), microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), logic dies, or similar elements. In some embodiments, the first die 101 is a logic die.

[0111] In some embodiments, the first die 101 includes a first substrate 101a, a first passivation layer 101l on the first substrate 101a, at least one first electronic element 101k disposed within the first passivation layer 101l, a first interconnect layer 101b on the first passivation layer 101l and the first electronic element 101k, and a first bonding layer 101h on the first interconnect layer 101b. In some embodiments, the first substrate 101a is a semiconductor layer. In some embodiments, the first substrate 101a comprises a semiconductor material, such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the first substrate 101a is a silicon substrate.

[0112] In some embodiments, the first electronic component 101k includes any known type of semiconductor element, such as N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) elements, capacitors, resistors, diodes, photodiodes, fuses, and / or similar elements. In some embodiments, the first electronic component 101k is electrically connected to an external circuit (not shown) and the first interconnect layer 101b. In some embodiments, the first electronic component 101k is surrounded by a first passivation layer 101l. In some embodiments, the first passivation layer 101l is disposed between the first substrate 101a and the first interconnect layer 101b. In some embodiments, the first passivation layer 101l comprises a dielectric material, such as oxides, nitrides, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymers, or similar materials.

[0113] In some embodiments, a first interconnect layer 101b is disposed on the front side of a first substrate 101a. In some embodiments, the first interconnect layer 101b is disposed on a first passivation layer 101l. In some embodiments, the first interconnect layer 101b includes a first dielectric layer 101c and a first interconnect structure 101d surrounded by the first dielectric layer 101c. In some embodiments, the first dielectric layer 101c is disposed above the first substrate 101a. In some embodiments, the first dielectric layer 101c includes a dielectric material, such as an oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer, or similar material. In some embodiments, the first dielectric layer 101c includes a plurality of dielectric layers stacked on top of each other. In some embodiments, each dielectric layer includes the same or different material as the other dielectric layers.

[0114] In some embodiments, the first interconnect structure 101d includes a first pad portion 101e, a first via portion 101f, and a first conductive pad 101g. In some embodiments, the first pad portion 101e and the first via portion 101f are embedded in a first dielectric layer 101c. In some embodiments, the first pad portion 101e extends laterally within the first dielectric layer 101c, and the first via portion 101f extends longitudinally within the first dielectric layer 101c. In some embodiments, the first via portion 101f is electrically coupled to the first pad portion 101e. In some embodiments, the first pad portion 101e and the first via portion 101f comprise a conductive material, such as gold, silver, copper, nickel, tungsten, aluminum, tin, the aforementioned alloys, or similar materials.

[0115] In some embodiments, a first conductive pad 101g is disposed above a first pad portion 101e and a first via portion 101f. In some embodiments, the first conductive pad 101g is surrounded by a first dielectric layer 101c, and the first dielectric layer 101c at least partially exposes the first conductive pad 101g. In some embodiments, the first conductive pad 101g is electrically connected to the first pad portion 101e via the first via portion 101f. In some embodiments, the first conductive pad 101g contacts the first via portion 101f. In some embodiments, the first conductive pad 101g comprises a conductive material, such as gold, silver, copper, nickel, tungsten, aluminum, tin, the aforementioned alloys, or similar materials. In some embodiments, the top or bottom surface of the first conductive pad 101g has a circular, quadrilateral, or polygonal shape.

[0116] In some embodiments, a first bonding layer 101h is disposed on a first interconnect layer 101b and a first substrate 101a. In some embodiments, the first bonding layer 101h comprises a dielectric material, such as an oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer, or similar material. In some embodiments, the first bonding layer 101h is used to form a bond with another bonding layer. In some embodiments, the top surface of the first conductive pad 101g is exposed and contacts the first bonding layer 101h. In some embodiments, the first bonding layer 101h partially covers the first conductive pad 101g.

[0117] In some embodiments, the second die 102 is disposed above the first die 101. In some embodiments, the first die 101 and the second die 102 are face-to-face. In some embodiments, the second die 102 is flipped vertically, and the second die 102 includes a second substrate 102a, a second passivation layer 102l under the second substrate 102a, a second electronic component 102k within the second passivation layer 102l, a second interconnect layer 102b under the second passivation layer 102l, a second bonding layer 102j under the second interconnect layer 102b, and a fourth bonding layer 102h on the second substrate 102a. In some embodiments, the second substrate 102a is a semiconductor layer. In some embodiments, the second substrate 102a contains a semiconductor material. In some embodiments, the second substrate 102a is a silicon substrate.

[0118] In some embodiments, the second bonding layer 102j is bonded to the first bonding layer 101h. In some embodiments, the second bonding layer 102j comprises a dielectric material, such as an oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer, or similar material. In some embodiments, the second grain 102 is bonded to the first grain 101 by bonding the first bonding layer 101h to the second bonding layer 102j. In some embodiments, the top or bottom surface of the second conductive pad 102g is exposed and contacts the second bonding layer 102j. In some embodiments, the second bonding layer 102j partially covers the second conductive pad 102g.

[0119] In some embodiments, the second interconnect layer 102b includes a second dielectric layer 102c and a second interconnect structure 102d surrounding the second dielectric layer 102c. In some embodiments, the second dielectric layer 102c is disposed between the second substrate 102a and the second bonding layer 102j. In some embodiments, the second dielectric layer 102c includes a dielectric material, such as an oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer, or similar material. In some embodiments, the second dielectric layer 102c includes a plurality of dielectric layers stacked on top of each other. In some embodiments, each dielectric layer includes the same or different material as the other dielectric layers.

[0120] In some embodiments, the second interconnect structure 102d includes a second pad portion 102e, a second via portion 102f, and a second conductive pad 102g. In some embodiments, the second pad portion 102e and the second via portion 102f are embedded in a second dielectric layer 102c. In some embodiments, the second pad portion 102e extends laterally within the second dielectric layer 102c, and the second via portion 102f extends longitudinally within the second dielectric layer 102c. In some embodiments, the second via portion 102f is electrically coupled to the second pad portion 102e. In some embodiments, the second dielectric layer 102c at least partially exposes the second pad portion 102e. In some embodiments, the second pad portion 102e and the second via portion 102f comprise a conductive material, such as gold, silver, copper, nickel, tungsten, aluminum, tin, the aforementioned alloys, or similar materials.

[0121] In some embodiments, a second conductive pad 102g is disposed beneath a second pad portion 102e and a second via portion 102f. In some embodiments, a second dielectric layer 102c surrounds the second conductive pad 102g and at least partially exposes the second conductive pad 102g. In some embodiments, the second conductive pad 102g is electrically connected to the second pad portion 102e via the second via portion 102f. In some embodiments, the second conductive pad 102g contacts the second via portion 102f. In some embodiments, the second conductive pad 102g comprises a conductive material, such as gold, silver, copper, nickel, tungsten, aluminum, tin, the aforementioned alloys, or similar materials. In some embodiments, the top or bottom surface of the second conductive pad 102g has a circular, quadrilateral, or polygonal shape.

[0122] In some embodiments, the second electronic element 102k includes any known type of semiconductor element, such as NMOS and / or PMOS elements, capacitors, resistors, diodes, photodiodes, fuses, and / or similar elements. In some embodiments, the second electronic element 102k is electrically connected to an external circuit and the second interconnect layer 102b. In some embodiments, the second electronic element 102k is surrounded by a second passivation layer 102l. In some embodiments, the second passivation layer 102l is disposed between the second substrate 102a and the second interconnect layer 102b. In some embodiments, the second passivation layer 102l comprises a dielectric material, such as oxides, nitrides, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymers, or similar materials.

[0123] In some embodiments, a fourth bonding layer 102h is disposed on the second substrate 102a. In some embodiments, the fourth bonding layer 102h comprises a dielectric material, such as an oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer, or similar material. In some embodiments, the fourth bonding layer 102h is used to form a bond with another bonding layer. In some embodiments, the fourth bonding layer 102h covers the second substrate 102a.

[0124] A first via 106 penetrates the second die 102 and enters the first die 101. In some embodiments, the first semiconductor structure 100 includes a plurality of first vias 106. In some embodiments, the first via 106 penetrates the second die 102, the first bonding layer 101h, the second bonding layer 102j, and is coupled to the first conductive pad 101g. In some embodiments, the first via 106 is a through-substrate via (TSV). A dielectric-to-dielectric bonding interface and the first via 106 are formed between the first die 101 and the second die 102, and no micro-bumps are required between the first die 101 and the second die 102. Therefore, the first via 106 in the second die 102 extending into the first die 101 can improve the overall structure and reliability of the first semiconductor structure 100.

[0125] In some embodiments, the second grain 102 and at least a portion of the first grain 101 surround the first via 106. In some embodiments, the second grain 102 and the first bonding layer 101h surround the first via 106. In some embodiments, the first via 106 is electrically isolated from the second interconnect structure 102d.

[0126] In some embodiments, the first via 106 protrudes from the first conductive pad 101g to the second grain 102. In some embodiments, the first via 106 comprises a conductive material, such as gold, silver, copper, nickel, tungsten, aluminum, tin, the aforementioned alloys, or similar materials. In some embodiments, the first via 106 extends in a direction perpendicular to the first conductive pad 101g.

[0127] In some embodiments, the first via 106 has a tapered cross-sectional structure. Due to the cross-sectional structure of the first via 106, the reliability of the first semiconductor structure 100, which includes a first die 101 and a second die 102 joined together, can be improved. In some embodiments, the first via 106 includes a first portion 106a having a first width W1, and a second portion 106b coupled to the first portion 106a and having a second width W2, the second width W2 being different from the first width W1. In some embodiments, because the first width W1 is different from the second width W2, the first via 106 has a stepped structure 106s disposed at the interface 106i of the first portion 106a and the second portion 106b. In some embodiments, the first portion 106a and the second portion 106b are integral.

[0128] In some embodiments, a first portion 106a of the first via 106 is disposed between a second portion 106b of the first via 106 and a first conductive pad 101g. In some embodiments, the first portion 106a is surrounded by a first bonding layer 101h and a second interconnect layer 102b, while the second portion 106b is surrounded by a second passivation layer 102l, a second substrate 102a, and a fourth bonding layer 102h.

[0129] In some embodiments, the second width W2 is greater than the first width W1. In some embodiments, the second width W2 is less than the first width W1. In some embodiments, the first portion 106a has a first cross-sectional region A1, the second portion 106b has a second cross-sectional region A2, and the size of the first cross-sectional region A1 is different from the size of the second cross-sectional region A2. In some embodiments, the size of the second cross-sectional region A2 is greater than the size of the first cross-sectional region A1. In some embodiments, the size of the second cross-sectional region A2 is smaller than the size of the first cross-sectional region A1. The first cross-sectional region A1 and the second cross-sectional region A2 have similar or different shapes. In some embodiments, the first cross-sectional region A1 and the second cross-sectional region A2 may each be circular, quadrilateral, or polygonal.

[0130] In some embodiments, the first via 106 further includes a barrier layer 106c surrounding the first portion 106a and the second portion 106b. In some embodiments, the barrier layer 106c is disposed between the second grain 102 and the first portion 106a, and between the second grain 102 and the second portion 106b. In some embodiments, the barrier layer 106c is a diffusion barrier, such as a titanium nitride layer, a tantalum nitride layer, a titanium layer, a tantalum layer, or a similar material.

[0131] In some embodiments, the first semiconductor structure 100 further includes a third die 103 stacked on the second die 102 and the first die 101. In some embodiments, the third die 103 has a similar configuration to the second die 102.

[0132] In some embodiments, the third die 103 is disposed above the second die 102. In some embodiments, the third die 103 and the second die 102 are face-to-back. In some embodiments, the third die 103 is flipped vertically, and the third die 103 includes a third substrate 103a, a third passivation layer 103l under the third substrate 103a, a third electronic element 103k within the third passivation layer 103l, a third interconnect layer 103b under the third passivation layer 103l, a third bonding layer 103j under the third interconnect layer 103b, and a fifth bonding layer 103h on the third substrate 103a. In some embodiments, the third substrate 103a is a semiconductor layer. In some embodiments, the third substrate 103a is a silicon substrate.

[0133] In some embodiments, the third bonding layer 103j is bonded to the second bonding layer 102h. In some embodiments, the third bonding layer 103j comprises a dielectric material. In some embodiments, the third grain 103 is bonded to the second grain 102 by bonding the third bonding layer 103j to the fourth bonding layer 102h. In some embodiments, the top or bottom surface of the third conductive pad 103g is exposed and contacts the third bonding layer 103j. In some embodiments, the third bonding layer 103j partially covers the third conductive pad 103g.

[0134] In some embodiments, the third interconnect layer 103b includes a third dielectric layer 103c and a third interconnect structure 103d surrounded by the third dielectric layer 103c. In some embodiments, the third dielectric layer 103c is disposed between the third substrate 103a and the third bonding layer 103j. In some embodiments, the third dielectric layer 103c includes a dielectric material.

[0135] In some embodiments, the third interconnect structure 103d includes a third pad portion 103e, a third via portion 103f, and a third conductive pad 103g. In some embodiments, the third pad portion 103e and the third via portion 103f are embedded in a third dielectric layer 103c. In some embodiments, the third pad portion 103e extends laterally within the third dielectric layer 103c, and the third via portion 103f extends longitudinally within the third dielectric layer 103c. In some embodiments, the third via portion 103f is electrically coupled to the third pad portion 103e. In some embodiments, the third dielectric layer 103c at least partially exposes the third pad portion 103e. In some embodiments, the third pad portion 103e and the third via portion 103f comprise a conductive material.

[0136] In some embodiments, a third conductive pad 103g is disposed beneath a third pad portion 103e and a third via portion 103f. In some embodiments, a third dielectric layer 103c surrounds the third conductive pad 103g, and the third dielectric layer 103c at least partially exposes the third conductive pad 103g. In some embodiments, the third conductive pad 103g is electrically connected to the third pad portion 103e via the third via portion 103f. In some embodiments, the third conductive pad 103g contacts the third via portion 103f. In some embodiments, the third conductive pad 103g comprises a conductive material. In some embodiments, the bottom or top surface of the third conductive pad 103g has a circular, quadrilateral, or polygonal shape.

[0137] In some embodiments, the third electronic component 103k includes any known type of semiconductor element, such as NMOS and / or PMOS elements, capacitors, resistors, diodes, photodiodes, fuses, and / or similar elements. In some embodiments, the third electronic component 103k is electrically connected to an external circuit and the third interconnect layer 103b. In some embodiments, the third electronic component 103k is surrounded by a third passivation layer 103l. In some embodiments, the third passivation layer 103l is disposed between the third substrate 103a and the third interconnect layer 103b. In some embodiments, the third passivation layer 103l comprises a dielectric material.

[0138] In some embodiments, a fifth bonding layer 103h is disposed on a third substrate 103a. In some embodiments, the fifth bonding layer 103h comprises a dielectric material. In some embodiments, the fifth bonding layer 103h is used to form a bond with another component (e.g., a carrier substrate 108). In some embodiments, the fifth bonding layer 103h covers the third substrate 103a.

[0139] The second via 107 penetrates the third die 103, the third bonding layer 103j, and the fourth bonding layer 102h, and is electrically connected to the first via 106. In some embodiments, the second via 107 penetrates the third die 103 and is coupled to a second portion 106b of the first via 106. In some embodiments, the second via 107 is a TSV. A dielectric-to-dielectric bonding interface and a second contact surface region 107x of the second via 107 are formed between the second die 102 and the third die 103, eliminating the need for microbumps between the second die 102 and the third die 103. Therefore, the second via 107 within the third die 103 can improve the overall structure and reliability of the first semiconductor structure 100.

[0140] In some embodiments, a third die 103 surrounds a second via 107. In some embodiments, the second via 107 is electrically isolated from a third interconnect structure 103d. In some embodiments, the first via 106 and the second via 107 are vertically stacked to form a vertical interconnect of the first semiconductor structure 100. In some embodiments, the first via 106 is disposed between the second via 107 and a first conductive pad 101g, and the first via 106 and the second via 107 improve the overall structure and reliability of the first semiconductor structure 100. In some embodiments, the first semiconductor structure 100 includes a plurality of second vias 102. In some embodiments, each of the plurality of second vias 102 is coupled to a corresponding one of the plurality of first vias 106. In some embodiments, the number of the plurality of first vias 106 is equal to the number of the plurality of second vias 102.

[0141] In some embodiments, the second via 107 comprises a conductive material, such as gold, silver, copper, nickel, tungsten, aluminum, tin, the aforementioned alloys, or similar materials. In some embodiments, the first via 106 and the second via 107 comprise the same material. In some embodiments, the first via 106 and the second via 107 extend in the same direction. In some embodiments, the second via 107 extends in a direction perpendicular to the third conductive pad 103g.

[0142] In some embodiments, the second via 107 has a tapered cross-sectional structure. Due to the cross-sectional structure of the second via 107, the reliability of the first semiconductor structure 100, which includes a second grain 102 and a third grain 103 joined together, can be improved. In some embodiments, the second via 107 includes a third portion 107a having a third width W3, and a fourth portion 107b coupled to the third portion 107a and having a fourth width W4. In some embodiments, the third width W3 is different from the fourth width W4, and the second via 107 has a stepped structure 107s disposed at the interface 107i of the third portion 107a and the fourth portion 107b. In some embodiments, the third portion 107a and the fourth portion 107b are integral.

[0143] In some embodiments, a third portion 107a of the second via 107 is disposed between a fourth portion 107b of the second via 107 and the first via 106. In some embodiments, the third portion 107a is surrounded by a third interconnect layer 103b, while the fourth portion 107b is surrounded by a third passivation layer 103l, a third substrate 103a, and a fifth bonding layer 103h.

[0144] In some embodiments, the fourth width W4 is greater than the third width W3. In some embodiments, the fourth width W4 is less than the third width W3. In some embodiments, the third portion 107a has a third cross-sectional region A3, and the fourth portion 107b has a fourth cross-sectional region A4, and the size of the third cross-sectional region A3 is different from the size of the fourth cross-sectional region A4. In some embodiments, the size of the fourth cross-sectional region A4 is greater than the size of the third cross-sectional region A3. In some embodiments, the size of the fourth cross-sectional region A4 is smaller than the size of the third cross-sectional region A3. The third cross-sectional region A3 and the fourth cross-sectional region A4 have similar or different shapes. In some embodiments, the third cross-sectional region A3 and the fourth cross-sectional region A4 may each be circular, quadrilateral, or polygonal.

[0145] In some embodiments, the second via 107 further includes a barrier layer 107c surrounding the third portion 107a and the fourth portion 107b. In some embodiments, the barrier layer 107c is disposed between the third grain 103 and the third portion 107a, and between the third grain 103 and the fourth portion 107b. In some embodiments, the barrier layer 107c includes a diffusion barrier, such as a titanium nitride layer, a tantalum nitride layer, a titanium layer, a tantalum layer, or a similar material.

[0146] Figures 2 to 4 Showing various shapes of the first guide hole 106 and the second guide hole 107. See also Figures 1 to 4 The first contact surface region 106x of the first guide hole 106 contacts the second contact surface region 107x of the second guide hole 107, and the size of the first contact surface region 106x is different from the size of the second contact surface region 107x. In some embodiments, the first contact surface region 106x and the second contact surface region 107x each have a circular, quadrilateral, or polygonal shape. In some embodiments, the second width W2 is greater than the third width W3. In some embodiments, the size of the first contact surface region 106x is substantially larger than the size of the second contact surface region 107x, and the first contact surface region 106x contacts the second contact surface region 107x and the third bonding layer 103j. In some embodiments, the second width W2 is smaller than the third width W3. In some embodiments, the size of the second contact surface region 107x is substantially larger than the size of the first contact surface region 106x, and the second contact surface region 107x contacts the first contact surface region 106x and the fourth bonding layer 102h. In some embodiments, the first contact surface region 106x and the second contact surface region 107x form a stepped structure. In some embodiments, the interface 103x between the second grain 102 and the third grain 103 is coplanar with the first contact surface region 106x and the second contact surface region 107x.

[0147] like Figure 2 and Figure 3 As shown, the cross-section of the third portion 107a of the second guide hole 107 and the cross-section of the second portion 106b of the first guide hole 106 have different shapes. In some embodiments, such as Figure 2 As shown, the first contact surface region 106x is circular, while the second contact surface region 107x is quadrilateral. In some embodiments, such as Figure 3 As shown, the first contact surface region 106x is quadrilateral in shape, while the second contact surface region 107x is circular in shape. Figure 4 As shown, the cross-section of the third part 107a of the second guide hole 107 and the cross-section of the second part 106b of the first guide hole 106 have the same shape.

[0148] In some embodiments, see Figure 1A conductive bump 104 is disposed under the first die 101. In some embodiments, the conductive bump 104 is received by a first substrate 101a and electrically connected to a third via 101j disposed within the first substrate 101a. In some embodiments, the conductive bump 104 is used to connect to an external circuit or external interconnect structure. In some embodiments, the conductive bump 104 is electrically connected to the first die 101, the second die 102, and the third die 103 via the third via 101j.

[0149] In some embodiments, the conductive bump 104 comprises a low-temperature reflowable material. In some embodiments, the conductive bump 104 comprises a soldering material, such as tin, lead, silver, copper, nickel, bismuth, or a combination thereof. In some embodiments, the conductive bump 104 comprises a conductive material, such as gold, silver, copper, nickel, tungsten, aluminum, tin, the aforementioned alloys, or similar materials. In some embodiments, the conductive bump 104 is a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump, a microbump, etc.

[0150] Figure 5 This is a schematic cross-sectional view of a second semiconductor structure 200 according to some embodiments of the present disclosure. The second semiconductor structure 200 includes a first semiconductor structure 100, a molding 105, and an interposer 201. In some embodiments, the molding 105 surrounds a first die 101, a second die 102, and a third die 103. In some embodiments, the first semiconductor structure 100 is electrically connected to the interposer 201 via conductive bumps 104.

[0151] Figure 6 To illustrate a flowchart of a method S300 for manufacturing a first semiconductor structure 100 according to some embodiments of the present disclosure, and Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figures 9 to 12 , Figure 13A , Figure 13B and Figures 14 to 23 A cross-sectional schematic diagram showing an intermediate stage in the formation of a first semiconductor structure 100 and a second semiconductor structure 200 according to some embodiments of the present disclosure.

[0152] Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figures 9 to 12 , Figure 13A , Figure 13B and Figures 14 to 23The displayed stages are also schematically shown in Figure 6 In the flowchart. In the following description, Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figures 9 to 12 , Figure 13A , Figure 13B and Figures 14 to 23 The manufacturing stage shown will refer to Figure 6 The process steps shown in the diagram will be discussed. Method S300 contains multiple operations, and the descriptions and illustrations should not be considered as limitations on the order of operations. Method S300 contains multiple steps (S301, S302, S303, S304, S305, S306, S307, S308, S309, S310, and S311).

[0153] See Figures 7A to 7B ,according to Figure 6 In step S301, the first grain 101 is formed. See also... Figure 7A ,according to Figure 6 In step S302, the formation of the first die 101 includes providing a first substrate 101a and a first dielectric layer 101c on the first substrate 101a. In some embodiments, the first substrate 101a is a semiconductor layer. In some embodiments, the first substrate 101a comprises a semiconductor material. In some embodiments, the first substrate 101a is a silicon substrate.

[0154] In some embodiments, a first dielectric layer 101c is disposed above a first substrate 101a. In some embodiments, the first dielectric layer 101c comprises a dielectric material. In some embodiments, the first dielectric layer 101c is formed by deposition, chemical vapor deposition (CVD), or other suitable processes. In some embodiments, a first passivation layer 101l is formed between the first substrate 101a and the first dielectric layer 101c, and a first electronic component 101k is formed on the first substrate 101a and within the first passivation layer 101l. In some embodiments, a third via 101j is formed within the first substrate 101a, and the third via 101j is electrically connected to the first electronic component 101k.

[0155] In some embodiments, a first interconnect structure 101d is formed within a first dielectric layer 101c. In some embodiments, the first interconnect structure 101d includes a first pad portion 101e and a first via portion 101f. In some embodiments, the first pad portion 101e and the first via portion 101f comprise a conductive material. In some embodiments, the first pad portion 101e and the first via portion 101f are formed by removing multiple portions of the first dielectric layer 101c to form multiple recesses, and then providing conductive material to fill the recesses. In some embodiments, the conductive material is provided by electroplating, sputtering, or other suitable processes.

[0156] In some embodiments, according to Figure 6 In step S303, a first interconnect structure 101d having a first conductive pad 101g is formed within the first dielectric layer 101c. In some embodiments, the first dielectric layer 101c at least partially exposes the first conductive pad 101g. In some embodiments, the first conductive pad 101g is formed by removing a portion of the first dielectric layer 101c to form a recess, and then providing a conductive material to fill the recess. In some embodiments, the conductive material is provided by electroplating, sputtering, or other suitable processes.

[0157] See Figure 7B ,according to Figure 6 In step S304, a first bonding layer 101h is formed on the first dielectric layer 101c to contact the first conductive pad 101g. In some embodiments, the first bonding layer 101h comprises a dielectric material. In some embodiments, the first bonding layer 101h and the first dielectric layer 101c cover and contact the top surface of the first conductive pad 101g. In some embodiments, the first bonding layer 101h is formed by deposition, CVD, or other suitable processes.

[0158] See Figure 8A and Figure 8B ,according to Figure 6 In step S305, the second grain 102 is formed. See also... Figure 8A ,according to Figure 6 In step S306, the formation of the second die 102 includes providing a second substrate 102a and a second dielectric layer 102c on the second substrate 102a. In some embodiments, the second substrate 102a is a semiconductor layer. In some embodiments, the second substrate 102a comprises a semiconductor material.

[0159] In some embodiments, a second dielectric layer 102c is disposed above a second substrate 102a. In some embodiments, the second dielectric layer 102c comprises a dielectric material. In some embodiments, the second dielectric layer 102c is formed by deposition, CVD, or other suitable processes. In some embodiments, a second passivation layer 102l is formed between the second substrate 102a and the second dielectric layer 102c, and a second electronic element 102k is formed on the second substrate 102a and within the second passivation layer 102l.

[0160] In some embodiments, a second interconnect structure 102d is formed within the second dielectric layer 102c. In some embodiments, the second interconnect structure 102d includes a second pad portion 102e and a second via portion 102f. In some embodiments, the second pad portion 102e and the second via portion 102f comprise a conductive material. In some embodiments, the second pad portion 102e and the second via portion 102f are formed by removing multiple portions of the second dielectric layer 102c to form multiple recesses, and then filling the recesses with a conductive material. In some embodiments, the conductive material is applied by electroplating, sputtering, or other suitable processes.

[0161] In some embodiments, according to Figure 6 In step S307, a second interconnect structure 102d having a second conductive pad 102g is formed within the second dielectric layer 102c. In some embodiments, the second dielectric layer 102c at least partially exposes the second conductive pad 102g. In some embodiments, the second conductive pad 102g is formed by removing a portion of the second dielectric layer 102c to form a recess, and then providing a conductive material to fill the recess. In some embodiments, the conductive material is provided by electroplating, sputtering, or other suitable processes.

[0162] See Figure 8B ,according to Figure 6 In step S308, a second bonding layer 102j is formed on the second dielectric layer 102c to contact the second conductive pad 102g. In some embodiments, the second bonding layer 102j comprises a dielectric material. In some embodiments, the second bonding layer 102j and the second dielectric layer 102c cover and contact the top surface of the second conductive pad 102g. In some embodiments, the second bonding layer 102j is formed by deposition, CVD, or other suitable processes.

[0163] See Figure 9 ,according to Figure 6 In step S309, the first bonding layer 101h is bonded to the second bonding layer 102j to bond the first grain 101 to the second grain 102. See also Figure 9 The second grain 102 is bonded to the first grain 101.

[0164] In some embodiments, a first grain 101 and a second grain 102 are formed, respectively. In some embodiments, the formation of the first grain 101 and the second grain 102 are performed simultaneously or separately. In some embodiments, the second grain 102 is flipped after its formation and before it is bonded to the first grain 101.

[0165] In some embodiments, fusion bonding is performed to bond the first grain 101 to the second grain 102. In some embodiments, fusion bonding includes bonding the first bonding layer 101h to the second bonding layer 102j.

[0166] In some embodiments, see Figure 10 After the second grain 102 is bonded to the first grain 101, a portion of the second substrate 102a is removed. A polishing process may be applied to remove the aforementioned portion of the second substrate 102a. After removal, the second substrate 102a is not completely removed and the second passivation layer 102l is not exposed.

[0167] In some embodiments, a fourth bonding layer 102h is disposed on the remaining portion of the second substrate 102a. In some embodiments, the fourth bonding layer 102h comprises a dielectric material. In some embodiments, the fourth bonding layer 102h completely covers and contacts the top surface of the second substrate 102a. In some embodiments, the fourth bonding layer 102h is disposed by deposition, CVD, or other suitable processes.

[0168] See Figure 11 ,according to Figure 6 In step S310, a portion of the second die 102 and a portion of the first die 101 are removed to form a first opening 106o, wherein the first opening 106o exposes the first conductive pad 101g, and the first opening 106o includes a first portion having a first width W1 and surrounded by the first die 101 and a second portion having a second width W2, the second width W2 being different from the first width W1. In some embodiments, according to step S310, the first opening 106o extends through the second die 102, and a portion of the first bonding layer 101h is removed to form the first opening 106o.

[0169] In some embodiments, the aforementioned portions of the second grain 102 and the first bonding layer 101h are removed by etching or other suitable processes. In some embodiments, the first opening 106o has a circular, quadrilateral, or polygonal shape. In some embodiments, the fourth bonding layer 102j is formed before the first opening 106o is formed, and the first opening 106o penetrates the fourth bonding layer 102j.

[0170] See Figure 12 ,according to Figure 6 In step S311, a first conductive material 106' is disposed within the first opening 106o to form a first via 106. In some embodiments, the first via 106 thus formed includes a first portion 106a having a first width W1, and a second portion 106b coupled to the first portion 106a and having a second width W2. In some embodiments, the second width W2 is greater than the first width W1.

[0171] In some embodiments, such as Figure 12 As shown, a first conductive material 106' is disposed on the first bonding layer 101h and within the first opening 106o. In some embodiments, the first conductive material 106' comprises gold, silver, copper, nickel, tungsten, aluminum, tin, the aforementioned alloys, or similar materials. In some embodiments, the first conductive material 106' is disposed by CVD, physical vapor deposition (PVD), sputtering, or other suitable processes.

[0172] In such Figure 12 After the first conductive material 106' is applied, a portion of the first conductive material 106' is removed from the second bonding layer 102h to form a first via 106. In some embodiments, the aforementioned portion of the first conductive material 106' is removed by planarization, etching, chemical mechanical planarization (CMP), or other suitable processes. In some embodiments, the first via 106 penetrates the second grain 102 and the first bonding layer 101h and contacts the first conductive pad 101g. In some embodiments, the first via 106 protrudes from the first conductive pad 101g. In some embodiments, such as... Figure 12 As shown, a first guide hole 106 with a tapered cross-sectional structure is formed.

[0173] In some embodiments, a first barrier layer 106c is formed within the first opening 106o, surrounding the first conductive material 106'. In some embodiments, the first barrier layer 106c is formed before the formation of the first portion 106a and the second portion 106b of the first via 106.

[0174] In some embodiments, method S300 further includes forming a third grain 103.

[0175] See Figure 13A The formation of the third grain 103 includes providing a third substrate 103a and a third dielectric layer 103c on the third substrate 103a. In some embodiments, the third substrate 103a is a semiconductor layer. In some embodiments, the third substrate 103a comprises a semiconductor material.

[0176] In some embodiments, a third dielectric layer 103c is disposed above a third substrate 103a. In some embodiments, the third dielectric layer 103c comprises a dielectric material. In some embodiments, the third dielectric layer 103c is formed by deposition, CVD, or other suitable processes. In some embodiments, a third passivation layer 103l is formed between the third substrate 103a and the third dielectric layer 103c, and a third electronic element 103k is formed on the third substrate 103a and within the third passivation layer 103l.

[0177] In some embodiments, a third interconnect structure 103d is formed within the third dielectric layer 103c. In some embodiments, the third interconnect structure 103d includes a third pad portion 103e and a third via portion 103f. In some embodiments, the third pad portion 103e and the third via portion 103f comprise a conductive material. In some embodiments, the third pad portion 103e and the third via portion 103f are formed by removing multiple portions of the third dielectric layer 103c to form multiple recesses, and then filling the recesses with a conductive material. In some embodiments, the conductive material is applied by electroplating, sputtering, or other suitable processes.

[0178] In some embodiments, a third interconnect structure 103d having a third conductive pad 103g is formed within a third dielectric layer 103c. In some embodiments, the third dielectric layer 103c at least partially exposes the third conductive pad 103g. In some embodiments, the third conductive pad 103g is formed by removing a portion of the third dielectric layer 103c to form a recess, and then providing a conductive material to fill the recess. In some embodiments, the conductive material is provided by electroplating, sputtering, or other suitable processes.

[0179] See Figure 13B A third bonding layer 103j, which contacts the third conductive pad 103g, is formed on the third dielectric layer 103c. In some embodiments, the third bonding layer 103j comprises a dielectric material. In some embodiments, the third bonding layer 103j and the third dielectric layer 103c cover and contact the top surface of the third conductive pad 103g. In some embodiments, the third bonding layer 103j is formed by deposition, CVD, or other suitable processes.

[0180] See Figure 14 In some embodiments, the third bonding layer 103j is bonded to the fourth bonding layer 102h to bond the third grain 103 to the second grain 102. In some embodiments, the third grain 103 is bonded to the second grain 102.

[0181] In some embodiments, a third grain 103 and a second grain 102 are formed, respectively. In some embodiments, the formation of the second grain 102 and the formation of the third grain 103 are performed simultaneously or separately. In some embodiments, the third grain 103 is flipped after its formation and before it is bonded to the second grain 102.

[0182] In some embodiments, fusion bonding is performed to bond the third grain 103 to the second grain 102. In some embodiments, fusion bonding includes bonding the third bonding layer 103j to the fourth bonding layer 102h.

[0183] In some embodiments, see Figure 15 After the third grain 103 is bonded to the second grain 102, a portion of the third substrate 103a is removed. A polishing process may be applied to remove the aforementioned portion of the third substrate 103a. After removal, the third substrate 103a is not completely removed and the third passivation layer 103l is not exposed.

[0184] In some embodiments, a fifth bonding layer 103h is formed on the remaining portion of the third substrate 103a. In some embodiments, the fifth bonding layer 103h comprises a dielectric material. In some embodiments, the fifth bonding layer 103h completely covers and contacts the top surface of the third substrate 103a. In some embodiments, the fifth bonding layer 103h is formed by deposition, CVD, or other suitable processes.

[0185] See Figure 16 A portion of the third grain 103 is removed to form a second opening 107o, wherein the second opening 107o exposes the first via 106, and the second opening 107o includes a third portion having a third width W3 and a fourth portion having a fourth width W4, the fourth width W4 being different from the third width W3. In some embodiments, the third width W3 is different from the second width W2. In some embodiments, the second opening 107o extends through the third grain 103.

[0186] In some embodiments, the aforementioned portion of the third grain 103 is removed by etching or any other suitable process. In some embodiments, the second opening 107o has a circular, quadrilateral, or polygonal shape.

[0187] See Figure 17A second conductive material 107' is disposed within the second opening 107o to form a second via 107. In some embodiments, the second via 107 thus formed has a tapered cross-sectional structure. In some embodiments, the second via 107 thus formed includes a third portion 107a having a third width W3, and a fourth portion 107b coupled to the third portion 107a and having a fourth width W4. In some embodiments, the fourth width W4 is greater than the third width W3. In some embodiments, the third portion 107a is coupled to a second portion of the first via 106.

[0188] In some embodiments, such as Figure 17 As shown, a second conductive material 107' is disposed on the first via 106 and within the second opening 107. In some embodiments, the second conductive material 107' comprises gold, silver, copper, nickel, tungsten, aluminum, tin, the aforementioned alloys, or similar materials. In some embodiments, the second conductive material 107' is disposed by CVD, PVD, sputtering, or other suitable processes.

[0189] After the second conductive material 107' is applied, a portion of the second conductive material 107' is removed from the fifth bonding layer 103h to form the second via 107. In some embodiments, the aforementioned portion of the second conductive material 107' is removed by planarization, etching, CMP, or other suitable processes. In some embodiments, the second via 107 penetrates the third grain 103 and contacts the first via 106. In some embodiments, a stepped structure is formed at the junction of the first via 106 and the second via 107.

[0190] In some embodiments, a second barrier layer 107c is formed within the second opening 107o, surrounding the second conductive material 107'. In some embodiments, the second barrier layer 107c is formed before the third portion 107a and the fourth portion 107b of the second via 107 are formed. In some embodiments, a barrier layer 107c is formed as follows: Figure 17 The intermediate structure 100i is shown.

[0191] See Figure 18 A support substrate 108 is disposed on the fifth bonding layer 103h. In some embodiments, the intermediate structure 100i is attached to the support substrate 108 via the fifth bonding layer 103h. In some embodiments, the support substrate 108 is a blank or dummy substrate used to support the intermediate structure 100i for further processing. In some embodiments, the intermediate structure 100i is detachable from the support substrate 108. In some embodiments, the fifth bonding layer 103h faces the support substrate 108.

[0192] See Figure 19 In some embodiments, it will be as follows Figure 18 The intermediate structure 100i shown is flipped and attached to the supporting substrate 108.

[0193] In some embodiments, such as Figures 20 to 21 As shown, conductive bumps 104 are formed. In some embodiments, such as... Figure 20 As shown, a portion of the first substrate 101a is removed to expose a portion of the third guide hole 101j, and then as follows: Figure 21 As shown, a conductive bump 104 is formed on the third via 101j. In some embodiments, the conductive bump 104 is electrically connected to the third die 103.

[0194] In some embodiments, the conductive bump 104 comprises a low-temperature reflowable material. In some embodiments, the conductive bump 104 comprises a soldering material, such as tin, lead, silver, copper, nickel, bismuth, or a combination thereof. In some embodiments, the conductive bump 104 comprises a conductive material, such as gold, silver, copper, nickel, tungsten, aluminum, tin, the aforementioned alloys, or similar materials. In some embodiments, the conductive bump 104 is a ball grid array (BGA) ball, a controlled collapse wafer interconnect (C4) bump, a microbump, etc. In some embodiments, it is formed as... Figure 1 The first semiconductor structure 100 is shown.

[0195] See Figure 22 In some embodiments, it will be as follows Figure 21 The first semiconductor structure 100 shown is flipped.

[0196] See Figure 23 This forms a molded part 105 surrounding the first grain 101, the second grain 102, and the third grain 103. In some embodiments, it will be as follows: Figure 22 The first semiconductor structure 100 shown is attached to the interposer 201 to form as shown. Figure 5 The second semiconductor structure 200 is shown.

[0197] In summary, the first die is bonded to the second die via fusion bonding, and through-silicon vias (TSVs) in the second die extend into the first die and are electrically coupled to the conductive pads of the first die. A dielectric-to-dielectric interface is formed between the first and second dies. The aforementioned TSVs have a tapered profile, thus reducing the thickness of the semiconductor structure and increasing its density (the product's z-axis height). Therefore, costs can be reduced while ensuring good electrical properties and reliability of the high-density semiconductor structure.

[0198] One aspect of this disclosure provides a semiconductor structure. The semiconductor structure includes a first die, a second die, and a first via. The first die includes a first substrate, a first dielectric layer on the first substrate, a first interconnect structure disposed within the first dielectric layer and having a first conductive pad, and a first bonding layer on the first dielectric layer, wherein the first dielectric layer at least partially exposes the first conductive pad. The second die includes a second bonding layer bonded to the first bonding layer, a second substrate on the second bonding layer, and a second interconnect structure between the second bonding layer and the second substrate. The first via penetrates the second die and the first bonding layer and is coupled to the first conductive pad.

[0199] The first via includes a first portion having a first width, and a second portion coupled to the first portion and having a second width, the second width being different from the first width, wherein the first portion is surrounded by the first bonding layer and adjacent to the second interconnect structure, and the second portion is surrounded by the second substrate.

[0200] Another aspect of this disclosure provides a semiconductor structure. The semiconductor structure includes a first die, a second die, a third die, a first via, and a second via. The first die includes a first substrate, a first interconnect structure disposed on the first substrate and having a first conductive pad, and a first bonding layer on the first conductive pad. The second die includes a second bonding layer bonded to the first bonding layer, a second substrate on the second bonding layer, and a second interconnect structure between the second bonding layer and the second substrate. The third die includes a third bonding layer bonded to the second die, a third substrate on the third bonding layer, and a third interconnect structure between the third bonding layer and the third substrate. The first via penetrates the second die and enters the first die. The second via penetrates the third die and is electrically connected to the first via. The second grain is disposed between the first grain and the third grain. The first guide hole has a tapered cross-sectional structure. A first contact surface area of ​​the first guide hole contacts a second contact surface area of ​​the second guide hole, and the size of the first contact surface area is different from the size of the second contact surface area.

[0201] Another aspect of this disclosure provides a method for manufacturing a semiconductor structure. The method includes the steps of forming a first die, forming a second die, and bonding the second die to the first die. The formation of the first die includes providing a first substrate and a first dielectric layer on the first substrate, forming a first interconnect structure having a first conductive pad within the first dielectric layer, and disposing a first bonding layer on the first dielectric layer that contacts the first conductive pad.

[0202] The formation of the second grain includes providing a second substrate and a second dielectric layer on the second substrate, forming a second interconnect structure having a second conductive pad in the second dielectric layer, and providing a second bonding layer on the second dielectric layer that contacts the second conductive pad.

[0203] The method further includes bonding a first bonding layer to the second bonding layer to bond the first die to the second die; removing a portion of the second die and a portion of the first bonding layer to form a first opening, wherein the first opening exposes the first conductive pad, and the first opening includes a first portion having a first width and surrounded by the first die and a second portion having a second width different from the first width; and disposing a first conductive material within the first opening to form a first via. The first via includes a first portion having the first width and a second portion coupled to the first portion and having the second width.

[0204] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0205] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the content of this disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this disclosure.

Claims

1. A semiconductor structure, comprising: A first die includes a first substrate, a first dielectric layer on the first substrate, a first interconnect structure disposed within the first dielectric layer and having a first conductive pad, and a first bonding layer on the first dielectric layer, wherein the first dielectric layer at least partially exposes the first conductive pad. A second grain, comprising a second bonding layer bonded to the first bonding layer, a second substrate on the second bonding layer, and a second interconnect structure between the second bonding layer and the second substrate; and A first via penetrates the second grain and the first bonding layer, and is coupled to the first conductive pad. The first via includes a first portion having a first width, and a second portion coupled to the first portion and having a second width, the second width being different from the first width. The first portion is surrounded by the first bonding layer and adjacent to the second interconnect structure, and the second portion is surrounded by the second substrate.

2. The semiconductor structure of claim 1, wherein the second width is greater than the first width.

3. The semiconductor structure of claim 1, wherein the first portion has a first cross-sectional region, the second portion has a second cross-sectional region, and the second cross-sectional region is larger than the first cross-sectional region.

4. The semiconductor structure of claim 1, wherein the first via has a stepped structure disposed at the interface between the first portion and the second portion.

5. The semiconductor structure of claim 1, wherein the first via has a tapered cross-sectional structure.

6. The semiconductor structure of claim 1, wherein the first portion and the second portion are integral.

7. The semiconductor structure of claim 1, wherein the first via further comprises a barrier layer surrounding the first portion and the second portion.

8. The semiconductor structure of claim 1, wherein the first via contacts the first bonding layer.

9. The semiconductor structure of claim 1, wherein the first portion of the first via is disposed between the second portion of the first via and the first conductive pad.

10. The semiconductor structure of claim 1, further comprising: A third grain, comprising a third bonding layer bonded to the second grain, a third substrate on the third bonding layer, and a third interconnect structure between the third bonding layer and the third substrate; and A second via penetrates the third grain and is electrically connected to the first via. The second guide hole includes a third portion having a third width, and a fourth portion coupled to the third portion and having a fourth width, the fourth width being different from the third width, and the third portion being coupled to the second portion of the first guide hole.

11. The semiconductor structure of claim 10, wherein the fourth width is greater than the third width, and the second width is greater than the third width.

12. The semiconductor structure of claim 10, wherein the third portion has a third cross-sectional region, the fourth portion has a fourth cross-sectional region, and the fourth cross-sectional region is larger than the third cross-sectional region.

13. The semiconductor structure of claim 10, wherein the second via has a stepped structure disposed at the interface between the third portion and the fourth portion.

14. The semiconductor structure of claim 10, wherein the second via has a tapered cross-sectional structure.

15. The semiconductor structure of claim 10, wherein the third portion and the fourth portion are integral.

16. The semiconductor structure of claim 10, wherein a first contact surface region of the first via contacts a second contact surface region of the second via, and the interface between the second grain and the third grain is coplanar with the second contact surface region.

17. The semiconductor structure of claim 16, wherein the size of the first contact surface region is different from the size of the second contact surface region, and the first contact surface region and the second contact surface region each have a circular, quadrilateral or polygonal shape.

18. The semiconductor structure of claim 10, wherein the first via is disposed between the second via and the first conductive pad.

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