Package structure and method of forming the same

Abstract

The package structure can be formed by attaching a lid structure to a bonded assembly including at least one semiconductor die and a package substrate, wherein the lid structure includes at least one threaded hole extending perpendicularly from a top surface of the lid structure toward the bonded assembly; providing a heat spreader including at least one through hole; and passing at least one threaded fastener through a respective one of the at least one through hole and engaging each of the at least one threaded fastener into a respective one of the at least one threaded hole, thereby securing the heat spreader to the lid structure.

Description

Technical Field

[0001] The embodiments disclosed herein relate to an encapsulation structure and a method for forming the same. Background Technology

[0002] Semiconductor packages generate heat during operation. If this heat is not effectively managed, it can reduce performance and reliability. Heat sinks can be used to effectively dissipate the heat generated by semiconductor packages, maintaining them at a controlled operating temperature, ensuring optimal performance, and extending their lifespan. Summary of the Invention

[0003] This disclosure discloses a method for forming a package structure, comprising: attaching a cover structure to a bonding assembly including at least one semiconductor die and a package substrate, wherein the cover structure includes at least one threaded hole extending perpendicularly from a top surface of the cover structure toward the bonding assembly; providing a heat sink including at least one through hole; and passing at least one threaded fastener through a corresponding one of the at least one through hole, and engaging each of the at least one threaded fastener into a corresponding one of the at least one threaded hole, thereby securing the heat sink to the cover structure.

[0004] This disclosure discloses a method for forming a package structure, comprising: attaching a cover structure to a bonding assembly including at least one semiconductor die and a package substrate, wherein the cover structure includes at least one threaded hole extending perpendicularly from a top surface of the cover structure toward the bonding assembly; attaching the bonding assembly to a printed circuit board; and mounting a heat sink to the cover structure using at least one threaded fastener, wherein the heat sink includes at least one through-hole, the at least one threaded fastener passing through the at least one through-hole, and the at least one threaded fastener being screwed into a corresponding one of the at least one threaded holes.

[0005] An embodiment of the present disclosure provides a packaging structure comprising: a bonding assembly including at least one semiconductor die and a packaging substrate; a cover structure attached to a top surface of the bonding assembly and including at least one threaded hole extending perpendicularly from the top surface of the cover structure toward the bonding assembly; a heat sink located on the cover structure and including at least one through hole; and at least one threaded fastener passing through the at least one through hole and screwed into a corresponding one of the at least one threaded holes. Attached Figure Description

[0006] Figure 1 This is a vertical cross-sectional view of an exemplary intermediate structure after an interposer via (TIV) structure has been formed on a first carrier wafer according to an embodiment of this disclosure.

[0007] Figure 2A This is a vertical cross-sectional view of an example intermediate structure after a local silicon interconnect (LSI) bridge has been attached to a first carrier wafer according to an embodiment of this disclosure. Figure 2B yes Figure 2A A top-down view of an exemplary intermediate structure. Figure 2C yes Figure 2A and Figure 2B A vertical cross-sectional view of the LSI bridge in an exemplary intermediate structure.

[0008] Figure 3 This is a vertical cross-sectional view of an exemplary intermediate structure after the formation of an intermediate layer molding compound material layer according to an embodiment of the present disclosure.

[0009] Figure 4 This is a vertical cross-sectional view of an exemplary intermediate structure formed after the intermediate layer molding compound matrix is ​​formed according to an embodiment of the present disclosure.

[0010] Figure 5 This is a vertical cross-sectional view of an exemplary intermediate structure after forming a first redistribution circuit structure according to an embodiment of the present disclosure.

[0011] Figure 6 This is a vertical cross-sectional view of an exemplary intermediate structure after which multiple semiconductor dies are attached to a first redistribution circuit structure according to an embodiment of the present disclosure.

[0012] Figure 7 This is a vertical cross-sectional view of an exemplary intermediate structure formed after the bottom filler material portion on the die side is formed according to an embodiment of this disclosure.

[0013] Figure 8 This is a vertical cross-sectional view of an exemplary intermediate structure after the formation of a core-level molding compound matrix according to an embodiment of the present disclosure.

[0014] Figure 9 This is a vertical cross-sectional view of an exemplary intermediate structure after the second carrier wafer is attached to the reconstructed wafer and the first carrier wafer is separated, according to an embodiment of the present disclosure.

[0015] Figure 10 This is a vertical cross-sectional view of an exemplary intermediate structure after forming a second redistribution circuit structure according to an embodiment of the present disclosure.

[0016] Figure 11 This is a vertical cross-sectional view of a composite package according to an embodiment of the present disclosure.

[0017] Figure 12 This is a vertical cross-sectional view of a bonding assembly including a composite package and a package substrate according to an embodiment of the present disclosure.

[0018] Figure 13A This is a vertical cross-sectional view of a first exemplary packaging structure formed by attaching a cover structure to a bonding assembly according to an embodiment of the present disclosure. Figure 13B yes Figure 13A A top view of the packaging structure. Figure 13B The vertical plane A-A' in is Figure 13A The vertical cross-sectional view of the cutting plane.

[0019] Figure 14A This is a vertical cross-sectional view of a first exemplary package structure after the heat sink is attached to the cover structure according to an embodiment of the present disclosure. Figure 14B yes Figure 14A A top view of the first exemplary encapsulation structure. Figure 14B The vertical plane A-A' in is Figure 14A The vertical cross-sectional view of the cutting plane. Figure 14C It is along Figure 14A A horizontal cross-sectional view of the packaging structure in the horizontal plane C-C'. Figure 14D It is along Figure 14B and Figure 14C A vertical cross-sectional view of the first exemplary package structure in the vertical plane D-D'.

[0020] Figure 15A This is a vertical cross-sectional view of a first exemplary encapsulation structure following the fixing of a threaded fastener, according to an embodiment of this disclosure. Figure 15B yes Figure 15A A top view of the packaging structure. Figure 15B The vertical plane A-A' in is Figure 15A The vertical cross-sectional view of the cutting plane. Figure 15C This is a perspective view of a first alternative configuration of the first exemplary structure. Figure 15D This is a perspective view of a second alternative configuration of the first exemplary structure.

[0021] Figure 16 This is a vertical cross-sectional view of a first exemplary package structure after attachment to a printed circuit board, according to an embodiment of the present disclosure.

[0022] Figure 17A According to embodiments of this disclosure, by attaching the cover structure to Figure 12 A vertical cross-sectional view of a second exemplary packaging structure formed by the joining of the components. Figure 17B yes Figure 17A A top view of the packaging structure. Vertical plane A-A' is... Figure 17A The cross-section of the vertical section.

[0023] Figure 18A This is a vertical cross-sectional view of a second exemplary package structure after the heat sink is attached to the cover structure according to an embodiment of the present disclosure. Figure 18B yes Figure 18A A top view of the second exemplary encapsulation structure. Figure 18B The vertical plane A-A' in is Figure 18A The vertical cross-sectional view of the cutting plane. Figure 18C It is along Figure 18A A horizontal cross-sectional view of the packaging structure in the horizontal plane C-C'. Figure 18D It is along Figure 18B and Figure 18C A vertical cross-sectional view of a second exemplary packaging structure in the vertical plane D-D'. Figure 18E It is along Figure 18A and Figure 18C A horizontal cross-sectional view of the second exemplary packaging structure in the horizontal plane E-E'. Figure 18E The vertical plane A-A' in is Figure 18A The vertical cross-sectional view of the cutting plane. Figure 18E The vertical plane D-D' in is Figure 18D The vertical cross-sectional view of the cutting plane.

[0024] Figure 19 This is a vertical cross-sectional view of a second exemplary encapsulation structure following a fixed threaded fastener, according to an embodiment of this disclosure.

[0025] Figure 20 This is a vertical cross-sectional view of a second exemplary package structure after attachment to a printed circuit board, according to an embodiment of this disclosure.

[0026] Figure 21A According to the embodiments disclosed herein, by means of Figure 17A and Figure 17B A vertical cross-sectional view of a third exemplary package structure formed by attaching a second exemplary package structure to a printed circuit board. Figure 21B yes Figure 21A A top view of the packaging structure. Vertical plane A-A' is... Figure 21A The cross-section of the vertical section.

[0027] Figure 22A This is a vertical cross-sectional view of a third exemplary package structure with the heat sink attached to the cover structure according to an embodiment of the present disclosure. Figure 22B yes Figure 22A A top view of the third exemplary encapsulation structure. Figure 22B The vertical plane A-A' in is Figure 22A The vertical cross-sectional view of the cutting plane. Figure 22C It is along Figure 22A A horizontal cross-sectional view of the packaging structure in the horizontal plane C-C'.

[0028] Figure 23AThis is a vertical cross-sectional view of a third exemplary package structure after additional threaded fasteners are fixed via a printed circuit board, according to an embodiment of this disclosure. Figure 23B yes Figure 23A A top view of the third exemplary encapsulation structure. Figure 23B The vertical plane A-A' in is Figure 23A The vertical cross-sectional view of the cutting plane. Figure 23C It is along Figure 23A A horizontal cross-sectional view of the packaging structure in the horizontal plane C-C'.

[0029] Figure 24 This is a vertical cross-sectional view of an alternative configuration of a third exemplary package structure after attaching additional threaded fasteners to a heat sink via a printed circuit board, according to an embodiment of this disclosure.

[0030] Figure 25 This is a vertical cross-sectional view of a fourth exemplary packaging structure formed by attaching a cover structure to a bonding assembly according to an embodiment of the present disclosure.

[0031] Figure 26 This is a vertical cross-sectional view of a fourth exemplary package structure after the bonding assembly has been attached to a printed circuit board and after the heat sink has been attached, according to an embodiment of the present disclosure.

[0032] Figure 27A This is a vertical cross-sectional view of a fourth exemplary package structure following the attachment-side heat sink according to an embodiment of this disclosure. Figure 27B yes Figure 27A A top view of the fourth exemplary encapsulation structure.

[0033] Figure 28 This is a vertical cross-sectional view of a fourth exemplary package structure after additional threaded fasteners are fixed to a side heat sink via a printed circuit board, according to an embodiment of this disclosure.

[0034] Figure 29 A first flowchart of forming a package structure is provided for an embodiment of this disclosure.

[0035] Figure 30 A second flowchart for forming a package structure is provided for embodiments of this disclosure. Detailed Implementation

[0036] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. Figures are not drawn to scale. Elements with the same reference numerals refer to the same elements and are assumed to have the same material composition and the same thickness range unless explicitly stated otherwise. All features of the original embodiments are assumed to be present in any derivative embodiments unless explicitly disclosed otherwise. Therefore, the features described with reference to the relevant embodiments in the drawings and / or specification provide support for the features in the embodiments. Unless explicitly stated otherwise, embodiments in which multiple instances of any of the said elements are repeated are explicitly contemplated. Some embodiments are explicitly contemplated in which non-essential elements are omitted, even if these embodiments are not explicitly disclosed but are known in the art.

[0037] Furthermore, for ease of description, this document uses spatially relative terms such as "below," "under," "lower," "above," and "upper" to describe the geometric features between the multiple elements shown in the figures. In addition to the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptive terms used herein may be interpreted accordingly. Unless otherwise expressly stated, each element with the same reference numerals is considered to have the same material composition and a thickness within the same thickness range.

[0038] The various embodiments disclosed herein relate to package structures that provide enhanced heat dissipation and structural stability. A cover structure with threaded holes provides mechanical connection to the heat sink via threaded fasteners. The heat sink provides better thermal management by effectively transferring heat away from the semiconductor die, thereby improving operational reliability and performance. Various configurations of cover structures and threaded fasteners can be used, which will now be described with reference to the accompanying drawings.

[0039] refer to Figure 1An exemplary intermediate structure according to an embodiment of the present disclosure is shown. The intermediate structure includes a first carrier wafer 310. The first carrier wafer 310 may include an optically transparent substrate such as a glass substrate, a sapphire substrate, etc., or a semiconductor substrate such as a silicon substrate. The diameter of the first carrier wafer 310 may be in the range of 150 mm to 450 mm, although smaller or larger diameters may also be used. The thickness of the first carrier wafer 310 may be in the range of 500 micrometers to 2,000 micrometers, but smaller or larger thicknesses may also be used. Alternatively, the first carrier wafer 310 may be in a rectangular panel format. A first adhesive layer 311 may be applied to the front surface of the first carrier wafer 310. In one embodiment, the first adhesive layer 311 may be a light-to-heat conversion (LTHC) layer. Alternatively, the first adhesive layer 311 may include a thermally decomposable adhesive material.

[0040] Two-dimensional repeats of via assemblies can be formed on a first carrier wafer 310. Each instance of a via assembly can be formed within a corresponding cell region UA ​​having a rectangular area. Multiple instances of the via assembly can be repeated along a first horizontal direction hd1 and a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The cell region UA ​​corresponds to the area of ​​the interposer die to be formed subsequently. For example, each cell region UA ​​can have a rectangular shape having a first side length along the first horizontal direction hd1 and a second side length along the second horizontal direction hd2. The first side length can be the length of a pair of first sides of a rectangle. The second side length can be the length of a pair of second sides of a rectangle. The first side length is referred to herein as a first die lateral dimension dld1. The second side length is referred to herein as a second die lateral dimension dld2. Each of the first die lateral dimension dld1 and the second die lateral dimension dld2 can be independently within the range of 300 micrometers to 6 centimeters, but smaller or larger dimensions can also be used.

[0041] Typically, multiple TIV structures 486 can be formed on a first binder layer 311 by deposition and patterning of a conductive material, or by transfer from above another carrier wafer. In an illustrative example, a sacrificial matrix layer (not shown) can be formed on the first binder layer 311. The sacrificial matrix layer includes a sacrificial material such as amorphous carbon, diamond-like carbon (DLC), a semiconductor material (e.g., amorphous silicon or silicon-germanium alloy), or a dielectric material such as silicate glass or organosilicon glass. The thickness of the sacrificial matrix layer can range from 3 micrometers to 60 micrometers, but smaller or larger thicknesses can also be used. A photoresist layer (not shown) can be applied on the sacrificial matrix layer. The photoresist layer can be photolithographically patterned to form multiple openings having the same pattern in a top-down view as the subsequently formed multiple TIV structures 486. An anisotropic etching process can be used to transfer the pattern of the multiple openings in the photoresist layer. Multiple cylindrical cavities can be formed as a result of the sacrificial matrix layer passing through the multiple openings in the photoresist layer. The photoresist layer can be removed, for example, by ashing. At least one conductive material, such as at least one metallic material, can be deposited in multiple cylindrical cavities. For example, the at least one conductive material may include a conductive metal barrier material (e.g., TiN, TaN, WN, or MoN) and a metal filler material (e.g., W, Ti, Ta, Mo, Ru, Co, etc.). Excess portions of the at least one conductive material can be removed from above a horizontal plate including the sacrificial matrix layer. The remaining portions of the at least one conductive material filling the multiple cylindrical cavities constitute multiple TIV structures 486. Subsequently, the sacrificial matrix layer can be selectively removed without removing the multiple TIV structures 486 and without removing the first adhesive layer 311.

[0042] Optionally, at least one conductive material layer can be deposited as a cover material layer, i.e., deposited as an unpatterned material layer with a uniform thickness. For example, the at least one conductive material layer may include a conductive metal barrier material (e.g., TiN, TaN, WN, or MoN) and a metal filler material (e.g., W, Ti, Ta, Mo, Ru, Co, etc.). The thickness of the at least one conductive material layer can range from 3 micrometers to 60 micrometers, but smaller or larger thicknesses can also be used. A photoresist layer (not shown) may be applied over the at least one conductive material layer. The photoresist layer may be photolithographically patterned to form multiple discrete photoresist material portions having the same pattern in a top-down view as the subsequently formed plurality of TIV structures 486. An anisotropic etching process may be performed to transfer the pattern of the plurality of discrete photoresist material portions through the at least one conductive material layer. The plurality of patterned portions of the at least one conductive material layer include a plurality of TIV structures 486.

[0043] In another alternative embodiment, a plurality of TIV structures 486 may be formed on another carrier wafer and may be attached to the top surface of the first adhesive layer 311. The plurality of TIV structures 486 may then be detached from the additional carrier wafer.

[0044] In one embodiment, the pattern of the plurality of TIV structures 486 within each unit region UA ​​can be a pattern obtained from a rectangular periodic array having a first spacing along a first horizontal direction hd1 and a second spacing along a second horizontal direction hd2 by omitting a subset of the plurality of TIV structures 486. Specifically, a subset of the plurality of TIV structures 486 can be omitted such that two rectangular corner regions have no TIV structures 486 and at least one central region has no TIV structures 486. The at least one central region corresponds to at least one region where at least one local silicon interconnect (LSI) bridge is to be located. In one embodiment, each TIV structure 486 includes a metal via structure.

[0045] refer to Figures 2A to 2C Multiple local silicon interconnect (LSI) bridges 405 may be provided. Each LSI bridge 405 includes a silicon substrate 410 (thinned and diced during fabrication of the LSI bridge 405), multiple through-silicon via structures 414 extending vertically through the silicon substrate 410, multiple through-substrate openings extending vertically through the silicon substrate 410, a dielectric liner 412 providing electrical isolation for the multiple through-silicon via structures 414, a back-side dielectric material layer 420, and multiple metal interconnect structures 480 embedded in the multiple dielectric material layers 450 and electrically connected and / or interconnected with the multiple through-silicon via structures 414. Multiple metal pads, referred to herein as LSI metal pads 488, may be provided on the topmost metal interconnect structure 480.

[0046] Multiple LSI bridges 405 can be placed within multiple openings in the TIV structure 486 array on the top surface of the first adhesive layer 311. Typically, at least one LSI bridge 405 can be placed within each cell region UA ​​using a pick and place tool. At least one local silicon interconnect (LSI) bridge 405 can be placed within each repeating cell region UA ​​using a pick and place tool. In one embodiment, multiple LSI bridges 405 can be placed within each repeating cell region UA ​​using a pick and place tool.

[0047] refer to Figure 3Encapsulation materials such as molding compounds (MCs) can be applied to multiple gaps within an assembly of multiple LSI bridges 405 and multiple TIV structures 486. MCs comprise epoxy-containing compounds that can be cured (i.e., hardened) to provide dielectric portions with sufficient stiffness and mechanical strength. MCs may include epoxy resin, hardeners, silica (as a filler), and other additives. Depending on viscosity and flowability, MCs can be supplied in liquid or solid form. Liquid MCs typically offer better handleability, good flowability, fewer voids, better filling, and fewer flow marks. Solid MCs typically offer less curing shrinkage, better isolation, and less die drift. High filler content (e.g., 85% by weight) in MCs can shorten molding time, reduce molding shrinkage, and decrease mold warpage. Uniform filler size distribution in MCs reduces flow marks and enhances flowability.

[0048] The MC can be cured at a curing temperature to form an MC matrix, referred herein as the first molding compound (MC) material layer or intermediate layer molding compound (MC) material layer 490L. The intermediate layer MC material layer 490L laterally surrounds each LSI bridge 405 and TIV structure 486. The intermediate layer MC material layer 490L may be a continuous material layer extending over the entire area of ​​the reconstructed wafer overlying the first carrier wafer 310.

[0049] refer to Figure 4 Excess portions of the interposer MC material layer 490L are removed from above a horizontal plane containing the top surfaces of the LSI bridge 405 and the TIV structure 486 through a planarization process (which may use chemical mechanical planarization (CMP)). After the planarization process, the surfaces of the multiple through-silicon via structures 414 may be physically exposed. The remaining portion of the interposer MC material layer 490L is referred to herein as the interposer molding compound (MC) matrix 490M.

[0050] The intermediate layer MC matrix 490M includes multiple molding compound (MC) intermediate layer frames located within corresponding unit regions UA and laterally adjacent to each other. Each MC intermediate layer frame corresponds to a portion of the intermediate layer MC matrix 490M within the unit region UA, i.e., the region of the single intermediate layer to be formed subsequently. Each MC intermediate layer frame laterally surrounds a corresponding group of at least one LSI bridge 405 and a corresponding array of multiple TIV structures 486.

[0051] refer to Figure 5A first redistribution wiring structure 500 can be formed on the top side of the two-dimensional repeating and intermediate layer MC matrix 490M of the unit via assembly. The first redistribution wiring structure 500 includes a plurality of first redistribution wiring interconnects 580, a plurality of first redistribution dielectric layers 560, and a plurality of first bonding structures 588.

[0052] Multiple first-layered dielectric layers 560 comprise respective dielectric polymer materials, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Each first-layered dielectric layer 560 can be formed by spin-coating and drying the corresponding dielectric polymer material. The thickness of each first-layered dielectric layer 560 can be from 2 micrometers to 40 micrometers, for example, from 4 micrometers to 20 micrometers. For example, each first-layered dielectric layer 560 can be patterned by applying and patterning a corresponding photoresist layer thereon, and by transferring the pattern in the photoresist layer into the first-layered dielectric layer 560 using an etching process (e.g., anisotropic etching). The photoresist layer can then be removed, for example, by ashing.

[0053] Each first-layer interconnect 580 can be formed by: sputtering a metal seed layer; applying and patterning a photoresist layer over the metal seed layer to form a pattern of multiple openings through the photoresist layer; electroplating a metal filler material (e.g., copper, nickel, or a stack of copper and nickel); removing the photoresist layer (e.g., by ashing); and etching multiple portions of the metal seed layer located between multiple electroplated metal filler material portions. The metal seed layer may include, for example, a stack of titanium barrier layers and copper seed layers. The thickness of the titanium barrier layer may range from 50 nm to 300 nm, and the thickness of the copper seed layer may range from 100 nm to 500 nm. The metal filler material of the first-layer interconnect 580 may include copper, nickel, or copper and nickel. The thickness of the metal filler material deposited for each first-layer interconnect 580 may range from 2 micrometers to 40 micrometers, for example, 4 micrometers to 10 micrometers, but smaller or larger thicknesses may also be used. The total number of wiring layers in the first layer wiring structure 500 (i.e., the number of layers of the internal interconnection 580 of the first layer wiring) can be from 1 to 10.

[0054] The plurality of first bonding structures 588 may include microbump structures that can subsequently be used to connect a plurality of semiconductor dies. The metal filler material of the microbump structures may include copper. The horizontal cross-sectional shape of the plurality of first bonding structures 588 may be rectangular, rounded rectangular, or circular. Other horizontal cross-sectional shapes may also be within the scope of this disclosure. In some embodiments, the plurality of first bonding structures 588 may be configured for microbump bonding and may have a thickness ranging from 5 micrometers to 100 micrometers, although smaller or larger thicknesses may also be used. In one embodiment, the plurality of first bonding structures 588 within each cell region UA ​​may be formed as an array of at least one microbump (e.g., copper pillar). The lateral dimension of each microbump may range from 10 micrometers to 50 micrometers, and the spacing may range from 20 micrometers to 100 micrometers.

[0055] refer to Figure 6 A group of at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) can be bonded to a corresponding group of first bonding structures 588 within each cell region UA. Each group of at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) includes at least one semiconductor die, and may include multiple semiconductor dies (semiconductor dies 701, semiconductor die 702, semiconductor die 703). For example, each group of at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) may include at least one system-on-chip (SoC) die (semiconductor die 701, semiconductor die 702) and / or at least one memory die (semiconductor die 703). Each SoC die (semiconductor die 701, semiconductor die 702) may include an application processor die, a central processing unit die, or a graphics processing unit die. In one embodiment, at least one memory die (semiconductor die 703) may include a high bandwidth memory (HBM) die comprising a vertical stack of static random access memory (SRAM) dies. In one embodiment, at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) may include at least one system-on-a-chip (SoC) die (semiconductor die 701, semiconductor die 702) and at least one high bandwidth memory (HBM) die. Each HBM die may include a vertical stack of static random access memory (SRAM) dies interconnected via an array of microbumps and laterally surrounded by a corresponding molding material encapsulation frame.

[0056] Each semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) may include its own array of on-die bump structures 788. Solder material portions may be applied to the on-die bump structures 788 of the semiconductor dies (semiconductor dies 701, semiconductor dies 702, semiconductor dies 703), or may be applied to the first bonding structures 588. The solder material portions are herein referred to as die-interposer-bonding (DIB) solder material portions 790, or first solder material portions. Each semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) may be placed face down such that the plurality of on-die bump structures 788 face the plurality of first bonding structures 588. Multiple semiconductor dies (semiconductor dies 701, 702, and 703) can be placed using pick-and-place devices, such that each die-on bump structure 788 can face a corresponding one of a plurality of first bonding structures 588. At least one semiconductor die (semiconductor die 701, 702, and 703) in each group can be placed within a corresponding unit area. For each pair of facing die-on bump structures 788 and first bonding structures 588, a DIB solder material portion 790 is attached to one of the die-on bump structures 788 and the first bonding structure 588.

[0057] In one embodiment, the die-on bump structure 788 and the first bonding structure 588 can be configured for microbump bonding. In this embodiment, both the die-on bump structure 788 and the first bonding structure 588 can be designed as copper pillar structures with a diameter of 10 to 50 micrometers and a height of 5 to 100 micrometers. The spacing of the microbumps in the periodic direction can range from 20 to 100 micrometers, but smaller or larger spacing can also be used. During reflow soldering, the lateral dimension of each DIB solder material portion 790 can be within 100% to 150% of the lateral dimension (e.g., diameter) of the adjacent die-on bump structure 788 or the adjacent first bonding structure 588.

[0058] refer to Figure 7A die-side underfill material can be applied to each gap between the first redistributed circuit structure 500 and a corresponding group of at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703). The die-side underfill material can include any underfill material known in the art. A die-side underfill material portion 792 can be formed within each cell region UA ​​between the first redistributed circuit structure 500 and the corresponding group of at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703). The die-side underfill material portion 792 can be formed by injecting the die-side underfill material around a corresponding array of a plurality of DIB solder material portions 790 in the corresponding cell region UA. Any known underfill material application method can be used, such as capillary underfill, molding underfill, or printed underfill.

[0059] The die-side bottom filler material portion 792 may laterally surround and contact a corresponding group of multiple DIB solder material portions 790 within the cell region UA. The die-side bottom filler material portion 792 may be formed within the cell region around and in contact with the multiple DIB solder material portions 790, the multiple first bonding structures 588, and the multiple die-on-bump structures 788. Typically, within each cell region UA, at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) including a corresponding set of die-on-bump structures 788 is attached to the first redistribution circuit structure 500 through the corresponding set of DIB solder material portions 790.

[0060] refer to Figure 8A molding compound (MC) can be applied to multiple gaps between multiple assemblies of a corresponding set of semiconductor dies (semiconductor dies 701, 702, 703) and corresponding die-side bottom filler material portions 792. The MC can include any material that can be used in the aforementioned intermediate layer MC matrix 490M. The MC may include epoxy resin, hardener, silica (as a filler material), and other additives. The MC can be cured at a curing temperature to form an MC matrix, referred to herein as a die-level MC matrix 796M or a second MC matrix. The die-level MC matrix 796M laterally surrounds and embeds each assembly of a set of semiconductor dies (semiconductor dies 701, 702, 703) and die-side bottom filler material portions 792. The die-level MC matrix 796M includes multiple molding compound (MC) die frames that are laterally adjacent to each other. Each MC die frame is part of the die-level MC matrix 796M located within a corresponding cell region UA. Therefore, each MC die frame laterally surrounds and embeds a corresponding set of semiconductor dies (semiconductor die 701, semiconductor die 702, semiconductor die 703) and a corresponding die-side bottom filler material portion 792. The Young's modulus of pure epoxy resin is approximately 3.35 GPa, and due to the presence of additives in the MC, its Young's modulus may be higher than that of pure epoxy resin. Therefore, the Young's modulus of the die-grade MC matrix 796M may be greater than 3.5 GPa.

[0061] Multiple portions of the die-level MC matrix 796M, which is overlaid on the top surface of a horizontal plane comprising multiple semiconductor dies (semiconductor dies 701, 702, and 703), can be removed using a planarization process. For example, chemical mechanical planarization (CMP) can be used to remove multiple portions of the die-level MC matrix 796M overlaid on the horizontal plane. The reconstructed wafer overlaid on the first carrier wafer 310 includes a die-level MC matrix 796M, a combination of multiple semiconductor dies (semiconductor dies 701, 702, and 703), multiple die-side bottom filler material portions 792, a first redistributed circuit structure 500, a combination of at least one LSI bridge 405, and a combination of multiple TIV structures 486. The portions of the die-level MC matrix 796M located within a unit region UA ​​constitute the MC die frame.

[0062] refer to Figure 9A second adhesive layer 321 may be applied over the die-level MC matrix 796M. Depending on the removal mechanism used subsequently, the second adhesive layer 321 may comprise a photothermal conversion (LTHC) layer or a thermally decomposable adhesive material layer. A second carrier wafer 320 may be attached to the die-level MC matrix 796M and a plurality of semiconductor dies (semiconductor dies 701, 702, and 703) through the second adhesive layer 321. The second carrier wafer 320 may comprise any material that can be used with the first carrier wafer 310 and may typically have approximately the same thickness range as the first carrier wafer 310.

[0063] The first carrier wafer 310 may be separated from the reconstructed wafer. In some embodiments, the first carrier wafer 310 and the first adhesive layer 311 can be removed by back-side grinding. Optionally, at least one selective etching process (e.g., wet etching or reactive ion etching) can be used in conjunction with the back-side grinding process to minimize incidental removal of surface portions of the plurality of LSI bridges 405 and the plurality of TIV structures 486. Alternatively or additionally, in embodiments where the first carrier wafer 310 comprises an optically transparent material and the first adhesive layer 311 comprises a photothermal conversion material, the first carrier wafer 310 can be irradiated to separate it. In embodiments where the first adhesive layer 311 comprises a thermally degradable adhesive material, annealing or laser irradiation can be used to separate the first carrier wafer 310. Appropriate cleaning processes can be performed to remove any residual portions of the first adhesive layer 311.

[0064] refer to Figure 10 A second redistribution wiring structure 600 can be formed on the physically exposed side of the two-dimensional repeating and intermediate layer MC matrix 490M of the cell via assembly. The second redistribution wiring structure 600 includes multiple second redistribution wiring interconnects 680, optionally multiple second interconnect level alignment structures (not shown), multiple second redistribution dielectric layers 660, and multiple second bonding structures 688. Typically, the second redistribution wiring structure 600 can be formed in the same manner as the first redistribution wiring structure 500, with appropriate variations in the photolithographic pattern and / or the thickness and material composition of the material layers. The multiple second bonding structures 688 can be formed as bonding pads for controlled collapse chip connection (C4) bonding.

[0065] refer to Figure 11The second carrier wafer 320 can be separated from the reconstructed wafer. In embodiments where the second carrier wafer 320 comprises an optically transparent material and the second adhesive layer 321 comprises a photothermal conversion material, the second carrier wafer 320 can be irradiated to separate it. In embodiments where the second adhesive layer 321 comprises a thermally decomposable adhesive material, an annealing process or laser irradiation can be used to separate the second carrier wafer 320. Appropriate cleaning processes can be performed to remove any residual portions of the second adhesive layer 321. The horizontal surface of the die-level MC matrix 796M can be physically exposed.

[0066] The reconstructed wafer includes a two-dimensional array of composite packages 400, and also a two-dimensional array of at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) group bonded to the corresponding composite package 400. The reconstructed wafer can be diced along multiple dicing channels by performing a dicing process. The multiple dicing channels correspond to the boundaries between adjacent pairs of unit regions UA. Each dicing unit obtained from the reconstructed wafer includes a fan-out package 800. Each diced portion of the die-level MC matrix 796M constitutes a die-level MC frame 796. Each diced portion of the interposer-level MC matrix 490M constitutes an interposer-level MC frame 490.

[0067] The reconstructed wafer comprises multiple diced sections including multiple fan-out packages 800. Each fan-out package 800 includes at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703), a composite package 400, a die-side bottom filler material portion 792, a die-level MC frame 796, and an array of at least one DIB solder material portion 790. Each composite package 400 includes a cell via assembly (including multiple TIV structures 486), at least one LSI bridge 405, an interposer-level MC frame 490, a first redistribution circuit structure 500, and a second redistribution circuit structure 600.

[0068] refer to Figure 12The packaging substrate 200 can be bonded to the fan-out package 800. The packaging substrate 200 can be a core-based packaging substrate including a core substrate 210, or a coreless packaging substrate without a package core. Alternatively, the packaging substrate 200 can include a system-on-integrated packaging substrate (SoIS) including multiple redistribution layers, multiple dielectric interlayers, and / or at least one embedded interposer (e.g., a silicon interposer). Such a system-on-integrated packaging substrate can include multiple layer-to-layer interconnect structures using solder material portions, microbumps, underfill material portions (e.g., molded underfill material portions), and / or adhesive films. Although this disclosure is described using a core-based packaging substrate, the scope of this disclosure is not limited to any particular type of substrate package. For example, SoIS can be used instead of a core-based packaging substrate. In embodiments using SoIS, the core substrate 210 can include a glass epoxy plate including an array of multiple through-plate holes. An array of multiple through-hole structures 214 containing metallic material can be provided in multiple through-plate holes. Each through-hole structure 214 may or may not include a cylindrical hollow. Optionally, multiple dielectric liner layers (not shown) can be used to electrically isolate the multiple through-hole structures 214 from the core substrate 210.

[0069] The packaging substrate 200 may include a surface laminar circuit (SLC) 240 and a die-side surface laminar circuit (SLC) 260. The board-side SLC may include multiple board-side insulating layers 242 with multiple board-side wiring interconnects 244 embedded therein. The die-side SLC 260 may include multiple die-side insulating layers 262 with multiple die-side wiring interconnects 264 embedded therein. The board-side insulating layers 242 and 262 may include a photosensitive epoxy material that can be patterned by photolithography and subsequently cured. The board-side wiring interconnects 244 and 264 may include copper, which may be deposited by electroplating within multiple patterns in the multiple board-side insulating layers 242 or the multiple die-side insulating layers 262.

[0070] In one embodiment, the chip-side surface-mount circuitry 260 includes a plurality of chip-side wiring interconnects 264 connected to an array of a plurality of substrate bonding pads 268. The array of substrate bonding pads 268 is configured to allow bonding through a plurality of C4 solder balls. The board-side surface-mount circuitry 240 includes a plurality of board-side wiring interconnects 244 connected to an array of a plurality of board-side bonding pads 248. The array of board-side bonding pads 248 is configured to allow bonding through a plurality of solder material portions having a size larger than C4 solder balls. Although this disclosure describes embodiments of the package substrate 200 including the chip-side surface-mount circuitry 260 and the board-side surface-mount circuitry 240, embodiments in which one of the chip-side surface-mount circuitry 260 and the board-side surface-mount circuitry 240 is omitted or replaced by an array of bonding structures such as microbumps are explicitly contemplated herein. In illustrative examples, the chip-side surface-mount circuitry 260 may be replaced by an array of microbumps or any other array of bonding structures.

[0071] The fan-out package 800 can be attached to the package substrate 200 using multiple second solder material portions, referred herein as interposer-substrate-bonding (ISB) solder material portions 290. Specifically, each ISB solder material portion 290 can be bonded to a corresponding substrate bonding pad 268 and a corresponding second bonding structure 688 located on the composite package 800. A reflow process can be performed to reflow the multiple ISB solder material portions 290, such that each ISB solder material portion 290 can be bonded to the corresponding substrate bonding pad 268 and the corresponding second bonding structure 688.

[0072] An underfill material may be applied in the gap between the composite package 800 and the package substrate 200. The underfill material may include any underfill material known in the art. Underfill material portions may be formed around a plurality of ISB solder material portions 290 and in the gap between the composite package 800 and the package substrate 200. This underfill material portion is referred to herein as interposer-substrate underfill material portion 292, or IP underfill material portion 292. An array of a plurality of solder material portions 190 may be formed on an array of a plurality of board-side bonding pads 248. A bonded assembly (composite package 800, package substrate 200) including the composite package 800 and the package substrate 200 may be formed.

[0073] refer to Figure 13A and Figure 13BThe cover structure 910 can be attached to a bonding assembly (composite package 800, package substrate 200) to form a first exemplary package structure. The cover structure 910 may include a metallic material (e.g., Cu) or a dielectric material providing high thermal conductivity (e.g., aluminum nitride). According to one aspect of this disclosure, the cover structure 910 includes at least one threaded hole 919 extending vertically downward from the top surface of the cover structure 910 toward the bonding assembly (composite package 800, package substrate 200). The vertical extension range of the at least one threaded hole 919 may be from 1 mm to 10 mm, for example, 2 mm to 5 mm, but smaller or larger vertical extension ranges may also be used. The at least one threaded hole 919 may include a plurality of threaded holes 919, which may be an array of a plurality of threaded holes 919. As used herein, a threaded hole refers to a hole having threads along its sidewalls for mating with threaded fasteners such as bolts or screws. In one embodiment, the cover structure 910 may include a horizontally extending plate portion and a vertically extending wall portion. At least one threaded hole 919 may be formed within the horizontal extension plate portion of the cover structure 910. The depth of the at least one threaded hole 919 may be in the range of 30% to 99% of the thickness of the horizontal extension plate portion of the cover structure 910, for example, in the range of 50% to 90%.

[0074] The cover structure 910 can be attached to a bonding assembly (composite package 800, package substrate 200) comprising at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) using an adhesive layer 905 and a first thermal interface material layer 911. The cover structure 910 can be attached to the bonding assembly (composite package 800, package substrate 200) using the adhesive layer 905 that bonds the cover structure 910 to the package substrate 200. In one embodiment, the adhesive layer 905 can be applied to a first element selected from the package substrate 200 and the cover structure 910, and a second element selected from the package substrate 200 and the cover structure 910 and different from the first element can be contacted with the adhesive layer 905. In an exemplary example, the adhesive layer 905 can be applied to a peripheral portion of the top surface of the package substrate 200. In the illustrated example, the adhesive layer 905 is applied between the frame-shaped bottom surfaces of the package substrate 200 and the cover structure 910.

[0075] Before attaching the cover structure 910 to the package substrate 200, a first thermal interface material (TIM) layer 911 may be applied to the top surface of the composite package 800. The first TIM layer 911 may include any thermal interface material known in the art. The first TIM layer 911 may be applied to the top surface of each of at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703). When the cover structure 910 is bonded to the bonding assembly (composite package 800, package substrate 200) through the adhesive layer 905, the first TIM layer 911 may contact the bottom surface of the horizontal extension portion of the cover structure 910. In one embodiment, the contact area between the first TIM layer 911 and the bottom surface of the horizontal extension portion of the cover structure 910 may be the same as or approximately the same as the area of ​​the top surface of the composite package 800.

[0076] refer to Figures 14A to 14D A heat sink 940 comprising at least one through-hole 949 may be provided. The heat sink 940 comprises a metallic material with high electrical conductivity, such as copper or aluminum. According to one aspect of this disclosure, the configuration of the at least one through-hole 949 through the heat sink 940 may be selected to match the pattern of at least one threaded hole 919 in the cover structure 910. In embodiments where the at least one threaded hole 919 comprises a plurality of threaded holes 919, the at least one through-hole 949 may comprise a plurality of through holes 949. Typically, the sidewalls of the at least one through-hole 949 may be smooth, and the lateral dimensions (e.g., diameter) of the at least one through-hole 949 may be selected to allow unobstructed passage of subsequently used threaded fasteners.

[0077] The heat sink 940 can be attached to the cover structure 910 using a second thermal interface material (TIM) layer 921. The second TIM layer 921 can comprise any thermal interface material known in the art. The thermal interface material of the second TIM layer 921 can be applied to an area that does not overlap with at least one threaded hole 919. Therefore, the second TIM layer 921 includes at least one through-hole such that the pattern of the at least one through-hole matches the pattern of the at least one threaded hole 919. In other words, the second TIM layer 921 does not overlap with any area of ​​the at least one threaded hole 919.

[0078] The heat sink 940 may include a horizontally extending heat sink plate portion in contact with the second TIM layer 921 and a plurality of heat sink fin portions extending vertically upward from the horizontally extending heat sink plate portion. In some embodiments, the plurality of heat sink fin portions may be arranged in a grid pattern. According to one embodiment of this disclosure, the pattern of the plurality of heat sink fin portions is selected to include an opening located above each of at least one through hole 949, the opening extending through the horizontally extending heat sink plate portion of the heat sink 940. Each opening in the plurality of heat sink fin portions acts as a keep-out zone, which prevents the formation of any physical structure that may hinder the application of threaded fasteners in subsequent processing steps.

[0079] refer to Figure 15A and Figure 15B At least one threaded fastener 960 can be used to secure the heatsink 940 to the cover structure 910. In other words, at least one threaded fastener 960 can be used to mount the heatsink 940 to the cover structure 910. The at least one threaded fastener 960 may include a plurality of threaded fasteners 960. Each of the at least one threaded fastener 960 can pass through a corresponding one of the at least one through hole 949. Each of the at least one threaded fastener 960 can engage with a corresponding one of the at least one threaded hole 919, thereby securing the heatsink 940 to the cover structure 910. In embodiments where the at least one threaded fastener 960 includes at least one bolt, each of the at least one threaded fastener 960 can be fitted into a corresponding threaded hole 919 in the cover structure 910 without altering the shape of the corresponding threaded hole 919. In embodiments where the at least one threaded fastener 960 includes at least one screw, each of the at least one threaded fastener 960 can be fitted into a corresponding threaded hole 919 while deforming the corresponding threaded hole 919.

[0080] Typically, the heatsink 940 can be mounted to the cover structure 910 using at least one threaded fastener 960. The at least one threaded fastener 960 is a mechanical structure that provides a mechanical connection between the heatsink 940 and the cover structure 910, regardless of any deformation that may occur in the cover structure 910 and / or the heatsink 940 during operation of the encapsulation structure. Therefore, the at least one threaded fastener 960 provides a mechanically stable connection unaffected by the thermal expansion of the cover structure 910, the first TIM layer 911, the second TIM layer 921, and the heatsink 940. The heatsink 940 includes at least one through-hole 949 through which the at least one threaded fastener 960 passes, and the at least one threaded fastener 960 screws into a corresponding one of the at least one threaded holes 919.

[0081] Figure 15C and Figure 15D Showing Figure 15A and Figure 15BThe alternative configuration of the first example structure in the processing steps. Generally, the positions of at least one threaded fastener 960 can be distributed over the entire area of ​​the cover structure 910, as long as at least one threaded fastener 960 can provide a reliable structural fastening between the heat sink and the cover structure 910. Figure 15C The first configuration is shown, in which a 3x3 array of threaded fasteners 960 is used, such that eight threaded fasteners 960 are positioned along the edge of the cover structure 910, and one threaded fastener 960 is located at the center of the cover structure 910. Figure 15D A second configuration is shown, in which four threaded fasteners 960 are used at the four corners of the cover structure 910, and an additional set of threaded fasteners 960 is provided at the center of the cover structure 960.

[0082] refer to Figure 16 A PCB 100 may be provided, comprising a printed circuit board (PCB) substrate 110 and a plurality of PCB bonding pads 180. The PCB 100 includes printed circuitry (not shown) at least on one side of the PCB substrate 110. The PCB 100 may be attached to a bonding assembly comprising a composite package 800, a package substrate 200, a cover structure 910, and a heat sink 940. In one embodiment, the bonding assembly (composite package 800, package substrate 200) is attached to the PCB 100 using an array of solder material portions 190, the array of solder material portions 190 providing solder bonding between the PCB 100 and the package substrate 200. In this embodiment, the array of solder material portions 190 may be arranged over an array of PCB bonding pads 180 and may be reflowed to form a plurality of solder joints bonded to each pair of board-side bonding pads 248 and PCB bonding pads 180. Additional underfill material portions, referred to herein as board-substrate underfill material portions 192 or BS underfill material portions 192, can be formed around the plurality of solder material portions 190 by applying and shaping an underfill material. The package substrate 200 is attached to the PCB 100 via an array of the plurality of solder material portions 190.

[0083] refer to Figure 17A and Figure 17B A second exemplary packaging structure is shown, which can be achieved by attaching the cover structure 910 to... Figure 12The cap structure 910 is formed by bonding assemblies (composite package 800, package substrate 200). The cap structure 910 includes at least one threaded hole 919 extending vertically from the top surface of the cap structure 910 toward the bonding assembly (composite package 800, package substrate 200). The cap structure 910 can be attached to the bonding assembly (composite package 800, package substrate 200) using the methods described above, for example, using an adhesive layer 905 applied between the package substrate 200 and the frame-shaped bottom surface of the cap structure 910. In this embodiment, a first thermal interface material (TIM) layer 911 can be applied to each of the top surfaces of at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703), and the cap structure 910 can be attached to at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) through the first TIM layer 911.

[0084] In the second exemplary packaging structure, the top surface of the cover structure 910 includes a basin 927. At least one threaded hole 919 extends vertically downward from a first horizontal plane HP1 including the topmost horizontal surface segment of the cover structure 910 to below a second horizontal plane HP2 including the bottom surface of the basin 927. Therefore, the depth of the basin 927 can be less than the vertical length of the at least one threaded hole 919. In one embodiment, the depth of the basin 927 can be in the range of 50 micrometers to 1 millimeter, for example from 100 micrometers to 300 micrometers, but smaller or larger depths can also be used.

[0085] According to one aspect of this disclosure, the basin 927 does not overlap with any of the at least one threaded hole 919 in a plan view (i.e., a view along a vertical direction, such as a top-down view or a horizontal sectional view). In one embodiment, the at least one threaded hole 919 comprises a plurality of threaded holes 919. Figure 17A and Figure 17B In the configuration shown, the threaded hole 919 selected from a plurality of threaded holes 919 can be seen in a horizontal cross-sectional view cut through the basin 927 (e.g.) Figure 17B The view is surrounded laterally by the basin 927, and a plurality of additional threaded holes 919 selected from a plurality of threaded holes 919 may be located outside the basin 927 in the horizontal cross-sectional view.

[0086] refer to Figures 18A to 18E The basin 927 may be filled with a thermal interface material to form a second thermal interface material (TIM) layer 921. In one embodiment, the amount of thermal interface material applied to the basin 927 may be controlled such that the second TIM layer 921 fills the entire volume of the basin, and the top surface of the second TIM layer 921 is formed at or near a first horizontal plane including the topmost horizontal surface segment of the cover structure 910.

[0087] A heat sink 940 comprising at least one through hole 949 may be provided. The heat sink 940 comprises a metallic material with high electrical conductivity, such as copper or aluminum. According to one aspect of this disclosure, the configuration of the at least one through hole 949 through the heat sink 940 may be selected to correspond to the pattern of at least one threaded hole 919 in the cover structure 910. If the at least one threaded hole 919 comprises a plurality of threaded holes 919, the at least one through hole 949 may comprise a plurality of through holes 949. Typically, the sidewalls of the at least one through hole 949 may be smooth, and the lateral dimension (e.g., diameter) of the at least one through hole 949 may be selected to allow unobstructed passage of subsequently used threaded fasteners.

[0088] The heat sink 940 can be attached to the cover structure 910 using a second TIM layer 921. The second TIM layer 921 may comprise any thermal interface material known in the art. The basin region of the cover structure 910 is covered by the second TIM layer 921, while the topmost surface segment of the cover structure 910 and at least one threaded hole 919 are not covered by the second TIM layer 921. Therefore, the heat sink 940 is directly mounted on the cover structure 910 and directly on the TIM layer 921.

[0089] The heat sink 940 may include a horizontally extending heat sink plate portion in contact with the second TIM layer 921 and a plurality of heat sink fin portions extending vertically upward from the horizontally extending heat sink plate portion. In some embodiments, the plurality of heat sink fin portions may be arranged in a grid pattern. According to one embodiment of this disclosure, the pattern of the plurality of heat sink fin portions is selected to include an opening located above each of at least one through hole 949, the opening extending through the horizontally extending heat sink plate portion of the heat sink 940. Each opening in the plurality of heat sink fin portions acts as a no-entry zone, preventing the formation of any physical structure that might hinder the application of threaded fasteners in subsequent processing steps.

[0090] refer to Figure 19At least one threaded fastener 960 can be used to secure the heatsink 940 to the cover structure 910. In other words, at least one threaded fastener 960 can be used to permanently mount the heatsink 940 to the cover structure 910. The at least one threaded fastener 960 may include a plurality of threaded fasteners 960. Each of the at least one threaded fastener 960 may pass through a corresponding one of the at least one through hole 949. Each of the at least one threaded fastener 960 may engage with a corresponding one of the at least one threaded hole 919, thereby securing the heatsink 940 to the cover structure 910. In embodiments where the at least one threaded fastener 960 includes at least one bolt, each of the at least one threaded fastener 960 may be fitted into a corresponding threaded hole 919 in the cover structure 910 without altering the shape of the corresponding threaded hole 919. In embodiments where the at least one threaded fastener 960 includes at least one screw, each of the at least one threaded fastener 960 may be fitted into a corresponding threaded hole 919 while deforming the corresponding threaded hole 919.

[0091] Typically, the heatsink 940 can be mounted to the cover structure 910 using at least one threaded fastener 960. The at least one threaded fastener 960 is a mechanical structure that provides a mechanical connection between the heatsink 940 and the cover structure 910, regardless of any deformation that may occur in the cover structure 910 and / or the heatsink 940 during operation of the encapsulation structure. Therefore, the at least one threaded fastener 960 provides a mechanically stable connection unaffected by the thermal expansion of the cover structure 910, the first TIM layer 911, the second TIM layer 921, and the heatsink 940. The heatsink 940 includes at least one through-hole 949 through which the at least one threaded fastener 960 passes, and the at least one threaded fastener 960 screws into a corresponding one of the at least one threaded holes 919.

[0092] refer to Figure 20A PCB 100 comprising a PCB substrate 110 and a plurality of PCB pads 180 may be provided. The PCB 100 includes printed circuitry (not shown) at least on one side of the PCB substrate 110. The printed circuit board 100 may be attached to a bonding assembly comprising a composite package 800, a package substrate 200, a cover structure 910, and a heat sink 940. In one embodiment, the bonding assembly (composite package 800, package substrate 200) is attached to the printed circuit board 100 using an array of solder material portions 190, the array of solder material portions 190 providing solder bonding between the printed circuit board 100 and the package substrate 200. In this embodiment, the array of solder material portions 190 may be arranged over an array of PCB pads 180 and may be reflowed to form a plurality of solder joints bonded to each pair of board-side bonding pads 248 and PCB pads 180. Additional underfill material portions, referred to herein as board-substrate underfill material portions 192 or BS underfill material portions 192, can be formed around the plurality of solder material portions 190 by applying and shaping an underfill material. The package substrate 200 is attached to the PCB 100 via an array of the plurality of solder material portions 190.

[0093] refer to Figure 21A and Figure 21B The third exemplary packaging structure can be derived from... Figure 17A and Figure 17B The second exemplary packaging structure is derived from that, which is achieved by using... Figure 17A and Figure 17B The second exemplary package structure is formed by attaching it to the printed circuit board 100. Therefore, the cover structure 910 can be attached to a bonding assembly (composite package 800, packaging substrate 200) including the composite package 800 and the packaging substrate 200, and subsequently the bonding assembly (composite package 800, packaging substrate 200) can be attached to the printed circuit board 100. Typically, reference... Figure 16 The described processing steps can be used to attach a bonding assembly (composite package 800, package substrate 200) to a printed circuit board 100. In one embodiment, the bonding assembly (composite package 800, package substrate 200) is attached to the printed circuit board 100 using an array of multiple solder material portions 190, the array of solder material portions 190 providing solder bonding between the printed circuit board 100 and the package substrate 200.

[0094] According to one aspect of this disclosure, the printed circuit board 100 includes at least one through-hole, referred herein as at least one through-board hole 109. The at least one through-board hole 109 is located in the region where the wall portion of a heat sink to be used subsequently contacts the printed circuit board 100.

[0095] refer to Figures 22A to 22C A heat sink 940 may be provided. The heat sink 940 includes a heat sink plate portion 940T having a perforated plate configuration, including at least one through hole 949, and having a lateral extent greater than the lateral extent of the bonding assembly (composite package 800, package substrate 200); a plurality of heat sink fin portions 940F extending vertically upward from the top surface of the heat sink plate portion 940T; and a wall portion 940W extending vertically downward from the periphery of the bottom surface of the heat sink plate portion 940T. The wall portion 940W may laterally surround the holes therein. In one embodiment, the wall portion 940W may have a moat configuration. In one embodiment, the wall portion 940W may include an assembly of four planar wall structures adjacent to each other to provide a vertically extending structure with a horizontal cross-sectional shape of a rectangular frame, i.e., a frame having an outer rectangular periphery and an inner rectangular periphery.

[0096] The basin 927 may be filled with a thermal interface material to form a second thermal interface material (TIM) layer 921. In one embodiment, the amount of thermal interface material applied to the basin 927 may be controlled such that the second TIM layer 921 fills the entire volume of the basin, and the top surface of the second TIM layer 921 is formed at or near a first horizontal plane including the topmost horizontal surface segment of the cover structure 910.

[0097] The heat sink 940 can be attached to the cover structure 910 using a second TIM layer 921. The second TIM layer 921 may comprise any thermal interface material known in the art. The basin region of the cover structure 910 is covered by the second TIM layer 921, while the topmost surface segment of the cover structure 910 and at least one threaded hole 919 are not covered by the second TIM layer 921. Therefore, the heat sink 940 is directly mounted on the cover structure 910 and directly on the TIM layer 921.

[0098] The heatsink plate portion 940T contacts the second TIM layer 921. A plurality of heatsink fin portions 940F extend vertically upward from the heatsink plate portion 940T. In some embodiments, the plurality of heatsink fin portions 940F may be arranged in a grid pattern. According to one embodiment of this disclosure, the pattern of the plurality of heatsink fin portions 940F is selected to include an opening located above each of at least one through hole 949, the opening extending through the heatsink plate portion 940T of the heatsink 940. Each opening in the plurality of heatsink fin portions 940F acts as a no-entry zone, preventing the formation of any physical structure that might hinder the application of threaded fasteners in subsequent processing steps.

[0099] The radiator 940 can be secured to the cover structure 910 using at least one threaded fastener 960. In other words, at least one threaded fastener 960 can be used to permanently mount the radiator 940 to the cover structure 910. The at least one threaded fastener 960 may include a plurality of threaded fasteners 960. Each of the at least one threaded fastener 960 can pass through a corresponding one of at least one through hole 949. Each of the at least one threaded fastener 960 can engage with a corresponding one of at least one threaded hole 919, thereby securing the radiator 940 to the cover structure 910. In embodiments where the at least one threaded fastener 960 includes at least one bolt, each of the at least one threaded fastener 960 can be fitted into a corresponding threaded hole 919 in the cover structure 910 without altering the shape of the corresponding threaded hole 919. In embodiments where the at least one threaded fastener 960 includes at least one screw, each of the at least one threaded fastener 960 can be fitted into a corresponding threaded hole 919 while deforming the corresponding threaded hole 919.

[0100] Typically, the heat sink 940 can be mounted to the cover structure 910 using at least one threaded fastener 960. The at least one threaded fastener 960 is a mechanical structure that provides a mechanical connection between the heat sink 940 and the cover structure 910, regardless of any deformation that may occur in the cover structure 910 and / or the heat sink 940 during operation of the encapsulation structure. Therefore, the at least one threaded fastener 960 provides a mechanically stable connection that is unaffected by the thermal expansion of the cover structure 910, the first TIM layer 911, the second TIM layer 921, and the heat sink 940.

[0101] Typically, the heatsink 940 can be mounted to the cover structure 910 using at least one threaded fastener 960. The heatsink 940 includes at least one through hole 949 through which the at least one threaded fastener 960 passes, and the at least one threaded fastener 960 is screwed into a corresponding one of the at least one threaded hole 919. When fully engaged with the at least one threaded hole 919, that is, when the heatsink 940 is secured to the cover structure 910, the at least one threaded fastener 960 is completely below the horizontal plane comprising the topmost surface of the plurality of heatsink fin portions 940F.

[0102] According to one aspect of this disclosure, the heat sink 940 includes a wall portion 940W that laterally surrounds the engagement assembly (composite package 800, package substrate 200) when the heat sink 940 is secured to the cover structure 910. The wall portion 940W may have a frame-shaped horizontal cross-sectional shape. The frame-shaped bottom surface of the wall portion 940W may be located at or slightly above a horizontal plane including the top surface of the printed circuit board 100. The frame-shaped bottom surface of the wall portion 940W of the heat sink 940 may include at least one additional threaded hole 979, referred to herein as at least one heat sink-side threaded hole 979. In one embodiment, each of the at least one heat sink-side threaded hole 979 may be positioned over a corresponding through-plate hole 109 to provide subsequent mechanical fixation of the wall portion 940W of the heat sink 940 to the printed circuit board 100.

[0103] refer to Figures 23A to 23C The bottom end of the wall portion 940W can be secured to the printed circuit board 100 using at least one additional threaded fastener 1060. This additional threaded fastener passes through at least one through-plate hole 109 in the printed circuit board 100 and engages with at least one additional threaded hole 979 (i.e., at least one heat sink-side threaded hole 979) in the bottom end of the wall portion 940W. The at least one additional threaded fastener 1060 is also referred to as a through-plate threaded fastener 1060. The through-plate threaded fastener 1060 can pass through a corresponding one of the at least one through-plate hole 109 and can engage with a corresponding one of the at least one heat sink-side threaded hole 979. The wall portion 940W of the heat sink 940 is secured to the printed circuit board 100.

[0104] refer to Figure 24 This illustrates an alternative configuration of a third exemplary package structure according to an embodiment of the present disclosure, after the threaded fastener 1060 of the through-plate is secured to the heat sink 940 via the printed circuit board 100. The alternative configuration of the third exemplary package structure can be derived from... Figures 23A to 23C The third exemplary encapsulation structure shown is derived from the use of a cover structure 910 containing at least one cavity 913. Each cavity 913 may be free of any solid material. Each cavity 913 may be filled with atmospheric gas. At least one cavity 913 may advantageously be used to influence the heat conduction mode within the cover structure 910.

[0105] According to various embodiments disclosed herein, the package structure may include: a bonding assembly (composite package 800, package substrate 200) comprising at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) and a package substrate 200; a cover structure 910 attached to the top surface of the bonding assembly (composite package 800, package substrate 200) and including at least one threaded hole 919 extending vertically from the top surface of the cover structure 910 toward the bonding assembly (composite package 800, package substrate 200); a heat sink 940 disposed on the cover structure 910 and including at least one through hole 949; and at least one threaded fastener 960 passing through at least one through hole 949 and screwed into a corresponding one of the at least one threaded hole 919.

[0106] This package structure may further include: a printed circuit board 100 that is bonded to the bonding assembly (composite package 800, package substrate 200) through an array of solder material portions 190; and at least one additional threaded fastener 1060 that passes through at least one through-hole 109 in the printed circuit board 100 and engages with at least one heat sink-side threaded hole 979 in the heat sink 940. In one embodiment, the heat sink 940 includes: a heat sink plate portion 940T that includes at least one through hole 949 and whose lateral extent is greater than the lateral extent of the bonding assembly (composite package 800, package substrate 200); and a wall portion 940W that laterally surrounds the bonding assembly (composite package 800, package substrate 200) when the heat sink 940 is mounted on the cover structure 910, wherein at least one heat sink-side threaded hole 979 is provided on the bottom surface of the wall portion 940W.

[0107] In one embodiment, the top surface of the cover structure 910 includes a basin 927; a first thermal interface material (TIM) layer 911 is located between at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) and the planar bottom surface of the cover structure 910; a second TIM layer 921 is located in the basin 927; and a heat sink 940 contacts the topmost surface segment of the cover structure 910 and the top surface of the second TIM layer 921. In one embodiment, the basin 927 does not overlap with any of the at least one threaded hole 919 in a plan view; and the at least one threaded hole 919 extends vertically downward from a first horizontal plane HP1 including the topmost horizontal surface segment of the cover structure 910 to below a second horizontal plane HP2 including the bottom surface of the basin 927.

[0108] refer to Figure 25 By modifying the cover structure 910, it is possible to... Figure 13A and Figure 13B as well as Figure 17A and Figure 17BEither of the first and second packaging structures shown derives a fourth exemplary packaging structure. Specifically, the cover structure 910 may be modified to provide at least one threaded side hole 929 including corresponding horizontally aligned threads.

[0109] refer to Figure 26 By performing the appropriate set of processing steps described above, the heat sink 940 can be attached to the cover structure 910, and the printed circuit board 100 can be attached to the bonding assembly (composite package 800, package substrate 200). For example, refer to Figures 14A to 15B The described group of processing steps or reference Figures 18A to 19 The described set of processing steps can be used to attach the heat sink 940 to the cover structure 910. Similarly, see reference... Figure 20 or Figure 21A and Figure 21B The described set of processing steps can be used to attach the printed circuit board 100 to the bonding assembly (composite package 800, package substrate 200). The attachment of the heat sink 940 to the cover structure 910 can be performed before or after the attachment of the printed circuit board 100 to the bonding assembly (composite package 800, package substrate 200).

[0110] refer to Figure 27A and Figure 27B A side heatsink 950 can be attached to a plurality of sidewalls of a cover structure 910 using a plurality of side thermal interface material layers 931 and a plurality of side threaded fasteners 970. Each side heatsink 950 may include a corresponding lateral through-hole 959 through which a corresponding side threaded fastener 970 may pass. Each side threaded fastener 970 engages with a corresponding threaded side hole 929 in the cover structure 910. Each side heatsink 950 may include a bottom surface containing a corresponding additional threaded hole 979, referred to herein as a heatsink side threaded hole 979. In one embodiment, each heatsink side threaded hole 979 may be positioned over a corresponding through-plate hole 109 to enable subsequent mechanical fixation of the side heatsink 950 to the printed circuit board 100. The heatsink 940 and the side heatsink 950 are independent components of a multi-piece heatsink system including at least one threaded fastener 960 and a side threaded fastener 970.

[0111] refer to Figure 28Each side heatsink 950 can be secured to the printed circuit board 100 using multiple additional threaded fasteners 1060. These additional threaded fasteners pass through multiple through-plate holes 109 in the printed circuit board 100 and engage with multiple additional threaded holes 979 (i.e., heatsink-side threaded holes 979) at the bottom end of the multiple side heatsinks 950. At least one additional threaded fastener 1060 is also referred to as a threaded fastener 1060 for at least one through-plate. Each through-plate threaded fastener 1060 can pass through a corresponding through-plate hole 109 and engage with a corresponding heatsink-side threaded hole 979. The side heatsinks 950 are secured to the printed circuit board 100.

[0112] In all embodiments disclosed herein, the pattern of the plurality of threaded fasteners 960 can be any pattern, as long as the plurality of threaded fasteners 960 can securely attach the cover structure 910 to the encapsulation substrate 200. Furthermore, in all embodiments using the plurality of side threaded fasteners 970, the pattern of the plurality of side threaded fasteners 970 can be any pattern, as long as the plurality of side threaded fasteners 970 can securely attach the plurality of side heat sinks 950 to the cover structure 910. Additionally, in all embodiments using the plurality of additional threaded fasteners 1060, the pattern of the plurality of additional threaded fasteners 1060 can be any pattern, as long as the plurality of additional threaded fasteners 1060 can securely attach the wall portion 940W of the heat sink 940 to the printed circuit board 100.

[0113] Figure 29 A first flowchart of forming a package structure is provided for an embodiment of this disclosure.

[0114] Refer to steps 2910 and Figures 1 to 13B , Figure 17A and Figure 17B as well as Figure 25 The cover structure 910 can be attached to a bonding assembly (composite package 800, packaging substrate 200) comprising at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) and a packaging substrate 200. The cover structure 910 includes at least one threaded hole 919 extending vertically from the top surface of the cover structure 910 toward the bonding assembly (composite package 800, packaging substrate 200).

[0115] Refer to steps 2920 and Figures 14A to 14D 18A to Figure 18E , 21A to Figure 22C and Figure 26 It can provide a heatsink 940 including at least one through hole 949.

[0116] Refer to steps 2930 and Figures 15A to 16 , Figure 19 and Figure 20 , Figures 23A to 24 and Figures 26 to 28 At least one threaded fastener 960 may pass through a corresponding one of at least one through hole 949, and each of the at least one threaded fastener 960 may engage with a corresponding one of at least one threaded hole 919. The radiator 940 is secured to the cover structure 910.

[0117] Figure 30 A second flowchart for forming an encapsulation structure is provided for embodiments of this disclosure.

[0118] Refer to step 3010 and Figures 1 to 13B , Figure 17A and Figure 17B as well as Figure 25 The cover structure 910 can be attached to a bonding assembly (composite package 800, packaging substrate 200) comprising at least one semiconductor die (semiconductor die 701, semiconductor die 702, semiconductor die 703) and a packaging substrate 200. The cover structure 910 includes at least one threaded hole 919 extending vertically from the top surface of the cover structure 910 toward the bonding assembly (composite package 800, packaging substrate 200).

[0119] Refer to step 3020 in the diagram and Figure 16 , Figure 20 , Figure 21A and Figure 21B as well as Figure 26 The bonding assembly (composite package 800, package substrate 200) can be attached to the printed circuit board 100.

[0120] Refer to step 3030 and Figures 14A to 15B , Figures 18A to 19 , Figures 22A to 24 and Figures 26 to 28 The radiator 940 can be mounted onto the cover structure 910 using at least one threaded fastener 960. The radiator 940 includes at least one through hole 949 through which at least one threaded fastener 960 passes, and at least one threaded fastener 960 is screwed into a corresponding one of the at least one threaded holes 919.

[0121] Some embodiments described herein provide a method for forming a package structure. This method includes attaching a cover structure to a bonding assembly comprising at least one semiconductor die and a package substrate, wherein the cover structure includes at least one threaded hole extending perpendicularly from a top surface of the cover structure toward the bonding assembly; providing a heat sink including at least one through-hole; and securing the heat sink to the cover structure by passing at least one threaded fastener through a corresponding one of the at least one through-hole and engaging each of the at least one threaded fastener into a corresponding one of the at least one threaded hole. In some embodiments, the method of forming the package structure further includes bonding the bonding assembly to a printed circuit board. In some embodiments, the heat sink includes a wall portion, wherein when the heat sink is secured to the cover structure, the wall portion laterally surrounds the bonding assembly; and the method of forming the package structure includes securing a bottom end of the wall portion to the printed circuit board. In some embodiments, the bottom end of the wall portion is secured to the printed circuit board using at least one additional threaded fastener, the at least one additional threaded fastener passing through at least one through-hole in the printed circuit board and engaging at least one additional threaded hole in the bottom end of the wall portion. In some embodiments, the method of forming a package structure further includes applying a first thermal interface material (TIM) layer to each top surface of the at least one semiconductor die, wherein the cap structure is attached to the at least one semiconductor die via the first thermal interface material layer. In some embodiments, the top surface of the cap structure includes a basin; the method of forming a package structure includes filling the basin with a second thermal interface material layer; and the heat sink is disposed directly on the cap structure and directly on the second thermal interface material layer. In some embodiments, the basin does not overlap with any of the at least one threaded hole in a plan view; and the at least one threaded hole extends vertically downward from a first horizontal plane including the topmost horizontal surface segment of the cap structure to below a second horizontal plane including the bottom surface of the basin. In some embodiments, the at least one threaded hole includes a plurality of threaded holes; a threaded hole selected from the plurality of threaded holes is laterally surrounded by the basin in a horizontal cross-sectional view cut through the basin; and a plurality of additional threaded holes selected from the plurality of threaded holes are located outside the basin in the horizontal cross-sectional view. In some embodiments, the heat sink includes: a heat sink plate portion including the at least one through hole, and the lateral extent of the plate portion being greater than the lateral extent of the bonding assembly; and a plurality of heat sink fin portions extending vertically upward from the top surface of the heat sink plate portion, wherein, when securing the heat sink to the cover structure, the at least one threaded fastener is located below a horizontal plane including the topmost surface of the plurality of heat sink fin portions. In some embodiments, the cover structure is attached to the bonding assembly using an adhesive layer that bonds the cover structure to the encapsulation substrate.

[0122] Some embodiments described herein provide a method for forming a package structure. This method includes attaching a cover structure to a bonding assembly comprising at least one semiconductor die and a package substrate, wherein the cover structure includes at least one threaded hole extending perpendicularly from a top surface of the cover structure toward the bonding assembly; attaching the bonding assembly to a printed circuit board; and mounting a heat sink to the cover structure using at least one threaded fastener, wherein the heat sink includes at least one through-hole through which the at least one threaded fastener passes, and the at least one threaded fastener is screwed into a corresponding one of the at least one threaded holes. In some embodiments, the printed circuit board includes at least one through-plate hole therethrough; the bottom of the heat sink includes at least one heat sink-side threaded hole; and the method of forming the package structure includes passing at least one additional threaded fastener through the at least one through-plate hole and engaging the at least one additional threaded fastener into the at least one heat sink-side threaded hole, thereby mounting the heat sink onto the printed circuit board. In some embodiments, the heat sink includes a wall portion, wherein when the heat sink is mounted to the cover structure, the wall portion laterally surrounds the bonding assembly; at least one heat sink-side threaded hole is provided on the bottom surface of the wall portion; and when the heat sink is mounted onto the printed circuit board, the bottom surface of the wall portion contacts the top surface of the printed circuit board. In some embodiments, the top surface of the cover structure includes a basin; the method of forming the package structure includes filling the basin with a thermal interface material (TIM) layer; and the heat sink is directly mounted on the cover structure and directly mounted on the thermal interface material layer. In some embodiments, the bonding assembly is attached to the printed circuit board using an array of multiple solder material portions, the array of multiple solder material portions providing solder bonding between the printed circuit board and the package substrate.

[0123] Some embodiments described herein provide a packaging structure. This packaging structure includes a bonding assembly comprising at least one semiconductor die and a packaging substrate; a cover structure attached to a top surface of the bonding assembly and including at least one threaded hole extending perpendicularly from the top surface of the cover structure toward the bonding assembly; a heat sink located on the cover structure and including at least one through-hole; and at least one threaded fastener passing through the at least one through-hole and screwed into a corresponding one of the at least one threaded holes. In some embodiments, the packaging structure further includes: a printed circuit board substrate bonded to the bonding assembly via an array of multiple solder material portions; and at least one additional threaded fastener passing through at least one through-plate hole in the printed circuit board and engaging at least one heat sink-side threaded hole in the heat sink. In some embodiments, the heat sink includes: a heat sink plate portion including the at least one through-hole, and having a lateral extent greater than the lateral extent of the bonding assembly; and a wall portion wherein, when the heat sink is mounted to the cover structure, the wall portion laterally surrounds the bonding assembly, wherein the at least one heat sink-side threaded hole is provided on the bottom surface of the wall portion. In some embodiments, the top surface of the cover structure includes a basin; a first thermal interface material (TIM) layer is located between the at least one semiconductor die and the planar bottom surface of the cover structure; a second thermal interface material layer is located in the basin; and the heat sink contacts the topmost surface segment of the cover structure and the top surface of the second thermal interface material layer. In some embodiments, the basin does not overlap with any of the at least one threaded hole in a plan view; and the at least one threaded hole extends vertically downward from a first horizontal plane including the topmost horizontal surface segment of the cover structure to below a second horizontal plane including the bottom surface of the basin.

[0124] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the scope of this disclosure. Each embodiment described using the term "comprising" is also inherently disclosed, unless explicitly disclosed otherwise herein, in some embodiments the term "comprising" may be replaced by "substantially consists of" or by the term "consisting of". When two or more elements are listed as alternatives in the same or different paragraphs, a Markush group comprising the list of such two or more elements may also be implicitly disclosed. Whenever the auxiliary verb "may" is used in this disclosure to describe the formation of an element or the execution of a processing step, embodiments in which such element or processing step is not performed are also explicitly contemplated, provided that the resulting apparatus or device can provide an equivalent result. Therefore, when used to form an element or perform a processing step, the auxiliary verb "may" should also be interpreted as "may" or "can, or cannot," provided that omitting the formation of such an element or processing step can provide the same or equivalent result, including slightly better and slightly worse results.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for forming an encapsulation structure, characterized in that, include: The cover structure is attached to a bonding assembly comprising at least one semiconductor die and a packaging substrate, wherein the cover structure includes at least one threaded hole extending vertically from the top surface of the cover structure toward the bonding assembly; Provide a heatsink containing at least one through hole; and At least one threaded fastener is passed through a corresponding one of the at least one through holes, and each of the at least one threaded fastener is engaged with a corresponding one of the at least one threaded holes, thereby securing the heat sink to the cover structure.

2. The method for forming an encapsulation structure according to claim 1, characterized in that, It also includes bonding the bonding assembly to a printed circuit board.

3. The method for forming an encapsulation structure according to claim 1, characterized in that, It also includes applying a first thermal interface material layer to each of the top surfaces of the at least one semiconductor die, wherein the cap structure is attached to the at least one semiconductor die via the first thermal interface material layer.

4. The method for forming an encapsulation structure according to claim 1, characterized in that, The heat sink includes: The heat sink plate portion includes the at least one through hole, and its lateral extent is greater than the lateral extent of the mating assembly; and Multiple radiator fins extend vertically upward from the top surface of the radiator plate portion. When securing the radiator to the cover structure, the at least one threaded fastener is located below a horizontal plane that includes the topmost surface of the plurality of radiator fin portions.

5. The method for forming an encapsulation structure according to claim 1, characterized in that, The cover structure is attached to the bonding assembly using an adhesive layer that bonds the cover structure to the packaging substrate.

6. A method for forming an encapsulation structure, characterized in that, include: The cover structure is attached to a bonding assembly comprising at least one semiconductor die and a packaging substrate, wherein the cover structure includes at least one threaded hole extending vertically from the top surface of the cover structure toward the bonding assembly; Attach the bonding assembly to the printed circuit board; and A radiator is mounted to the cover structure using at least one threaded fastener, wherein the radiator includes at least one through hole through which the at least one threaded fastener passes, and the at least one threaded fastener is screwed into a corresponding one of the at least one threaded holes.

7. The method for forming an encapsulation structure according to claim 6, characterized in that, The printed circuit board includes at least one through-hole. The bottom of the radiator includes at least one radiator-side threaded hole; and The method of forming the package structure includes passing at least one additional threaded fastener through the at least one through-plate hole and engaging the at least one additional threaded fastener into the at least one heat sink-side threaded hole, thereby mounting the heat sink on the printed circuit board.

8. The method for forming an encapsulation structure according to claim 6, characterized in that, The top surface of the cover structure includes a basin; The method of forming the encapsulation structure includes filling the basin with a thermal interface material layer; and The heat sink is directly mounted on the cover structure and directly on the thermal interface material layer.

9. A packaging structure, characterized in that, include: A bonding assembly, comprising at least one semiconductor die and a packaging substrate; A cover structure is attached to the top surface of the engagement assembly and includes at least one threaded hole extending vertically from the top surface of the cover structure toward the engagement assembly. A heat sink is located on the cover structure and includes at least one through hole; as well as At least one threaded fastener passes through the at least one through hole and is screwed into a corresponding one of the at least one threaded holes.

10. The packaging structure according to claim 9, characterized in that, Also includes: A printed circuit board is bonded to the bonding assembly via an array of multiple solder material portions; as well as At least one additional threaded fastener passes through at least one through-plate hole in the printed circuit board and engages with at least one heat sink-side threaded hole in the heat sink.

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