Smart movement of external content to internal storage

Abstract

An example accelerator circuit [202A] includes a direct memory access (DMA) circuit [405] configured to copy contents of an off-chip memory to an internal memory of a device. In some examples, the off-chip memory is external to the device. The example accelerator circuit [202A] also includes a decoder circuit [410] configured to determine that a transaction from a processor circuit of the device is associated with a memory address included in a region of the off-chip memory to be copied to the internal memory. In some examples, the decoder circuit [410] is also configured to direct the transaction to one of the off-chip memory or the internal memory based on whether DMA copying of the region of the off-chip memory to the internal memory has completed.

Description

[0001] This specification generally relates to accessing memory, and more specifically, to the intelligent movement of content, such as external content, to internal memory. Background Technology

[0002] Some silicon-on-a-chip (SoC) devices, such as microcontroller units (MCUs) and microprocessor units (MPUs), include internal flash memory that can be programmed with content associated with one or more applications to be executed by the SoC device. This content may be code (e.g., instructions, program code, etc.) to be executed by the SoC device to implement the application, data to be processed by the application, etc. However, some other SoC devices, such as some high-performance MCUs and MPUs, do not include such internal flash memory. SoC devices that do not include internal flash memory (e.g., MCUs, MPUs, etc.) may rely on off-chip memory to store the content (e.g., code, data, etc.) of the applications to be executed by those SoC devices. Summary of the Invention

[0003] For methods and apparatuses performing intelligent movement of external content to internal memory, example accelerator circuitry includes direct memory access (DMA) circuitry configured to copy the contents of off-chip memory to the internal memory of the device. In some instances, the off-chip memory is external to the device. The example accelerator circuitry also includes decoder circuitry configured to determine that a transaction from the device's processor circuitry is associated with a memory address contained in a region of the off-chip memory to be copied to the internal memory. In some instances, the decoder circuitry is also configured to direct the transaction to either the off-chip memory or the internal memory based on whether the DMA copy of the region of the off-chip memory to the internal memory has been completed.

[0004] For a method and apparatus for performing intelligent movement of external content to internal memory, an example apparatus includes internal memory, processor circuitry, and accelerator circuitry configured to initiate a copy of a region of off-chip memory to the internal memory based on configuration information provided by at least one of a bootloader or an application. In some instances, the bootloader is stored in the off-chip memory. In some instances, the accelerator circuitry is configured to determine that a transaction from the processor circuitry is associated with a memory address contained in the region of the off-chip memory, and to direct the transaction to either the off-chip memory or the internal memory based on whether the copy of the region of the off-chip memory to the internal memory has been completed.

[0005] For methods and apparatuses for performing intelligent movement of external content to internal memory, an example system includes random access memory (RAM), processor circuitry, off-chip memory external to the processor circuitry, and accelerator circuitry configured to copy one or more regions of the off-chip memory to the RAM based on configuration information provided by at least one of a bootloader or an application. In some instances, the accelerator circuitry is configured to determine that a transaction from the processor circuitry is associated with a memory address contained in a first of the regions of the off-chip memory to be copied to the RAM. In some instances, the accelerator circuitry is configured to direct the transaction to either the off-chip memory or the RAM based on whether the copy from the first region of the off-chip memory to the RAM has been completed. Attached Figure Description

[0007] Figure 1 This is a block diagram of an example system containing a first example microcontroller unit configured to access code and data from off-chip memory.

[0008] Figure 2 This is a block diagram of an example system including a second example microcontroller unit, which includes one or more example mirror accelerator circuits configured to perform intelligent movement of external content (e.g., code and data) from off-chip memory to internal memory.

[0009] Figure 3 It shows Figure 2 Example operation of one of the mirror accelerator circuits.

[0010] Figure 4 yes Figure 2 A block diagram of an example implementation of one of the mirror accelerator circuits.

[0011] Figure 5 It means by Figure 2 A flowchart illustrating an example mirroring process implemented in one of the mirror accelerator circuits.

[0012] Figures 6 to 8 This is a flowchart representing example machine-readable instructions or example operations, which can be implemented, instantiated, or executed by at least one of a programmable circuit system to implement example software tools (e.g., example software compiler, example software linker, etc.), which generate configuration information for use with... Figures 2 to 5 The example image accelerator circuitry is used to perform intelligent movement of content (e.g., code and data) that can be outside or inside internal memory.

[0013] Figures 9 to 10 It shows that it can be contained in Figure 2 Example execution results of the mirror accelerator circuit implementation in the example microcontroller unit.

[0014] Figure 11 This is a block diagram of an example processing platform, which includes components configured to implement, instantiate, or execute. Figures 6 to 8 Example machine-readable instructions or execution Figures 6 to 8 The example operations are used to implement the programmable circuit system of the example software tools disclosed herein.

[0015] Figure 12 This is a block diagram of an example software / firmware / instruction distribution platform (e.g., one or more servers) used to distribute software, instructions, or firmware (e.g., corresponding to...) Figures 6 to 8 Example machine-readable instructions) are distributed to client devices associated with end users or consumers (e.g., for licensing, selling, or using), retailers (e.g., for selling, reselling, licensing, or sublicensing), or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, for example, retailers or other end users (e.g., direct purchase customers).

[0016] The drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and this specification refer to features and / or parts that are (functionally and / or structurally) the same or similar. Although the drawings show areas with clearly defined lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, boundaries or lines may be invisible, mixed, or irregular. Detailed Implementation

[0017] As mentioned above, some MCUs include internal flash memory, which can be programmed with content associated with one or more applications to be executed by the MCU. High-performance MCUs are a new class of SoCs that utilize higher process nodes and higher-performance central processing unit (CPU) cores compared to MCUs with internal flash memory. For example, such high-performance MCUs may use 16 nanometer (nm), 14 nm, and / or even 10 nm process nodes, and multi-core (e.g., quad-core) architectures supporting operation at frequencies from 400 MHz to 1 GHz or higher. However, for at least some high-performance MCUs, migrating flash memory to such process nodes may be difficult or unavailable. Therefore, high-performance MCUs may rely on external flash memory, such as off-chip flash memory or separate on-die flash memory contained in, for example, a system-on-a-chip package (SIP), and associated interface technologies, such as Octal Serial Peripheral Interface (OSPI), Extended Serial Peripheral Interface (xSPI), etc., to store programmable content (e.g., code, data, etc.) for applications to be executed by the MCU. Some such MCUs can directly access / execute content (or parts thereof) from off-chip memory, or copy content (or parts thereof) from off-chip memory to the internal memory of the SoC device before accessing / executing content (or parts thereof). However, due to limited bus width (e.g., 8 bits) and clock rate (e.g., 166 MHz), external flash memory technology can be 4 to 8 times slower than internal flash memory technology.

[0018] Therefore, the use of external flash memory can impose one or more constraints on system designs employing high-performance MCUs. For example, executing code from external flash memory using Execute In-In (XIP) can be 4 to 8 times slower than executing from internal flash memory. Furthermore, executing code from internal memory (such as the MCU's internal random access memory (RAM)) is comparable to executing from internal flash memory. However, executing from internal memory increases boot time because copying content from external flash memory to internal memory (a process known as image downloading) takes time, resulting in boot times exceeding 75 milliseconds (ms) in some instances. However, some MCU system designs aim to achieve boot times of <30 ms with a 16 MB internal flash memory size.

[0019] As mentioned above, XIP is a method used by MCUs that rely on external flash memory to store the contents of the application to be executed by the MCU. In some such methods, when the MCU is booted, it configures the external flash memory in XIP mode. The MCU then copies the data associated with the application to internal memory (e.g., internal RAM), but leaves the application code in the external flash memory. The MCU then executes the program code in-situ from the external flash memory. Compared to image download methods, this method results in relatively faster boot times; for example, in some instances, boot times are <60 ms. However, executing the program from external flash memory is slower than from internal memory; for example, in some instances, it is 4.5 times slower.

[0020] As mentioned above, image download is another method used by MCUs that rely on external flash memory to store the contents of the application to be executed by the MCU. In some such methods, when the MCU is booted, it copies the complete application contents (e.g., program code, read-only data, read / write data, etc., collectively referred to as the application image) from the external flash memory to the MCU's internal memory (e.g., RAM). After the image copy (also known as image download) is complete, the MCU then executes the program code from the internal memory (e.g., RAM). This method makes executing the application from internal memory comparable in speed to executing from internal flash memory. However, the application boot time is slower than execution from internal flash memory because it takes time to wait for the image copy from external flash memory to internal memory (e.g., RAM) to complete; in some instances, this time can be as long as 80 ms.

[0021] In contrast to the methods described above, the disclosed techniques perform intelligent movement of application content from off-chip memory to internal memory. This enables execution from internal memory (e.g., internal RAM) using dynamic content loading from external flash memory, while achieving a boot target equivalent to execution from internal flash memory, in some instances, which can be <30 ms. Some of these disclosed techniques (also known as intelligent external content mirroring techniques) are based on example mirroring accelerator circuitry that intelligently mirrors content from external (e.g., off-chip) memory to internal memory for access by the MCU's central processing unit (CPU). In some disclosed instances, the bootloader configures the mirroring accelerator circuitry (e.g., also known as a mirroring accelerator, Fast Local Copy (FLC) accelerator circuitry, FLC accelerator, etc.) during bootstrapping to initiate (e.g., trigger) an external content mirroring operation using direct memory access (DMA) to mirror or copy application content from external (e.g., off-chip) memory to the MCU's internal memory. The CPU then resets and begins application execution without waiting for the mirroring operation to complete. While an external content mirroring operation is in progress, the mirroring accelerator examines memory transactions from the CPU and transfers those associated with completed content mirroring to internal memory (e.g., internal RAM). However, for transactions associated with content still being mirrored, the mirroring accelerator redirects those transactions to external memory (e.g., off-chip flash memory). In some instances, the mirroring accelerator also performs address translation while redirecting CPU transactions to external memory. In some instances, DMA uses the on-the-fly authentication and / or error correction coding (ECC) features of the available memory controller (e.g., flash controller) to securely and reliably copy data from external (e.g., off-chip) memory.

[0022] The intelligent external content mirroring techniques disclosed herein offer one or more advantages over other methods. In some instances, the disclosed intelligent external content mirroring techniques can achieve near-instantaneous CPU startup; for example, setup time is <1 ms in some instances. Furthermore, the intelligent external content mirroring disclosed herein is transparent to the application being booted and executed, and the application can be developed and debugged by assuming that the application's code and data reside in internal memory (e.g., internal RAM). Some of the intelligent external content mirroring techniques disclosed herein employ intelligent layout algorithms to increase the probability of CPU transactions being associated with completed mirroring operations, resulting in a higher internal memory "hit" rate. For example, to help ensure that application content (e.g., code and data) is mirrored (e.g., copied) from external (e.g., off-chip) memory to internal memory (e.g., RAM) before being accessed by the CPU, some disclosed intelligent external content mirroring techniques include software tools (e.g., compilers, linkers, etc.) that generate a program code layout in memory, which is ordered based on the order of function call execution during application code startup. For example, such software tools (e.g., compilers, linkers, etc.) can use static call graphs and dynamic code coverage to implement smart layout algorithms to arrange program code in the order of function calls, thereby improving the internal memory "hit" rate by making the content mirror follow the function call order of the program code.

[0023] Although this document describes intelligent external content mirroring in the context of external (e.g., off-chip) flash memory, such intelligent external content mirroring technology can be used with any type and / or number of external (e.g., off-chip) memories, storage devices, etc. Intelligent external content mirroring can also be applied to mirroring content from a first internal memory (e.g., slower internal memory) to a second internal memory (e.g., faster internal memory). Furthermore, although this document describes intelligent external content mirroring in the context of an implementation in an MCU, such intelligent external content mirroring technology can be implemented in any type of system, device, SoC, integrated circuit, etc., such as in MCUs, MPUs, etc.

[0024] Turn to the attached diagram. Figure 1 A block diagram of a first example MCU 100 configured to access code and data from example off-chip memory 105 is shown. Although Figure 1The processing device shown is described as MCU 100, but the components shown within MCU 100 can also be implemented in any processing system or device (e.g., an MPU system). MCU 100 and off-chip memory 105 may be included in example device or system 108, which may be any computing device, system, component, etc. MCU 100 includes one or more example CPUs 110. In the illustrated example, a given CPU 110 of MCU 100 includes an example processor core 115, example local internal memory 120, example instruction cache 125, and example data cache 130. Although CPU 110 is shown as containing a single processor core 115, in some instances, CPU 110 may contain any number of processor cores. Furthermore, local internal memory 120 (also referred to as local memory 120) may be implemented by any number and / or type of memory, such as Level 1 (L1) RAM in the illustrated example. In the illustrated example, local memory 120 is implemented by one or more tightly coupled memories (TCMs). Figure 1 The Chinese text marks them as "ATCM" and "BTCM".

[0025] Figure 1 The example MCU 100 also includes an example shared internal memory 135, an example memory controller circuitry 140, and an example interconnect circuitry 145. The shared internal memory 135 (also referred to as shared memory 135) can be implemented by any number and / or type of memory, such as Level 2 (L2) RAM in the illustrated example. The memory controller circuitry 140 (also referred to as memory controller 140) can be implemented by any number and / or type of memory controller circuitry configured to interface with any number and / or type of off-chip memory 105. For example, the memory controller circuitry 140 may implement an example serial peripheral interface 148, such as OSPI and xSPI, to interface with the off-chip memory 105. In some instances, the memory controller circuitry 140 also implements authentication and / or ECC functions for accessing the contents (e.g., code, data, etc.) of the off-chip memory 105.

[0026] In the example MCU 100, interconnect circuitry 145 couples CPU 110 to shared internal memory 135 and memory controller circuitry 140. Interconnect circuitry 145 can be implemented using any number and / or type of interconnect technology, such as one or more buses, one or more registers, one or more memories, one or more switching structures, etc. Thus, interconnect circuitry 145 enables one or more CPUs 110 to access shared internal memory 135 and off-chip memory 105 via memory controller 140. Furthermore, in some instances, interconnect circuitry 145 enables memory controller 140 to access shared internal memory 135 and the respective local internal memory 120 of one or more CPUs 110.

[0027] The off-chip memory 105 in the illustrated example can be implemented by any number and / or type of memory, storage device, etc. For example, the off-chip memory 105 can be implemented by one or more external flash memories, one or more external RAMs, one or more external ROMs, etc., and / or contain one or more external flash memories, one or more external RAMs, one or more external ROMs, etc. In the illustrated example, the off-chip memory 105 is configured to store content (e.g., code, data, etc.) associated with one or more applications to be executed by corresponding entities in one or more CPUs 110 of the MCU 100.

[0028] Furthermore, the MCU 100 in the illustrated example is configured to implement one or more of the XIP method and image download method described above to access content stored on off-chip memory 105. Thus, off-chip memory 105 includes a first example content area 150 for storing content (e.g., code, data, etc.) associated with an application to be executed from off-chip memory 105. For example, off-chip memory 105 includes an example content area 155 for storing content associated with the first application to be executed from CPU 110 (in... Figure 1 Such XIP content is associated with one or more applications executed by CPU 110 (marked as "CPU-0"); example content area 160 is used to store content related to a second application to be executed by CPU 110 (in... Figure 1 Such XIP content is associated with one or more applications executed by CPU 110 (labeled "CPU-n"); etc. The off-chip memory 105 of the illustrated example also includes a second example content area 165 for storing content associated with an application (e.g., code, data, etc.), an image of which will be downloaded to internal memory (e.g., local memory 120 and / or shared memory 135) and executed from internal memory. For example, off-chip memory 105 includes an example content area 170 for storing content associated with the first application to be executed by CPU 110 (in... Figure 1Such non-XIP content is associated with one or more applications executed by CPU 110 (marked as "CPU-0"); example content area 175 is used to store content related to a second application to be executed by CPU 110 (in... Figure 1 Such non-XIP content associated with one or more applications executed (marked as "CPU-n"); etc.

[0029] In the illustrated example, off-chip memory 105 also stores an example secondary bootloader 180 to implement XIP and image download methods for accessing the contents of off-chip memory 105. In some instances, the secondary bootloader 180 is invoked by the primary bootloader of MCU 100 upon power-up of MCU 100. In some instances, to implement the XIP method for accessing XIP content 150 of off-chip memory 105, the secondary bootloader 180 configures CPU 110 and / or memory controller 140 to copy data from the corresponding XIP content areas 155 to 160 of off-chip memory 105 to shared memory 135 and / or the corresponding local memory 120 of CPU 110. The secondary bootloader 180 then configures CPU 110 to execute program code in-situ from the corresponding XIP content areas 155 to 160 of off-chip memory 105.

[0030] In some instances, to implement an image download method for accessing non-XIP content 165 of off-chip memory 105, secondary bootloader 180 configures CPU 110 and / or memory controller 140 to copy application images (e.g., code and data) from the corresponding non-XIP content areas 170 to 175 of off-chip memory 105 to shared memory 135 and / or the corresponding local memory 120 of CPU 110. Secondary bootloader 180 also configures CPU 110 to execute program code from shared memory 135 and / or the corresponding local memory 120 of CPU 110 after the image copying is complete.

[0031] Figure 2A block diagram of a second example MCU 200 is shown, which includes one or more example mirror accelerator circuits 202 configured to perform intelligent movement of external content (e.g., code and data) from example off-chip memory 205 to internal memory. The MCU 200 and off-chip memory 205 may be included in an example device or system 208, which may be any computing device, system, component, etc. The MCU 200 includes one or more example CPUs 210, which may be implemented by corresponding processor circuitry. For example, the MCU 200 includes example CPU 210A and example CPU 210B. In the illustrated example, the CPU 210A of the MCU 200 includes an example processor core 215A, example local internal memory 220A, an example instruction cache 225A, and an example data cache 230A. The processor core 215A may be implemented by any number and / or type of processor circuitry. Although CPU 210A is shown as containing a single processor core 215A, in some instances, CPU 210A may contain any number of processor cores. Furthermore, local internal memory 220A (also referred to as local memory 220A) may be implemented by any number and / or type of memory, such as L1 RAM in the illustrated example. In some instances, local memory 220A is implemented by one or more TCMs.

[0032] Similarly, in the illustrated example, the CPU 210B of the MCU 200 includes an example processor core 215B, an example local internal memory 220B, an example instruction cache 225B, and an example data cache 230B. The processor core 215B can be implemented by any number and / or type of processor circuitry. Although the CPU 210B is shown as containing a single processor core 215B, in some instances, the CPU 210B can contain any number of processor cores. Furthermore, the local internal memory 220B (also referred to as local memory 220B) can be implemented by any number and / or type of memory, such as L1 RAM in the illustrated example. In some instances, the local memory 220B is implemented by one or more TCMs. In the following description, CPU 210A and CPU 210B are collectively referred to as CPU 210, processor core 215A and processor core 215B are collectively referred to as processor core 215, local internal memory 220A and local internal memory 220B are collectively referred to as local internal memory 220, instruction cache 225A and instruction cache 225B are collectively referred to as instruction cache 225, and data cache 230A and data cache 230B are collectively referred to as data cache 230.

[0033] Figure 2The example MCU 200 also includes an example shared internal memory 235, an example memory controller circuitry 240, and an example interconnect circuitry 245. The shared internal memory 235 (also referred to as shared memory 235) can be implemented by any number and / or type of memory, such as L2 RAM in the illustrated example. The memory controller circuitry 240 (also referred to as memory controller 240) can be implemented by any number and / or type of memory controller circuitry configured to interface with any number and / or type of off-chip memory 205. For example, the memory controller circuitry 240 may implement an example serial peripheral interface 248, such as OSPI and xSPI, to interface with the off-chip memory 205. In some instances, the memory controller circuitry 240 also implements authentication and / or ECC functions for accessing the contents (e.g., code, data, etc.) of the off-chip memory 205.

[0034] In the example MCU 200, interconnect circuitry 245 couples mirror accelerator circuitry 202 to shared internal memory 235 and memory controller circuitry 240. Interconnect circuitry 245 can be implemented using any number and / or type of interconnect technology, such as one or more buses, one or more registers, one or more memories, one or more switching structures, etc. Thus, interconnect circuitry 245 enables CPU 210 to access shared internal memory 235 and off-chip memory 205 via mirror accelerator circuitry 202 and memory controller 240. Furthermore, in some instances, interconnect circuitry 245 enables memory controller 240 to access shared internal memory 235 and the corresponding local internal memory 220 of CPU 210.

[0035] The off-chip memory 205 in the illustrated example can be implemented by any number and / or type of memory, storage device, etc. For example, the off-chip memory 205 can be implemented by one or more external flash memories, one or more external RAMs, one or more external ROMs, etc., and / or contain one or more external flash memories, one or more external RAMs, one or more external ROMs, etc. In the illustrated example, the off-chip memory 205 is configured to store content (e.g., code, data, etc.) associated with one or more applications to be executed by a responder in the CPU 210 of the MCU 200.

[0036] Furthermore, the MCU 200 of the illustrated example is configured to implement intelligent external content mirroring of content stored on off-chip memory 205. Thus, off-chip memory 205 includes example content area 265 for storing application content (e.g., code, data, etc.) to be mirrored to internal memory (e.g., local memory 120 and / or shared memory 135). For example, off-chip memory 205 includes example content area 270 for storing such non-XIP content associated with one or more applications to be executed by the first CPU 210A; example content area 275 for storing such non-XIP content associated with one or more applications to be executed by the second CPU 210B; and so on.

[0037] As mentioned above, MCU 200 includes mirror accelerator circuitry 202 for performing intelligent movement of external content (e.g., code and data) from off-chip memory 205 to internal memory such as shared memory 235 and / or local memory 220. In the illustrated example, CPU 210 is associated with (e.g., coupled to) a corresponding mirror accelerator circuitry 202. For example, mirror accelerator circuitry 202 includes example mirror accelerator circuitry 202A associated with CPU 210A (e.g., coupled to CPU 210A) and example mirror accelerator circuitry 202B associated with CPU 210B (e.g., coupled to CPU 210B). Mirror accelerator circuitry 202A and mirror accelerator circuitry 202B are collectively referred to as mirror accelerator circuitry 202.

[0038] In the illustrated example, off-chip memory 205 also stores an example secondary bootloader 280 for configuring mirror accelerator circuitry 202 to mirror external content (e.g., code and data) from off-chip memory 205 to internal memory, such as shared memory 235 and / or local memory 220. In some instances, secondary bootloader 280 is invoked by primary bootloader of MCU 200 upon power-up of MCU 200. In some instances, secondary bootloader 280 uses configuration information to configure mirror accelerator circuitry 202, specifying a region of off-chip memory 205 containing the content of CPU 210 associated with the corresponding mirror accelerator circuitry 202. For example, secondary bootloader 280 may use configuration information to configure mirror accelerator circuitry 202A, specifying the start address, size, etc., of content region 270 associated with CPU 210A coupled to mirror accelerator circuitry 202A. In some instances, off-chip memory 205 may contain multiple regions containing content associated with an application to be executed by CPU 210A. In such instances, secondary bootloader 280 may use configuration information to configure mirror accelerator circuit 202A, specifying the start address, size, etc., of different content regions of off-chip memory 205 associated with CPU 210A. Similarly, secondary bootloader 280 may use configuration information to configure mirror accelerator circuit 202B, specifying the start address, size, etc., of content region 275 associated with CPU 210B coupled to mirror accelerator circuit 202B. In some instances, off-chip memory 205 may contain multiple regions containing content associated with an application to be executed by CPU 210B. In such instances, secondary bootloader 280 may use configuration information to configure mirror accelerator circuit 202B, specifying the start address, size, etc., of different content regions of off-chip memory 205 associated with CPU 210B.

[0039] In some instances, the configuration information provided to the mirror accelerator circuit 202 by the secondary bootloader 280 also specifies the target address of the mirrored content in shared memory 235 and / or local memory 220. For example, the configuration information provided to the mirror accelerator circuit 202A by the secondary bootloader 280 may specify the target address of shared memory 235 or local memory 220A, and the mirror accelerator circuit 202A will mirror the content area 270 associated with CPU 210A to the target address. In instances where the off-chip memory 205 contains multiple areas containing content associated with an application to be executed by CPU 210A, the configuration information provided to the mirror accelerator circuit 202A by the secondary bootloader 280 may specify different target addresses of shared memory 235 and / or local memory 220A, and different areas of the off-chip memory 205 will be mirrored to the different target addresses. Similarly, the configuration information provided to the mirroring accelerator circuit 202B by the secondary bootloader 280 can specify the target address of the shared memory 235 or the local memory 220B, etc., and the mirroring accelerator circuit 202A will mirror the content area 275 associated with the CPU 210A to the target address, etc. In an instance where the off-chip memory 205 contains multiple areas containing content associated with the application to be executed by the CPU 210B, the configuration information provided to the mirroring accelerator circuit 202B by the secondary bootloader 280 can specify different target addresses for the shared memory 235 and / or the local memory 220B, etc., and different areas of the off-chip memory 205 will be mirrored to the different target addresses, etc.

[0040] In the aforementioned examples, the secondary bootloader 280 is responsible for providing configuration information to the mirror accelerator circuit 202 to configure it, thereby mirroring external content (e.g., code and data) from off-chip memory 205 to internal memory, such as shared memory 235 and / or local memory 220. However, in some examples, one or more applications executed by CPU 210 may be responsible for providing configuration information to one or more of the mirror accelerator circuits 202 to configure them, thereby mirroring external content (e.g., code and data) from off-chip memory 205 to internal memory. In some examples, a combination of the secondary bootloader 280 and one or more applications executed by CPU 210 may be responsible for providing configuration information to one or more of the mirror accelerator circuits 202 to configure them, thereby mirroring external content (e.g., code and data) from off-chip memory 205 to internal memory.

[0041] In some instances, after the mirror accelerator circuit 202 is configured by the secondary bootloader 280, the mirror accelerator circuit 202 begins mirroring the contents of off-chip memory 205 to shared memory 235 and / or local memory 220. Furthermore, the mirror accelerator circuit 202 intelligently directs transactions from CPU 210 to off-chip memory 205 or internal memory (e.g., shared memory 235, local memory 220, etc.) depending on the state of the content mirroring.

[0042] For example, mirror accelerator circuit 202A can be configured to copy one or more regions of off-chip memory 205 to shared RAM 220A and / or local RAM 235 based on configuration information provided by bootloader 280. Mirror accelerator circuit 202A can then determine that a transaction from CPU 210A (or more generally, processor circuit 210A) is associated with a memory address contained in the first region (e.g., region 265) of the off-chip memory 205 to be copied to shared RAM 220A and / or local RAM 235. Mirror accelerator circuit 202A can then direct the transaction to either off-chip memory 205 or shared RAM 220A and / or local RAM 235 based on whether the copying of the first region (e.g., region 265) of off-chip memory 205 to shared RAM 220A and / or local RAM 235 has been completed.

[0043] Similarly, the mirror accelerator circuit 202B can be configured to copy one or more other regions of the off-chip memory 205 to the shared RAM 220B and / or local RAM 235 based on configuration information provided by the bootloader 280. The mirror accelerator circuit 202B can then determine that a transaction from the CPU 210B (or more generally, the processor circuit 210B) is associated with a memory address contained in the first of those other regions of the off-chip memory 205 to be copied to the shared RAM 220B and / or local RAM 235 (e.g., region 270). The mirror accelerator circuit 202B can then direct the transaction to either the off-chip memory 205 or the shared RAM 220B and / or local RAM 235 based on whether the copying of the first of those other regions of the off-chip memory 205 (e.g., region 270) to the shared RAM 220B and / or local RAM 235 has been completed.

[0044] Figure 3 It shows Figure 2 Other example operations of one of the mirror accelerator circuits 202 (e.g., mirror accelerator circuit 205A). However, Figure 2 Any of the mirror accelerator circuits 202, such as mirror accelerator circuit 205B, can perform similar operations. (Steering) Figure 3 The mirror accelerator circuit 202A is configured to copy (or mirror) area 265 of off-chip memory 205 to shared RAM 235 based on configuration information provided by bootloader 280. In the illustrated example, bootloader 280 also causes the mirror accelerator circuit 202A or memory controller circuit 240 of MCU 200 to copy area 305, which contains initialized read / write data associated with area 265, to shared RAM 235 during the boot of MCU 200.

[0045] After initiating a copy (or mirroring), the mirroring accelerator circuit 202A then determines that an example transaction 310 (e.g., instruction or data access transaction 310) from the CPU 210A (or more generally, processor circuit 210A) is associated with a memory address contained in off-chip memory 205 in region 265 to be copied to shared RAM 235. The mirroring accelerator circuit 202A then directs transaction 310 to either off-chip memory 205 or shared RAM 220A based on whether the copy from region 265 of off-chip memory 205 to shared RAM 235 has been completed.

[0046] In the illustration, the mirror accelerator circuit 205A is configured to determine that the copying of region 265 of off-chip memory 205 to shared RAM 235 has been completed (by...). Figure 3 After the directed line 315 (shown in the diagram) is executed, transaction 310 is directed to shared RAM 235. However, the mirror accelerator circuit 205A is configured to determine that the copy from region 265 of off-chip memory 205 to shared RAM 235 has not yet been completed (by...). Figure 3 After the directed line 320 (shown in the diagram), transaction 310 is directed to off-chip memory 205. (Note that in some instances, mirror accelerator circuitry 202A is configured to copy region 265 of off-chip memory 205 to local memory 220A of CPU 210. In such instances, mirror accelerator circuitry 202A directs transaction 310 to local memory 220A after determining that the copy from region 265 of off-chip memory 205 to local memory 220A has been completed.)

[0047] like Figure 3 As shown in the example, the mirror accelerator circuit 202A can be configured such that (e.g., by the memory controller circuit 240) at least one of authentication or error correction is performed on the contents of region 265 of off-chip memory 205 copied to shared RAM 235 (or local RAM 220A). Furthermore, as Figure 3As shown in the example, the mirror accelerator circuit 202A can be configured to perform address translation on transaction 310 before directing transaction 310 to off-chip memory 205. However, in some instances, the mirror accelerator circuit 202A can be configured to perform address translation on transaction 310 before directing transaction 310 to shared RAM 235 (or local RAM 220A).

[0048] Figure 4 It shows Figure 2 A block diagram of an example embodiment of one of the mirror accelerator circuits 202 (e.g., mirror accelerator circuit 202A). However, Figure 2 Any of the mirror accelerator circuits 202, such as mirror accelerator circuit 205B, can be implemented similarly. (Turning) Figure 4 The illustrated example of the mirror accelerator circuit 202A includes an example direct memory access (DMA) circuit 405 configured to copy the contents of off-chip memory (e.g., off-chip memory 205) to the device's internal memory, such as the local RAM 220A and / or shared RAM 235 of the MCU 200. In some instances, the off-chip memory is external to the device. The illustrated example of the mirror accelerator circuit 202A also includes an example transaction decoder circuit 410 configured to determine that a transaction (e.g., transaction 310) from the device's processor circuitry (e.g., CPU 210A of the MCU 200) is associated with a memory address contained in off-chip memory (e.g., off-chip memory 205) in a region (e.g., region 265) to be copied to internal memory (e.g., local RAM 220A and / or shared RAM 235). In the illustrated example, the transaction decoder circuit 410 directs the transaction to either off-chip memory or internal memory based on whether the DMA copy from the off-chip memory region to internal memory has been completed.

[0049] For example, after determining that the DMA copy from region 265 of off-chip memory 205 to internal memory (e.g., local RAM 220A and / or shared RAM 235) has been completed, the transaction decoder circuit 410 directs the transaction to internal memory (e.g., local RAM 220A and / or shared RAM 235). However, after determining that the DMA copy from region 265 of off-chip memory 205 to internal memory (e.g., local RAM 220A and / or shared RAM 235) has not yet been completed, the transaction decoder circuit 410 directs the transaction to off-chip memory 205. In some instances, the transaction decoder circuit 410 performs address translation on the transaction before directing it to internal memory (e.g., local RAM 220A and / or shared RAM 235). In some instances, the transaction decoder circuit 410 performs address translation on the transaction before directing it to off-chip memory 205.

[0050] In the illustrated example, DMA circuit 405 is configured to copy region 265 of off-chip memory 205 to local RAM 220A and / or shared RAM 235 based on example configuration information 415 provided by a bootloader (e.g., bootloader 280) stored in off-chip memory 205. In the illustrated example, configuration information 415 specifies at least one of the start address 420 of region 265 of off-chip memory 205, the end address of region 265 of off-chip memory 205, or the size 425 of region 265 of off-chip memory 205, and the start address 430 of the internal memory (e.g., local RAM 220A and / or shared RAM 235) to which region 265 of off-chip memory 205 is to be copied (e.g., mirrored). In the illustrated example, mirroring accelerator circuit 202A and... Specifically, DMA circuit 405 updates the configuration information 415 of region 265 with a current copy size 435 indicating the amount of region 265 that has been copied (e.g., mirrored) and a region control field 440 indicating the mirroring status of region 265 (e.g., not started, started, complete / done, etc.). In the illustrated example, mirroring accelerator circuit 202A uses the current copy size 435 and / or the region control field 440 to determine how to direct incoming transaction 310 from CPU 210A.

[0051] In some instances of the mirror accelerator circuit 202A, multiple regions of off-chip memory 205 are copied (e.g., mirrored) to internal memory (e.g., local RAM 220A and / or shared RAM 235). In such instances, configuration information 415 specifies at least one of the following: (i) the corresponding start and end addresses of the regions of off-chip memory 205, or (ii) the corresponding start address and size of the regions of off-chip memory 205. In some such instances, configuration information 415 also specifies the corresponding start addresses of the internal memory (e.g., local RAM 220A and / or shared RAM 235) to which the multiple regions of off-chip memory 205 are to be copied (e.g., mirrored). In some instances, the execution of bootloader 280 (e.g., by CPU 210A) causes DMA circuitry 405 to initiate a copy of a region of off-chip memory 205 to internal memory (e.g., local RAM 220A and / or shared RAM 235) based on configuration information 415, and causes the CPU 210A (or more generally, processor circuitry 210A) to initiate the execution of an application associated with the contents of the region of off-chip memory 205 before the copy of the region of off-chip memory 205 to internal memory (e.g., local RAM 220A and / or shared RAM 235) has been completed.

[0052] Figure 5 The text shows the representation of... Figure 2 A flowchart illustrating an example mirroring process 500 implemented by one of the mirror accelerator circuits 202 (e.g., mirror accelerator circuit 205A). However, Figure 2 Any of the mirroring accelerator circuits 202, such as mirroring accelerator circuit 205B, can perform the example mirroring process 500. Process 500 begins at block 505, where transaction decoder circuit 410 detects a transaction, such as transaction 310, from CPU 210A. At block 505, transaction decoder circuit 410 also determines the memory address and size associated with the detected transaction. At block 510, transaction decoder circuit 410 evaluates configuration information 415 stored in mirroring accelerator circuit 205A (e.g., start address 420 and size 425) to determine whether the detected transaction is contained in a region to be mirrored by mirroring accelerator circuit 205A, also known as a tracking region. If the detected transaction is not contained in the tracking region (corresponding to the "No" branch from block 510), then at block 515, transaction decoder circuit 410 directs the transaction to internal memory (e.g., local RAM 220A and / or shared RAM 235).

[0053] However, if the detected transaction is contained within the trace area (corresponding to the "Yes" branch from box 510), then at box 520, the transaction decoder circuit 410 evaluates the configuration information 415 (e.g., current copy size 435 and / or area control field 440) to determine whether the DMA circuit 405 has completed copying (e.g., mirroring) the trace area. If the DMA copying (e.g., mirroring) of the trace area is complete (corresponding to the "Yes" branch from box 520), then at box 515, the transaction decoder circuit 410 directs the transaction to internal memory (e.g., local RAM 220A and / or shared RAM 235). However, if the DMA copying (e.g., mirroring) of the trace area is not complete (corresponding to the "No" branch from box 520), then at box 525, the transaction decoder circuit 410 directs the transaction to off-chip memory (e.g., after performing address translation). The example process 500 then ends.

[0054] although Figures 2 to 5 The example illustrates an MCU 200 that includes a mirror accelerator circuit 202 to implement the intelligent external content mirroring disclosed herein, but the mirror accelerator circuit 202 is not limited thereto. Rather, the mirror accelerator circuit 202 can be included in any type of system, device, SoC, integrated circuit, etc., such as an MCU, MPU, etc.

[0055] The intelligent external content mirroring technologies disclosed in this article use software tools (such as software compilers, linkers, etc.) to generate... Figures 2 to 5 The example mirroring accelerator circuit 202 uses configuration information to perform intelligent movement of external content (e.g., code and data) from off-chip memory to internal memory. As mentioned above, some such software tools also employ intelligent layout algorithms to increase the likelihood of CPU transactions being associated with completed mirroring operations, resulting in a higher internal memory "hit" rate. For example, to help ensure that application content (e.g., code and data) is mirrored (e.g., copied) from external (e.g., off-chip) memory to internal memory (e.g., RAM) before being accessed by the CPU, at least some of the software tools disclosed herein (e.g., compilers, linkers, etc.) generate a program code layout in memory that is ordered based on the order in which function calls are executed during application code startup. In some instances, such software tools (e.g., compilers, linkers, etc.) may use static call graphs and dynamic code coverage to implement intelligent layout algorithms to arrange program code according to the order of function calls, thereby improving the internal memory "hit" rate by making content mirroring follow the function call order of the program code. For these reasons, smart layout algorithms can improve the boot speed of electronic devices by allowing faster code execution before image transfer is complete, thereby reducing the boot time of electronic devices.

[0056] Figures 6 to 8 This is a flowchart illustrating the operation of an example software tool that generates a program content layout in off-chip memory and generates associated configuration information for use with the software. Figures 2 to 5 The example mirror accelerator circuit 202 is used to perform intelligent movement of external content (e.g., code and data) from off-chip memory to internal memory. For example, Figure 6 It is a flowchart representing at least one of the following that can be implemented, instantiated, or executed by a programmable circuit system to execute example machine-readable instructions and / or example operations 600 that are code-annotated and constructed using the example software tools disclosed herein. Figure 6 Example machine-readable instructions and / or example operations 600 begin at block 605, where the example system configuration tool determines the memory layout of system 208, which includes MCU 200 and off-chip memory 205.

[0057] At box 610, the example compiler tool annotates and compiles the application code to be stored in off-chip memory 205. In some instances, the compiler tool annotates specific program code functions to be mirrored from off-chip memory 205 to the internal memory of system 208 (e.g., shared memory 235 and / or local memory 220). In some instances, the annotations are based on attributes (also called keywords) applied to function definitions and / or declarations automatically by the software compiler and / or based on user input. In some instances, annotations can be applied to both global and local functions.

[0058] Table 1 shows example syntax for comments applied to the source code by the example software compiler.

[0059]

[0060] Table 1

[0061] Table 2 shows the example syntax used by the example software compiler to apply the comments in Table 1 to the example function func3().

[0062]

[0063] Table 2

[0064] In Tables 1 and 2, the keyword “fast_local_copy” indicates that the program code associated with the function func3() will be mirrored from off-chip memory 205 to the internal memory of system 208 (e.g., shared memory 235 and / or local memory 220). In Tables 1 and 2, the variable “flcregionid” is used to define different possible regions into which the program code functions annotated with the keyword “fast_local_copy” will be grouped within off-chip memory 205.

[0065] Table 2 shows example syntax of comments applied to assembly code by the example software compiler.

[0066]

[0067] Table 3

[0068] At box 615, the example software linker constructs the compiled program code from box 610 based on the memory layout determined at box 605 to determine the program content (e.g., program image, such as code, data, etc.) of the application to be stored in off-chip memory 205. In some instances, the software linker uses attributes to collect function input segments into recorded output segments, which correspond to regions identified by the region variable flcregionid. Example segment names corresponding to different values ​​of the region variable flcregionid are provided in Table 4.

[0069]

[0070] Table 4

[0071] In some instances, at block 615, the software linker sorts the input segments based on a linear execution order provided by a call graph, such as a static function dependency call graph that identifies functions that can be invoked during startup. Furthermore, at block 615, the software linker aggregates the sorted input segments into region-specific output segments.

[0072] In some instances, at box 615, the linker software places the output section in off-chip memory specified by the linker command file. Example linker command files are provided in Table 5.

[0073]

[0074] Table 5

[0075] In some instances, at box 615, the software linker automatically generates corresponding start / stop symbols that can be used to program the FLC (or smart image) area. Examples of such symbols are provided in Table 6.

[0076]

[0077] Table 6

[0078] Figure 7 It is a flowchart representing at least one of the following that can be implemented, instantiated, or executed by a programmable circuit system to execute example machine-readable instructions and / or example operations 700 that are code-annotated and constructed using the example software tools disclosed herein. Figure 7 The example machine-readable instructions and / or example operations 700 contain those described above. Figure 6 Boxes 605 and 615 contain example machine-readable instructions and / or example operations 600. However, example machine-readable instructions and / or example operations 700 also include boxes 705 and 710. At box 705, the example software analyzer generates analysis data of program code and data to be stored in off-chip memory 205. At box 710, the compiler tools continue as described above. Figure 6 The intelligent layout algorithm is executed based on the analyzed data before the program code is annotated and compiled, as described in box 610.

[0079] Example machine-readable instructions and / or example operations 700 include software analyzer operations at block 705 and intelligent layout algorithms at block 710, the goal of which is to reduce CPU transaction misses to off-chip memory 205 (e.g., flash memory) due to incomplete mirroring operations to internal memory (e.g., shared memory 235 and / or local memory 220). In some instances, at block 705, the software analyzer supports this goal by generating analysis data based on an instrumented image of the program code executed with one or more test vectors (e.g., using trace and / or debugger tools). At block 710, the resulting analysis data can be used by a compiler or other layout tools to perform intelligent layout of the code, such that code functions are mirrored in the order they are executed during startup and / or based on execution frequency. By allowing DMA copying to begin earlier (e.g., several gigabytes), the program code is more likely to have been copied to RAM by the time it is executed by CPU 210, thereby reducing CPU transaction misses to off-chip memory 205 (e.g., flash memory). Furthermore, in the presence of asynchronous events, such as interrupt or error handling operations not in the boot code sequence, system 208 will still operate as expected, directing CPU transactions to off-chip memory 205 (e.g., corresponding to...). Figure 5 (Transition from box 520 to box 525).

[0080] Figure 8 This indicates that it can be used for implementation. Figure 7 The flowcharts for example machine-readable instructions and / or example operation 800 at boxes 705 and 710. Figure 8 Example machine-readable instructions and / or example operations 800 begin at box 805, where the software linker generates a static function dependency call graph for the application code being built. At box 810, the compiler or other layout tool performs a topological sort on the call graph based on analysis data provided by the analyzer tool described above, thereby obtaining the execution order of functions, function execution frequencies, etc., or any combination thereof. However, not all functions will actually be executed during system startup. For example, some functions may be less frequently executed error handlers, conditional interrupt routines, etc. Therefore, at box 815, the compiler or other layout tool uses analyzer data to identify those functions that execute in the normal startup sequence (and, in some instances, their execution frequencies). Then, at box 820, the compiler or other layout tool performs a smart layout algorithm, such as dynamic code convergence analysis, to prune the topologically sorted call graph based on actual function usage / calling, thereby placing functions that execute in the normal startup sequence at the beginning of the pruned graph and placing the remaining less frequently executed functions at the end of the graph. Alternatively or concurrently, in some instances, at box 820, the compiler or other layout tools prune the topologically ordered call graph to place functions in the pruned graph based on their execution frequency (e.g., placing more frequently executed functions closer to the beginning of the pruned graph). In some such instances, at box 820, the compiler or other layout tools also identify the target internal memory for placing a given function based on its execution frequency, e.g., placing more frequently executed functions in faster memory (e.g., TCM). The software compiler and software linker then use the pruned graph from box 820 to perform the remaining operations of boxes 610 and 615 described above to place application code in off-chip memory 205 based on the order of the pruned call graph.

[0081] In light of the foregoing, some example software tools disclosed herein are embodied in at least one non-transitory computer-readable medium containing computer-readable instructions to cause at least one processor circuit (e.g., example programmable circuit system 1112, described in further detail below) to aggregate input segments of program code into output segments, at least based on comments associated with input segments of program code. In some instances, the comments contain identifiers for identifying areas of off-chip memory. In some instances, the instructions of the software tool also cause one or more of at least one processor circuit to place output segments into corresponding areas of off-chip memory based on the area identifiers.

[0082] In some instances, the computer-readable instructions implementing the software tool also cause one or more of the processor circuits to sort the input segments of the program code based on a call graph.

[0083] In some instances, the computer-readable instructions implementing the software tool also cause one or more of the processor circuits to add comments to the sorted input segment of the program code.

[0084] In some instances, comments contain keywords that indicate that the input segment of the program code will be copied from off-chip memory to the device's internal memory.

[0085] In some instances, the computer-readable instructions implementing the software tool also cause one or more of at least one processor circuitry to analyze program code based on test data to determine analysis data, and to sort the input segments of the program code based on the analysis data. In some instances, the computer-readable instructions implementing the software tool also cause one or more of at least one processor circuitry to sort program data based on access patterns, such that more frequently accessed program data is copied to faster memory (e.g., TCM).

[0086] In some instances, the computer-readable instructions implementing the software tool also cause one or more of the processor circuits to add comments to the sorted input segment of the program code.

[0087] Figures 9 to 10 It shows that it can be contained in Figure 2 Example execution results of the mirror accelerator circuit 202 implemented in the example microcontroller unit 200. Figure 9 Example execution results 900 are shown, including example bootloader initialization time 905, image copy time 910, application start time 915, total boot time 920, and application execution speed 925 associated with the intelligent external content mirroring technology 930 disclosed herein, compared with XIP method 935 and image download method 940. From Figure 9 As can be seen, the intelligent external content mirroring technology 930 can achieve a total boot time 920 that meets the 30 ms target, while making the application execution speed 925 comparable to the speed of execution from internal memory. Figure 10 A similar example execution result of 1000 is shown.

[0088] The foregoing examples have described intelligent content mirroring technology based on an example mirroring accelerator circuit that intelligently mirrors content from external (e.g., off-chip) memory to internal memory. However, intelligent content mirroring technology is not limited to such examples. Instead, it can be applied to other contexts.

[0089] For example, the mirroring accelerator circuitry described herein can be adapted to move (e.g., mirror) code and / or data from slower internal memory (e.g., L2 RAM) to faster internal memory (e.g., TCM) in the context of runtime and / or dynamic overlay management. Using the mirroring accelerator circuitry described herein to perform such internal content mirroring can achieve performance improvements with very low overhead because the application or CPU utilizing the mirrored code and / or data does not need to check DMA completion before accessing the code and / or data. Instead, depending on whether the DMA mirroring of the code / data has been completed, the mirroring accelerator circuitry automatically directs the code / data transaction to the appropriate faster or slower internal memory.

[0090] As another example, the mirror accelerator circuitry described herein can be adapted to support data overlay applications that swap different blocks of code and / or data from flash memory to main memory. As described herein, using mirror accelerator circuitry to perform such data swapping reduces flash read accesses, thereby improving system reliability and reducing power consumption.

[0091] As another example, the mirroring accelerator circuitry described herein can be adapted to support over-the-air (OTA) updates, such as firmware OTA (FOTA) updates. For instance, a FOTA update allows firmware updates (e.g., code and / or data) to be received and stored in external flash memory. The mirroring accelerator circuitry described herein can be used to mirror firmware updates from external flash memory to internal or on-chip flash memory (or other flash memory) to provide the storage redundancy utilized by the FOTA process.

[0092] Figure 11 This is a block diagram of an example programmable circuit system platform 1100, which is configured to support... Figures 6 to 8 The example machine-readable instructions or example operations are implemented or instantiated in combination to implement the example software tools disclosed herein, thereby supporting the intelligent movement of external content from external (e.g., off-chip) memory to internal memory. The programmable circuit system platform 1100 can be used for, for example, servers, personal computers, workstations, self-learning machines (e.g., neural networks), mobile devices (e.g., cellular phones, smartphones, tablet computers, such as iPads). TM ), or any other type of computing or electronic device.

[0093] The programmable circuit system platform 1100 of the illustrated example includes a programmable circuit system 1112. The programmable circuit system 1112 of the illustrated example is hardware. For example, the programmable circuit system 1112 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers from any desired family or manufacturer. The programmable circuit system 1112 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices.

[0094] The programmable circuit system 1112 of the illustrated example includes local memory 1113 (e.g., cache, registers, etc.). The programmable circuit system 1112 of the illustrated example communicates with main memories 1114 and 1116 via bus 1118, the main memories including volatile memory 1114 and non-volatile memory 1116. Volatile memory 1114 may be implemented by one or more synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), or any other type of RAM device. Non-volatile memory 1116 may be implemented by flash memory or any other desired type of memory device, or a combination thereof. Access to the main memories 1114 and 1116 of the illustrated example is controlled by memory controller 1117. In some instances, the memory controller 1117 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired series or manufacturer, or any other type of circuit system to manage data flows to and from the main memories 1114, 1116.

[0095] The programmable circuit system platform 1100 of the illustrated example also includes an interface circuit system 1120. The interface circuit system 1120 can be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, or a Peripheral Component Interconnect High Speed ​​(PCIe) interface.

[0096] In the illustrated example, one or more input devices 1122 are connected to the interface circuitry 1120. The input devices 1122 allow a user (e.g., a human user, a machine user, etc.) to input one or a combination of data or commands into the programmable circuitry 1112. The input devices 1122 may be implemented as one or a combination of, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touchscreen, a trackpad, a trackball, a dot device, or a speech recognition system.

[0097] One or more output devices 1124 are also connected to the interface circuitry 1120 of the illustrated example. The output devices 1124 may be implemented, for example, by one or a combination of a display device (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, a flat panel display (IPS), a touchscreen, etc.), a haptic output device, a printer, or a speaker. Therefore, the interface circuitry 1120 of the illustrated example includes one or a combination of a graphics driver card, a graphics driver chip, or a graphics processor circuitry system such as a GPU.

[0098] The interface circuit system 1120 of the illustrated example also includes communication devices, such as one or a combination of a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, or network interface, to facilitate the exchange of data with external machines (e.g., any kind of computing device) via network 1126. Communication can be carried out via, for example, Ethernet connection, Digital Subscriber Line (DSL) connection, telephone line connection, coaxial cable system, satellite system, beyond-line-of-sight wireless system, line-of-sight wireless system, cellular telephone system, optical connection, etc.

[0099] The programmable circuit system platform 1100 of the illustrated example also includes one or more mass storage disks or devices 1128 for storing one or more of firmware, software, or data. Examples of such mass storage disks or devices 1128 include one or more magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices, such as flash memory devices and SSDs.

[0100] can be Figures 6 to 8 The machine-readable instructions 1132 implemented by the machine-readable instructions may be stored in one or a combination of the following locations: in a mass storage device 1128, in volatile memory 1114, in non-volatile memory 1116, or on at least one non-transitory computer-readable storage medium (e.g., a removable CD or DVD).

[0101] Figure 12 The diagram shows a block diagram of an example software distribution platform 1205, which is used to distribute software (e.g., ...) Figure 11Example machine-readable instructions 1132) are distributed to other hardware devices (e.g., one or more hardware devices owned or operated by a third party from the owner or operator of the software distribution platform). Example software distribution platform 1205 may be implemented by any computer server, data facility, cloud service, etc., capable of storing software and transferring it to other computing devices. The third party may be a customer of an entity that owns or operates software distribution platform 1205. For example, an entity that owns or operates software distribution platform 1205 may be software (e.g., ...). Figure 11 The example machine-readable instruction 1132 is provided by at least one of the developers, sellers, or licensors. A third party may be a consumer, user, retailer, OEM, etc., who purchases or licenses one or a combination of the software for use, resale, or sublicense. In the illustrated example, the software distribution platform 1205 includes one or more servers and one or more storage devices. The storage devices store the machine-readable instruction 1132, which may correspond to... Figures 6 to 8 Example machine-readable instructions, as described above. One or more servers of the example software distribution platform 1205 communicate with the example network 1210, which may correspond to any one or more of the Internet or any of the example networks described above. In some instances, the one or more servers respond to a request to transfer software to a requesting party as part of a commercial transaction. Payment for the delivery, sale, and / or licensing of the software may be processed by one or more servers of the software distribution platform and / or by a third-party payment entity. The servers enable one or more purchasers or licensors to download machine-readable instructions 1132 from the software distribution platform 1205. For example, this may correspond to... Figures 6 to 8 Software with example machine-readable instructions can be downloaded to example programmable circuit system platform 1100, which will execute machine-readable instructions 1132 to implement the example software tools described herein. In some instances, one or more servers of software distribution platform 1205 periodically distribute software (e.g., Figure 11 Example machine-readable instruction 1132) is used to provide, transmit, or force an update at least one of these actions to ensure that improvements, patches, updates, etc., are distributed and applied to the software at the end-user device. Although referred to as software above, distributed “software” may alternatively be firmware.

[0102] Although Figures 2 to 5 An example of implementing system 208 is shown, but Figures 2 to 5One or more of the elements, processes, or apparatuses shown may be combined, divided, rearranged, omitted, eliminated, or implemented in any other way. Furthermore, the example MCU 200, example mirror accelerator circuit 202, example off-chip memory 205, example CPU 210, example processor core 215, example local memory 220, example instruction cache 225, example data cache 230, example shared memory 235, example memory controller circuitry 240, example interconnect circuitry 245, example DMA circuitry 405, example transaction decoder circuitry 410, or more generally, example system 208, may be implemented by hardware alone, or by hardware in combination with software and firmware. Therefore, for example, any of the following: example MCU 200, example mirror accelerator circuitry 202, example off-chip memory 205, example CPU 210, example processor core 215, example local memory 220, example instruction cache 225, example data cache 230, example shared memory 235, example memory controller circuitry 240, example interconnect circuitry 245, example DMA circuitry 405, example transaction decoder circuitry 410, or more generally example system 208, may be implemented by a programmable circuitry system in conjunction with one or more machine-readable instructions (e.g., firmware or software), processor circuitry, analog circuitry, digital circuitry, logic circuitry, programmable processor, programmable microcontroller, graphics processing unit (GPU), digital signal processor (DSP), ASIC, programmable logic device (PLD), or field-programmable logic device (FPLD) (e.g., FPGA). Additionally, example system 208 may include, besides... Figures 2 to 5 The elements, processes, or devices shown may be one or more elements, processes, or devices other than or in place of the elements, processes, or devices shown, or may include more than one of any or all of the elements, processes, and devices shown.

[0103] Figures 6 to 8 The document illustrates flowcharts representing example machine-readable instructions or example operations, which can be executed by a programmable circuit system for implementing or instantiating at least one of the example software tools described herein to perform code annotation and construction. The example operations can be executed by a programmable circuit system for implementing or instantiating at least one of the example software tools described herein to perform code annotation and construction. The machine-readable instructions can be one or more executable programs or portions of one or more executable programs that can be executed by a programmable circuit system, such as those described below. Figure 11The example processor platform 1100 described illustrates a programmable circuit system 1112. In some instances, machine-readable instructions cause operations, tasks, etc., to be performed or executed in a real-world manner automatically. As used herein, "automatic" means without human intervention.

[0104] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as one or a combination of the following: cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical discs (e.g., Blu-ray discs, optical discs (CDs), digital versatile discs (DVDs), etc.), redundant arrays of independent disks (RAID), registers, ROM, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), or any other storage device or storage disk. The instructions of the non-transitory computer-readable and / or machine-readable media may be programmed or executed by a programmable circuit system located in one or more hardware devices, but the entire program or a portion thereof may alternatively be executed or instantiated by one or more hardware devices other than the programmable circuit system or embodied in dedicated hardware. Machine-readable instructions can be distributed across multiple hardware devices or executed by two or more hardware devices (e.g., server and client hardware devices). For example, client hardware devices can be executed by endpoint client hardware devices (e.g., hardware devices associated with human and / or machine users) or intermediate client hardware device gateways (e.g., radio access networks (RAN)) that facilitate communication between the server and endpoint client hardware devices. Similarly, non-transitory computer-readable storage media can contain one or more media. Furthermore, although references... Figures 6 to 8The flowcharts shown describe example programs, but many other methods of implementing the example software tools described herein can be used alternatively. For example, the execution order of the flowchart blocks can be changed, or some of the described blocks can be changed, eliminated, or combined. Additionally or alternatively, any or all of the flowchart blocks can be implemented by one or more hardware circuits (e.g., processor circuitry, discrete or integrated analog and / or digital circuitry, FPGA, ASIC, etc.) configured to perform the corresponding operations without executing software or firmware. Programmable circuitry can be distributed across different network locations or local to one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, XPU, etc.)). For example, programmable circuitry can be one or a combination of: a CPU or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers spanning a server rack, multiple processors distributed across one or more server racks, etc., or any combination thereof.

[0105] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, and encapsulated format. The machine-readable instructions described herein can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), bit streams (e.g., computer-readable bit streams, machine-readable bit streams, etc.)) or data structures (e.g., as parts of instructions, code, code representations, etc.), which can be used to create, manufacture, or generate machine-executable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located at the same or different locations within a network or network set (e.g., in the cloud, at an edge device, etc.). Machine-readable instructions may require one or more of the following to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, decapsulated, distributed, redistributed, compiled, etc., so that the machine-readable instructions can be directly read, interpreted, or executed by a computing device or other machine. For example, machine-readable instructions may be stored in multiple parts, which are individually compressed, encrypted, or stored on separate computing devices, and which, when decrypted, decompressed, or combined, form a set of one or more computer-executable or machine-executable instructions, the implementation of which together form one or more functions or operations of, for example, the program described herein.

[0106] In another instance, machine-readable instructions may be stored in a state where they can be read by a programmable circuit system, but libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., need to be added to execute the machine-readable instructions on a particular computing device or another device. In yet another instance, the machine-readable instructions or corresponding programs may need to be configured (e.g., storage settings, data inputs, recorded network addresses, etc.) before they can be executed wholly or partially. Therefore, as used herein, machine-readable, computer-readable, or machine-readable media may contain one or a combination of instructions and programs, regardless of the specific format or state of the machine-readable instructions or programs.

[0107] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0108] As mentioned above, Figures 6 to 8Example operations can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and non-transitory machine-readable storage media are explicitly defined as comprising any type of computer-readable storage device or disk that does not contain propagation signals and does not contain transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media include one or more optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, or any other storage device or disk in which information is stored for any duration (e.g., extended time period, permanent, transient, temporary buffer, cached information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined as comprising any physical (mechanical, magnetic, electromechanical, or electrical) hardware for retaining information for a period of time, but excluding the propagation of signals and the transmission medium. Examples of non-transitory computer-readable storage devices or non-transitory machine-readable storage devices include one or a combination of the following: any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disk, magnetic disk, disk drive, or redundant array of independent disks (RAID) system. As used herein, the term "device" refers to a physical structure, such as one or a combination of the following: mechanical, electromechanical, or electrical equipment, hardware, or circuitry that may or may not be configured by, or manufactured to execute, computer-readable instructions, machine-readable instructions, etc.

[0109] "Including" and "comprises" (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a technical solution uses any form of "including" or "comprises" (e.g., includes, encompassing, including, having, etc.) as a preposition or within any kind of technical solution description, additional elements, terms, etc., may be present without exceeding the scope of the corresponding technical solution or description. As used herein, the phrase "at least" is open-ended when used as a transitional term, for example, in a technical solution preposition, in the same way as the terms "including" and "comprises". The term "and / or" when used, for example, in the form of A, B, and / or C, refers to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, projects, objects, and things, the phrase “at least one of A and B” means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, projects, objects, and things, the phrase “at least one of A or B” means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the execution or implementation of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or implementation of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” means an implementation scheme that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0110] As used herein, singular references (e.g., "a(a)", "an(an)", "first", "second", etc.) do not exclude plurals. As used herein, the term "a(a)" or "an(an)" refers to one or more of the objects mentioned. The terms "a(a)" (or "an(an)"), "one or more", and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. Moreover, while individual features may be contained in different instances or technical solutions, these features may be combined, and inclusion in different instances or technical solutions does not imply that the combination of features is infeasible or disadvantageous at least one of them.

[0111] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the earth. The first part is above the second part if at least one portion of the second part is between the earth and the first part. Similarly, as used herein, the first part is "below" the second part when the first part is closer to the earth than the second part. As mentioned above, the first part may be above or below the second part, provided that one or more of the following conditions are met: there are other parts between them; there are no other parts between them; the first and second parts touch; or the first and second parts are not in direct contact with each other.

[0112] Notwithstanding the foregoing, in the case of at least one of a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, or an integrated circuit (IC) package containing a semiconductor die, referenced during fabrication or manufacturing, "above" does not refer to ground but to the underlying substrate on which the relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Therefore, as used herein, and unless the context otherwise states or implies, when a first component is located further away from the substrate on which both components are fabricated or otherwise provided (e.g., a semiconductor wafer) during fabrication / manufacturing than a second component, the first component (e.g., a transistor or other semiconductor device) within the semiconductor die is "above" the second component within the semiconductor die. Similarly, unless the context otherwise states or implies, when a first component within an IC package (e.g., a semiconductor die) is located further away from the printed circuit board (PCB) to which the IC package is to be mounted or attached, the first component is "above" the second component within the IC package during manufacturing. Semiconductor devices are typically used in an orientation different from their orientation during manufacturing. Therefore, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, or an integrated circuit (IC) package containing a semiconductor die, or a combination thereof, the definition of “above” in the preceding paragraph (i.e., the term “above” describes the relationship between two parts relative to the ground) may be governed by the context of use.

[0113] As used herein, a statement that any part (e.g., layer, film, region, area, or plate) is situated on another part in any manner (e.g., positioned thereon, located on thereon, placed thereon, or formed thereon, etc.) indicates that the referenced part is in contact with said other part, or that the referenced part is above said other part, with one or more intermediate parts positioned therebetween.

[0114] As used herein, unless otherwise indicated, a connection reference (e.g., attachment, coupling, connection, and engagement) may include an intermediate member between elements referenced by the connection reference between those elements or by at least one of the elements in relative movement. Therefore, a connection reference does not necessarily imply that two elements are directly connected or fixed to each other. As used herein, the statement that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.

[0115] Unless otherwise specifically stated, this document uses descriptive terms such as “first,” “second,” and “third” without intending or otherwise indicating priority, physical order, arrangement, or any sorting in the list, but merely as markers or at least one of arbitrary names to distinguish elements for ease of understanding of the described instance. In some instances, the descriptive term “first” may be used to refer to an element in the detailed description, while the same element may be referred to in the technical solution by different descriptive terms such as “second” or “third.” In such cases, such descriptive terms are used only to clearly identify those elements within the context of the discussion (e.g., within the technical solution), in which elements may otherwise share the same name.

[0116] As used herein, “approximately” and “about” modify their objects / values ​​to identify the potential for variation in real-world applications. For example, “approximately” and “about” may modify dimensions that may be imprecise due to at least one of manufacturing tolerances or other real-world defects. For example, unless otherwise specified herein, “approximately” and “about” may indicate that such dimensions are within tolerances of + / - 10%.

[0117] As used in this article, "largely real-time" means occurring in a near-instantaneous manner, taking into account the potential for computation time, transmission delays, and other latency in the real world. Therefore, unless otherwise specified, "largely real-time" means real-time plus 1 second.

[0118] As used herein, the phrase “communication” includes variations thereof, encompassing one or a combination of direct communication or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication or constant communication, but also includes selective communication at at least one of periodic intervals, predetermined intervals, non-periodic intervals or one-off events.

[0119] As used herein, a “programmable circuit system” is defined as comprising at least one of the following: (i) one or more special-purpose circuits (e.g., application-specific integrated circuits (ASICs)) that are structured to perform specific operations and comprise one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform one or more specific functions or operations and comprise one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include programmable microprocessors, such as: a central processing unit (CPU) that can execute a first instruction to perform one or more operations or functions; a field-programmable gate array (FPGA) that can be programmed with a second instruction to configure or structure at least one of the FPGA, thereby instantiating one or more operations or functions corresponding to the first instruction; a graphics processing unit (GPU) that can execute a first instruction to perform one or more operations or functions; a digital signal processor (DSP) that can execute a first instruction to perform one or more operations or functions; an XPU; a network processing unit (NPU); one or more microcontrollers that can execute a first instruction to perform one or more operations or functions; or an integrated circuit, such as an application-specific integrated circuit (ASIC). For example, an XPU can be implemented by a heterogeneous computing system that includes a variety of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination thereof) and configuration technologies (e.g., application programming interfaces (APIs)) that can distribute computing tasks to any or more of the various types of programmable circuit systems that are suitable and can be used to perform computing tasks.

[0120] As used herein, an integrated circuit / circuit system is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, FPGA, chip, microchip, programmable circuit system, semiconductor substrate coupling multiple circuit elements, system-on-a-chip (SoC), etc.

[0121] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0122] A device “configured” to perform a task or function may be configured during manufacturing by the manufacturer (e.g., by programming or hardwiring at least one of) to perform at least one of the following: perform the function, or may be configured (or reconfigured) by the user after manufacturing to perform the function or other additional or alternative functions. The configuration may be performed by at least one of firmware or software programming of the device, by at least one of the construction or layout of the device’s hardware components and interconnects, or a combination thereof.

[0123] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0124] In this specification and claims, the described "circuit system" may comprise one or more circuits. A circuit or device described herein as including certain components may alternatively be adapted to couple to those components used to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., one or a combination of resistors, capacitors, or inductors), or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., at least one of a semiconductor die or integrated circuit (IC) package) and may be adapted to couple to at least some of the passive elements or sources during or after manufacturing, for example, by at least one of an end user or a third party, to form the described structure.

[0125] The circuits described herein can be reconfigured to include the replaced components, thereby providing functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in at least one of series or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. While some elements in the described examples are included in the integrated circuit and others are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features shown as outside the integrated circuit may be included in the integrated circuit, and some features shown as inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are at least one of the following: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; or (iv) incorporated in / on the same printed circuit board.

[0126] The use of the phrase “ground” in the foregoing description includes at least one of chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, or any other form of grounding connection applicable to or suited to the teachings of this specification. Unless otherwise stated, “about,” “approximately,” or “generally” preceding a value indicates + / - 10% of said value, or, if the value is zero, a reasonable range of values ​​near zero.

[0127] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

[0128] Based on the foregoing, it should be understood that example systems, apparatuses, articles, and methods for implementing intelligent movement of external content from off-chip memory to internal memory have been described. The described systems, apparatuses, articles, and methods improve the efficiency of computing devices by mirroring application content from off-chip memory to internal memory, allowing program execution to begin almost immediately without waiting for the mirroring operation to complete. This intelligent content mirroring reduces the total boot time of devices with application code and data stored in off-chip memory, while achieving application execution speeds comparable to execution from internal memory. Furthermore, such intelligent content mirroring supports in-situ execution of program code from off-chip memory even before the mirroring of the program code is complete. The described systems, apparatuses, articles, and methods also relate to one or more improvements in the operation of machines such as computers or other electronic, electromechanical, or mechanical devices.

[0129] Other examples and combinations thereof include the following. Example 1 includes an accelerator circuit comprising: direct memory access (DMA) circuitry configured to copy the contents of off-chip memory to internal memory of a device, the off-chip memory being external to the device; and decoder circuitry configured to: determine that a transaction from processor circuitry of the device is associated with a memory address contained in a region of the off-chip memory to be copied to the internal memory; and direct the transaction to either the off-chip memory or the internal memory based on whether the DMA copy from the region of the off-chip memory to the internal memory has been completed.

[0130] Example 2 includes the accelerator circuitry according to Example 1, wherein the DMA circuitry is configured to copy the region of the off-chip memory to the internal memory based on configuration information provided by a bootloader stored in the off-chip memory, wherein the configuration information is used to specify at least one of the start address of the region of the off-chip memory and the end address of the region of the off-chip memory or the size of the region of the off-chip memory.

[0131] Example 3 includes the accelerator circuitry according to Example 2, wherein the configuration information is used to specify the starting address of the internal memory to which the region of the off-chip memory is to be copied.

[0132] Example 4 includes the accelerator circuitry according to Example 2, wherein the region is one of a plurality of regions of the off-chip memory to be copied to the internal memory, the configuration information being used to specify at least one of: (i) a corresponding start address and end address of the region of the off-chip memory, or (ii) the corresponding start address and corresponding size of the region of the off-chip memory, and the processor circuitry executing the bootloader is intended to: cause the DMA circuitry to initiate the copy of the region of the off-chip memory to the internal memory based on the configuration information; and cause the processor circuitry to initiate the execution of an application associated with the contents of the region of the off-chip memory before the copy of the region of the off-chip memory to the internal memory has been completed.

[0133] Example 5 includes an accelerator circuit according to any one of Examples 1 to 4, wherein the decoder circuit is configured to: direct the transaction to the internal memory after determining that the DMA copy from the region of the off-chip memory to the internal memory has been completed; and to direct the transaction to the off-chip memory after determining that the DMA copy from the region of the off-chip memory to the internal memory has not been completed.

[0134] Example 6 includes the accelerator circuitry according to Example 5, wherein the decoder circuitry is configured to perform address translation on the transaction before directing the transaction to the internal memory.

[0135] Example 7 includes an accelerator circuit according to Example 5 or Example 6, wherein the decoder circuit is configured to perform address translation on the transaction before directing the transaction to the off-chip memory.

[0136] Example 8 includes an apparatus comprising: internal memory; processor circuitry; and accelerator circuitry configured to: initiate a copy of a region of external memory to the internal memory based on configuration information provided by a bootloader, the bootloader being stored in the external memory; determine that a transaction from the processor circuitry is associated with a memory address contained in the region of the external memory; and direct the transaction to either the external memory or the internal memory based on whether the copy of the region of the external memory to the internal memory has been completed.

[0137] Example 9 includes the apparatus according to Example 8, wherein the processor circuitry is a first processor circuitry, the accelerator circuitry is a first accelerator circuitry, the region of the off-chip memory is a first region, the configuration information is first configuration information, and the apparatus includes: a second processor circuitry; and a second accelerator circuitry configured to: initiate a copy of the second region of the off-chip memory to the internal memory based on the second configuration information provided by the bootloader; determine that a transaction from the second processor circuitry is associated with a memory address contained in the second region of the off-chip memory; and direct the transaction to either the off-chip memory or the internal memory based on whether the copy of the second region of the off-chip memory to the internal memory has been completed.

[0138] Example 10 includes the apparatus according to Example 8, wherein the processor circuitry is a first processor circuitry, the accelerator circuitry is a first accelerator circuitry, the internal memory is a first internal memory, the area of ​​the off-chip memory is a first area, the configuration information is first configuration information, and the apparatus includes: a second internal memory; a second processor circuitry; and a second accelerator circuitry configured to: initiate a copy of the second area of ​​the off-chip memory to the second internal memory based on the second configuration information provided by the bootloader; determine that a transaction from the second processor circuitry is associated with a memory address contained in the second area of ​​the off-chip memory; and direct the transaction to either the off-chip memory or the second internal memory based on whether the copy of the second area of ​​the off-chip memory to the second internal memory has been completed.

[0139] Example 11 includes the apparatus according to Example 10, wherein the first internal memory includes a first tightly coupled memory associated with the first processor circuitry, and the second internal memory includes a second tightly coupled memory associated with the second processor circuitry.

[0140] Example 12 includes an apparatus according to any one of Examples 8 to 11, wherein the accelerator circuitry is configured to perform at least one of authentication or error correction on the contents of the region of the off-chip memory copied to the internal memory.

[0141] Example 13 includes an apparatus according to any one of Examples 8 to 11, wherein the accelerator circuitry is configured to: direct the transaction to the internal memory after determining that the copy from the region of the off-chip memory to the internal memory has been completed; and direct the transaction to the off-chip memory after determining that the copy from the region of the off-chip memory to the internal memory has not been completed.

[0142] Example 14 includes the apparatus according to Example 13, wherein the accelerator circuitry is configured to perform address translation on the transaction before directing the transaction to the internal memory.

[0143] Example 15 includes a system comprising: random access memory; processor circuitry; off-chip memory located outside the processor circuitry; and accelerator circuitry configured to: copy one or more regions of the off-chip memory to the random access memory based on configuration information provided by a bootloader; determine that a transaction from the processor circuitry is associated with a memory address contained in a first of the regions of the off-chip memory to be copied to the random access memory; and direct the transaction to the off-chip memory or one of the random access memories based on whether the copy from the first region of the off-chip memory to the random access memory has been completed.

[0144] Example 16 includes the system according to Example 15, wherein the bootloader is stored in the off-chip memory.

[0145] Example 17 includes a system according to Example 15 or Example 16, wherein the processor circuitry is a first processor circuitry, the one or more regions of the off-chip memory are one or more first regions associated with the first processor circuitry, and the off-chip memory includes one or more second regions associated with a second processor circuitry.

[0146] Example 18 includes the system according to Example 17, wherein the random access memory is a first random access memory, the accelerator circuit is a first accelerator circuit, the configuration information is first configuration information, and the system includes: a second random access memory; a second processor circuit; and a second accelerator circuit configured to: copy one or more second regions of the off-chip memory to one of the first random access memory or the second random access memory based on the second configuration information provided by the bootloader; determine that a transaction from the second processor circuit is associated with a memory address contained in the first of the second regions of the off-chip memory to be copied to the first random access memory or the second random access memory; and direct the transaction to one of the following based on whether the copy from the first of the second regions of the off-chip memory to the first random access memory or the second random access memory has been completed: the off-chip memory, or the first random access memory or the second random access memory.

[0147] Example 19 includes a system according to any one of Examples 15 to 18, wherein the accelerator circuitry is configured to perform address translation on the transaction before directing the transaction to the random access memory.

[0148] Example 20 includes a system according to any one of Examples 15 to 19, wherein the accelerator circuitry is configured to perform address translation on the transaction before directing the transaction to the off-chip memory.

[0149] Example 21 includes the system according to Example 15, further including a non-transitory computer-readable medium comprising computer-readable instructions for causing a computing device to perform at least the following operations: analyzing program code based on test data to determine analysis data; determining a call graph based on the program code and the analysis data; sorting input segments of the program code based on the call graph; aggregating the input segments of the program code into output segments based on annotations associated with the input segments of the program code, the annotations including area identifiers for identifying the first and second areas of the off-chip memory; and placing the output segments into the first and second areas of the off-chip memory based on the area identifiers.

[0150] Example 22 includes the system according to Example 21, wherein the call graph is a second call graph, and the instructions are used to cause the computing device to perform the following operations: determine a first call graph based on the program code; and prune the first call graph based on the analysis data to determine the second call graph.

[0151] Example 23 includes the system according to Example 22, wherein the instructions are used to cause the computing device to prune the first call graph based on at least one of the function execution order or function execution frequency specified in the analysis data.

[0152] Example 24 includes a non-transitory computer-readable medium comprising computer-readable instructions for causing at least one processor circuit to perform at least the following operations: aggregating the input segments of the program code into output segments based on annotations associated with the input segments of the program code, the annotations including a region identifier for identifying a region of off-chip memory; and placing the output segments into a corresponding region of the off-chip memory based on the region identifier.

[0153] Example 25 includes a non-transitory computer-readable medium according to Example 24, wherein the computer-readable instructions are used to cause one or more of the at least one processor circuitry to sort the input segments of the program code based on a call graph.

[0154] Example 26 includes a non-transitory computer-readable medium according to Example 25, wherein the computer-readable instructions are used to cause one or more of the at least one processor circuitry to add the annotation to the sorted input segment of the program code.

[0155] Example 27 includes a non-transitory computer-readable medium according to any one of Examples 24 to 26, wherein the annotation contains keywords indicating that the input segment of the program code will be copied from the off-chip memory to the internal memory of the device.

[0156] Example 28 includes a non-transitory computer-readable medium according to any one of Examples 24 to 27, wherein the computer-readable instructions are configured to cause one or more of the at least one processor circuitry to analyze the program code based on test data to determine analysis data, and to sort the input segments of the program code based on the analysis data.

[0157] Example 29 includes a non-transitory computer-readable medium according to Example 28, wherein the computer-readable instructions are used to cause one or more of the at least one processor circuitry to add the annotation to the sorted input segment of the program code.

[0158] The appended claims are hereby incorporated by reference in this detailed description. Although certain example systems, devices, articles, and methods have been described herein, the scope of this patent is not limited thereto. Rather, this patent covers all systems, devices, articles, and methods that fall fully within the scope of the claims of this patent.

Claims

1. An accelerator circuit, comprising: A direct memory access (DMA) circuit is configured to copy the contents of an off-chip memory to the internal memory of the device, the off-chip memory being external to the device; as well as The decoder circuit is configured as follows: The transaction from the processor circuitry of the device is associated with a memory address contained in the off-chip memory and to be copied to the internal memory. and Based on whether the DMA copy from the region in the off-chip memory to the internal memory has been completed, the transaction is directed to either the off-chip memory or the internal memory.

2. The accelerator circuit according to claim 1, The DMA circuitry is configured to copy the region from the off-chip memory to the internal memory based on configuration information provided by a bootloader stored in the off-chip memory. The configuration information is used to specify the start address of the region of the off-chip memory and at least one of the following: The end address of the region in the off-chip memory, or The size of the region of the off-chip memory.

3. The accelerator circuit of claim 2, wherein the configuration information is used to specify the starting address of the internal memory to which the area of ​​the off-chip memory is to be copied.

4. The accelerator circuit of claim 2, wherein the region is one of a plurality of regions of the off-chip memory to be copied to the internal memory, the configuration information being used to specify at least one of: (i) the corresponding start address and end address of the region of the off-chip memory, or (ii) the corresponding start address and corresponding size of the region of the off-chip memory, and the purpose of the processor circuit executing the bootloader is: This enables the DMA circuit to initiate a copy of the region from the off-chip memory to the internal memory based on the configuration information; and This causes the processor circuitry to initiate the execution of an application associated with the contents of the area in the off-chip memory before the copying from the area in the off-chip memory to the internal memory is completed.

5. The accelerator circuit of claim 1, wherein the decoder circuit is configured to: After determining that the DMA copy from the off-chip memory region to the internal memory has been completed, the transaction is directed to the internal memory; and After determining that the DMA copy from the region in the off-chip memory to the internal memory has not yet been completed, the transaction is directed to the off-chip memory.

6. The accelerator circuit of claim 5, wherein the decoder circuit is configured to perform address translation on the transaction before directing the transaction to the internal memory.

7. The accelerator circuit of claim 5, wherein the decoder circuit is configured to perform address translation on the transaction before directing the transaction to the off-chip memory.

8. An apparatus comprising: Internal memory; Processor circuitry; as well as The accelerator circuit is configured as follows: Based on the configuration information provided by the bootloader, a copy of a region from off-chip memory to the internal memory is initiated, wherein the bootloader is stored in the off-chip memory; Determine that the transaction from the processor circuitry is associated with a memory address contained in the region of the off-chip memory; and Based on whether the copy from the region in the off-chip memory to the internal memory has been completed, the transaction is directed to either the off-chip memory or the internal memory.

9. The apparatus of claim 8, wherein the processor circuit is a first processor circuit, the accelerator circuit is a first accelerator circuit, the region of the off-chip memory is a first region, the configuration information is first configuration information, and the apparatus comprises: Second processor circuit; and The second accelerator circuit is configured as follows: Based on the second configuration information provided by the bootloader, a copy of the second region of the off-chip memory to the internal memory is initiated; It is determined that the transaction from the second processor circuitry is associated with a memory address contained in the second region of the off-chip memory; and Based on whether the copy from the second region of the off-chip memory to the internal memory has been completed, the transaction is directed to either the off-chip memory or the internal memory.

10. The apparatus of claim 8, wherein the processor circuit is a first processor circuit, the accelerator circuit is a first accelerator circuit, the internal memory is a first internal memory, the area of ​​the off-chip memory is a first area, the configuration information is first configuration information, and the apparatus comprises: Second internal memory; Second processor circuit; and The second accelerator circuit is configured as follows: Based on the second configuration information provided by the bootloader, a copy of the second region of the off-chip memory to the second internal memory is initiated; The transaction from the second processor circuitry is determined to be associated with a memory address contained in the second region of the off-chip memory; and Based on whether the copy from the second region of the off-chip memory to the second internal memory has been completed, the transaction is directed to either the off-chip memory or the second internal memory.

11. The apparatus of claim 10, wherein the first internal memory includes a first tightly coupled memory associated with the first processor circuitry, and the second internal memory includes a second tightly coupled memory associated with the second processor circuitry.

12. The apparatus of claim 8, wherein the accelerator circuitry is configured to perform at least one of authentication or error correction on the contents of the region of the off-chip memory copied to the internal memory.

13. The apparatus of claim 8, wherein the accelerator circuit is configured to: After determining that the copy from the off-chip memory area to the internal memory has been completed, the transaction is directed to the internal memory; and After determining that the copy from the region of the off-chip memory to the internal memory has not yet been completed, the transaction is directed to the off-chip memory.

14. The apparatus of claim 13, wherein the accelerator circuitry is configured to perform address translation on the transaction before directing the transaction to the internal memory.

15. A system comprising: Random access memory; Processor circuitry; Off-chip memory, which is located outside the processor circuitry; as well as The accelerator circuit is configured as follows: Based on the configuration information provided by the bootloader, one or more regions of the off-chip memory are copied to the random access memory; The transaction from the processor circuitry is associated with a memory address in the first of the regions to be copied to the random access memory, contained in the off-chip memory. and Based on whether the copy from the first region of the off-chip memory to the random access memory has been completed, the transaction is directed to either the off-chip memory or the random access memory.

16. The system of claim 15, wherein the processor circuit is a first processor circuit, the one or more regions of the off-chip memory are one or more first regions associated with the first processor circuit, and the off-chip memory includes one or more second regions associated with the second processor circuit.

17. The system of claim 16, wherein the random access memory is a first random access memory, the accelerator circuit is a first accelerator circuit, the configuration information is first configuration information, and the system comprises: Second random access memory; The second processor circuit; as well as The second accelerator circuit is configured as follows: Based on the second configuration information provided by the bootloader, the one or more second regions of the off-chip memory are copied to one of the first random access memory or the second random access memory; The transaction from the second processor circuitry is associated with a memory address in the first of the second areas of the first random access memory or the second random access memory, which is contained in the off-chip memory and is to be copied to either the first random access memory or the second random access memory. and Based on whether the copying of the first in the second region of the off-chip memory to the first random access memory or the second random access memory has been completed, the transaction is directed to one of the following: the off-chip memory, or the first random access memory or the second random access memory.

18. The system of claim 15, further comprising a non-transitory computer-readable medium, the non-transitory computer-readable medium including computer-readable instructions for causing a computing device to perform at least the following operations: Based on the test data, the program code is analyzed to determine the analysis data; Based on the program code and the analysis data, the call graph is determined; Based on the call graph, the input segments of the program code are sorted; Based on comments associated with the input segments of the program code, the input segments of the program code are aggregated into output segments, the comments containing a region identifier for identifying the region of the off-chip memory; and Based on the area identifier, the output segment is placed into the area of ​​the off-chip memory.

19. The system of claim 18, wherein the call graph is a second call graph, and the instructions are used to cause the computing device to perform the following operations: Based on the program code, a first call graph is determined; and Based on the analysis data, the first call graph is pruned to determine the second call graph.

20. The system of claim 19, wherein the instructions are used to cause the computing device to trim the first call graph based on at least one of a function execution order or a function execution frequency specified in the analysis data.

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