A thermal simulation test wafer and its fabrication process

Abstract

This invention discloses a semiconductor testing technology field, specifically relating to a thermal simulation test wafer and its fabrication process. The thermal simulation test wafer includes at least one basic heating unit of a target size, which is cut from the wafer structure along a dicing line. Each basic heating unit is encapsulated based on a heating layer, a thermal sensing layer, a via layer, a pad layer, a passivation layer, and a bump layer arranged from bottom to top. This solution can simulate the thermal and physical properties of a real wafer, integrating heating and temperature measurement functions. It can be modularly combined to adapt to different testing scenarios, thereby significantly reducing testing costs, shortening development cycles, and improving the accuracy and reliability of test data.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and in particular to a thermal simulation test wafer and a fabrication process for the thermal simulation test wafer. Background Technology

[0002] In the semiconductor industry, with the continuous improvement of chip integration and power density, thermal management has become a core factor affecting product performance, reliability, and lifespan. Therefore, during the product design phase, it is essential to conduct precise thermal simulation tests on semiconductor chips, product packages, thermal adhesives, vapor chambers, and graphene thermal gradient materials to reproduce the actual heat dissipation characteristics of the product and verify the effectiveness of the heat dissipation solution.

[0003] The primary source of heat generation in chip products is the bare die, i.e., the individual functional unit after wafer dicing. The core requirement of thermal simulation testing is to accurately reproduce the dimensions, heat output, and other thermal and physical properties of the actual product, and to achieve precise temperature acquisition during the testing process. Currently, there are two main types of mainstream thermal simulation testing methods in the industry, both of which have significant technical shortcomings: Using real semiconductor products for thermal simulation testing is extremely costly. Real products are expensive to produce, and there is significant material loss per test. Furthermore, test failures can lead to the scrapping of both the chip and the packaging materials, resulting in high testing risks. In addition, real chips cannot integrate temperature sensors and can only rely on external infrared thermal imaging or point contact temperature measurement. This results in low accuracy of the test data, which cannot accurately reflect the chip junction temperature, and the test results have limited reference value.

[0004] Designing and manufacturing dedicated test wafers for different products is extremely incompatible. Each product requires a separate design, development, and fabrication of test wafers, resulting in long design cycles, high costs, and the need for redesign for each new project. This leads to high testing costs and significantly slows down product development and iteration cycles.

[0005] Furthermore, existing testing solutions not only struggle to balance versatility and accuracy but also fail to achieve integrated testing across multiple temperature domains and scenarios on a single carrier. For testing thermal adhesives and graphene thermal gradient materials, there is a lack of dedicated and efficient carriers, resulting in cumbersome testing processes and significant data deviations. Therefore, there is an urgent need in this field for a silicon-based thermal simulation testing solution that uses materials identical to those in real products, integrates heating and temperature measurement functions, and is highly versatile and cost-effective. This solution would enable efficient testing of semiconductor chips and thermal gradient materials, accelerate product iteration, and optimize thermal design. Summary of the Invention

[0006] In order to overcome the above-mentioned defects of the prior art, the present invention provides a thermal simulation test wafer and a method for thermal simulation test wafer, so as to solve the problems existing in the background art.

[0007] A thermal simulation test wafer, with silicon as the substrate material, includes at least one basic heating unit of a target size; The basic heating unit consists of a heating layer, a heat sensing layer, a via layer, a pad layer, a passivation layer, and a bump layer stacked sequentially from bottom to top. The heating layer is located above the substrate material and adopts a copper wire winding structure to simulate chip heating and match the heating power of real semiconductor products. The thermal sensing layer adopts a copper wire winding structure to obtain the heating temperature of the corresponding heating layer in real time. The via layer includes a first via portion and a second via portion that are insulated from each other. The first via portion is perpendicularly connected to the heating layer and the pad layer and forms an electrical path. The second via portion is perpendicularly connected to the thermal sensing layer and the pad layer and forms an electrical path. The pad layer is provided with multiple pads; The passivation layer has windows for exposing the pads; The bump layer includes multiple bumps protruding from the pads to achieve electrical connection with external testing equipment.

[0008] Furthermore, the wafer is arranged in a matrix with 1mm×1mm basic heating units, and each basic heating unit is surrounded by a dicing channel. The wafer is cut and assembled into test wafers of 1mm×1mm to 10mm×10mm.

[0009] Furthermore, the heating layer is formed based on serpentine or labyrinthine traces of a metallic material with a target resistivity.

[0010] Furthermore, the thermal sensing layer includes a first thermal sensing region, a second thermal sensing region, and a temperature sensor, wherein the first thermal sensing region and the second thermal sensing region are arranged in a mirror-symmetric manner with respect to the temperature sensor; The temperature sensor includes one of a PN junction diode, a transistor, or a thermistor.

[0011] Furthermore, a first dielectric isolation layer is provided between the heating layer and the thermal sensing layer, and a second dielectric isolation layer is provided between the thermal sensing layer and the via layer. Both the first and second dielectric isolation layers are made of silicon dioxide, thereby achieving interlayer electrical insulation and thermal conduction buffering.

[0012] Furthermore, the thickness of the copper wire in the heating layer is 2μm~5μm.

[0013] Furthermore, the pad layer includes at least four pads, wherein the first and second pads are used to provide operating current to the heating layer, and the third and fourth pads are used to connect to an external measurement circuit to read the signal of the thermal sensing layer.

[0014] The fabrication process of the thermal simulation test wafer includes the following steps: S1. Wafer dicing: According to the testing requirements of the product under test or thermal gradient material, the thermal simulation test wafer is diced into test dies of corresponding size along the 120um dicing track on the wafer. The test dies are composed of M×N basic heating units of 1mm×1mm, where M and N are both positive integers. S2. Equipment Connection: The cut test die is flip-chip soldered to the external test platform or substrate through the bump layer to complete the connection between the power supply line of the heating layer and the temperature signal acquisition line of the thermal sensing layer. S3. Parameter Adjustment: Based on the actual heating power of the product under test, adjust the voltage or current applied to the copper wire of the heating layer in the test die to match the heating power of the heating layer with that of the actual product. S4. Thermal simulation test: Apply working current to the heating layer to make it heat up to simulate the power consumption of the product under test. Monitor and test the temperature data of the bare die in real time through the thermal sensing layer and transmit it to the external measurement circuit. S5. Performance Evaluation: Based on the monitored temperature data, evaluate the thermal performance of the heat sink and heat dissipation materials in contact with the test die, or verify the thermal reliability of the semiconductor product package.

[0015] Furthermore, S4 can perform multiple thermal simulation tests under different temperature environments and test conditions to realize the thermal performance verification of a single wafer in multiple scenarios, with the temperature environment covering the temperature range of 0℃ to 200℃.

[0016] Furthermore, the wafer is used for integrated testing of single wafers under multiple temperature ranges and testing conditions, and is adapted for thermal performance simulation testing of semiconductor chips, thermal adhesives, and graphene thermal gradient materials.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This solution uses monocrystalline silicon material identical to that of the actual product, with physical parameters such as thermal conductivity and thermal diffusivity perfectly matching those of the actual chip. During transient thermal response testing, the testing unit provided by this invention can accurately capture the temperature rise curve during power loading, which is crucial for studying the thermal fatigue characteristics of power semiconductors.

[0018] 2. This solution achieves high-precision temperature measurement while eliminating the influence of contact resistance through the four-wire method, resulting in a temperature measurement accuracy of ±0.1℃. This level of accuracy is difficult to achieve with traditional thermal simulation methods, providing reliable experimental data for establishing more accurate chip thermal models (RC network models), and will strongly promote the overall technological progress of the semiconductor industry in the field of high-performance packaging heat dissipation.

[0019] 3. The standardized design of the pad and bump layers adopted in this solution allows the test chip to be automatically assembled using a chip mounter. This high compatibility with mass production processes enables thermal simulation testing to be extended from the laboratory stage to sampling verification at the production line, providing assurance for the product's full lifecycle thermal management.

[0020] 4. This solution can simulate the thermal and physical properties of real wafers, integrate heating and temperature measurement functions, and can be adapted to different testing scenarios through modular combination, thereby significantly reducing testing costs, shortening development cycles, and improving the accuracy and reliability of test data. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0022] Figure 1 This is a cross-sectional view of the thermal simulation test wafer according to an embodiment of this application; Figure 2 This is a schematic diagram of the basic heat dissipation unit according to an embodiment of this application; Figure 3 This is a layer structure diagram of the heating layer in an embodiment of this application; Figure 4 This is a layer structure diagram of the thermal sensing layer in an embodiment of this application; Figure 5 This is a layer structure diagram of the via layer in an embodiment of this application; Figure 6 This is a layer structure diagram of the pad layer in an embodiment of this application; Figure 7 This is a layer structure diagram of the passivation layer in an embodiment of this application; Figure 8 This is a layer structure diagram of the convex layer in an embodiment of this application; Figure 9 This is a schematic diagram of a thermal simulation test wafer of one size according to an embodiment of this application; Figure 10 This is a schematic diagram of a thermal simulation test wafer of another size according to an embodiment of this application; Figure 11 This is a schematic diagram of a thermal simulation test wafer of another size according to an embodiment of this application; In the figure, 1-heating layer, 2-thermal sensing layer, 3-via layer, 4-pad layer, 5-passivation layer, 6-bump layer, 201-first thermal sensing area, 202-second thermal sensing area, 203-temperature sensor, 301-first via, 302-second via, 501-electrical contact window, 601-bump. Detailed Implementation

[0023] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention. Example

[0024] See Figures 1 to 8 This solution discloses a thermal simulation test wafer, whose overall architecture is based on standardized semiconductor processing technology. Using silicon as the substrate material, the thermal simulation test wafer includes at least one basic heating unit of a target size. The basic heating unit is cut from the wafer structure along the dicing track. The basic heating unit is encapsulated based on a heating layer 1, a thermal sensing layer 2, a via layer 3, a pad layer 4, a passivation layer 5, and a bump layer 6 arranged from bottom to top.

[0025] In some embodiments, the target size of the basic heating unit is 1mm×1mm to 10mm×10mm.

[0026] like Figure 1 , Figure 2 As shown, the target size of the basic heating unit can be selected as 1mm × 1mm. The wafer structure of this application can include one basic heating unit, that is, the size of the wafer is 1mm × 1mm, or the wafer structure can include multiple basic heating units. For example, M × N basic heating units, where M = 1, 2, 3...., N = 1, 2, 3....... The wafer structure can be formed by cutting along the dicing lines on the carrier wafer according to the required size, for example, it can be cut into sizes such as 2×2, 3×3, 5×5, 6×2, 7×3, etc. By cutting the entire wafer into test wafers containing any number of basic units, it is possible to simulate real wafers of different sizes and powers. For example, the 1mm × 1mm wafer structure test can be used for extremely small wafers, such as heat dissipation materials for certain power devices, RF wafers, etc. A 10mm×10mm wafer structure can be used to simulate a medium-sized CPU or GPU wafer. By connecting all units in parallel, a high total heat dissipation power can be achieved. Alternatively, without dicing, the entire carrier wafer can be used as a test carrier. The entire wafer can be placed in a test socket, and all or some units can be powered on, heated, and their temperatures measured simultaneously. This enables wafer-level aging testing and allows for the evaluation of heat dissipation solutions for the entire wafer or large wafer array.

[0027] Specifically, heating layer 1 is used to simulate wafer heating, and thermal sensing layer 2 is used to obtain the heating temperature corresponding to heating layer 1. For example... Figure 5As shown, via layer 3 is located above thermal sensing layer 2, and its core function is to achieve vertical electrical signal interconnection. Via layer 3 contains multiple metallized vias (this application employs a first via portion 301 and a second via portion 302). These metallized vias are formed by deep-hole etching in an insulating dielectric layer and filling with conductive metal (such as electroless copper plating). Each metallized via precisely mates with the end of the underlying circuit, leading the power supply circuit of heating layer 1 and the signal circuit of thermal sensing layer 2 upwards to pad layer 4. This vertical interconnection technology avoids parasitic inductance and capacitance interference caused by large-scale cross-wiring in the same plane. The first via portion 301 of via layer 3 is used to vertically connect heating layer 1 and pad layer 4, forming an electrical path between them. The second via portion 302 is used to vertically connect thermal sensing layer 2 and pad layer 4, forming an electrical path between them. The first via portion 301 and the second via portion 302 are mutually insulated.

[0028] Multiple pads are provided on the pad layer 4, and windows are provided on the passivation layer 5 to expose the pads on the pad layer 4. The bump layer 6 includes multiple bumps 601 protruding from the pads. It is understood that in the wafer structure, the heating layer 1, the thermal sensing layer 2, and the pad layer 4 are metal layers located at different horizontal levels. The vias in the via layer 3 are vertical metal pillars filled with a metallic material, such as tungsten or copper, responsible for connecting them vertically in the Z-axis direction to form a three-dimensional circuit. By insulating the first via portion 301 connecting the heating layer 1 and the second via portion 302 connecting the thermal sensing layer 2, the heating circuit and the sensing circuit are ensured not to interfere with each other.

[0029] In some embodiments, refer to Figure 3 As shown, heating layer 1 is formed by serpentine or labyrinthine traces of a metallic material with a target resistivity. The target resistivity can be any desired resistance value such as 10Ω or 20Ω, and the metallic material can be copper, or a material doped with polycrystalline silicon or tantalum nitride. It is understood that, according to Joule's law P=V² / R, the heating power is inversely proportional to the resistance. If sufficient power (e.g., 1W) is to be generated with a relatively low, standard driving voltage (e.g., 3.3V or 5V), a sufficiently large resistance is required. By designing the metallic traces into a serpentine or labyrinthine shape, the total length of the conductors is maximized within a limited planar area.

[0030] Based on the formula R=ρ*L / A, it is known that since resistance is proportional to length, increasing the length directly leads to an increase in resistance, thus enabling high heat dissipation power even at low voltages. Furthermore, the heat sources of real wafers (such as CPU cores) are typically relatively uniform planar structures, rather than point heat sources. A simple sheet resistor or short straight wire will generate a very localized, non-uniform hot spot. Snake-shaped or labyrinthine traces can be evenly distributed throughout the basic heat-generating unit, such as a 1mm² area. When current flows through, heat is evenly released from the entire meandering path, forming a large-area, highly uniform heat source. This more realistically simulates the heating conditions of a real wafer, reduces the distortion rate of test data caused by non-uniform heat sources, and improves the overall heat dissipation performance evaluation of the heat dissipation material. Furthermore, the temperature sensor is located above heating layer 1.

[0031] If the heat from heating layer 1 is concentrated, the sensor will measure a localized, drastically fluctuating temperature, rather than the average junction temperature of the entire wafer. A serpentine or labyrinthine structure can distribute the heating wires more evenly, allowing heat to be conducted to the temperature sensor more smoothly. This structure improves the thermal coupling between the heat source and the overall wafer structure, making the data read by the temperature sensor more representative of the wafer's perceived temperature, thus improving the accuracy and reliability of the test.

[0032] Reference Figure 4 As shown, the thermal sensing layer 2 includes a first thermal sensing region 201, a second thermal sensing region 202, and a temperature sensor 203. The first thermal sensing region 201 and the second thermal sensing region 202 are arranged in a mirror-symmetric manner with respect to the temperature sensor 203.

[0033] In some embodiments, a first dielectric isolation layer is provided between the heating layer 1 and the thermal sensing layer 2, and a second dielectric isolation layer is provided above the thermal sensing layer 2.

[0034] Understandably, heating layer 1 is made of a metallic material with a target resistivity and is used to conduct current and generate heat. It needs to be connected to a power source and has a high potential. Thermal sensing layer 2 contains a temperature sensor 203, which is typically composed of diodes. This sensor needs to be connected to a measurement circuit to read voltage changes and thus obtain the temperature. If heating layer 1 and thermal sensing layer 2 are in direct contact, the large current and high voltage of heating layer 1 will flow directly into the diodes, potentially burning them out or causing severe signal crosstalk, rendering the temperature measurement ineffective. By setting a first dielectric isolation layer, the dielectric physically blocks direct contact between heating layer 1 and thermal sensing layer 2, ensuring that the two circuits are electrically independent and do not interfere with each other. For example, the first dielectric isolation layer can be silicon dioxide. Furthermore, thermal sensing layer 2 is used to measure heat conducted down from the wafer structure, rather than directly measuring the heat generated by the resistance wire of heating layer 1 itself. By setting the first dielectric isolation layer, the direct point-to-point conduction of heat from heating layer 1 to the temperature sensor 203 of thermal sensing layer 2 can be avoided, preventing falsely high local readings.

[0035] By setting a second dielectric isolation layer above the thermal sensing layer 2, it is ensured that the upper pad layer 4 and the lower thermal sensing layer 2 are electrically insulated, and an electrical path is formed through the via layer 3.

[0036] The size of the cutting channel is 100um-150um, and in this example, it is preferably 120um.

[0037] The thermal sensing layer 2 includes one of a PN junction diode, a transistor, or a thermistor.

[0038] like Figure 6 As shown, pad layer 4 is responsible for rearranging the fine signal lines led out from the lower layer into a pad array conforming to flip-chip package specifications. The metal linewidth of pad layer 4 is significantly larger than that of the lower layer traces, aiming to reduce lead resistance and parasitic heat generation in non-test areas. Pad layer 4 is configured with independent power pads, ground potential pads, and current input and voltage acquisition pads required for four-wire temperature measurement. Through reasonable spatial topology design, signal decoupling and fan-out are achieved. It includes at least four pads, of which the first and second pads are used to provide operating current to heating layer 1, and the third and fourth pads are used to connect to external measurement circuitry to read signals from thermal sensing layer 2.

[0039] like Figure 7As shown, passivation layer 5 covers the pad layer 4 and all etched structures beneath it. Passivation layer 5 is made of polyimide (PI) material and formed by spin coating. PI material has excellent thermal stability and mechanical toughness, serving not only as an electrical insulating medium but also as a stress buffer layer, effectively absorbing shear stress caused by thermal expansion coefficient (CTE) mismatch. Electrical contact windows 501 are formed on passivation layer 5 at specific locations corresponding to the pad layer 4 using photolithography.

[0040] like Figure 8 As shown, the bump layer 6 is located at the top of the test unit and serves as a physical bridge connecting the internal circuitry of the chip to the external test substrate. Multiple bumps 601 are grown within the electrical contact window 501 of the passivation layer 5 using an electroplating process. These bumps 601 are typically made of tin-silver-copper (SAC) alloy or gold balls, and their height and spacing strictly adhere to flip-chip standard specifications. The bumps 601 not only provide electrical pathways but also serve as primary heat conduction paths, simulating the heat dissipation behavior of a real chip in an actual package.

[0041] Example 1 (Preparation of an 8-inch thermal simulation test wafer) This embodiment prepares an 8-inch thermal simulation test wafer. The specific preparation process includes the following steps: Substrate preparation: Single-crystal silicon, consistent with real semiconductor products, is selected as the substrate material. An 8-inch wafer substrate is fabricated using semiconductor industry standard processes to ensure the material consistency between the wafer and the real product, laying the foundation for high fidelity in subsequent thermal simulation tests. Heating layer fabrication: A heating layer with copper wire winding structure is fabricated on the surface of the wafer substrate using an electroplating process. The copper wire winding is designed as a serpentine trace according to the target heating power. By adjusting the wire diameter and the number of winding turns of the copper wire, the resistivity is controlled so that the heating power of the heating layer can be accurately matched to the heating requirements of different real semiconductor products, thereby achieving accurate simulation of the chip heating characteristics. Fabrication of the first dielectric isolation layer: A first dielectric isolation layer of silicon dioxide is deposited on the surface of the heating layer. The thickness of the isolation layer is controlled by a vapor deposition process to achieve electrical insulation between the heating layer and the subsequent thermal sensing layer. At the same time, it buffers the heat conduction of the heating layer and avoids local heat concentration that may cause temperature measurement deviation. Fabrication of thermal sensing layer: A thermal sensing layer with copper wire winding structure is fabricated on the surface of the first dielectric isolation layer. A PN junction diode temperature sensor is integrated in the thermal sensing layer, and a first thermal sensing area and a second thermal sensing area with mirror symmetry are set on both sides of the sensor. The copper wire winding is electrically connected to the temperature sensor to realize real-time and uniform acquisition of the temperature of the heating layer. Fabrication of the second dielectric isolation layer: A second dielectric isolation layer made of silicon dioxide is deposited on the surface of the thermal sensing layer, with the same process as the first dielectric isolation layer, to achieve electrical insulation between the thermal sensing layer and the via layer, ensuring the independence of the temperature signal transmission of the thermal sensing layer; Via layer fabrication: A via layer is fabricated on the surface of the second dielectric isolation layer by etching and electroplating. The via layer includes a first via portion and a second via portion that are insulated from each other. Both are filled with copper metal to form a metal pillar structure. The first via portion penetrates the second dielectric isolation layer vertically and is electrically connected to the heating layer. The second via portion penetrates the second dielectric isolation layer vertically and is electrically connected to the thermal sensing layer, forming independent electrical paths respectively. Pad layer fabrication: A metal pad layer is fabricated on the surface of the via layer. The pad layer has four independent pads. The first pad and the second pad are electrically connected to the end of the first via that is away from the heating layer. The third pad and the fourth pad are electrically connected to the end of the second via that is away from the thermal sensing layer, thereby achieving the separation of power supply and temperature signal acquisition lines. Passivation layer fabrication: A passivation layer of polyimide is coated on the surface of the pad layer. A spin coating process is used to ensure uniform coating. Then, an etching process is used to open windows at the corresponding positions of each pad to expose the pad portion. This achieves insulation protection for the pad layer and the layers below it without affecting the subsequent electrical connection with the bump layer. Bump layer fabrication: At the window of the passivation layer, tin-based bumps are fabricated using a ball-planting process to form a bump layer. The bumps are directly electrically connected to the exposed pads. The size and height of the bumps are adapted to the flip-chip soldering requirements of external testing equipment to ensure a stable connection with external equipment. Unit Arrangement and Post-processing: The fabricated structure is arranged in a matrix uniformly on an 8-inch wafer substrate with 1mm×1mm basic heating units. Cutting channels are reserved around each basic heating unit. Finally, the wafer is subjected to electrolytic testing, cleaning, and drying to verify the stability of electrical connections of each layer, the uniformity of heating of the heating layer, and the accuracy of temperature measurement of the thermal sensing layer. After passing the test, the 8-inch thermal simulation test wafer is obtained.

[0042] Example 2 (Preparation of a 12-inch thermal simulation test wafer) This embodiment prepares a 12-inch thermal simulation test wafer, and its preparation process is basically the same as that in Example 1, with the only difference being: Using a 12-inch single-crystal silicon wafer substrate, the basic heating units are still arranged in a matrix uniformly in the 1mm×1mm specification, and the test bare chips that can be cut and combined cover the full size range of 1mm×1mm~10mm×10mm. Based on the size of the 12-inch wafer and the testing requirements, the overall arrangement density of the copper wire winding in the heating layer is adjusted to ensure the heating consistency of each basic heating unit. The arrangement of the via layer, pad layer, and bump layer is adjusted synchronously with the basic heating unit. The materials, manufacturing processes, and functional designs of the remaining layers are the same as in Example 1. The 12-inch thermal simulation test wafer after preparation can achieve the same thermal simulation test effect as the 8-inch wafer.

[0043] Example 3 (Application of thermal simulation test wafer cutting and testing) This embodiment uses the 8-inch thermal simulation test wafer prepared in Example 1 to test the thermal performance of the graphene heat dissipation material. The specific operation steps are as follows: S1. Wafer dicing: Based on the test sample size of the graphene heat dissipation material, the wafer is diced into 2mm×2mm test blanks along the dicing path on the wafer. Each test blank consists of 2×2 1mm×1mm basic heat dissipation units. S2. Equipment Connection: The cut test die is flip-chip soldered to the external thermal simulation test platform through the bump layer, so that the power supply line of the test platform is connected to the first and second pads of the pad layer, and the temperature acquisition line is connected to the third and fourth pads, thus completing the circuit construction for power supply of the heating layer and temperature signal acquisition of the thermal sensing layer. S3. Parameter Adjustment: Adjust the output parameters of the test platform according to the actual heat generation power of the semiconductor chip to be simulated, and adapt the copper wire winding resistivity of the heating layer in the test die to make the heat generation power of the heating layer completely match that of the real chip. S4. Thermal simulation test: Graphene heat dissipation material is uniformly attached to the surface of the test die. Working current is applied to the heating layer to make it heat up. The temperature data of the test die is collected in real time through the thermal sensing layer and transmitted to the external test platform. The test is carried out at ambient temperatures of -20℃, 25℃ and 150℃ respectively, and the temperature change curves and steady-state temperature under different temperature ranges are recorded. S5. Performance Evaluation: Based on temperature data in different temperature ranges, analyze the thermal conductivity and thermal resistance characteristics of graphene heat dissipation materials under different temperature environments to determine whether they meet the heat dissipation requirements of target semiconductor products, providing accurate data support for the selection and optimization of heat dissipation materials.

[0044] The thermal simulation test wafer of this invention is not limited to the above-mentioned 8-inch and 12-inch specifications. The combination of its basic heating units and the specific size of the dicing channels can be adjusted according to actual testing needs. It is applicable to the thermal performance testing of various semiconductor products and thermal gradient materials such as semiconductor chips, thermal adhesives, and heat spreaders. Any simple adjustments and applications based on the structural design of this invention are within the protection scope of this invention.

[0045] Examples of methods for thermal simulation testing of wafers based on different scenarios are as follows: I. Evaluating the performance of GPU air coolers 1) Cut a piece from the carrier wafer Figure 9 The 10mm×10mm thermal simulation test wafer shown contains 10×10 basic units.

[0046] 2) Package the thermal simulation test wafer onto a substrate simulating the size of a real GPU. Prepare two GPU air coolers to be tested (Cooler A and Cooler B). 3) Under the same ambient temperature, the packaged thermal simulation test wafer is tightly assembled with heat sink A and heat sink B in sequence.

[0047] 4) Apply a constant total power of 150W to all heating units of the thermal simulation test wafer to simulate high GPU load operation.

[0048] 5) Turn on the radiator fan and keep it at the same speed.

[0049] 6) The temperature sensor built into the wafer is tested through thermal simulation. The temperature is continuously monitored until it reaches a stable state, and the steady-state junction temperature is recorded at this point.

[0050] The test results show that, under the same power consumption and fan speed, the heatsink with a lower steady-state junction temperature has better heat dissipation performance.

[0051] II. Screening and Evaluation of Thermal Insulation Grease (TIM) Performance 1) Cutting uses one Figure 10 The 3mm×3mm thermal simulation test wafer shown is shown.

[0052] 2) Prepare three different brands or models of thermal grease (TIM1, TIM2, TIM3) and use a standard heatsink with known performance as a reference.

[0053] 3) Apply a standard thickness of TIM1 uniformly to the surface of the thermal simulation test wafer.

[0054] 4) Install the reference radiator and apply a constant heating power of 20W.

[0055] 5) After the temperature stabilizes, record the junction temperature Tj1.

[0056] 6) Thoroughly clean the surface of the thermal simulation test wafer and heat sink, repeat the above steps, and test TIM2 and TIM3 in sequence to obtain the junction temperatures Tj2 and Tj3.

[0057] The test results showed that the lower the junction temperature, the lower the thermal resistance and the better the thermal conductivity of the thermal grease.

[0058] Furthermore, the interfacial thermal resistance of each type of silicone grease can be quantitatively calculated using known power and measured temperature difference, providing valuable data for engineering applications.

[0059] III. Verifying the thermal reliability of wafer packaging 1) Cut one Figure 11 The 18mm×15mm thermal simulation test wafer shown was packaged with two different molding compounds (EMCA and EMCB) to make two test samples.

[0060] 2) Place both samples in a constant temperature chamber at the same ambient temperature.

[0061] 3) Apply the same constant power (e.g., 10W).

[0062] 4) Monitor and record the surface temperature of the package when both reach thermal steady state (using built-in sensors) and the time required to reach steady state.

[0063] Specifically, during the testing processes 2) to 4), no additional heat sink was installed, allowing the package to operate under natural convection.

[0064] The test results showed that the package with a lower steady-state temperature indicates that its molding compound and substrate have a better thermal conductivity path.

[0065] This example also allows for power cycling tests on the sample, which involves periodically switching the heating power on and off (e.g., powering on for 5 minutes and off for 5 minutes) to simulate the thermal cycling of the wafer during actual operation. Monitoring the drift of temperature sensor data after hundreds or thousands of cycles can assess the reliability of the package structure due to thermal stress aging.

[0066] This invention, through its innovative modular architecture and multi-layer functional integration technology, solves the core pain points that have long plagued the semiconductor thermal management field, such as high testing costs, poor versatility, and low data acquisition accuracy. This invention can serve not only as a verification platform for heat dissipation material research and development but also as an auxiliary tool for chip packaging design, possessing extremely high industrial application value and market potential.

[0067] The above description is only a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. Any equivalent modifications or changes made by those skilled in the art based on the content disclosed in the present invention should be included within the scope of protection set forth in the claims.

Claims

1. A thermal simulation test wafer, characterized by, A silicon substrate material includes at least one basic heating unit of a target size; The basic heating unit is sequentially stacked from bottom to top as a heating layer, a thermal sensing layer, a via layer, a pad layer, a passivation layer, and a bump layer; The heating layer is above the substrate material and adopts a copper wire winding structure to simulate chip heating and the heating power matches the heating requirement of a real semiconductor product; The thermal sensing layer adopts a copper wire winding structure to obtain the heating temperature of the corresponding heating layer in real time; The via layer includes a first via part and a second via part which are insulated from each other, the first via part vertically connects the heating layer and the pad layer and forms an electrical path, and the second via part vertically connects the thermal sensing layer and the pad layer and forms an electrical path; The pad layer is provided with a plurality of pads; The passivation layer is provided with a window for exposing the pads; The bump layer includes a plurality of bumps protruding from the pads to realize electrical connection with external test equipment.

2. The thermal simulation test wafer of claim 1, wherein, The basic heating units of 1mm×1mm are arranged in a matrix on the wafer, and each basic heating unit is provided with a cutting channel in the periphery, and the wafer is cut along the cutting channel and combined into a test die of 1mm×1mm-10mm×10mm.

3. The thermal simulation test wafer of claim 1, wherein, The heating layer is formed by a serpentine or labyrinth-shaped trace of a metal material with a target resistivity.

4. The thermal simulation test wafer of claim 1, wherein, The thermal sensing layer includes a first thermal sensing area, a second thermal sensing area, and a temperature sensor, the first thermal sensing area and the second thermal sensing area are arranged in mirror symmetry with respect to the temperature sensor; The temperature sensor includes one of a PN junction diode, a transistor, or a thermistor.

5. The thermal simulation test wafer of claim 1, wherein, A first dielectric isolation layer is arranged between the heating layer and the thermal sensing layer, and a second dielectric isolation layer is arranged between the thermal sensing layer and the via layer, both the first and second dielectric isolation layers are made of silicon dioxide to realize electrical insulation and thermal conduction buffering between layers.

6. The thermal simulation test wafer of claim 2, wherein, The copper wire thickness of the heating layer is 2-5μm.

7. The thermal simulation test wafer of claim 1, wherein, The pad layer includes at least four pads, the first and second pads are used to provide working current for the heating layer, and the third and fourth pads are used to be connected to an external measurement circuit to read the signal of the thermal sensing layer.

8. The process for preparing a thermal simulation test wafer according to any one of claims 1 to 7, wherein The method includes the following steps: S1, wafer cutting: according to the test requirements of the product to be tested or the thermal gradient material, the thermal simulation test wafer is cut into a test die of a corresponding size along the 120um cutting channel on the wafer, the test die is composed of M×N basic heating units of 1mm×1mm, and M and N are both positive integers; S2, equipment connection: the cut test die is flip-chip bonded with an external test platform or substrate through the bump layer to complete the connection of the power supply circuit of the heating layer and the temperature signal acquisition circuit of the thermal sensing layer; S3, parameter adjustment: according to the real heating power of the product to be tested, the voltage or current applied to the copper wire of the heating layer in the test die is adjusted to match the heating power of the heating layer with the real product; S4, thermal simulation test: working current is applied to the heating layer to heat it to simulate the power consumption of the product to be tested, and the temperature data of the test die is monitored and tested in real time by the thermal sensing layer and transmitted to the external measurement circuit. S5, performance evaluation: according to the monitored temperature data, the thermal performance of the heat sink in contact with the test die, the heat dissipation material, or the thermal reliability of the semiconductor product package is evaluated.

9. The preparation process of a thermal simulation test wafer of claim 8, wherein, The S4 can perform multiple thermal simulation tests under different temperature environments and different test conditions to realize single wafer multi-scene thermal performance verification, and the temperature environment covers a temperature range of 0-200 DEG C.

10. The thermal simulation test wafer of claim 1, wherein, The wafer is applied to integrated testing of single wafer multi-temperature range and multiple test conditions, and is suitable for thermal performance simulation testing of semiconductor chips, heat dissipation glue, and graphene thermal gradient materials.

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