A method and apparatus for measuring test conditions of semiconductor devices

Abstract

This invention discloses a method and apparatus for measuring test conditions of semiconductor devices, relating to the field of semiconductor device testing technology. Addressing problems such as understress testing, overstress failure, and fatigue failure in existing technologies, it employs a measurement device capable of independently powering the main circuit and control circuit of the device under test (DUT) and outputting electrical stress over a wide range. Test conditions are accurately extracted by characterizing the thermal properties of the DUT in the same heat flow mode as the specified test items. This avoids interference between the main circuit and control circuit, bypasses the thermal instability electrical stress range of the DUT, and prevents thermal instability failure, thus improving stability and accuracy. It effectively avoids understress testing, overstress failure, and fatigue failure, improving the reliability of semiconductor devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device testing technology, and specifically to a method and equipment for measuring semiconductor device test conditions. Background Technology

[0002] Early failure of semiconductor devices can paralyze systems and cause project failures, often at a huge cost in high-reliability applications. Therefore, in accordance with relevant standards such as GJB128B, eliminating devices with potential problems or manufacturing defects through aging tests is crucial for improving device reliability.

[0003] The essence of aging is to accelerate the elimination of defective devices rather than damage qualified devices. "Understressing" generally fails to achieve the purpose of aging, while "overstressing" easily damages devices. Qualified devices, after reaching thermal equilibrium (thermal steady state) under accurate test stress (test conditions), typically do not experience parameter degradation; instead, their parameters tend to stabilize. Experiments show that for every 10-12°C increase in the junction temperature of a semiconductor device, the rate of parameter degradation doubles, or in other words, the device's lifespan is halved—this is the so-called 10°C rule. Research has found that during device aging, high junction temperatures and thermal runaway not only fail to eliminate defective products but also introduce new potential failures. Therefore, accurate measurement of test conditions is crucial for improving device reliability.

[0004] Currently, the more popular methods for measuring aging conditions are the thermal resistance method and the interruption method:

[0005] 1. The thermal resistance method uses the formula... To check the junction temperature of the device under test (DUT) In the formula The power stress applied to the DUT, The steady-state thermal resistance from the junction to the reference point, The temperature is used as a reference point. Research has found that in measuring... At that time, the wicking effect of the thermocouple and positional error will produce an error of about 15%, which will be further increased when measured on thermal resistance testing equipment. It is difficult to make the thermal flow pattern (heat dissipation pattern) of the device consistent with the thermal flow pattern of the device during aging on the aging equipment. Therefore, the error of the aging conditions determined by the thermal resistance method may be higher than 25%, leading to understress aging or overstress failure.

[0006] 2. The interruption method involves intermittently applying a short-term test current during the aging process to measure the temperature-sensitive parameter (TSP) of the device under test (DUT) in real time and estimate the junction temperature. The electrical stress is then adjusted based on the estimated junction temperature. This method has several problems: ① After interruption and reapplication of electrical stress, the device needs time to recover to its original thermal steady state. Frequent interruptions result in the device being constantly in a thermal transient state, leading to a completely different stress state compared to continuous aging. ② Repeated interruptions and resumptions of electrical stress generate additional power cycling stress at interconnect interfaces such as bond points and solder layers, accelerating fatigue failure of even qualified devices. ③ After fatigue failure, the TSP of the device generally drifts, causing a systematic deviation in the estimated junction temperature, which in turn leads to deviations in subsequent electrical stress measurements, creating a vicious cycle. Therefore, the interruption method often does not measure the actual operating junction temperature of the device and also alters the aging process.

[0007] In addition, the output range of conventional testing equipment is relatively narrow, making it impossible to measure high reverse voltage devices (such as the reverse leakage stress of silicon Schottky diodes above 50 volts); moreover, when measuring the forward electrical stress of transistors, the output of the control terminal and the output of the main circuit are not independent, which means that the output of the control circuit and the main circuit cannot be freely set and are prone to mutual interference, making the transistors prone to "thermal instability" failure and with low accuracy. Summary of the Invention

[0008] The purpose of this invention is to provide a method and equipment for measuring test conditions of semiconductor devices, thereby improving the accuracy of test conditions, avoiding problems such as understress aging, overstress failure and fatigue failure, and thus improving the reliability of the devices.

[0009] To achieve the above objectives, this invention employs a measuring device capable of independently powering the main circuit and control circuit of the DUT and outputting electrical stress over a wide range. Under the same heat flow mode as the specified test items, the test conditions are accurately extracted by characterizing the thermal properties of the DUT. The specific technical solution is as follows:

[0010] A semiconductor device test condition measurement device, characterized in that it can independently power the main circuit and control circuit of the DUT and can output electrical stress over a wide range, specifically including:

[0011] The system includes a control module (including memory), a human-machine interface, a main power supply, a secondary power supply, a current source, and a junction temperature calibration and measurement module. The control module is communicatively connected to the human-machine interface, main power supply, secondary power supply, current source, and junction temperature calibration and measurement module. It controls the main power supply, secondary power supply, current source, and junction temperature calibration module based on commands input through the human-machine interface and electrical signals fed back from the main power supply, secondary power supply, current source, and temperature measurement module. The human-machine interface displays device status and allows command input. The main power supply is electrically connected to the DUT and supplies power to the DUT's main circuit. The secondary power supply is also electrically connected to the DUT and supplies power to the DUT's control circuit. The current source is electrically connected to the DUT and provides test current to the DUT's test circuit to measure the DUT's TSP (Total Power Spectrum). The temperature measurement module measures the DUT's case temperature during junction temperature calibration and measures the temperature of a reference point during DUT thermal characterization. The junction temperature calibration module is used for electrical calibration of the DUT's junction temperature.

[0012] Furthermore, the main power supply and the auxiliary power supply provide independent power to the DUT, which can avoid interference between the main circuit and the control circuit, avoid the thermal instability electrical stress range of the DUT, avoid thermal instability failure, and improve stability and accuracy.

[0013] Furthermore, the main power supply, auxiliary power supply, and current source are all DC programmable power supplies, and their output electrical stress range is higher than that of traditional measuring equipment, enabling a single measuring device to meet the testing needs of various devices without the need to replace the power supply.

[0014] A method for measuring test conditions of a semiconductor device, characterized by accurately extracting test conditions by characterizing the thermal properties of the device under test (DUT) in the same heat flow mode as the specified test items, specifically including the following steps:

[0015] Step 1: Install the DUT in the junction temperature calibration device, and establish the DUT junction temperature using electrical methods and measuring equipment. The functional relationship between TSP;

[0016] Step 2: Then install the DUT in the test fixture of the test equipment, and the DUT and the test fixture will form a fixed heat flow pattern;

[0017] Step 3: Electrically connect the DUT to the measuring device, and apply background thermal stress to the DUT at room temperature or using a heating device. Using measuring equipment, an electrical stress is applied to the DUT, causing the junction of the DUT to be heated to the test-specified temperature and reach thermal steady state under the combined effect of electrical stress and background thermal stress. The steady-state thermal resistance of the DUT junction to the reference point is then measured. ;

[0018] Step 4: Record the electrical stress, background thermal stress, and thermal resistance applied to the DUT in Step 3. The measurement data is used to extract the test stress required for the DUT to reach the specified junction temperature and thermal steady state.

[0019] Step 5: Disconnect the electrical connection between the DUT and the measuring equipment, then connect the DUT to the testing equipment. Apply the test stress extracted in Step 4 to the DUT as the test condition through the testing equipment to start the test.

[0020] In a preferred embodiment of the present invention, TSP is the junction voltage of the DUT, and the test stress required for the DUT to reach the specified junction temperature and thermal steady state is the power stress and the background thermal stress at room temperature.

[0021] In another preferred embodiment of the present invention, TSP is the junction voltage of the DUT, and the test stress required for the DUT to reach the specified junction temperature and thermal steady state is the current stress and the background thermal stress at room temperature.

[0022] In another preferred embodiment of the present invention, TSP is the on-resistance of the DUT, and the test stress required for the DUT to reach the specified junction temperature and thermal steady state is the power stress and the background thermal stress at room temperature.

[0023] In another preferred embodiment of the present invention, TSP is the saturation voltage of the DUT, and the test stress required for the DUT to reach the specified junction temperature and thermal steady state is the power stress and the background thermal stress at room temperature.

[0024] In the final preferred embodiment of the present invention, TSP is the junction voltage of the DUT, and the test stress required for the DUT to reach the specified junction temperature and thermal steady state is the power stress and the background thermal stress above room temperature. .

[0025] In step 2, the heat flow mode is a conventional heat dissipation mode used in this technical field.

[0026] In step 3, the reference point can be any position on the DUT, a position on the test fixture, or a position in the heating device that provides background thermal stress.

[0027] In steps 1, 3, and 5, the measuring device can be a semiconductor device test condition measuring device as described in this invention, or it can be other measuring devices with the same function as the test condition measuring device.

[0028] Compared with the prior art, the beneficial effects of this application are as follows:

[0029] 1. This invention employs a measuring device that can independently power the main circuit and control circuit of the DUT and output electrical stress over a wide range: ① It avoids interference between the main circuit and the control circuit; ② It avoids the electrical stress range of the DUT's thermal instability, thus preventing the DUT from failing due to thermal instability and improving measurement stability and accuracy; ③ A single measuring device can meet the testing needs of various DUTs without the need to replace the device.

[0030] 2. Test conditions are accurately extracted by characterizing the thermal properties of the DUT in the same heat flow mode as the specified test items. In other words, the test conditions are accurately extracted by characterizing the thermal properties of the DUT in the same heat flow mode in which the test is conducted. This improves accuracy, avoids problems such as understress testing, overstress failure, and fatigue failure, and ultimately improves the reliability of the device. Attached Figure Description

[0031] The specification of this invention application includes 11 drawings, which are described below:

[0032] Figure 1 This is a schematic diagram of the technical solution of this application;

[0033] Figure 2 This is a diagram illustrating the configuration of the measuring equipment used in this application;

[0034] Figure 3 This is a flowchart of the measurement method of this application;

[0035] Figure 4 This is the wiring diagram for measuring the diode test conditions in this application;

[0036] Figure 5 This is the wiring diagram for measuring the test conditions of the Zener diode in this application;

[0037] Figure 6 This is the wiring diagram for measuring the test conditions of the NPN transistor in this application;

[0038] Figure 7 Wiring diagram for the test conditions of the enhanced N-MOSFET of this application;

[0039] Figure 8 This is the wiring diagram for measuring the test conditions of the gallium nitride N-MOSFET in this application;

[0040] Figure 9 This is the wiring diagram for the IGBT test conditions of this application;

[0041] Figure 10 Wiring diagram for test conditions of the three-terminal fixed positive output voltage regulator of this application;

[0042] Figure 11This is the wiring diagram for measuring the test conditions of the Schottky diode in this application.

[0043] In the diagram: 1-DUT, 2-Measuring equipment, 3-Junction temperature calibration module, 4-Test equipment, 41-Test fixture, 201-Control module (including memory), 202-Human-machine interface, 211-Main power supply, 212-Auxiliary power supply, 221-Current source, 222-Temperature measurement module, ADJ-Adjustment terminal. - Test current. Detailed Implementation

[0044] The following is in conjunction with the appendix Figures 1-11 The preferred embodiments of the present invention will be described in further detail below. The specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0045] Example 1

[0046] like Figure 1 , 2 As shown, in the case of Figure 1 When the device under test (DUT1) shown is subjected to environmental testing, a semiconductor device test condition measuring device 2 is used to improve the accuracy of test conditions and the reliability of the device. Specifically, it includes:

[0047] The system includes a control module (including a memory) 201, a human-machine interface 202, a main power supply 211, an auxiliary power supply 212, a current source 221, a junction temperature calibration module 3, and a temperature measurement module 222. The control module 201 is communicatively connected to the human-machine interface 202, the main power supply 211, the auxiliary power supply 212, the current source 221, the junction temperature calibration module 3, and the temperature measurement module 222. It controls the main power supply 211, the auxiliary power supply 212, the current source 221, and the junction temperature calibration module 3 based on commands input from the human-machine interface and electrical signals fed back from the main power supply 211, the auxiliary power supply 212, the current source 221, and the temperature measurement module 222. The human-machine interface 202 displays the device status and receives command inputs. The main power supply 211 is electrically connected to the DUT1 and supplies power to the main circuit of the DUT1. The auxiliary power supply 212 is electrically connected to the DUT1 and supplies power to the control circuit of the DUT1. The current source 221 is electrically connected to the DUT1 and provides test current to the DUT1 test circuit. The temperature measurement module 222 is used to measure the TSP of DUT1 during junction temperature calibration and to measure the temperature of the reference point during the thermal characteristic characterization of DUT1. The junction temperature calibration module 3 is used to calibrate the junction temperature of DUT1 by electrical method.

[0048] Specifically, the main power supply 211 and the auxiliary power supply 212 provide independent power to the DUT1, which can avoid interference between the main circuit and the control circuit, avoid the thermal instability voltage and current range of the DUT1, avoid thermal instability failure, and improve stability and accuracy.

[0049] Specifically, the main power supply 211 is a DC programmable power supply with an output voltage range of 0–200V and an output current range of 0–200A. The auxiliary power supply 212 is a DC programmable power supply with an output voltage range of 0–50V and an output current range of 0–20A. The current source 221 is a DC programmable current source that outputs a test current. The range is 0–100 mA, which is greater than the range of traditional measuring equipment. This means that a single test condition measuring device 2 can meet the testing requirements of various devices without the need to replace the equipment.

[0050] Specifically, when measuring high voltage and high current DUT1, the main power supply 211 is generally used to power the main circuit of DUT1; when measuring low voltage and low current DUT1, the auxiliary power supply 212 is generally used to power the main circuit of DUT1.

[0051] Example 2

[0052] In this embodiment, DUT1 is a diode; and the test equipment 4 is a power aging equipment.

[0053] like Figure 1 , 3 As shown in Figure 4, in the context of... Figure 1 To improve the accuracy of aging conditions and the reliability of the device during the aging test of the DUT1 shown, a semiconductor device test condition measurement method is adopted, which specifically includes the following steps:

[0054] Step 1: Install DUT1 in junction temperature calibration module 3, and establish the junction temperature of DUT1 using electrical methods through measuring device 2. With junction voltage The functional relationship between them;

[0055] Step 2: After the junction temperature calibration is completed, the DUT1 is installed in the test fixture 41 of the test equipment 4, and the DUT1 and the test fixture 41 form a fixed heat flow pattern.

[0056] Step 3: Electrically connect DUT1 to measuring device 2. At room temperature, use measuring device 2 to apply a forward junction voltage to DUT1. and current Heat the junction of DUT1 to the test-specified 150°C (generally specified for silicon devices). ℃) or 175℃ (generally specified for silicon carbide devices 175~ (℃) and reach thermal steady state, measure the steady-state thermal resistance from the DUT1 junction to the reference point. ;

[0057] Step 4: Record the actions applied to DUT1 in Step 3. , and The measurement data was collected, and the power stress required for DUT1 to reach the specified junction temperature and achieve thermal steady state was extracted from it. ( equal Multiply );

[0058] Step 5: Disconnect the electrical connection between DUT1 and measuring device 2, then connect DUT1 to testing device 4. The power stress extracted in step 4 will be measured using testing device 4. The test was started by applying aging conditions to DUT1 and ended after 96 hours by removing the aging stress.

[0059] Example 3

[0060] like Figure 5 As shown, in this embodiment, DUT1 is a Zener diode; and the test equipment 4 is a power aging equipment.

[0061] The difference between this embodiment and Embodiment 2 is as follows:

[0062] Step 3: Connect DUT1 electrically to measuring device 2. At room temperature, apply reverse current to DUT1 using measuring device 2. (generally ≤ Rated value The junction of DUT1 is heated to the test-specified 150°C (generally specified for silicon devices). (℃) and reach thermal steady state, measure the steady-state thermal resistance from the DUT1 junction to the reference point. ;

[0063] Step 4: Record the actions applied to DUT1 in Step 3. and The measurement data was collected, and the electrical stress required for DUT1 to reach the specified junction temperature and thermal steady state was extracted from it. ;

[0064] Step 5: Disconnect the electrical connection between DUT1 and measuring device 2, then connect DUT1 to testing device 4. The electrical stress extracted in step 4 will be measured using testing device 4. The test was started by applying aging conditions to DUT1 and ended after 96 hours by removing the aging stress.

[0065] The other steps and methods are the same.

[0066] Example 4

[0067] like Figure 6 As shown, in this embodiment, DUT1 is a transistor; and the test equipment 4 is a power aging equipment.

[0068] The difference between this embodiment and Embodiment 2 is as follows:

[0069] Step 1: Install DUT1 in junction temperature calibration module 3, and establish the junction temperature of DUT1 using electrical methods through measuring device 2. With junction voltage The functional relationship between (the junction voltage between the base (B) and emitter (E) of an NPN transistor);

[0070] Step 3: Connect DUT1 electrically to measuring device 2. At room temperature, apply a positive collector voltage to DUT1 using measuring device 2. By adjusting the base voltage Heat the junction of DUT1 to the test-specified 150°C (generally specified for silicon devices). (℃) and reach thermal steady state, measure the steady-state thermal resistance from the DUT1 junction to the reference point. ;

[0071] Step 4: Record the actions applied to DUT1 in Step 3. collector current and The measurement data was collected, and the power stress required for DUT1 to reach the specified junction temperature and achieve thermal steady state was extracted from it. ( equal Multiply );

[0072] Step 5: Disconnect the electrical connection between DUT1 and measuring device 2, then connect DUT1 to testing device 4. The power stress extracted in step 4 will be measured using testing device 4. The aging conditions were applied to DUT1 to start the test, and the aging stress was removed after 160 hours (240 hours for PNP type) to end the test.

[0073] The other steps and methods are the same.

[0074] Example 5

[0075] like Figure 7 As shown, in this embodiment, DUT1 is an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET); and the test equipment 4 is a power aging equipment.

[0076] The difference between this embodiment and Embodiment 2 is as follows:

[0077] Step 1: Install DUT1 in junction temperature calibration module 3, and establish the junction temperature of DUT1 using electrical methods through measuring device 2. With junction voltage The functional relationship between (the junction voltage between the source and drain of an N-channel MOSFET);

[0078] Step 3: Electrically connect DUT1 to measuring device 2. At room temperature: Apply a positive drain voltage to DUT1 within the thermal stability voltage range of DUT1 using measuring device 2. By adjusting the gate voltage Heat the junction of DUT1 to the test-specified 150°C (generally specified for silicon devices). ℃) or 175℃ (generally specified for silicon carbide devices 175~ (℃) and reach thermal stability; or apply a positive gate voltage to DUT1 within the thermal stability current range of DUT1 using measuring device 2. By adjusting the drain voltage Heat the junction of DUT1 to the test-specified 150°C (generally specified for silicon devices). ℃) or 175℃ (generally specified for silicon carbide devices 175~ (℃) and reached thermal steady state. The steady-state thermal resistance from the DUT1 junction to the reference point was measured. ;

[0079] Step 4: Record the actions applied to DUT1 in Step 3. Drain current and The measurement data was collected, and the power stress required for DUT1 to reach the specified junction temperature and achieve thermal steady state was extracted from it. ( equal Multiply );

[0080] Step 5: Disconnect the electrical connection between DUT1 and measuring device 2, then connect DUT1 to testing device 4. The power stress extracted in step 4 will be measured using testing device 4. The test was started by applying aging conditions to DUT1 and ended after 160 hours by removing the aging stress.

[0081] The other steps and methods are the same.

[0082] Example 6

[0083] like Figure 8 As shown, in this embodiment, DUT1 is an N-channel gallium nitride MOSFET; and the test equipment 4 is a power aging equipment.

[0084] The difference between this embodiment and embodiment 5 is as follows:

[0085] Step 1: Install DUT1 in junction temperature calibration module 3, and establish the junction temperature of DUT1 using electrical methods through measuring device 2. With on resistance The functional relationship between (the channel resistance between the drain D and the source S);

[0086] Step 3: Connect DUT1 to measuring device 2 electrically. At room temperature, use measuring device 2 to apply drain voltage to DUT1 in its fully open saturated conduction state. The junction of DUT1 is heated to the test-specified 200°C (generally specified as 175°C). (℃) and reach thermal steady state, measure the steady-state thermal resistance from the DUT1 junction to the reference point. ;

[0087] Step 5: Disconnect the electrical connection between DUT1 and measuring device 2, then connect DUT1 to testing device 4. The power stress extracted in step 4 will be measured using testing device 4. The test was started by applying aging conditions to DUT1 and ended after 168 hours by removing the aging stress.

[0088] The other steps and methods are the same.

[0089] Example 7

[0090] like Figure 9 As shown, in this embodiment, DUT1 is an insulated gate bipolar transistor (IGBT); and the test equipment 4 is a power aging equipment.

[0091] The difference between this embodiment and embodiment 4 is that:

[0092] Step 1: Install DUT1 in junction temperature calibration module 3, and establish the junction temperature of DUT1 using electrical methods through measuring device 2. With saturation voltage The functional relationship between (the saturation voltage drop between the emitter E and collector C when the IGBT is fully turned on);

[0093] Step 3: Connect DUT1 electrically to measuring device 2. At room temperature, apply collector-emitter voltage to DUT1 using measuring device 2. (Typically between 3 and 20V), by adjusting the gate-emitter voltage Heat the junction of DUT1 to the test-specified 150°C (generally specified for silicon devices). (℃) and reach thermal steady state, measure the steady-state thermal resistance from the DUT1 junction to the reference point. ;

[0094] Step 5: Disconnect the electrical connection between DUT1 and measuring device 2, then connect DUT1 to testing device 4. The power stress extracted in step 4 will be measured using testing device 4. The test was started by applying aging conditions to DUT1 and ended after 168 hours by removing the aging stress.

[0095] The other steps and methods are the same.

[0096] Example 8

[0097] In this embodiment, DUT1 is an integrated circuit IC; and the test equipment 4 is a power aging equipment.

[0098] The difference between this embodiment and Embodiment 2 is as follows:

[0099] Step 1: Install DUT1 in junction temperature calibration module 3, and establish the junction temperature of DUT1 using electrical methods through measuring device 2. With junction voltage The functional relationship between (the junction voltage of the isolation diode on the IC substrate) and (the IC substrate isolation diode).

[0100] Step 5: Disconnect the electrical connection between DUT1 and measuring device 2, then connect DUT1 to testing device 4. The power stress extracted in step 4 will be measured using testing device 4. The test was started by applying aging conditions to DUT1 and ended after 168 hours by removing the aging stress.

[0101] The other steps and methods are the same.

[0102] Specifically, in step 1, the isolation diode on the IC substrate is generally the IC ground pin (GND) and the positive power supply pin. Intrinsic diodes between.

[0103] Example 9

[0104] like Figure 10 As shown, in this embodiment, DUT1 is an integrated voltage regulator; and the test equipment 4 is a power aging equipment.

[0105] The difference between this embodiment and Embodiment 2 is as follows:

[0106] Step 1: Install DUT1 in junction temperature calibration module 3, and establish the junction temperature of DUT1 using electrical methods through measuring device 2. and The functional relationship between (the junction voltage between the output terminal OUT and the input terminal IN of the positive output voltage regulator);

[0107] Step 3: Electrically connect DUT1 to measuring device 2, and use a heating device to provide DUT1 with a high background thermal stress. The input voltage is applied to DUT1 using measuring device 2. and output current The junction of DUT1 is heated to the test-specified 150°C (generally specified for silicon devices). (℃) and reach thermal steady state, measure the steady-state thermal resistance from the DUT1 junction to the reference point. ;

[0108] Step 4: Record the actions applied to DUT1 in Step 3. Output voltage , , and The measurement data was collected, and the power stress required for DUT1 to reach the specified junction temperature and achieve thermal steady state was extracted from it. ( equal and pressure difference multiplied by and background thermal stress ;

[0109] Step 5: Disconnect the electrical connection between DUT1 and measuring device 2, then connect DUT1 to testing device 4. The power stress extracted in step 4 will be measured using testing device 4. The test was started by applying aging conditions to DUT1 and ended after 168 hours by removing the aging stress.

[0110] The other steps and methods are the same.

[0111] Specifically, in step 3, the background thermal stress It is usually provided by a precision oven, and the set temperature is usually 125℃.

[0112] Specifically, in step 4, the power stress Typically 100 milliwatts.

[0113] Example 10

[0114] like Figure 11 As shown, in this embodiment, DUT1 is a Schottky diode; and the test equipment 4 is a high-temperature reverse bias (HTRB) device.

[0115] The difference between this embodiment and Embodiment 2 is as follows:

[0116] Step 3: Electrically connect DUT1 to the aging condition measuring device 2. First, apply the reverse bias voltage specified in the test to the junction of DUT1 using the aging condition measuring device 2. Without changing the background thermal stress, gradually increase the background thermal stress of DUT1 using heating equipment. Until the junction of DUT1 is heated to the test-specified 150°C (generally specified for silicon devices). (℃) and reach thermal steady state, measure the steady-state thermal resistance from the DUT1 junction to the reference point. ;

[0117] Step 4: Record the actions applied to DUT1 in Step 3. Reverse leakage current , and The measurement data was collected, and the power stress required for DUT1 to reach the specified junction temperature and achieve thermal steady state was extracted from it. ( equal Multiply and background thermal stress ;

[0118] Step 5: Disconnect the electrical connection between DUT1 and the aging condition measuring device 2, then connect DUT1 to the testing device 4. The power stress extracted in Step 4 is then measured using the testing device 4. and background thermal stress The aging conditions were applied to DUT1 to begin the experiment, and after 48 hours, the aging conditions were first applied to... Cool to room temperature, then remove The experiment is now over.

[0119] Specifically, in step 2, the test fixture 41 is generally set in a precision oven, which is the heating device mentioned in step 3.

[0120] Specifically, in step 3, national military standards generally stipulate... Equal to 50-85% of the rated operating peak reverse voltage .

[0121] Specifically, in step 3, since the reverse leakage current of the Schottky diode increases exponentially with temperature, a large amount of reverse leakage power consumption will be generated when approaching the maximum junction temperature of DUT1. Self-heating can easily lead to thermal runaway, therefore, generally It will be about 25 to 50°C lower than the maximum junction temperature of DUT1.

[0122] Specifically, in steps 2 and 3 of Examples 2-10, the junction temperature of DUT1 is... Subjected to the "self-heating effect" of power stress and background thermal stress Driven by both factors, and satisfying the junction temperature formula:

[0123]

[0124] At room temperature, The temperature is the laboratory temperature; when background thermal stress is applied to DUT1 using heating equipment, The set temperature for the heating equipment, which is DUT1. ,and Generally higher than the laboratory temperature, at this time... That is .

[0125] Since the thermal characterization and aging tests of DUT1 were conducted in the same heat flow mode formed by DUT1 and test fixture 41, and the same test stress was used, therefore , and No changes were observed. According to the junction temperature formula, the junction temperature during the aging process of DUT1 is... The junction temperature is completely consistent with that used in the thermal characterization, meaning that there will be no understress, overstress, or fatigue stress. The actual test stress is accurate and reliable, thereby improving the reliability of DUT1 in use.

[0126] Specifically, in embodiments 2 to 9, the measuring device 2 can be a semiconductor device test condition measuring device as described in this invention, or it can be other measuring devices with the same function.

[0127] Specifically, in Examples 2 to 10, the test item referred to as power aging (BI) in screening tests is generally referred to as steady-state operating life test (SSOP) in quality consistency tests (routine tests) or qualification tests. The only difference between the two is the test time, and the SSOP time (usually not less than 1000 hours) is generally longer than the BI time.

[0128] Specifically, in step 1 of embodiments 2 to 10, the junction temperature calibration module 3 can be an oil bath, a precision oven, or a temperature-controlled metal hot plate, etc., which can effectively and accurately control the temperature of the DUT1.

[0129] Specifically, in step 2 of embodiments 2-10, the test fixture 41 can be a module fixed on the test equipment 4 or a detachable module. The module and DUT1 constitute a fixed heat flow pattern. The heat flow pattern includes elements such as heat source (e.g., power stress of DUT1), heat transfer path (e.g., through the radiator to the cooling medium), heat dissipation system (e.g., using radiator for air cooling or liquid cooling), and control boundary conditions (e.g., background thermal stress).

[0130] Specifically, in step 3 of embodiments 2 to 10, the reference point can be any position on the DUT1, or on the test fixture 41, or in a heating device (such as an oven) that provides background thermal stress.

[0131] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for measuring test conditions of semiconductor devices, characterized in that, The test conditions are accurately extracted by characterizing the thermal properties of the device under test in the same heat flow mode as the specified test items. The specific steps include: Step 1: Install the device under test in the junction temperature calibration device, and use electrical methods to establish the functional relationship between the junction temperature of the device under test and the temperature sensitive parameter through the measuring equipment; Step 2: Then install the device under test in the test fixture of the test equipment, and the device under test and the test fixture will form a fixed heat flow pattern; Step 3: Connect the device under test (DUT) to the measuring equipment. Apply background thermal stress to the DUT at room temperature or using a heating device. Apply electrical stress to the DUT using the measuring equipment. Under the combined effect of electrical stress and background thermal stress, the junction of the DUT is heated to the temperature specified in the test and reaches a thermal steady state. Measure the steady-state thermal resistance of the junction of the DUT to the reference point. Step 4: Record the measurement data such as electrical stress, background thermal stress and thermal resistance applied to the device under test in Step 3, and extract the test stress required for the device under test to reach the specified junction temperature and thermal steady state. Step 5: Disconnect the electrical connection between the device under test and the measuring equipment, then connect the device under test to the testing equipment. Apply the test stress extracted in Step 4 to the device under test as the test condition through the testing equipment to start the test.

2. The method for measuring test conditions of a semiconductor device according to claim 1, characterized in that, The temperature-sensitive parameter is the junction voltage of the device under test (DUT). The test stress required for the DUT to reach the specified junction temperature and thermal steady state is the power stress and the background thermal stress at room temperature.

3. The method for measuring test conditions of a semiconductor device according to claim 1, characterized in that, The temperature-sensitive parameter is the junction voltage of the device under test. The test stress required for the device under test to reach the specified junction temperature and thermal steady state is the current stress and the background thermal stress at room temperature.

4. The method for measuring test conditions of a semiconductor device according to claim 1, characterized in that, The temperature-sensitive parameter is the on-resistance of the device under test. The test stress required for the device under test to reach the specified junction temperature and thermal steady state is the power stress and the background thermal stress at room temperature.

5. The method for measuring test conditions of a semiconductor device according to claim 1, characterized in that, The temperature-sensitive parameter is the saturation voltage of the device under test. The test stress required for the device under test to reach the specified junction temperature and thermal steady state is the power stress and the background thermal stress at room temperature.

6. The method for measuring test conditions of a semiconductor device according to claim 1, characterized in that, The temperature-sensitive parameter is the junction voltage of the device under test (DUT). The test stress required for the DUT to reach the specified junction temperature and thermal steady state is the power stress and the background thermal stress above room temperature.

7. The method for measuring test conditions of a semiconductor device according to claim 1, characterized in that, In step 3, the reference point can be any position on the device under test, a position on the test fixture, or a position in the heating device that provides background thermal stress.

8. A semiconductor device test condition measuring device, characterized in that, It can independently power the main circuit and control circuit of the device under test and output electrical stress over a wide range, specifically including: The device includes a control module (including memory), a human-machine interface, a main power supply, a secondary power supply, a current source, and a junction temperature calibration and measurement module. The control module is communicatively connected to the human-machine interface, main power supply, secondary power supply, current source, and junction temperature calibration and measurement module. It controls the main power supply, secondary power supply, current source, and junction temperature calibration module based on commands input from the human-machine interface and electrical signals fed back from the main power supply, secondary power supply, current source, and temperature measurement module. The human-machine interface displays device status and allows command input. The main power supply is electrically connected to the device under test (DUT) and supplies power to the DUT's main circuit. The secondary power supply is also electrically connected to the DUT and supplies power to the DUT's control circuit. The current source is electrically connected to the DUT and provides test current to the DUT's test circuit to measure its temperature-sensitive parameters. The temperature measurement module measures the DUT's case temperature during junction temperature calibration and measures the temperature of a reference point during DUT thermal characteristic characterization. The junction temperature calibration module is used for electrical calibration of the DUT's junction temperature.

9. A semiconductor device test condition measuring device according to claim 8, characterized in that, The main power supply and the auxiliary power supply provide independent power to the device under test, which can avoid interference between the main circuit and the control circuit, avoid the thermal instability electrical stress range of the device under test, and avoid thermal instability failure.

10. A semiconductor device test condition measuring device according to claim 8, characterized in that, The main power supply, auxiliary power supply, and current source are all DC programmable power supplies, and their output electrical stress range is higher than that of traditional measuring equipment, enabling a single measuring device to meet the testing needs of various devices without the need to replace the equipment.

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