Return address prediction stack management methods, devices, equipment and program products

Abstract

This application provides a return address prediction stack management method, apparatus, device, and program product. The method mainly manages the free status of each entry in the physical storage space by providing a free list, and updates the status of the corresponding entry to free when the return instruction retires, thereby realizing the accurate release and dynamic reclamation of prediction stack entries, thus avoiding the loss of effective information due to sequential overwriting and improving the utilization rate of return address prediction stack entries.

Description

Technical Field

[0001] This application belongs to the field of computer technology, and in particular relates to a method, apparatus, device and program product for return address prediction stack management. Background Technology

[0002] The return address predictor is a hardware module in the processor used to predict the target address of return instructions. The return address predictor is typically maintained using a stack structure: when a call instruction is predicted, the return address is pushed onto the stack; when a return instruction is predicted, the address is popped from the top of the stack as the prediction target address.

[0003] In related technologies, return address prediction stacks typically employ a linked list structure to decouple the logical order of the prediction stack from its physical storage location. This scheme maintains a stack top pointer and a write pointer, and utilizes the pointer relationships stored in the entries to implement push and pop operations. When a predicted call instruction occurs, the return address is written to the location pointed to by the pointer, and the corresponding pointer is updated; when a predicted return instruction occurs, the return address is read from the location pointed to by the stack top pointer, and the stack top pointer is updated along the pointer relationships.

[0004] However, the above scheme uses a sequential write method when allocating new entries. When the prediction stack is full, the earliest written entry is overwritten according to the order in which the entries were stored. This allocation method may cause entries in the prediction stack that still have predictive value to be lost due to premature overwriting, reducing the utilization rate of the return address prediction stack and the prediction accuracy. Summary of the Invention

[0005] This application provides a return address prediction stack management method, apparatus, device, and program product, which can avoid the loss of effective information due to sequential overwriting and improve the utilization rate of return address prediction stack entries.

[0006] A first aspect of this application provides a return address prediction stack management method, comprising: providing physical storage space for the prediction stack, a free list, and a stack top read pointer, wherein the physical storage space includes multiple entries, each entry is used to store a return address and a pointer to the logically next entry, and the free list is used to manage the free state of each entry in the physical storage space; in response to a prediction call instruction, allocating a free entry from the free list, writing the return address of the prediction call instruction into the allocated free entry, and updating the stack top read pointer; in response to a prediction return instruction, reading the return address from the entry pointed to by the stack top read pointer as the prediction target address, and updating the stack top read pointer; in response to a return instruction retirement, updating the state of the entry corresponding to the return instruction in the free list to free; wherein the free list is used to dynamically manage the allocation and release of entries in the physical storage space, so that entries released when a return instruction retires can be reallocated by subsequent prediction call instructions.

[0007] In the technical solution of this application, the free list is provided to manage the free status of each entry in the physical storage space, and the status of the corresponding entry is updated to free when the return instruction retires, so as to realize the accurate release and dynamic reclamation of the prediction stack entries, thereby avoiding the loss of effective information due to sequential overwriting and improving the utilization rate of the return address prediction stack entries.

[0008] Optionally, in one possible implementation of the first aspect, before allocating a free entry from the free list in response to a predicted invocation instruction, the method further includes: maintaining a top-of-stack write pointer and a bottom-of-stack pointer, the top-of-stack write pointer pointing to the entry allocated when the next predicted invocation instruction is pushed onto the stack, and the bottom-of-stack pointer pointing to the logically earliest allocated and not yet released entry in the physical storage space; determining whether the top-of-stack write pointer is equal to the bottom-of-stack pointer; if the top-of-stack write pointer is equal to the bottom-of-stack pointer, searching for a target entry in the physical storage space and updating the bottom-of-stack pointer to the target entry, wherein the pointer of the target entry to the logically next entry is equal to the entry currently pointed to by the bottom-of-stack pointer. Thus, by maintaining the top-of-stack write pointer and the bottom-of-stack pointer, and searching for a target entry in the physical storage space whose pointer to the logically next entry is equal to the entry currently pointed to by the bottom-of-stack pointer when the top-of-stack write pointer is equal to the bottom-of-stack pointer, and updating the bottom-of-stack pointer to the target entry, the method accurately locates the second-earliest allocated entry in a stack-full overlay scenario, providing an accurate stack bottom position for overlay decisions.

[0009] Optionally, in another possible implementation of the first aspect, the method further includes: maintaining a stack bottom pointer, which points to the earliest logically allocated and not yet released entry in the physical storage space; the allocation of a free entry from the free list includes: scanning the free list to determine if there is an entry in a free state; if there is an entry in a free state, selecting one from the free entries as the allocated free entry; if there is no entry in a free state, using the entry currently pointed to by the stack bottom pointer as the allocated free entry. Thus, by scanning the free list to determine if there is a free entry, allocating from the free entries if they exist, and using the entry pointed to by the stack bottom pointer as the allocation object if they do not exist, the method prioritizes the use of released resources, only overwriting the earliest allocated entry when the stack is full, thereby optimizing the resource allocation order.

[0010] Optionally, in another possible implementation of the first aspect, each entry in the free list is further used to store a sequence number, which represents the allocation timing of the calling instructions stored in the corresponding physical storage space entry in the program execution order; the method further includes: in response to the predicted calling instruction, writing the sequence number of the predicted calling instruction into the sequence number field corresponding to the allocated free entry. Thus, by storing the value-retrieval block sequence number for each entry in the free list and writing the sequence number into the sequence number field corresponding to the allocated free entry when predicting the calling instruction, a binding relationship is established between each physical storage space entry and the allocation timing of the instruction, thereby providing a basis for identifying the timeliness of entries during exception recovery.

[0011] Optionally, in another possible implementation of the first aspect, the method further includes: in response to a pipeline interruption, obtaining the type of the interrupt instruction and the backup stack top read pointer; restoring the current stack top read pointer according to the type of the interrupt instruction and the backup stack top read pointer; obtaining the sequence number of the interrupt instruction; traversing the free list and updating the status of the physical storage space entries corresponding to free list entries with sequence numbers later than the interrupt instruction sequence number to free. Thus, by obtaining the sequence number of the interrupt instruction when the pipeline is interrupted and traversing the free list to update the status of the physical storage space entries corresponding to free list entries with sequence numbers later than the interrupt instruction sequence number to free, invalid entries allocated on the incorrect path are accurately released, ensuring that the predicted stack state is consistent with the correct execution path.

[0012] Optionally, in another possible implementation of the first aspect, the method further includes: in response to a pipeline interrupt, obtaining the type of the interrupt instruction and the backup stack top read pointer; restoring the current stack top read pointer according to the type of the interrupt instruction and the backup stack top read pointer; traversing the physical storage space from the entry pointed to by the restored stack top read pointer along the pointer pointing to the logical next entry, marking the status of the traversed entries as occupied; and updating the status of the untraversed entries in the physical storage space to free. Thus, by traversing the physical storage space from the entry pointed to by the restored stack top read pointer during a pipeline interrupt, marking the traversed physical storage space entries as occupied and marking the untraversed entries as free, accurate restoration of the predicted stack state is achieved without relying on sequence numbers, reducing dependence on hardware resources.

[0013] Optionally, in another possible implementation of the first aspect, after updating the status of the entry corresponding to the return instruction in the free list to free in response to the retirement of the return instruction, the method further includes: determining whether the entry pointed to by the stack bottom pointer has been released, wherein the stack bottom pointer points to the logically earliest allocated and not yet released entry in the physical storage space; if the entry pointed to by the stack bottom pointer has been released, then searching for the target entry in the physical storage space and updating the stack bottom pointer to the target entry, wherein the pointer of the target entry to the logically next entry is equal to the entry currently pointed to by the stack bottom pointer. Thus, by determining whether the entry pointed to by the stack bottom pointer has been released after the return instruction retires, and if it has been released, searching for the target entry in the physical storage space whose pointer to the logically next entry is equal to the entry currently pointed to by the stack bottom pointer, and updating the stack bottom pointer to the target entry, the accuracy of the stack bottom pointer is dynamically maintained, providing a reliable basis for subsequent stack full overwrite decisions.

[0014] A second aspect of this application provides a return address prediction stack management device, comprising: The configuration module is used to provide the physical storage space, free list and stack top read pointer of the prediction stack. The physical storage space includes multiple entries, each of which stores the return address and a pointer to the logical next entry. The free list is used to manage the free status of each entry in the physical storage space. The first update module is used to respond to the predicted call instruction by allocating a free entry from the free list, writing the return address of the predicted call instruction to the allocated free entry, and updating the stack top read pointer. The second update module is used to read the return address from the entry pointed to by the stack top read pointer as the prediction target address in response to the prediction return instruction, and update the stack top read pointer. The third update module is used to update the status of the entry corresponding to the return instruction in the free list to free in response to the retirement of the return instruction. The free list is used to dynamically manage the allocation and release of entries in the physical storage space so that the entries released when the return instruction retires can be reallocated by subsequent predicted call instructions.

[0015] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the return address prediction stack management method of the first aspect described above.

[0016] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the return address prediction stack management method of the first aspect described above.

[0017] The fifth aspect of this application provides a computer program product that, when run on an electronic device, causes the electronic device to execute the return address prediction stack management method of the first aspect described above.

[0018] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram illustrating the update process of a return address prediction stack; Figure 2 This is a schematic diagram illustrating the update process of a return address prediction stack maintained by a linked list; Figure 3 This is a flowchart illustrating a return address prediction stack management method provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a return address prediction stack provided in an embodiment of this application; Figure 5 This is an example diagram illustrating the return address prediction stack update process when a call instruction occurs, as provided in an embodiment of this application. Figure 6 This is an example diagram illustrating the return address prediction stack update process when a return instruction occurs, as provided in an embodiment of this application. Figure 7 This is an example diagram illustrating the return address prediction stack update process during the retirement of a return instruction, as provided in an embodiment of this application. Figure 8 This is an example diagram of the return address prediction stack update process when a pipeline interruption occurs, provided in an embodiment of this application. Figure 9 This is a schematic diagram of the structure of a return address prediction stack management device provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0021] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0022] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0023] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0025] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0027] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0028] In related technologies, the return address predictor is a hardware module in the processor used to predict the target address of a return instruction, and is an important component of branch prediction. The return address predictor is typically maintained using a stack structure: when a call instruction is predicted, the return address (i.e., the address of the instruction following the call instruction) is pushed onto the stack; when a return instruction is predicted, the address is popped from the top of the stack as the prediction target address.

[0029] Figure 1 A schematic diagram illustrating the update process of a return address prediction stack is shown. Figure 1 As shown, a basic return address prediction stack consists of a prediction stack and a top of stack (StkTop) pointer. The prediction stack stores the return address, and the top of stack pointer points to the prediction stack position where the address to be popped by the next predicted return instruction should be. When a predicted call instruction occurs, the return address is pushed onto the prediction stack, and the top of stack pointer is updated (+1) to point to the newly pushed entry. When a predicted return instruction occurs, the return address is popped from the top of stack pointer as the predicted jump address, and the top of stack pointer is updated (-1) to point to the entry at the second-to-top. However, this design has a problem: when a new predicted call instruction is pushed onto the stack, the old, popped return address information may be overwritten and lost. When an exception or pipeline interrupt occurs and the prediction stack state needs to be restored, the return address information in the entry pointed to by the top of stack pointer cannot be recovered.

[0030] To address the aforementioned problems, relevant technologies have proposed solutions such as... Figure 2The diagram illustrates an update process for a return address prediction stack maintained by a linked list, where the logical order of the prediction stack is decoupled from its physical storage location. Specifically, the physical storage space of the prediction stack (Physical stack registers, PhyStk) contains multiple entries, each storing two fields: the return address and a pointer to the logical next entry in the prediction stack (Prev). The Prev pointer points to the logically next entry closer to the bottom of the stack (i.e., allocated earlier). The scheme also uses two key pointers to maintain the prediction stack: the StkTop pointer, pointing to the logical top of the stack where the next predicted return instruction should be popped; and the NextWr pointer, pointing to the physical storage location where the next predicted call instruction should be pushed. When a predicted call instruction occurs, the return address is written to the return address field of the entry pointed to by the NextWr pointer, the current StkTop value is written to the Prev field of that entry, the StkTop pointer is updated to the value of NextWr, and the NextWr pointer is incremented. When a prediction return instruction occurs, the return address of the entry pointed to by the StkTop pointer is read as the prediction target address, and the StkTop pointer is updated to the entry pointed to by the Prev field of that entry. Since the NextWr pointer is not decremented during prediction return instructions, subsequent prediction call instructions will not immediately overwrite the contents of popped entries. When an exception or pipeline interruption occurs, the prediction stack state is restored by recovering the StkTop pointer and using the Prev pointer of each entry along the linked list.

[0031] However, the aforementioned chained return address prediction stack uses a push strategy where the NextWr pointer increments sequentially when allocating new entries. When the prediction stack is full, it overwrites the oldest entry according to the age order of the calling instructions. This approach leads to the following problems: In programs with frequent call and return instruction execution, for the same size prediction stack, the linked list consumes stack entries faster, making overwriting more likely and reducing stack utilization. Furthermore, in nested call scenarios, later call instructions are often executed earlier, and the age-order overwriting strategy results in expired entries still occupying stack space, while entries with predictive value are overwritten and information is lost, thus reducing the prediction accuracy of the return address prediction stack.

[0032] In view of this, embodiments of this application provide a method, apparatus, device, and program product for managing a return address prediction stack. The method first provides a physical storage space for the prediction stack, a free list, and a stack top read pointer. The physical storage space includes multiple entries, each storing a return address and a pointer to the logically next entry. The free list manages the free state of each entry in the physical storage space. Then, in response to a prediction call instruction, a free entry is allocated from the free list, the return address of the prediction call instruction is written to the allocated free entry, and the stack top read pointer is updated. Next, in response to a prediction return instruction, the return address is read from the entry pointed to by the stack top read pointer as the prediction target address, and the stack top read pointer is updated. Finally, in response to a return instruction retirement, the state of the entry corresponding to the return instruction in the free list is updated to free. The free list dynamically manages the allocation and release of entries in the physical storage space, so that entries released when a return instruction retires can be reallocated by subsequent prediction call instructions. Therefore, by providing a free list to manage the free status of each entry in the physical storage space, and updating the status of the corresponding entry to free when the return instruction retires, the prediction stack entries can be accurately released and dynamically reclaimed, thereby avoiding the loss of effective information due to sequential overwriting and improving the utilization rate of the return address prediction stack entries.

[0033] To illustrate the technical solution of this application, specific embodiments are described below.

[0034] Reference Figure 3 The diagram illustrates a flowchart of a return address prediction stack management method provided in an embodiment of this application. Figure 3 As shown, the return address prediction stack management method may include the following steps: Step 301: Provide the physical storage space, free list, and stack top read pointer of the prediction stack.

[0035] In the embodiments of this application, reference can be made to Figure 4 The diagram shows a schematic of a return address prediction stack. Figure 4 As shown, the prediction stack includes physical storage space PhyStk, a free list (FreeList), and a top of stack read pointer (TopRd).

[0036] The physical storage space of the prediction stack is the core hardware structure of the return address predictor, used to store the return address information of the predicted call instructions. The physical storage space contains multiple entries, each storing a return address and a pointer to the logically next entry. The pointer to the logically next entry, the Prev pointer, is used to establish a logical linked list relationship between entries in the prediction stack. The Prev pointer points to the next entry closer to the bottom of the stack (i.e., allocated earlier) in the logical relationship of the current entry in the prediction stack.

[0037] The free list manages the free status of entries in the physical memory space and is a hardware structure used to dynamically manage the allocation status of prediction stack entries. There is a one-to-one correspondence between the free list and physical memory entries. Each entry contains two key fields: a valid bit and a fetch block sequence number. The valid bit is a single-bit flag; a high bit indicates that the corresponding entry in the physical memory space is free and can be allocated to a newly predicted call instruction; a low bit indicates that the entry is occupied by valid predicted call instruction information. The fetch block sequence number (FBlkId) records the fetch block sequence number of the call instruction stored in the entry. This sequence number is generated by the processor's fetch pipeline and increments with the program order of the instruction flow. It is used to identify the allocation timing of entries during exception recovery and to release entries not on the valid path.

[0038] The stack top read pointer is a key pointer used to locate the top of the prediction stack logic stack. This stack top read pointer always points to the top of the prediction stack logic stack, that is, the position where the next prediction return instruction should pop the entry of the return address.

[0039] In one embodiment, maintaining the return address prediction stack also involves a top-of-stack write pointer (TopWr) and a bottom-of-stack pointer (Bottom). The top-of-stack write pointer points to the physical storage space entry allocated when the next predicted call instruction is pushed onto the stack, and the bottom-of-stack pointer points to the logically earliest allocated entry in the current prediction stack that has not yet been used by the corresponding return instruction. These three pointers (top-of-stack read pointer, top-of-stack write pointer, and bottom-of-stack pointer) jointly maintain the dynamic state of the prediction stack and are updated accordingly when events such as predicted call instructions, predicted return instructions, return instruction retirement, and exception recovery occur.

[0040] It should be noted that, to support the restoration of the return address prediction stack in the event of exceptions or pipeline interruptions, each prediction call instruction and prediction return instruction backs up the current prediction stack's top write pointer and top read pointer during prediction. Prediction stack entries are allocated when the prediction call instruction occurs and are retained until the corresponding return instruction retires, thus ensuring that the information of valid entries in the prediction stack is still preserved when a branch is mispredicted or other interrupts require rollback. The correct top read pointer is restored using the backed-up top write pointer and top read pointer, and invalid entries on the incorrect path are released by comparing the value fetch sequence number, thereby achieving complete prediction stack restoration.

[0041] In the embodiments of this application, reference can continue to be made to Figure 4 The physical storage space contains multiple entries, each storing a return address and a pointer (Prev) to the logically next entry. The free list corresponds to the physical storage space, with each entry containing a valid bit and a value block sequence number (FBlkId). The stack top read pointer (TopRd) points to the logical top entry, the stack top write pointer (TopWr) points to the next allocated free entry, and the stack bottom pointer (Bottom) points to the earliest allocated and not yet freed entry. This structure, through the dynamic management of the free list, achieves precise allocation and reclamation of predicted stack entries.

[0042] Step 302: In response to the predicted call instruction, allocate a free entry from the free list, write the return address of the predicted call instruction to the allocated free entry, and update the stack top read pointer.

[0043] In this context, a predicted call instruction refers to an instruction that the processor predicts to be a call instruction during the branch prediction phase. When a predicted call instruction occurs, the return address prediction stack needs to push the address of the next instruction after the current call instruction (i.e., the return address) onto the prediction stack for use in the prediction of the subsequent corresponding return instruction.

[0044] In one embodiment, step 302 involves maintaining the top and bottom pointers of the stack and updating the state of the free list. Specifically, before allocating a free entry from the free list in response to a predicted call instruction, the following steps can be performed: maintaining the top and bottom pointers of the stack, where the top pointer points to the entry allocated when the next predicted call instruction is pushed onto the stack, and the bottom pointer points to the logically earliest allocated and not yet released entry in the physical storage space; determining whether the top pointer equals the bottom pointer; and if the top pointer equals the bottom pointer, searching for the target entry in the physical storage space and updating the bottom pointer to the target entry, wherein the pointer of the target entry to the logically next entry is equal to the entry currently pointed to by the bottom pointer. Thus, by maintaining the top and bottom pointers of the stack, and searching for the target entry in the physical storage space when the top pointer equals the bottom pointer, where the pointer to the logically next entry is equal to the entry currently pointed to by the bottom pointer, and updating the bottom pointer to the target entry, the second-earliest allocated entry can be accurately located in a full-overlay scenario, providing an accurate bottom position for overlay decisions.

[0045] It's important to note that before allocating free entries from the free list, the top and bottom pointers of the stack are maintained. The top pointer (TopWr) points to the physical storage space entry that should be allocated when the next predicted call instruction is pushed onto the stack, and the bottom pointer (Bottom) points to the logically earliest allocated entry in the current prediction stack that has not yet been used by the corresponding return instruction. The top pointer is checked against the bottom pointer to determine if the prediction stack is full. When they are equal, it means that all entries in the current prediction stack are occupied, and there are no free entries available for allocation. In this case, an entry is searched in the physical storage space (PhyStk) whose Prev pointer is equal to the entry currently pointed to by the bottom pointer. This found entry is the logically second-earliest allocated entry (i.e., the entry allocated later than the current bottom entry and closer to the top of the stack). The bottom pointer is then updated to reflect this found entry. Through the above operations, the stack bottom pointer is moved from the earliest allocated entry to the second earliest allocated entry, thereby allowing the earliest allocated entry to be overwritten during subsequent allocations, while maintaining the stack bottom pointer always pointing to the earliest allocated and unreleased entry in the current prediction stack.

[0046] In one embodiment, the specific method for allocating free entries from the free list can employ a freescan strategy. Specifically, a stack pointer can be maintained, pointing to the logically earliest allocated and not yet released entry in the physical storage space. The free list can then be scanned to determine if any entries are currently free. If a free entry exists, it is selected as the allocated free entry. If no free entry exists, the entry currently pointed to by the stack pointer is used for allocation. Thus, by scanning the free list to determine if a free entry exists, allocating from the free entries if one exists, and using the entry pointed to by the stack pointer if none exists, free resources are utilized preferentially, and the earliest allocated entry is only overwritten when the stack is full, optimizing the resource allocation order.

[0047] It's important to note that, firstly, a stack bottom pointer is maintained, pointing to the earliest logically allocated and not yet freed entry in the physical memory space. When a free entry needs to be allocated, the free list is scanned, iterating through the valid bits of all entries in the free list to determine if any entry is free (i.e., the valid bit is high). If a free entry exists, one is selected from these free entries (e.g., the first free entry selected according to the scan order) as the allocated entry for the current predicted call instruction to be pushed onto the stack. If no free entry exists, i.e., the prediction stack is full, the entry currently pointed to by the stack bottom pointer is used as the allocated entry. This strategy implements an allocation mechanism that prioritizes the use of freed resources: only when no free resources are available is the earliest allocated entry in the prediction stack overwritten, thereby maximizing the retention of valid prediction information.

[0048] Furthermore, after allocating free entries, a return address write operation can be performed. Specifically, the return address of the currently predicted call instruction can be written to the return address field of the allocated entry. At the same time, the Prev pointer of the entry is updated to the value of the current stack top read pointer TopRd, thereby establishing a linked list relationship between the newly pushed entry and the current stack top, making the newly pushed entry the new logical stack top.

[0049] In one embodiment, each entry in the free list also stores a sequence number representing the allocation timing. Specifically, each entry in the free list stores a sequence number, which may be a value block sequence number FBlkId, used to represent the allocation timing of the call instructions stored in the corresponding physical storage space entry in the program execution order; furthermore, in response to a predicted call instruction, the sequence number of the predicted call instruction can be written into the sequence number field corresponding to the allocated free entry. Thus, by storing a value block sequence number for each entry in the free list and writing the sequence number into the sequence number field corresponding to the allocated free entry when predicting a call instruction, a binding relationship is established between each physical storage space entry and the allocation timing of the instruction, thereby providing a basis for identifying the timeliness of entries during anomaly recovery.

[0050] It should be noted that each entry in the free list, in addition to storing a valid bit, also stores a sequence number field. This sequence number is used to characterize the allocation timing of the call instructions stored in the physical memory space entry corresponding to that entry in the program execution order. When a call instruction is predicted to occur, the sequence number of the current call instruction (i.e., the fetch block sequence number FBlkId) is written to the sequence number field corresponding to the allocated free entry. This sequence number is generated by the processor fetch pipeline and increments with the program order of the instruction flow. Therefore, when an exception or pipeline interrupt occurs, by comparing the size relationship of the sequence numbers, it is possible to identify which entries belong to instructions allocated later than the interrupt (abort) instruction (i.e., entries on the wrong path), thereby accurately releasing these invalid entries.

[0051] Furthermore, after writing the return address and sequence number, the stack top read pointer is updated. Specifically, the stack top read pointer TopRd is updated to the position of the currently allocated entry (i.e., the position pointed to by the original stack top write pointer TopWr), making this entry the new logical top of the prediction stack for use when reading the return address in subsequent prediction return instructions. Subsequently, the stack top write pointer is updated to prepare for the allocation of the next prediction call instruction. The update of the stack top write pointer depends on the empty / full state of the prediction stack: if the current allocation is a free entry in the free list (i.e., a free entry exists), the free list is scanned again, and one of the remaining free entries is selected as a candidate for the next allocation, and the stack top write pointer is updated to the position of that entry; if the current allocation is the entry pointed to by the stack bottom pointer (i.e., the stack bottom entry is overwritten when the stack is full), the stack top write pointer is updated to the entry pointed to by the updated stack bottom pointer (i.e., the second earliest allocated entry), so that the allocation will continue to follow the earliest allocation priority overwriting strategy when the next prediction call instruction occurs.

[0052] In one embodiment, when a push operation of a predicted call instruction causes an overwrite, this application also involves further maintenance of the stack bottom pointer. As described in the preceding embodiments, when the stack top write pointer equals the stack bottom pointer (i.e., the stack is full), before allocating the entry pointed to by the stack bottom pointer, the stack bottom pointer has been pre-updated to the entry whose Prev pointer points to the current stack bottom entry. This operation ensures that the stack bottom pointer always accurately points to the earliest allocated and not yet released entry in the current prediction stack, providing a reliable basis for subsequent overwrite decisions.

[0053] In one possible implementation, the return address of the current call instruction can first be pushed onto the return address field of the PhyStk entry in the physical memory space pointed to by the stack top write pointer TopWr, and the Prev pointer of that entry can be updated to the value of the current stack top read pointer TopRd. Then, the valid bit of the corresponding entry in the free list is updated to low to mark that the entry is occupied, and the sequence number FBlkId of the current call instruction is written into the sequence number field of that entry. Finally, the equality relationship between the stack top write pointer and the stack bottom pointer is used to determine whether an overwrite has occurred. If an overwrite has occurred, the entry whose Prev pointer is equal to the entry currently pointed to by the stack bottom pointer is searched in the physical memory space, and the stack bottom pointer is updated to the found entry. Then, the stack top read pointer is updated to the value of the stack top write pointer, and the free list is scanned to update the stack top write pointer. For ease of understanding, the above process can be referred to as follows: Figure 5 The diagram shows an example of a predictive stack update process for the return address when a call instruction occurs.

[0054] Step 303: In response to the predictive return instruction, read the return address from the entry pointed to by the stack top read pointer as the predictive target address, and update the stack top read pointer.

[0055] In this context, a predicted return instruction refers to an instruction that the processor predicts as a return instruction during the branch prediction phase. When a predicted return instruction occurs, the return address prediction stack needs to pop the return address from the current stack top as the predicted target jump address for the return instruction, which is then used by the subsequent instruction fetch pipeline.

[0056] In one embodiment, the processing of predicted return instructions involves reading the return address from the entry pointed to by the top stack read pointer and updating the top stack read pointer according to the linked list relationship. Specifically, firstly, the return address field of the PhyStk entry in the physical memory space currently pointed to by the top stack read pointer TopRd is read, and this return address is output as the prediction target address to the branch predictor module for subsequent instruction value retrieval operations. This operation realizes the prediction of the target address of the predicted return instruction.

[0057] Furthermore, after completing the return address read, the stack top read pointer is updated. The update method is as follows: the stack top read pointer is updated to the entry pointed to by the pointer (Prev pointer) that points to the logically next entry. Since the Prev pointer points to the logically next entry closer to the bottom of the stack (i.e., allocated earlier), this update operation moves the stack top read pointer from its current stack top position to the second-to-last position in the logical stack; that is, the next-latest allocated entry becomes the new logical stack top. Through this operation, the prediction stack implements a pop operation. Although the current stack top entry still retains its data in physical storage space, it has been logically removed from the stack top, ready for the next predicted return instruction read to use the new stack top position.

[0058] It's important to note that when a predicted return instruction occurs, only the stack top read pointer is updated; the free list is not modified. The popped entry retains its data in physical storage, and its free state is not immediately released. The actual release of this entry occurs when the corresponding return instruction retires. This delayed release mechanism ensures that in the event of a misprediction of a branch or an exception, the correct prediction stack state can be restored using the backup stack top read pointer, preventing information loss due to premature release.

[0059] In one possible implementation, the return address field of the PhyStk entry in the physical memory space pointed to by the stack top read pointer TopRd is first read, and this address is output as the predicted target address (Address Out). Then, the stack top read pointer is updated to the entry position pointed to by the entry's Prev pointer, making the stack top read pointer point to the second-to-top entry in the logical stack, completing the pop operation. Throughout this process, the state of the FreeList remains unchanged, and the valid bit of the popped entry remains low (indicating it is occupied). The release of this entry awaits the retirement of the corresponding return instruction. For ease of understanding, the above process can be referred to as follows: Figure 6 The diagram shows an example of a return address prediction stack update process when a return instruction occurs.

[0060] In one embodiment, the processing of the predicted return instruction is indirectly related to the sequence number storage feature described in the foregoing embodiments. As described in the foregoing embodiments, each entry in the free list stores a sequence number, which is used to characterize the allocation timing of the stored call instruction in the program execution order. Although the sequence number is not directly used when the predicted return instruction occurs, the storage of the sequence number is of great significance in anomaly recovery scenarios. When the predicted return instruction needs to be rolled back due to a branch misprediction, the entries allocated on the erroneous path can be identified and released through sequence number comparison, ensuring that the prediction stack state is consistent with the correct execution path. The writing operation of this sequence number has been completed in the predicted call instruction processing in step 302, and will not be described again here.

[0061] In this embodiment, the stack top read pointer update operation described in the foregoing embodiments provides a foundation for the subsequent return instruction retirement step. When a return instruction is actually retired, it is necessary to determine that the return instruction corresponding to the popped entry has completed retirement, thereby updating the entry's state to idle. At this time, the updated stack top read pointer can be used to locate the entry position corresponding to the retired return instruction.

[0062] Step 304: In response to the return instruction retiring, update the status of the entry corresponding to the return instruction in the free list to free.

[0063] The free list is used to dynamically manage the allocation and release of entries in physical memory, so that entries released when a return instruction retires can be reallocated by subsequent predictive call instructions. Return instruction retirement refers to the stage in the processor pipeline where a return instruction successfully completes execution and submits its result to the architectural state. When a return instruction retires, the prediction stack entry corresponding to that instruction is logically no longer needed, and the physical memory resources it occupies can be released for reallocation by subsequent predictive call instructions.

[0064] In one embodiment, the retirement process for a return instruction involves updating the status of the popped entry in the free list to free and dynamically maintaining the stack bottom pointer. Specifically, when a return instruction retires, the position of the prediction stack entry corresponding to that return instruction is first determined. This entry position is the entry pointed to by the TopRd pointer read from the top of the stack during the prediction execution phase of the return instruction, which is the entry popped when predicting the return instruction in the aforementioned embodiment. The valid bit corresponding to this entry in the free list FreeList is pulled high to mark that the entry has been released and can be reallocated for subsequent prediction call instructions. Through this operation, precise release and dynamic reclamation of prediction stack entries are achieved.

[0065] In one embodiment, the stack bottom pointer still needs to be dynamically maintained after the return instruction retires. Specifically, after step 304, it can be determined whether the entry pointed to by the stack bottom pointer (Bottom) has been released. The stack bottom pointer points to the logically earliest allocated and not yet released entry in the physical storage space. If the entry pointed to by the stack bottom pointer has been released, the target entry is searched in the physical storage space, and the stack bottom pointer is updated to the target entry. The Prev pointer of the target entry is equal to the entry currently pointed to by the stack bottom pointer. Thus, by determining whether the entry pointed to by the stack bottom pointer has been released after the return instruction retires, and if it has been released, searching in the physical storage space for the target entry whose Prev pointer is equal to the entry currently pointed to by the stack bottom pointer, and updating the stack bottom pointer to the target entry, the accuracy of the stack bottom pointer is dynamically maintained, providing a reliable basis for subsequent stack full overwrite decisions.

[0066] It's important to note that after updating the status of the entry corresponding to the return instruction to free, it's necessary to determine whether the entry pointed to by the stack bottom pointer (Bottom) has been freed. The stack bottom pointer points to the logically oldest allocated entry in physical memory that hasn't yet been used by the corresponding return instruction. When the entry pointed to by the stack bottom pointer happens to be the one that has been freed in this instance, it means that the oldest entry in the current prediction stack has been removed, and the stack bottom pointer needs to move forward to point to the new oldest entry.

[0067] Furthermore, in the above scenario, it is necessary to search for an entry in the physical storage space PhyStk whose Prev pointer is equal to the entry currently pointed to by the stack bottom pointer. Since the Prev pointer points to a logically earlier allocated entry, the found entry is the logically second-earliest allocated entry (i.e., an entry allocated later than the current stack bottom entry and closer to the stack top), and this entry is used as the new stack bottom pointer. If there is no entry in the physical storage space whose Prev pointer is equal to the current stack bottom pointer, it means that the prediction stack is empty, the stack bottom pointer is updated to the value of the stack top write pointer TopWr, and the prediction stack is marked as idle.

[0068] It should be noted that the dynamic maintenance mechanism of the stack bottom pointer ensures that it always accurately points to the oldest allocated and not yet freed entry in the current prediction stack. This mechanism provides a reliable basis for the stack full overwrite decision when subsequent prediction call instructions occur. When the prediction stack is full, the oldest entry that needs to be overwritten can be accurately located, thus preserving as much valid entry information as possible when the stack is full.

[0069] In one possible implementation, first, the position of the entry corresponding to the retirement return instruction is determined, and the valid bit of that entry in the FreeList is raised to mark that the entry has been released. Then, it is determined whether the entry pointed to by the bottom stack pointer (Bottom) has been released. If it has been released, the entry whose Prev pointer is equal to the entry currently pointed to by the bottom stack pointer (PhyStk) is searched in the physical storage space, and the bottom stack pointer is updated to the found entry. If no such entry exists, the bottom stack pointer is updated to the value of the top stack pointer (TopWr). For ease of understanding, the above process can be referred to as follows: Figure 7 The diagram illustrates an example of the return address prediction stack update process when a return instruction retires.

[0070] It should be noted that the handling of return instruction retirement and the allocation mechanism of predicted call instructions in step 302 form a complete resource management closed loop: when a predicted call instruction occurs, a free entry is allocated from the free list; when a return instruction retires, the corresponding entry is released back to the free list. This mechanism achieves precise dynamic management of prediction stack entries, effectively avoiding the problems of invalid entries occupying space and valid information being prematurely overwritten due to sequential overwriting in traditional schemes. Simultaneously, the dynamic maintenance mechanism of the stack bottom pointer ensures that even in the context of out-of-order allocation and reclamation, the oldest entry can still be accurately identified and located, providing a reliable basis for stack full overwriting decisions.

[0071] The return address prediction stack management method disclosed in the above embodiments of this application first provides a physical storage space for the prediction stack, a free list, and a stack top read pointer. The physical storage space includes multiple entries, each storing a return address and a pointer to the logically next entry. The free list manages the free state of each entry in the physical storage space. Then, in response to a prediction call instruction, a free entry is allocated from the free list, the return address of the prediction call instruction is written to the allocated free entry, and the stack top read pointer is updated. Next, in response to a prediction return instruction, the return address is read from the entry pointed to by the stack top read pointer as the prediction target address, and the stack top read pointer is updated. Finally, in response to a return instruction retirement, the state of the entry corresponding to the return instruction in the free list is updated to free. The free list dynamically manages the allocation and release of entries in the physical storage space, so that entries released when a return instruction retires can be reallocated by subsequent prediction call instructions. Therefore, by providing a free list to manage the free status of each entry in the physical storage space, and updating the status of the corresponding entry to free when the return instruction retires, the prediction stack entries can be accurately released and dynamically reclaimed, thereby avoiding the loss of effective information due to sequential overwriting and improving the utilization rate of the return address prediction stack entries.

[0072] In one possible implementation of this application, the state of the return address prediction stack can also be restored in response to a pipeline interruption. A pipeline interruption refers to a branch misprediction, exception, or interrupt event occurring in the processor pipeline, causing the current instruction flow to need to be rolled back to a correct execution point for re-execution. When a pipeline interruption occurs, the return address prediction stack may contain valid entries allocated based on the incorrect path. These entries need to be precisely released, and the stack top read pointer needs to be restored to the correct state to ensure the accuracy of subsequent predictions.

[0073] In one embodiment, pipeline interrupt recovery can employ a sequence number-based precise recovery mechanism. Specifically, in response to a pipeline interruption, the interrupt instruction type and the backup stack top read pointer can be obtained; based on the interrupt instruction type and the backup stack top read pointer, the current stack top read pointer can be restored; the sequence number of the interrupt instruction can be obtained; the free list can be traversed, and the status of the physical storage space entries corresponding to free list entries with sequence numbers later than the interrupt instruction sequence number can be updated to free. Thus, by obtaining the interrupt instruction sequence number when the pipeline is interrupted and traversing the free list to update the status of the physical storage space entries corresponding to free list entries with sequence numbers later than the interrupt instruction sequence number to free, invalid entries allocated on the wrong path can be precisely released, ensuring that the predicted stack state is consistent with the correct execution path.

[0074] It should be noted that when a pipeline interrupt occurs, the type of the interrupt instruction and the pre-backed stack top read pointer are first obtained. During the prediction of call and return instruction execution, the current stack top read and write pointers are backed up; this backup information is stored in checkpoints for restoring the correct pointer state during exception recovery.

[0075] Furthermore, the current stack top read pointer can be restored in different ways depending on the type of interrupt instruction. Specifically: If the interrupt instruction type is a CALL instruction, the stack top read pointer is restored to its value after the CALL instruction is executed, that is, updated to the TopWr value backed up during prediction of the CALL instruction, which points to the position of the entry pushed by the CALL instruction. If the interrupt instruction type is a RETURN instruction, the stack top read pointer is restored to its value after the RETURN instruction is executed, that is, updated to the entry pointed to by the Prev pointer of the entry backed up during prediction of the RETURN instruction, which points to the new stack top position after the RETURN instruction is popped. If the interrupt instruction is of another type, the stack top read pointer is restored to the value backed up by that instruction.

[0076] After restoring the stack top read pointer, the sequence number of the interrupt instruction (i.e., the fetch block sequence number FBlkId) is obtained. This sequence number is an identifier of the interrupt instruction in the program execution order, used to determine the allocation timing of each predicted stack entry relative to the interrupt instruction. Then, all valid entries in the FreeList (i.e., free list entries corresponding to entries in the occupied state) are traversed, and the sequence number stored in each free list entry is compared with the interrupt instruction's sequence number. For free list entries with a later sequence number than the interrupt instruction's sequence number (i.e., a larger value indicating a later allocation time), the status of the physical storage space entry corresponding to these free list entries is updated to free (i.e., the valid bit of the corresponding free list entry is pulled high). These entries were allocated after the interrupt instruction and on the wrong path, therefore they should be released during restoration.

[0077] After releasing the erroneous path entry, a free scan (FreeScan) is performed based on the restored free list's valid bit state. A free entry is selected and allocated to the top-of-stack write pointer (TopWr) as the push position for the next predicted instruction. This series of operations ensures precise restoration of the prediction stack state, guaranteeing the accuracy of subsequent predictions.

[0078] In one possible implementation, firstly, the stack top read pointer TopRd is restored based on the interrupt instruction type and the backed-up pointer. Then, the interrupt instruction sequence number AbortFBlkId is obtained. All entries in the FreeList are traversed, and the valid bits of the physical memory space entries corresponding to free list entries with sequence numbers later than the interrupt instruction sequence number are pulled high (released). Finally, a free scan FreeScan is performed to update the stack top write pointer TopWr. For ease of understanding, the above process can be referred to as follows: Figure 8 The diagram shows an example of a return address prediction stack update process when a pipeline interruption occurs.

[0079] In one embodiment, pipeline interrupt recovery can also employ an alternative based on linked list traversal, which does not rely on a sequence number field. Specifically, in response to a pipeline interruption, the type of the interrupt instruction and the backup stack top read pointer can be obtained; based on the interrupt instruction type and the backup stack top read pointer, the current stack top read pointer is restored; starting from the entry pointed to by the restored stack top read pointer, the physical memory space is traversed along pointers pointing to the logical next entry, marking the status of traversed entries as occupied; and the status of untraversed entries in the physical memory space is updated to free. Thus, by starting from the entry pointed to by the restored stack top read pointer during a pipeline interruption, traversing the physical memory space along pointers pointing to the logical next entry, marking traversed physical memory space entries as occupied and untraversed entries as free, accurate recovery of the predicted stack state is achieved without relying on a sequence number, reducing dependence on hardware resources.

[0080] When a pipeline interruption occurs, the interrupt instruction type and a pre-backed stack top read pointer are first obtained, and the current stack top read pointer is restored according to the interrupt instruction type. This restoration method is the same as that described in the previous embodiments, and will not be repeated here.

[0081] It should be noted that after restoring the stack top read pointer, recovery can be performed using linked list traversal. Specifically, starting from the entry pointed to by the restored stack top read pointer TopRd, the physical storage space PhyStk is traversed towards the bottom of the stack along the pointer Prev, which is logically the next entry above that entry. During the traversal, the status of all traversed physical storage space entries is marked as occupied (i.e., the valid bit of the corresponding entry is pulled low in the free list). These traversed entries are located in the linked list of the current valid path and are the valid entries corresponding to the correct execution path.

[0082] Specifically, for entries in the physical storage space that have not been traversed (i.e., entries not on the valid path list), the status of these entries is updated to free (i.e., the valid bit of the corresponding entry is pulled high). These entries belong to those allocated on the wrong path but not included in the valid list, and therefore should be released during recovery.

[0083] After the state update is completed, FreeScan can be performed based on the restored free list valid bit status to select a free entry and allocate it to the stack top write pointer TopWr as the push position for the next predicted call instruction after restoration.

[0084] It should be understood that this alternative solution has the same technical effect as the serial number-based recovery solution, but the implementation methods differ: the serial number-based solution relies on serial number field comparison, providing more accurate timing judgment capabilities; the linked list traversal-based solution does not rely on the serial number field, but can identify the effective path solely through the linked list relationship, reducing dependence on hardware storage resources. The two solutions can be selected or combined according to the specific design requirements of the processor.

[0085] It should be noted that the above embodiments together constitute a complete management method for the return address prediction stack. The physical storage space, free list, and stack top read pointer provided in step 301 lay the foundation for dynamic management of the prediction stack; step 302, by allocating free entries from the free list and updating the stack top read pointer when predicting a call instruction, achieves on-demand resource allocation; step 303, by reading the return address from the stack top and updating the stack top read pointer when predicting a return instruction, achieves accurate popping of the stack top; step 304, by releasing the corresponding entry when the return instruction retires, achieves precise resource reclamation; and restoring the prediction stack state when the pipeline is interrupted ensures state consistency under abnormal conditions. These steps work together to form a complete closed-loop management system.

[0086] The return address prediction stack management method disclosed in the above embodiments of this application dynamically manages return address prediction stack entries by introducing a free list, achieving precise release of expired entries and effectively solving the resource utilization efficiency problem under the fixed-order coverage strategy. Specifically, this application maintains the free list state and releases the corresponding entries when the return instruction retires, achieving precise resource management of entries and ensuring active use of the return address prediction stack space; by prioritizing the allocation of released entries to new call instructions, while retaining older information that has not yet been called by return instructions, the return address prediction stack can better adapt to scenarios with frequent inner nested calls; by implementing dynamic recycling of prediction stack entries, the meaningless coverage of valid entries is reduced under the same prediction stack size, thereby improving the hit rate of return address prediction.

[0087] See Figure 9 The diagram shows a schematic of a return address prediction stack management device provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0088] The return address prediction stack management device may specifically include the following modules: The configuration module 901 is used to provide the physical storage space, free list and stack top read pointer of the prediction stack. The physical storage space includes multiple entries, each of which is used to store the return address and a pointer to the logical next entry. The free list is used to manage the free status of each entry in the physical storage space. The first update module 902 is used to respond to the predicted call instruction by allocating a free entry from the free list, writing the return address of the predicted call instruction to the allocated free entry, and updating the stack top read pointer. The second update module 903 is used to read the return address from the entry pointed to by the stack top read pointer as the prediction target address in response to the prediction return instruction, and update the stack top read pointer. The third update module 904 is used to update the status of the entry corresponding to the return instruction in the free list to free in response to the retirement of the return instruction; wherein, the free list is used to dynamically manage the allocation and release of entries in the physical storage space, so that the entries released when the return instruction retires can be reallocated by subsequent predicted call instructions.

[0089] The return address prediction stack management device disclosed in the above embodiments of this application first provides a physical storage space for the prediction stack, a free list, and a stack top read pointer. The physical storage space includes multiple entries, each entry storing a return address and a pointer to the logically next entry. The free list manages the free state of each entry in the physical storage space. Then, in response to a prediction call instruction, a free entry is allocated from the free list, the return address of the prediction call instruction is written to the allocated free entry, and the stack top read pointer is updated. Next, in response to a prediction return instruction, the return address is read from the entry pointed to by the stack top read pointer as the prediction target address, and the stack top read pointer is updated. Finally, in response to a return instruction retirement, the state of the entry corresponding to the return instruction in the free list is updated to free. The free list is used to dynamically manage the allocation and release of entries in the physical storage space so that entries released when a return instruction retires can be reallocated by subsequent prediction call instructions. Therefore, by providing a free list to manage the free status of each entry in the physical storage space, and updating the status of the corresponding entry to free when the return instruction retires, the prediction stack entries can be accurately released and dynamically reclaimed, thereby avoiding the loss of effective information due to sequential overwriting and improving the utilization rate of the return address prediction stack entries.

[0090] Furthermore, in one possible implementation of this application embodiment, the configuration module 901 is specifically used to: maintain a stack top write pointer and a stack bottom pointer, wherein the stack top write pointer points to the entry allocated when the next predicted call instruction is pushed onto the stack, and the stack bottom pointer points to the logically earliest allocated and not yet released entry in the physical storage space.

[0091] The aforementioned return address prediction stack management device may further include the following modules: The overlay processing module is used to determine whether the top write pointer of the stack is equal to the bottom pointer of the stack before allocating a free entry from the free list in response to a predicted call instruction; if the top write pointer of the stack is equal to the bottom pointer of the stack, the target entry is searched in the physical storage space and the bottom pointer of the stack is updated to the target entry, wherein the pointer of the target entry to the logical next entry is equal to the entry currently pointed to by the bottom pointer of the stack.

[0092] Therefore, by maintaining the top and bottom pointers of the stack, and when the top pointer equals the bottom pointer, searching the physical storage space for the target entry whose pointer points to the logical next entry is equal to the current entry pointed to by the bottom pointer, and updating the bottom pointer to that target entry, the system can accurately locate the second-earliest allocated entry in a full stack-overlay scenario, providing an accurate bottom position for overlay decisions.

[0093] Furthermore, in another possible implementation of the embodiments of this application, the configuration module 901 is further used to: maintain a stack bottom pointer, which points to the earliest logically allocated and unreleased entry in the physical storage space; The first update module 902 mentioned above may specifically include the following units: The first processing unit is used to scan the free list and determine whether there is an entry with a free status. If there is an entry with a free status, it selects one of the entries with a free status as the free entry to be allocated. If there is no entry with a free status, it uses the entry currently pointed to by the bottom pointer of the stack as the free entry to be allocated.

[0094] Therefore, by scanning the free list to determine if there are any free entries, allocation is made from the free entries if they exist, and the entry pointed to by the stack bottom pointer is used as the allocation object if they do not exist. This prioritizes the use of released resources and only overwrites the earliest allocated entry when the stack is full, thus optimizing the resource allocation order.

[0095] Furthermore, in another possible implementation of this application embodiment, each entry in the free list is also used to store a sequence number, which is used to characterize the allocation timing of the calling instructions stored in the corresponding physical storage space entry in the program execution order; the above-mentioned return address prediction stack management device may further include the following modules: The sequence number binding module is used to write the sequence number of the predicted call instruction into the sequence number field corresponding to the allocated free entry in response to the predicted call instruction.

[0096] Therefore, by storing the value block sequence number for each entry in the free list and writing the sequence number into the sequence number field corresponding to the allocated free entry when predicting the call instruction, a binding relationship is established between each physical storage space entry and the allocation timing of the instruction, thereby providing a basis for identifying the timeliness of the entry during abnormal recovery.

[0097] Furthermore, in another possible implementation of this application embodiment, the above-mentioned return address prediction stack management device may further include the following modules: The first recovery module is used to respond to pipeline interruptions by obtaining the type of the interrupt instruction and the backup stack top read pointer; restoring the current stack top read pointer based on the type of the interrupt instruction and the backup stack top read pointer; obtaining the sequence number of the interrupt instruction; traversing the free list and updating the status of the physical storage space entries corresponding to the free list entries with sequence numbers later than the interrupt instruction sequence number to free.

[0098] Therefore, by obtaining the sequence number of the interrupt instruction when the pipeline is interrupted, and traversing the free list, the status of the physical storage space entry corresponding to the free list entry with a sequence number later than the interrupt instruction sequence number is updated to free, thereby accurately releasing invalid entries allocated on the wrong path and ensuring that the predicted stack state is consistent with the correct execution path.

[0099] Furthermore, in another possible implementation of this application embodiment, the above-mentioned return address prediction stack management device may further include the following modules: The second recovery module is used to respond to pipeline interruptions by obtaining the type of the interrupt instruction and the backup stack top read pointer; restoring the current stack top read pointer based on the type of the interrupt instruction and the backup stack top read pointer; traversing the physical storage space from the entry pointed to by the restored stack top read pointer, following the pointer pointing to the logical next entry, marking the status of the traversed entries as occupied; and updating the status of the untraversed entries in the physical storage space to free.

[0100] Therefore, by reading the entry pointed to by the pointer at the top of the restored stack when the pipeline is interrupted, and traversing the physical storage space along the pointer pointing to the next logical entry, the traversed physical storage space entries are marked as occupied and the untraversed entries are marked as free, so as to achieve accurate recovery of the predicted stack state without relying on the sequence number, and reduce the dependence on hardware resources.

[0101] Furthermore, in another possible implementation of this application embodiment, the above-mentioned return address prediction stack management device may further include the following modules: The stack bottom pointer maintenance module is used to determine whether the entry pointed to by the stack bottom pointer has been released after updating the status of the entry corresponding to the return instruction in the free list to free in response to the retirement of the return instruction. The stack bottom pointer points to the logically earliest allocated and not released entry in the physical storage space. If the entry pointed to by the stack bottom pointer has been released, the target entry is searched in the physical storage space and the stack bottom pointer is updated to the target entry. The pointer of the target entry to the logical next entry is equal to the entry currently pointed to by the stack bottom pointer.

[0102] Therefore, by determining whether the entry pointed to by the stack bottom pointer has been released after the return instruction retires, if it has been released, the pointer pointing to the next logical entry in the physical storage space is found to be equal to the target entry of the current stack bottom pointer, and the stack bottom pointer is updated to the target entry, thereby dynamically maintaining the accuracy of the stack bottom pointer and providing a reliable basis for subsequent stack full overwrite decisions.

[0103] The return address prediction stack management device provided in this application embodiment can be applied in the foregoing method embodiment. For details, please refer to the description of the above method embodiment, which will not be repeated here.

[0104] Figure 10 This is a schematic diagram of the structure of the electronic device provided in an embodiment of this application. For example... Figure 10 As shown, the electronic device 1000 of this embodiment includes: at least one processor 1010 ( Figure 10 The diagram shows only one processor, a memory 1020, and a computer program 1021 stored in the memory 1020 and executable on the at least one processor 1010. When the processor 1010 executes the computer program 1021, it implements the steps in the above-described return address prediction stack management method embodiment.

[0105] The electronic device 1000 can be a desktop computer, laptop, handheld computer, cloud server, or other computing device. This electronic device may include, but is not limited to, a processor 1010 and a memory 1020. Those skilled in the art will understand that... Figure 10 This is merely an example of electronic device 1000 and does not constitute a limitation on electronic device 1000. It may include more or fewer components than shown, or combine certain components, or different components. For example, it may also include input / output devices, network access devices, etc.

[0106] The processor 1010 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0107] In some embodiments, the memory 1020 may be an internal storage unit of the electronic device 1000, such as a hard disk or memory of the electronic device 1000. In other embodiments, the memory 1020 may be an external storage device of the electronic device 1000, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the electronic device 1000. Furthermore, the memory 1020 may include both internal and external storage units of the electronic device 1000. The memory 1020 is used to store operating systems, applications, boot loaders, data, and other programs, such as the program code of computer programs. The memory 1020 can also be used to temporarily store data that has been output or will be output.

[0108] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0109] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0110] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0111] In the embodiments provided in this application, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0112] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0113] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0114] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0115] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on an electronic device, the electronic device can implement the steps in the various method embodiments described above.

[0116] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A return address prediction stack management method, characterized in that, include: Provides physical storage space, free list and stack top read pointer for prediction stack, wherein the physical storage space includes multiple entries, each entry is used to store the return address and a pointer to the logical next entry, and the free list is used to manage the free status of each entry in the physical storage space; In response to a predicted call instruction, a free entry is allocated from the free list, the return address of the predicted call instruction is written to the allocated free entry, and the stack top read pointer is updated. In response to the predicted return instruction, the return address is read from the entry pointed to by the stack top read pointer as the predicted target address, and the stack top read pointer is updated. In response to the retirement of a return instruction, the status of the entry corresponding to the return instruction in the free list is updated to free; wherein, the free list is used to dynamically manage the allocation and release of entries in the physical storage space, so that the entries released when the return instruction retires can be reallocated by subsequent predicted call instructions.

2. The method according to claim 1, characterized in that, Before allocating a free entry from the free list in response to a predicted invocation instruction, the method further includes: Maintain a top write pointer and a bottom pointer. The top write pointer points to the entry allocated when the next predicted call instruction is pushed onto the stack, and the bottom pointer points to the earliest logically allocated and unreleased entry in the physical storage space. Determine whether the top stack pointer is equal to the bottom stack pointer; When the top write pointer of the stack is equal to the bottom pointer of the stack, the target entry is searched in the physical storage space, and the bottom pointer of the stack is updated to the target entry, wherein the pointer of the target entry to the logical next entry is equal to the entry currently pointed to by the bottom pointer of the stack.

3. The method according to claim 1, characterized in that, The method further includes: Maintain a stack bottom pointer, which points to the earliest logically allocated and not yet released entry in the physical storage space; The allocation of free entries from the free list includes: Scan the free list to determine if there are any entries with a free status; If there are entries in the free state, then select one from the entries in the free state as the free entry to be assigned; If there is no free entry, the entry currently pointed to by the bottom pointer of the stack will be used as the free entry to be allocated.

4. The method according to claim 1, characterized in that, Each entry in the free list is also used to store a sequence number, which represents the allocation timing of the call instructions stored in the corresponding physical storage space entry in the program execution order; the method further includes: In response to a predicted invocation instruction, the sequence number of the predicted invocation instruction is written into the sequence number field corresponding to the allocated free entry.

5. The method according to claim 4, characterized in that, The method further includes: In response to a pipeline interrupt, obtain the type of the interrupt instruction and the backed-up stack top read pointer; Based on the type of the interrupt instruction and the backed-up stack top read pointer, restore the current stack top read pointer; Obtain the sequence number of the interrupt instruction; Traverse the free list and update the status of the physical storage space entries corresponding to free list entries whose serial numbers are later than the serial number of the interrupt instruction to free.

6. The method according to claim 1, characterized in that, The method further includes: In response to a pipeline interrupt, obtain the type of the interrupt instruction and the backed-up stack top read pointer; Based on the type of the interrupt instruction and the backed-up stack top read pointer, restore the current stack top read pointer; Starting from the entry pointed to by the restored stack top read pointer, the physical storage space is traversed along the pointer pointing to the logical next entry, and the status of the traversed entries is marked as occupied. Update the status of unvisited entries in the physical storage space to free.

7. The method according to claim 1, characterized in that, After responding to the return instruction to retire and updating the status of the entry corresponding to the return instruction to idle in the idle list, the method further includes: Determine whether the entry pointed to by the stack bottom pointer has been released, wherein the stack bottom pointer points to the logically earliest allocated and not released entry in the physical storage space; If the entry pointed to by the stack bottom pointer has been released, the target entry is searched in the physical storage space, and the stack bottom pointer is updated to the target entry, wherein the pointer of the target entry to the logical next entry is equal to the entry currently pointed to by the stack bottom pointer.

8. A return address prediction stack management device, characterized in that, include: The configuration module is used to provide the physical storage space, free list and stack top read pointer of the prediction stack. The physical storage space includes multiple entries, each entry is used to store the return address and a pointer to the logical next entry, and the free list is used to manage the free status of each entry in the physical storage space. The first update module is used to, in response to the predicted call instruction, allocate a free entry from the free list, write the return address of the predicted call instruction into the allocated free entry, and update the stack top read pointer; The second update module is used to read the return address from the entry pointed to by the stack top read pointer as the prediction target address in response to the prediction return instruction, and update the stack top read pointer. The third update module is used to update the status of the entry corresponding to the return instruction to free in the free list in response to the retirement of the return instruction; wherein, the free list is used to dynamically manage the allocation and release of entries in the physical storage space, so that the entries released when the return instruction retires can be reallocated by subsequent predicted call instructions.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when run on an electronic device, causes the electronic device to perform the method as described in any one of claims 1 to 7.

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