A pixel driving circuit, a display panel, and a display device

Abstract

This disclosure provides a pixel driving circuit, a display panel, and a display device, relating to the field of display technology. The gate of a driving transistor is connected to a first node, a first terminal of a first storage module is connected to the first node, and a second terminal is connected to a second node. The first electrode of the driving transistor is connected to a first power supply voltage terminal, and the second electrode of the driving transistor is connected to a third node. The third node is electrically connected to a light-emitting element. A first reset module is connected between a first reset signal terminal and the first node, and a second reset module is connected between a second reset signal terminal and the second node. In the first reset phase, the first and second reset modules are configured to be simultaneously turned on, resetting the first and second nodes respectively. This improves the display effect. The pixel driving circuit's operating phases include a time-division multiplexing first reset phase, a threshold compensation phase, and a data writing phase; this helps stabilize the gate potential of the driving transistor and improve the light emission accuracy of the light-emitting element.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a display panel, and a display device. Background Technology

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0003] In practical applications, by writing data signals line by line to the pixel driving circuit of a display product, the display product can perform corresponding displays according to preset data signals. However, with the increasing demands for higher resolution and higher frequency, the design of pixel circuits faces new challenges. In applications with higher resolution and higher frequency, ensuring that the light-emitting elements can emit light according to the preset effect without being affected by other factors, thereby improving the display effect, is one of the technical problems that urgently need to be solved at this stage. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a pixel driving circuit, a display panel, and a display device, which helps to stabilize the gate potential of the driving transistor and improve the light emission accuracy of the light-emitting element.

[0005] In a first aspect, this disclosure provides a pixel driving circuit for driving a light-emitting element, including a driving transistor, a threshold compensation module, a data writing module, a first reset module, a second reset module, and a first storage module. The gate of the driving transistor is connected to a first node, and a first terminal of the first storage module is connected to the first node, while a second terminal is connected to a second node. The first electrode of the driving transistor is connected to a first power supply voltage terminal, and the second electrode of the driving transistor is connected to a third node, which is electrically connected to the light-emitting element. The pixel driving circuit operates in three phases: a time-division multiplexing first reset phase, a threshold compensation phase, and a data writing phase. The first reset module is connected between a first reset signal terminal and the first node, and the second reset module is connected between the second reset signal terminal and the second node. In the first reset phase, the first and second reset modules are configured to be simultaneously turned on to reset the first and second nodes, respectively. The threshold compensation module is connected between the first and third nodes and is configured to provide a first power supply voltage signal from the first power supply voltage terminal to the gate of the driving transistor during the threshold compensation phase to perform threshold compensation on the driving transistor. The data writing module is connected between a data signal terminal and the second node and is configured to provide a data signal from the data signal terminal to the second node during the data writing phase.

[0006] Secondly, based on the same inventive concept, this disclosure provides a display panel including the pixel driving circuit provided in the first aspect.

[0007] Thirdly, based on the same inventive concept, this disclosure provides a display device, including the display panel provided in the second aspect of this disclosure.

[0008] The technical solution provided in this disclosure has the following advantages compared with the prior art: In the pixel driving circuit provided in this embodiment, a first storage module is introduced between the first node and the second node, and a first reset module is introduced for the first node, and a second reset module is introduced for the second node. During the first reset stage, the first and second reset modules are simultaneously turned on. The first reset module resets the first node, and the second reset module resets the second node simultaneously. This allows the first and second nodes to be reset to their respective reference voltages simultaneously. Thus, when the first node is reset, the second node is also reset to a fixed potential, thereby avoiding the problem of the first node's potential changing due to potential coupling with the second node, which helps ensure that the first node maintains an accurate reset potential. When the first node maintains an accurate reset potential, the driving transistor can be fully turned on, thereby greatly improving the efficiency and sufficiency of the driving transistor during the threshold compensation stage. Therefore, by simultaneously resetting the first and second nodes, the potential of the first node is ensured to remain a stable fixed potential before the threshold compensation stage, which helps improve the stability and high precision of the subsequent threshold compensation process, thereby improving the accuracy of the driving current.

[0009] Furthermore, since the threshold compensation process and the data writing process are performed separately in this disclosure, that is, the data writing process and the threshold compensation process are completely isolated. During the threshold compensation stage, the data writing module is disconnected, making the threshold compensation process more independent and unaffected by the data writing process. The signal at the first power supply voltage terminal can effectively and quickly write charge to the first node. Through threshold compensation, the potential of the first node can be stabilized at a preset potential, thereby completely eliminating the coupling interference of the data writing process on the threshold compensation process, ensuring the accuracy of threshold voltage capture and the potential stability of the first node. Since the potential of the first node is already stable, the data signal can be accurately written during the data writing stage. This allows the potential of the first node to reach or be closer to the expected potential after the data writing stage and before the subsequent light emission stage, which is beneficial to improving the light emission accuracy of the light-emitting element and thus improving the display effect. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a circuit diagram of a pixel driving circuit in related technologies; Figure 2 As shown Figure 1 A timing diagram of a corresponding pixel driving circuit; Figure 3 The diagram shown is a schematic diagram of a pixel driving circuit provided in an embodiment of this disclosure; Figure 4 The diagram shown is a timing diagram of a pixel driving circuit provided in an embodiment of this disclosure; Figure 5 The diagram shown is another schematic diagram of a pixel driving circuit provided in an embodiment of this disclosure; Figure 6 The diagram shown is another schematic diagram of a pixel driving circuit provided in an embodiment of this disclosure; Figure 7 The diagram shown is another schematic diagram of a pixel driving circuit provided in an embodiment of this disclosure; Figure 8 The diagram shown is another schematic diagram of a pixel driving circuit provided in an embodiment of this disclosure; Figure 9 The diagram shown is another schematic diagram of a pixel driving circuit provided in an embodiment of this disclosure; Figure 10 The diagram shown is a schematic diagram of a pixel driving circuit provided in an embodiment of this disclosure. Figure 11 The image shown is a plan view of a display panel provided in an embodiment of this disclosure; Figure 12 The diagram shown is a structural schematic of a display device 200 provided in an embodiment of this disclosure. Detailed Implementation

[0013] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0014] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0015] Figure 1 This is a circuit diagram of a pixel driving circuit in related technologies. Please refer to it. Figure 1 The pixel driving circuit includes transistors T1-T7 and a capacitor C. Transistor T3 is a driving transistor used to provide driving current to the light-emitting element D. The gate, first terminal, and second terminal of driving transistor T3 are connected to the first node N01, the third node N03, and the second node N02, respectively. Transistor T5 is the aforementioned first reset transistor. Its first terminal and second terminal are connected to the first reset signal terminal Vref01 and the first node N01, respectively. Its gate is connected to the first control signal terminal S1N to receive a reset control signal. Transistor T5 provides a gate reset signal to the first node N01, namely the first reset voltage signal and the second reset voltage signal mentioned in the previous embodiment. Transistor T2 is a data writing transistor. Its first terminal and second terminal are connected to the data voltage signal terminal Source and the second node N02, respectively. Its gate receives the control signal SP. Data writing transistor T2 transmits the data voltage signal Source to the second node N02. It should be noted that in the embodiments of this disclosure, the signal terminals and the signals transmitted by the signal terminals are represented by the same reference numerals. Transistor T4 has its first and second terminals connected to the third node N03 and the first node N01, respectively. Its gate is connected to the second control signal terminal S2N to receive the control signal S2N. Transistor T4 is used for threshold compensation of transistor T3. Transistor T7 has its first and second terminals connected to the anode reset signal terminal Vref02 and the first terminal of the light-emitting element D, respectively. Its gate is connected to the control signal terminal SPX. Transistor T7 is used to reset the first terminal (e.g., the anode) of the light-emitting element D. Transistor T1 has its first and second terminals connected to the first power supply signal terminal PVDD and the second node N02, respectively. Its gate is connected to the light-emitting control signal terminal Emit. Transistor T6 has its first and second terminals connected to the third node N03 and the first terminal of the light-emitting element D, respectively. Its gate is connected to the light-emitting control signal terminal Emit, and it is used to transmit the drive current to the light-emitting element D. The second terminal of the light-emitting element D receives the second power supply signal PVEE.

[0016] Figure 2 As shown Figure 1 A corresponding timing diagram of the pixel driving circuit will be shown below. Figure 2 right Figure 1The working principle is explained below. The specific workflow of the pixel driving circuit includes the initialization stage t1, the threshold compensation and data writing stage t2, the anode reset stage t3, and the light emission stage t4.

[0017] During the initialization phase t1, the high-potential signal of the first control signal S1N controls the transistor T5 to turn on, transmitting the gate reset signal Vref1 to the control terminal of the transistor T3 for initialization.

[0018] During the threshold compensation and data writing stage t2, transistor T5 is turned off, control signal SP controls transistor T2 to turn on, and the second control signal S2N controls transistor T4 to turn on. The data voltage signal Vdata is written to transistor T3 through transistor T2. Transistor T4 is connected between the gate and the first electrode of transistor T3, and can capture the threshold voltage of transistor T3 to the gate of transistor T3 to achieve threshold voltage compensation and self-compensate the deviation of the threshold voltage of the driving transistor.

[0019] During the anode reset phase, the control signal SPX controls the transistor T7 to turn on, and the anode reset signal Vref2 is transmitted to the anode of the light-emitting element D through the transistor T7 to reset the light-emitting element D.

[0020] During the light-emitting stage t4, transistors T2, T4, T5, and T7 are all off, while transistors T1, T3, and T6 are all on. The driving current is transmitted to the first electrode of the light-emitting element D, and the light-emitting element D emits light.

[0021] It is evident that in the pixel driving circuit of related technologies, threshold compensation and data writing occur simultaneously. Figure 1 For example, during the threshold compensation and data writing stage t2, transistor T4 is turned on to attempt to stabilize the potential of the first node. Simultaneously, transistor T2 is turned on to write data signals to the second node. Because of the capacitor C between the first and second nodes, voltage fluctuations and jumps when the data signal is written to the second node N02 will couple to the first node through capacitor C, interfering with the ongoing threshold compensation process. This coupling interference makes the potential of the first node unstable, thus reducing the accuracy of the threshold voltage capture. If the threshold voltage compensation result is affected by the data writing, the final drive current will not be able to accurately eliminate the threshold voltage bias of the drive transistor, leading to a potential deviation in the first node. This severely reduces the driving accuracy of the pixel drive circuit, affecting the final display effect.

[0022] Therefore, this disclosure provides a new pixel driving circuit, please refer to the following for details. Figure 3 , Figure 3 The diagram shown is a schematic representation of a pixel driving circuit provided in an embodiment of this disclosure. Figure 4The diagram shown is a timing diagram of a pixel driving circuit provided in an embodiment of this disclosure. Please refer to it. Figure 3 and Figure 4 The pixel driving circuit 00 provided in this embodiment is used to drive the light-emitting element D0. The pixel driving circuit 00 includes a driving transistor DT, a threshold compensation module 11, a data writing module 12, a first reset module 21, a second reset module 22, and a first storage module 31. The gate of the driving transistor DT is connected to the first node N1, the first end of the first storage module 31 is connected to the first node N1, and the second end is connected to the second node N2. The first electrode of the driving transistor DT is connected to the first power supply voltage terminal PVDD, and the second electrode of the driving transistor DT is connected to the third node N3. The third node N3 is electrically connected to the light-emitting element D0. The working stages of the pixel driving circuit 00 include a first reset stage t01, a threshold compensation stage t02, and a data writing stage t03, all executed in a time-division manner.

[0023] The first reset module 21 is connected between the first reset signal terminal Vref1 and the first node N1, and the second reset module 22 is connected between the second reset signal terminal Vref2 and the second node N2. During the first reset phase, the first reset module 21 and the second reset module 22 are configured to be turned on simultaneously to reset the first node N1 and the second node N2 respectively.

[0024] The threshold compensation module 11 is connected between the first node N1 and the third node N3. The threshold compensation module 11 is configured to provide the first power supply voltage signal provided by the first power supply voltage terminal PVDD to the gate of the driving transistor DT during the threshold compensation stage t02, so as to perform threshold compensation on the driving transistor DT.

[0025] The data writing module 12 is connected between the data signal terminal Vdata and the second node N2. The data writing module 12 is configured to provide the data signal of the data signal terminal Vdata to the second node N2 during the data writing stage t03.

[0026] In the pixel driving circuit provided in this embodiment, the first reset stage t01, the threshold compensation stage t02, and the data writing stage t03 are executed in a time-division manner. For example, the first reset stage t01 is executed first, the threshold compensation stage t02 is executed after the first reset stage t01 is completed, and the data writing stage t03 is executed after the threshold compensation stage t02 is completed.

[0027] In this pixel driving circuit 00, a first storage module 31 is introduced between the first node N1 and the second node N2, and a first reset module 21 is introduced for the first node N1, and a second reset module 22 is introduced for the second node N2. During the first reset phase t01, the first reset module 21 and the second reset module 22 are simultaneously turned on. The first reset module 21 resets the first node N1, and the second reset module 22 resets the second node N2. This allows the first node N1 and the second node N2 to be reset to their respective reference voltages simultaneously. Thus, when the first node N1 is reset, the second node N2 is also reset to a fixed potential, thereby avoiding the problem of the potential of the first node N1 changing due to potential coupling with the second node N2, which helps ensure that the first node N1 maintains an accurate reset potential. When the first node N1 maintains an accurate reset potential, the driving transistor DT can be fully turned on, thereby greatly improving the efficiency and sufficiency of the driving transistor DT during the threshold compensation phase t02. Therefore, by simultaneously resetting the first node N1 and the second node N2, the potential of the first node N1 is ensured to remain at a stable fixed potential before the threshold compensation stage. This is beneficial to improving the stability and high precision of the subsequent threshold compensation process, thereby improving the accuracy of the driving current.

[0028] Furthermore, since the threshold compensation process and the data writing process are performed separately in this disclosure, that is, the data writing process and the threshold compensation process are completely isolated. During the threshold compensation stage, the data writing module 12 is disconnected, making the threshold compensation process more independent and unaffected by the data writing process. The signal of the first power supply voltage terminal PVDD can effectively and quickly write charge to the first node N1. Through threshold compensation, the potential of the first node N1 can be stabilized at the preset potential, thereby completely eliminating the coupling interference of the data writing process on the threshold compensation process, ensuring the accuracy of threshold voltage capture and the potential stability of the first node N1. Since the potential of the first node N1 is already stable, the data signal can be accurately written during the data writing stage. This allows the potential of the first node N1 to reach or be closer to the expected potential after the data writing stage and before the subsequent light emission stage t04, which is beneficial to improving the light emission accuracy of the light-emitting element and thus improving the display effect.

[0029] Furthermore, in the pixel driving circuit provided in this embodiment, since the potential of the first node N1 is reset simultaneously with the potential of the second node N2, the potential of the first node N1 will not be coupled and will not jump. The driving transistor DT can be fully turned on in the subsequent threshold compensation stage, ensuring that the signal at the first power supply voltage terminal can effectively and quickly write charge to the first node N1. In high-frequency or high-refresh-rate scenarios, the compensation efficiency is crucial due to the short threshold compensation time. A fully turned-on driving transistor DT allows the pixel driving circuit to complete threshold compensation to the maximum extent within a limited compensation time. The efficiency and accuracy of the compensation process are effectively improved, and the potential stored in the first node N1 can more accurately reflect the relationship between the data signal and the threshold voltage. This is beneficial for improving the uniformity and accuracy of the displayed image in high-frequency application scenarios, thus enhancing the display effect.

[0030] Please continue to refer to this. Figure 3 and Figure 4 In one optional embodiment of this disclosure, the control terminals of the first reset module 21 and the second reset module 22 are connected to the same first control signal terminal S1. In the first reset stage t01, the first reset module 21 and the second reset module 22 are turned on in response to the control signal of the first control signal terminal S1.

[0031] When the control terminals of the first reset module 21 and the second reset module 22 are connected to the same first control signal terminal S1, and the signal from the same first control signal terminal S1 controls the simultaneous on / off of the first reset module 21 and the second reset module 22, the reset process of the first reset module 21 on the first node N1 and the reset process of the second reset module 22 on the second node N2 are perfectly synchronized in time. This design eliminates the need to introduce different control signal terminals and corresponding control signal lines for the first reset module 21 and the second reset module 22. In actual wiring and manufacturing, two independent control signal lines may experience timing misalignment due to differences in resistance, capacitance, and delay. Using a single first control signal terminal S1 to drive the modules completely eliminates the risk of misalignment, ensures the reliability of the circuit operation, simplifies the circuit design, enhances the stability of the pixel driving circuit, and simplifies the complexity of panel wiring when applied to display products.

[0032] Furthermore, since the first reset module 21 and the second reset module 22 are connected to the same first control signal terminal, the reset processes of the first node N1 and the second node N2 are completely synchronized. Simultaneously, when the first node N1 is reset to a reference potential, the second node N2 is also reset to a stable potential. Because the potential of the second node N2 is stable, its potential will not jump during the subsequent threshold compensation stage, thus preventing coupling interference to the potential of the first node N1. This effectively ensures the accuracy of the potential of the first node N1, avoids coupling and changes in the first node N1, and ensures that the driving transistor DT can be fully turned on during the threshold compensation stage, effectively improving the efficiency and accuracy of compensation.

[0033] Therefore, in this embodiment, the first node N1 and the second node N2 are reset using the same first control signal terminal, achieving optimal synchronization. This design not only simplifies the control structure of the pixel circuit, but more importantly, it completely eliminates node coupling crosstalk during the reset phase, ensuring high precision and stability of the first node N1 potential, thereby effectively improving the driving accuracy and display effect of the entire pixel driving circuit in high-frequency, short-time-sequence applications.

[0034] The above embodiments are only illustrated by the example of the control terminals of the first reset module 21 and the second reset module 22 being connected to the same control signal terminal. However, this disclosure is not limited to this. In some other embodiments of this disclosure, the two modules can be connected to different control signal terminals. For example, please refer to [reference needed]. Figure 5 , Figure 5 The diagram shows another module schematic of the pixel driving circuit provided in an embodiment of this disclosure. In an optional embodiment of this disclosure, the control terminal of the first reset module 21 is connected to the first control signal terminal S1, and the control terminal of the second reset module 22 is connected to the second control signal terminal S0; in the first reset stage, the first reset module 21 is turned on in response to the signal of the first control signal terminal S1, and the second reset module 22 is turned on in response to the signal of the second control signal terminal S0.

[0035] When the control terminals of the first reset module 21 and the second reset module 22 are connected to different control signal terminals, the first control signal terminal S1 sends a conduction signal to drive the first reset module 21 to conduct, and the second control signal terminal S0 also sends a conduction signal to drive the second reset module 22 to conduct. Therefore, simultaneous reset of the first node N1 and the second node N2 can be achieved. Synchronous reset of the first node N1 and the second node N2 avoids the coupling effect of their potentials, preventing potential jumps in the second node N2 during the threshold compensation stage that could affect the potential of the first node N1. This also helps improve the efficiency and accuracy of compensation, effectively enhancing the potential accuracy of the first node N1. Furthermore, connecting the control terminals of the first reset module 21 and the second reset module 22 to different control signal terminals allows for greater flexibility in timing, adapting to different panel characteristics.

[0036] In practical applications, when the transistors contained in the first reset module 21 and the second reset module 22 are of the same type, such as both being P-type transistors, the control terminals of the first reset module 21 and the second reset module 22 can be connected to the same control signal terminal. When the transistors contained in the first reset module 21 and the second reset module 22 are of different types, such as one containing a P-type transistor and the other containing an N-type transistor, the control terminals of the first reset module 21 and the second reset module 22 can be connected to different control signal terminals.

[0037] Figure 6 The diagram shown is another schematic representation of a pixel driving circuit provided in an embodiment of this disclosure. Please refer to [the diagram / illustration]. Figure 6 In one optional embodiment of this disclosure, the pixel driving circuit 00 further includes a third reset module 23. The third reset module 23 is connected between the third reset signal terminal Vref0 and the second node N2. The third reset module 23 is configured to reset the second node N2 in a third reset phase, which overlaps with the threshold compensation phase. This means that in the threshold compensation phase, the second node N2 no longer depends solely on a single reset in the first reset phase, but can be locked at a stable reference potential through the third reset phase.

[0038] This embodiment introduces a third reset module 23 to continuously clamp the potential of the second node N2, thereby maximizing the stability and sufficiency of the first node N1 during the critical threshold compensation phase. Even if the first node N1 and the second node N2 are synchronously reset during the first reset phase, during the threshold compensation phase, the signal at the first power supply voltage terminal is written to the first node N1 through the conducting drive transistor DT. Minor changes in the potential of the first node N1 may be reverse-coupled to the second node N2. As a storage node, the potential of the second node N2 may experience slight drift due to parasitic capacitance coupling from the first power supply voltage signal, control lines, and other signal lines. This embodiment introduces the third reset module 23, which is turned on during the threshold compensation phase. This ensures that the potential of the second node N2 is continuously locked at the reference potential, completely eliminating any minor potential drift that may occur during the threshold compensation phase due to floating. The stability of the second node N2's potential minimizes any coupling interference it causes to the first node N1 (which is undergoing threshold compensation) through the first storage module 31. In a stable environment where the potential of the first node N1 is undisturbed, the driving transistor DT can more accurately and efficiently capture the threshold voltage onto the first node N1.

[0039] Therefore, this embodiment provides a dual protection mechanism for the second node N2. A reset synchronization is completed in the first reset phase, and then continuous clamping is performed through the third reset module 23 in the third reset phase. This significantly improves the anti-interference capability and compensation accuracy of the pixel driving circuit under high frequency and short timing, which is more conducive to improving the display quality.

[0040] Please continue to refer to this. Figure 6 and Figure 4 In one optional embodiment of this disclosure, the third reset stage and the threshold compensation stage t02 coincide. That is, the timing of controlling the turn-on and turn-off of the third reset module 23 is consistent with the timing of controlling the turn-on and turn-off of the threshold compensation module 11. When the pixel driving circuit enters the threshold compensation stage, the threshold compensation module 11 is turned on to compensate the first node N1. Simultaneously, the third reset module 23 is turned on to clamp the potential of the second node N2 to the reference potential. This completely coincident timing design, while maintaining all the advantages of the aforementioned embodiments, further optimizes the anti-interference capability of the compensation process and the simplicity of the timing design. Throughout the threshold compensation stage, the second node N2 is precisely and continuously clamped to a stable reference potential. Since the potential of the second node N2 has no floating time during the threshold compensation stage, it is not subject to reverse coupling from the potential change of the first node N1, nor is it subject to parasitic coupling interference from other signal lines and power supplies. The stability of the second node N2 potential allows the first node N1 to complete compensation in a clean, interference-free environment. This maximizes the accuracy and efficiency of threshold compensation.

[0041] Therefore, in this embodiment, the third reset stage is set to completely overlap with the threshold compensation stage. By maximizing the stability of the potential of the second node N2, all coupling interference that the first node N1 may be affected by during the threshold compensation process is eliminated, which greatly improves the accuracy and sufficiency of threshold compensation under high frequency and short timing, and ultimately ensures the driving accuracy and display uniformity of the pixel driving circuit.

[0042] Please continue to refer to this. Figure 6 In one optional embodiment of this disclosure, the control terminals of the third reset module 23 and the threshold compensation module 11 are connected to the same control signal terminal S2. During the threshold compensation stage, the third reset module 23 and the threshold compensation module 11 are configured to be turned on under the control of the same control signal.

[0043] This embodiment uses a single control signal terminal and a single physical signal line to simultaneously control the third reset module 23 and the threshold compensation module 11. During the threshold compensation stage, when the control signal at the control signal terminal is an on signal, the threshold compensation module 11 is turned on, causing the driving transistor DT to enter self-compensation mode. Simultaneously, the third reset module 23 is turned on, continuously clamping the potential of the second node N2 at the spinal potential. Since the threshold compensation module 11 and the third reset module 23 are controlled by the same signal, their on and off states are completely synchronized. This ensures that the second node N2 is locked at the reference potential precisely throughout the entire threshold compensation stage. The stable potential of the second node N2 completely isolates any interference from the second node N2 to the first node N1, allowing the first node N1 to operate in a clean and stable environment to the maximum extent when performing threshold voltage capture. This enables the driving transistor DT to complete threshold compensation with the highest precision, ensuring that the potential of the first node N1 can reach the expected value within a short time, thus improving the accuracy of the first node N1 potential and the driving precision.

[0044] Compared to using two control signal terminals and two independent synchronization signal lines, the single-signal control of the threshold compensation module 11 and the third reset module 23 in this embodiment eliminates the need for additional timing control circuitry to generate two independent signal lines that require precise alignment. This reduces the number of control terminals and the wiring complexity within the pixel array, which is beneficial for high-integration designs. In high-frequency applications, even two signals generated by the same driver chip may experience slight timing deviations due to differences in parasitic parameters after passing through the panel wiring. Using a single signal line for control fundamentally eliminates this risk of timing misalignment, ensuring the synchronization of the threshold compensation module 11 and the third reset module 23, and improving the reliability and yield of pixel circuit mass production.

[0045] Figure 7 The diagram shown is another schematic representation of a pixel driving circuit provided in an embodiment of this disclosure. Please refer to [the diagram / illustration]. Figure 7In one optional embodiment of this disclosure, the third reset signal terminal Vref0 multiplexes the second reset signal terminal Vref2. The second reset signal terminal Vref2 is used to provide a reference potential to the second node N2 during the first reset phase, and the third reset signal terminal Vref0 is used to provide a reference potential to the second node N2 during the third reset phase. In this embodiment, the third reset signal terminal Vref0 multiplexes the second reset signal terminal Vref2, so that during both the first and third reset phases, this signal terminal will reset the second node N2 to the same reference potential.

[0046] Pixel driving circuits typically require multiple reference potential terminals. By multiplexing the third reset signal terminal Vref0 with the second reset signal terminal Vref2, panel designers do not need to add a separate reference potential terminal for the third reset module 23, reducing the number of high-precision reset signal lines on the panel. In high-resolution panels, the wiring of reset signal lines occupies valuable area; this multiplexing method helps simplify the pixel array structure.

[0047] If two different reset signal terminals are used for the first and third reset stages, even if their nominal values ​​are the same, there may be slight voltage differences due to factors such as power supply drive or load fluctuations. This embodiment, by reusing the same reset signal terminal, ensures that after the second node N2 is reset to the reference potential in the first reset stage, the reference potential remains consistent during the third reset stage when it is continuously clamped. This eliminates the slight potential jumps of the second node N2 caused by the switching of the reference voltage source, further ensuring the stability of the second node N2. This provides a high-precision environmental guarantee for the threshold compensation of the first node N1, effectively improving the compensation accuracy of the first node N1.

[0048] Please continue to refer to this. Figure 7 In one optional embodiment of this disclosure, the signal at the first reset signal terminal Vref1 is the first reset signal, and the signal at the second reset signal terminal Vref2 is the second reset signal. The voltage polarities of the first reset signal and the second reset signal are opposite.

[0049] The first reset signal is provided to the first node N1 during the first reset phase to reset the first node N1. The second reset signal is provided to the second node N2 during both the first reset phase and the threshold compensation phase to reset and clamp the second node N2. The two signals have opposite polarities, meaning that the voltage values ​​have opposite polarities; for example, one is a positive voltage and the other is a negative voltage.

[0050] For example, the first reset signal is the voltage that turns on the driving transistor DT, thus ensuring that the driving transistor DT is in a conducting state during the first reset phase, thereby providing a more sufficient voltage margin for the signal writing to the first node N1 at the first power supply voltage terminal during the subsequent threshold compensation phase. The second reset signal is a voltage with the opposite polarity to the first reset signal. Taking a P-type transistor as an example, optionally, the first reset signal is a negative voltage signal, and the second reset signal is a positive voltage signal. During the first reset phase, the first node N1 is reset to a lower potential. For the P-type driving transistor DT, resetting its gate to a lower voltage ensures that the driving transistor DT is turned on during the first reset phase. Although the purpose of the first reset phase is to clear residual charge, setting the first node N1 to a lower starting potential provides a more sufficient voltage margin for the signal writing to the first node N1 at the first power supply voltage terminal during the subsequent threshold compensation phase. During the data writing phase, the final potential change of the first node N1 depends on the voltage change of the second node N2, i.e., the data signal voltage minus the voltage of the second reset signal. During the data writing phase, since the voltage of the second node N2 changes from the voltage of the second reset signal to the voltage of the data signal, setting the voltage of the second reset signal to a positive voltage ensures that the data signal can modulate the potential of the second node N2 within a large voltage range. This is equivalent to maximizing the modulation amplitude of the first storage module 31 on the final potential of the first node N1, thereby expanding the grayscale display range of the entire pixel driving circuit.

[0051] In this embodiment, the voltage of the first reset signal is set to a negative voltage, and the voltage of the second reset signal is set to a positive voltage. During the first reset phase, synchronous reset is achieved when the voltage polarities of the first node N1 and the second node N2 are opposite, eliminating coupling interference caused by the floating of the second node N2. During the threshold compensation phase, the potential of the second node N2 is continuously clamped by the high potential of the second reset signal, stabilizing the negative potential compensation process of the first node N1 and ensuring that the first node N1 performs high-precision threshold compensation at a precise starting point.

[0052] It should be noted that the above embodiments are only illustrated using the example of a P-type transistor as the driving transistor DT. In some other embodiments of this disclosure, the driving transistor DT can also be set as an N-type transistor as needed. In this case, the first reset signal will be a positive voltage signal and the second reset signal will be a negative voltage signal. This disclosure does not limit this.

[0053] Figure 8 The diagram shown is another schematic representation of a pixel driving circuit provided in an embodiment of this disclosure. Please refer to [the diagram / illustration]. Figure 8In one optional embodiment of this disclosure, the pixel driving circuit further includes a light-emitting control module 16 and a fourth reset module 24. The light-emitting control module 16 is connected between the third node N3 and the anode of the light-emitting element D0. The cathode of the light-emitting element D0 is connected to the second power supply voltage terminal PVEE. The light-emitting control module 16 is configured to be turned on during the light-emitting phase, transmitting the driving current provided by the driving transistor DT to the light-emitting element D0, causing the light-emitting element D0 to emit light under the action of the driving current. The fourth reset module 24 is connected between the first reset signal terminal Vref1 and the anode of the light-emitting element D0. The fourth reset module 24 is configured to reset the anode of the light-emitting element D0 before the light-emitting phase. Optionally, the control terminal of the fourth reset module 24 is connected to the first control signal terminal S1.

[0054] In the pixel driving circuit provided in this embodiment, after the first reset stage, threshold compensation stage, and data writing stage are completed, the light emission stage can be entered. Before the light emission stage, the anode of the light-emitting element is reset by the fourth reset module 24. The fourth reset module 24 reuses the first reset signal terminal Vref1 used to reset the first node N1, and the voltage of this signal terminal is used as the reset voltage of the anode. This scheme helps to ensure the consistency of the initial state of the light-emitting element at the beginning of each frame period, thereby improving the uniformity and response speed of the displayed image.

[0055] The light-emitting element has a fixed capacitance characteristic. After the light-emitting phase of the previous frame ends, residual charge may remain on the anode of the light-emitting element, causing inconsistent starting voltage at the beginning of the next frame. This disclosure eliminates residual charge by turning on the fourth reset module 24 before the light-emitting phase, forcing the anode of the light-emitting element to the voltage of the first reset signal terminal Vref1, thus ensuring that the light-emitting element has the same controlled starting potential at the beginning of each frame. When the light-emitting phase arrives and the driving transistor DT and the light-emitting control module 16 are turned on, the driving current can be established more quickly and stably because the anode voltage of the light-emitting element is already at a stable reset potential, thereby improving the pixel response speed.

[0056] Since the signal terminal of the fourth reset module 24 reuses the first reset signal terminal Vref1, the panel driving circuit does not need to draw a separate reset signal line for the anode reset of the light-emitting element, which simplifies the panel wiring and helps to achieve high integration and low cost.

[0057] When the control terminal of the fourth reset module 24 and the control terminal of the first reset module 21 are both connected to the first control signal terminal S1, the fourth reset module 24 and the first reset module 21 are simultaneously turned on or off. The process of the fourth reset module 24 resetting the anode of the light-emitting element coincides with the process of the first reset module 21 resetting the first node N1. This also helps to simplify the number of signal terminals of the pixel driving circuit, eliminating the need to introduce a separate control signal terminal for the fourth reset module 24. It also helps to simplify panel wiring, achieve high integration and reduce costs, and facilitates timing integration to improve refresh efficiency, making it more suitable for high-frequency application requirements.

[0058] Figure 9 The diagram shown is another schematic representation of a pixel driving circuit provided in an embodiment of this disclosure. Please refer to [the diagram / illustration]. Figure 9 In one optional embodiment of this disclosure, the pixel driving circuit 00 further includes a second storage module 32. The second storage module 32 is connected between the second node N2 and the first power supply voltage terminal to enhance the storage capacity and potential stability of the second node N2, and to control the potential during the data writing phase. The second node N2 needs to maintain the data signal voltage value during the data writing phase and remain stable during the subsequent light emission phase. The charge on the second node N2 will leak over time through the leakage current of the transistor. The introduction of the second storage module 32 significantly increases the total capacitance of the second node N2 to ground. The larger capacitance means that the second node N2 can store more charge, thereby effectively suppressing charge leakage, enhancing the potential maintenance capability of the second node N2 during the light emission phase, making the light emission current more stable during the light emission phase, and improving the brightness uniformity and stability of the image.

[0059] During the data writing phase, the potential of the second node N2 jumps from the reference potential to the data signal potential. The final potential of the first node N1 is generated by the coupling of the first capacitor, and its coupling coefficient depends on the total capacitance on the first node N1 and the second node N2. Typically, pixel driving circuits involve a specific capacitance ratio, and the addition of the second capacitor changes the total capacitance on the second node N2 side. By designing the capacitance value of the first storage module 31, the voltage coupling ratio between the first node N1 and the second node N2 can be precisely controlled. This helps to achieve a more accurate final driving potential of the first node N1 based on the characteristics of the driving transistor DT, further optimizing the pixel driving accuracy.

[0060] In addition, considering that the second node N2 may still be briefly floating during the non-reset phase, when the second storage module 32 is introduced, the second storage module 32 connects the second node N2 to the stable first power supply voltage terminal PVDD. If the second node N2 is briefly floating at some point, the second storage module 32 provides a path to the first power supply voltage terminal PVDD, making the potential of the second node N2 less susceptible to drastic fluctuations due to external interference, thereby enhancing the anti-interference capability of the second node N2.

[0061] Figure 10 The diagram shows a schematic of a pixel driving circuit provided in an embodiment of this disclosure. Optionally, the data writing module 12 includes transistor T21, and the first reset module 21 includes transistors T51 and T52 connected in series, with the gates of both transistors T51 and T52 connected to the first control signal terminal S1. Optionally, the second reset module 22 includes transistor T18, and the threshold compensation module 11 includes transistors T41 and T42 connected in series, with T41 and T42 connected to the same control signal terminal S2. Transistors T51 and T52 are dual-gate transistors, as are transistors T41 and T42. Dual-gate transistors have low leakage current. By setting all transistors connected to the first node N1 as dual-gate transistors, it is beneficial to avoid or reduce the impact of leakage current on the potential of the first node N1, making the potential of the first node N1 more stable. Optionally, the third reset module 23 includes transistor T12, the fourth reset module 24 includes transistor T17, and the light emission control module 16 includes transistor T16. In the specific circuit diagram corresponding to the pixel driving circuit, the gate of the transistor in each module is connected to the control terminal to which the corresponding module is connected. It should be noted that this embodiment only uses P-type transistors in the pixel driving circuit as an example for illustration, which simplifies the manufacturing process of the pixel driving circuit. However, this disclosure is not limited to this; in some other embodiments of this disclosure, at least some transistors may be set as N-type transistors. Optionally, the first storage module 31 includes a first capacitor C1, and the second storage module 32 includes a second capacitor C2.

[0062] The following will combine Figure 10 Circuit diagram and Figure 4 The timing sequence describes the operation of the pixel driving circuit provided in the embodiments of this disclosure.

[0063] In the first reset phase t01, the control signal of the first control signal terminal S1 is at a low level. The transistors in the first reset module 21 and the second reset module 22 simultaneously turn on in response to the control signal of the first control signal terminal S1. The potential of the first node N1 is reset to potential Vref1, and the potential of the second node N2 is reset to potential Vref2. It should be noted that this embodiment uses the same reference numerals for the signal terminals and the signals transmitted at the signal terminals as an example for illustration.

[0064] During the threshold compensation stage t02, the control signal at the control signal terminal S2 is at a low level, the transistor corresponding to the third reset module 23 is turned on, and the potential of the second node N2 is continuously clamped at Vref2. The transistor corresponding to the threshold compensation module 11 is turned on, and the signal PVDD at the first power supply voltage terminal is written to the first node N1 to perform threshold compensation on the driving transistor DT. During this stage, the potential of the first node N1 is continuously written until it stabilizes at PVDD+Vth. In this process, the continuous clamping of the second node N2 avoids the coupling of the potential jump of the second node N2 to the first node N1, ensuring that the driving transistor DT is fully turned on, so that the threshold voltage compensation is more sufficient.

[0065] During the data writing phase t03, the control signal SP is low, and the transistor corresponding to the data writing module 12 is turned on, writing the data signal Vdata to the second node N2. The potential of the second node N2 jumps from Vref2 to Vdata and is coupled to the first node N1 through the first capacitor. At this time, the potential of the first node N1 finally becomes PVDD + Vth + ΔV. Here, ΔV is the coupling amount, which is the jump variable of the potential change of the second node N2 coupled to the first node N1, and its value is ΔV = β(Vdata - Vref2), where β is the coupling coefficient.

[0066] During the light-emitting stage, the control signal EM is low, the transistor in the light-emitting control module 16 is turned on, and the driving current flows through the driving transistor DT and the light-emitting element D0. The gate-source voltage of the driving transistor DT is Vgs = Vn1 - PVDD = PVDD + Vth + ΔV - PVDD = Vth + ΔV. Where Vn1 is the potential of the first node, and the driving current I = K(Vgs - Vth). 2 =K(Vth+△V-Vth) 2 =K(△V) 2 =K(β(Vdata-Vref2)) 2 Where K represents the driving parameter coefficient of the driving transistor DT. It can be seen that the driving current is only related to the voltage values ​​of the data signal and the second reset signal, and is independent of the threshold voltage of the driving transistor DT.

[0067] Based on the same inventive concept, this disclosure also provides a display panel 100. Figure 11 The diagram shown is a plan view of a display panel 100 provided in an embodiment of this disclosure. Please refer to... Figure 11 The display panel includes the pixel driving circuit 00 provided in the above embodiments of this disclosure. It should be noted that... Figure 11 The arrangement and number of pixel driving circuits in the display panel are for illustrative purposes only and are not intended to limit the scope of this disclosure. The display panel provided in the embodiments of this disclosure has the same technical effects as the pixel driving circuits mentioned in the foregoing embodiments, and repeated details will not be elaborated upon.

[0068] Based on the same inventive concept, this disclosure also provides a display device. Figure 12 The diagram shown is a structural schematic of a display device 200 provided in an embodiment of this disclosure. Please refer to it. Figure 12 The display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided in this disclosure can be any electronic device with touch and display functions, such as a display screen, mobile phone, tablet computer, laptop computer, e-reader, or television. The display device 200 provided in this disclosure has the beneficial effects of the display panel provided in this disclosure; for details, please refer to the specific descriptions of the display panel in the above embodiments, which will not be repeated here.

[0069] Understandable Figure 12 The rectangular structure is used as an example to illustrate one shape of the display device 200. In some other embodiments of this disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and this disclosure does not specifically limit it.

[0070] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0071] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pixel driving circuit for driving a light-emitting element, characterized in that, The system includes a driving transistor, a threshold compensation module, a data writing module, a first reset module, a second reset module, and a first storage module. The gate of the driving transistor is connected to a first node. The first terminal of the first storage module is connected to the first node, and the second terminal is connected to a second node. The first electrode of the driving transistor is connected to a first power supply voltage terminal, and the second electrode of the driving transistor is connected to a third node. The third node is electrically connected to the light-emitting element. The pixel driving circuit operates in three phases: a time-division multiplexing first reset phase, a threshold compensation phase, and a data writing phase. The first reset module is connected between the first reset signal terminal and the first node, and the second reset module is connected between the second reset signal terminal and the second node; during the first reset phase, the first reset module and the second reset module are configured to be turned on simultaneously to reset the first node and the second node respectively; The threshold compensation module is connected between the first node and the third node. The threshold compensation module is configured to provide the first power supply voltage signal provided by the first power supply voltage terminal to the gate of the driving transistor during the threshold compensation stage, so as to perform threshold compensation on the driving transistor. The data writing module is connected between the data signal terminal and the second node, and the data writing module is configured to provide the data signal from the data signal terminal to the second node during the data writing phase.

2. The pixel driving circuit according to claim 1, characterized in that, The control terminals of the first reset module and the second reset module are connected to the same first control signal terminal. During the first reset phase, the first reset module and the second reset module are turned on in response to the control signal of the first control signal terminal.

3. The pixel driving circuit according to claim 1, characterized in that, The control terminal of the first reset module is connected to the first control signal terminal, and the control terminal of the second reset module is connected to the second control signal terminal; during the first reset phase, the first reset module responds to the signal of the first control signal terminal and the second reset module responds to the signal of the second control signal terminal.

4. The pixel driving circuit according to claim 1, characterized in that, It also includes a third reset module, which is connected between the third reset signal terminal and the second node. The third reset module is configured to reset the second node in a third reset phase, which overlaps with the threshold compensation phase.

5. The pixel driving circuit according to claim 4, characterized in that, The third reset phase and the threshold compensation phase overlap.

6. The pixel driving circuit according to claim 4, characterized in that, The control terminals of the third reset module and the threshold compensation module are connected to the same control signal terminal. During the threshold compensation stage, the third reset module and the threshold compensation module are configured to be turned on under the control of the same control signal.

7. The pixel driving circuit according to claim 4, characterized in that, The third reset signal terminal reuses the second reset signal terminal.

8. The pixel driving circuit according to claim 1, characterized in that, The signal at the first reset signal terminal is the first reset signal, and the signal at the second reset signal terminal is the second reset signal. The voltage polarities of the first reset signal and the second reset signal are opposite.

9. The pixel driving circuit according to claim 8, characterized in that, The first reset signal is a negative voltage signal, and the second reset signal is a positive voltage signal.

10. The pixel driving circuit according to claim 1, characterized in that, It also includes a light-emitting control module and a fourth reset module. The light-emitting control module is connected between the third node and the anode of the light-emitting element, and the cathode of the light-emitting element is connected to the second power supply voltage terminal. The light-emitting control module is configured to be turned on during the light-emitting phase. The fourth reset module is connected between the first reset signal terminal and the anode of the light-emitting element. The fourth reset module is configured to reset the anode of the light-emitting element before the light-emitting phase.

11. The pixel driving circuit according to claim 1, characterized in that, It also includes a second storage module, which is connected between the second node and the first power supply voltage terminal.

12. A display panel, characterized in that, Includes the pixel driving circuit described in any one of claims 1 to 11.

13. A display device, characterized in that, Includes the display panel as described in claim 12.

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