Data driver circuits and display devices

Abstract

Exemplary embodiments of this disclosure relate to a data driver circuit and a display device. More specifically, the display device may include: a display panel, in which multiple gate lines, multiple data lines, multiple sub-pixels, and a demultiplexer are disposed; a data driver circuit that provides data voltages corresponding to image data to multiple data channels; and a controller that controls the data driver circuit and provides image data to the data driver circuit. The demultiplexer includes multiple MUX stages, and the connection between the multiple data channels and multiple data lines is controlled by switching operations of the multiple MUX stages. The data driver circuit controls the length of at least one of a first extension time and a second extension time among multiple preset extension times of the multiple MUX stages based on bit switching counts of the image data. The data driver circuit and the display device can optimize the extension time of the MUX stages by using the counted bit switching values ​​of the image data to reduce peak current and improve ground bounce noise.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an apparatus, such as, but not limited to, particularly to a data driver circuit and a display device including the data driver circuit. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing. Therefore, various types of display devices are being used, such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs).

[0003] In display devices, organic light-emitting displays use self-emissive organic light-emitting diodes (OLEDs), thus offering advantages in response speed, contrast ratio, luminous efficiency, brightness, and viewing angle.

[0004] This display device can incorporate multiple multiplexers between data channels and data lines to reduce the number of data channels and meet setup time requirements.

[0005] The descriptions provided in the background section should not be construed as prior art simply because they are mentioned in or associated with that section. The background section may include information describing one or more aspects of the subject matter art, and the descriptions in that section do not limit this disclosure. Summary of the Invention

[0006] The inventors of this disclosure have realized that the use of multiple multiplexers increases the amount of bit switching, which in turn increases the amount of peak current switched by the multiplexers, resulting in ground bounce noise.

[0007] Embodiments of this disclosure may provide a data driver circuit and display device that can reduce / prevent peak current and improve ground bounce noise by controlling the extension time of the multiplexer MUX stage.

[0008] Embodiments of this disclosure may provide a data driver circuit and display device that can achieve low-power driving by controlling the extension time of the MUX stage to reduce peak current.

[0009] Embodiments of this disclosure may provide a data driver circuit and a display device that can optimize the extension time of a MUX level based on the counting result of bit switching counts of image data.

[0010] The problems and limitations that the embodiments of this disclosure aim to solve or overcome are not limited to those described above. Other problems and limitations not mentioned will be clearly understood by those skilled in the art through the following description.

[0011] Embodiments of this disclosure may provide a display device comprising: a display panel having multiple gate lines, multiple data lines, multiple sub-pixels, and a demultiplexer therein; a data driver circuit providing data voltages corresponding to image data to multiple data channels; and a controller controlling the data driver circuit and providing the image data to the data driver circuit. The demultiplexer includes multiple MUX stages, and controls the connections between the multiple data channels and multiple data lines through switching operations of the multiple MUX stages. Furthermore, the data driver circuit can control the length of at least one of a first extension time and a second extension time of the multiple MUX stages based on a bit switching count of the image data.

[0012] Embodiments of this disclosure may provide a data driver circuit comprising: a latch circuit that receives and latches image data from a controller; a bit counting circuit that counts bit switching counts of the image data output from the latch circuit; a switch controller that controls the length of at least one of a first extension time and a second extension time of a plurality of MUX stages in a demultiplexer for connections between a plurality of data channels and a plurality of data lines based on the bit switching counts; a digital-to-analog converter that converts the image data output from the latch circuit into a data voltage based on gamma grayscale voltage; and an output buffer that outputs the data voltage to the demultiplexer through the plurality of data channels.

[0013] According to embodiments of this disclosure, a data driver circuit and display device capable of reducing peak current and improving ground bounce noise can be provided by controlling the extension time of the MUX level.

[0014] According to embodiments of this disclosure, peak current can be reduced by controlling the extension time of the MUX stage to provide a data driver circuit and display device capable of low-power driving.

[0015] According to embodiments of this disclosure, a data driver circuit and display device capable of optimizing the extended time of a MUX level can be provided based on the counting results of bit switching counts of image data.

[0016] The effects of the embodiments disclosed herein are not limited to those described above, and those skilled in the art will clearly understand other effects not mentioned in the claims.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0018] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated in and constituting a part of this application, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0019] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0020] Figure 2 This is a diagram illustrating an implementation example of a display device according to an embodiment of the present disclosure.

[0021] Figure 3 This is a diagram illustrating an example of a subpixel according to an embodiment of the present disclosure.

[0022] Figure 4 This is a diagram illustrating a data driver circuit according to an embodiment of the present disclosure.

[0023] Figure 5 This is a diagram illustrating an example implementation of a gamma voltage circuit according to an embodiment of the present disclosure.

[0024] Figure 6 This is a diagram illustrating a demultiplexer included in a display device according to an embodiment of the present disclosure.

[0025] Figure 7A , Figure 7B and Figure 8 This is a diagram illustrating an example of extended time in a control display device according to an embodiment of the present disclosure.

[0026] Figures 9 to 11 This is a diagram illustrating an example of controlling extended time based on MUX switching count in a display device according to an embodiment of the present disclosure. Detailed Implementation

[0027] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, which illustrate specific examples or embodiments that may be implemented, and wherein the same reference numerals and symbols may be used to designate the same or similar components, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein are omitted where it is determined that the description may make the subject matter of some embodiments of this disclosure considerably unclear. Unless used with the term “only,” the terms “comprising,” “having,” “containing,” and “constituting” as used herein are generally intended to allow for the addition of additional components. As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0028] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” are used herein to describe elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0029] When referring to the first element and the second element as "connected or joined," "in contact or overlapping," etc., it should be interpreted as meaning that not only can the first element be "directly connected or joined" or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first element and the second element, or the first element and the second element can be "connected or joined," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or joined," "in contact or overlapping," etc., with each other.

[0030] When time-related terms such as “after,” “follow,” “next,” or “before” are used to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless the terms “directly” or “immediately” are used together.

[0031] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical or corresponding information of an element or feature (e.g., level, range, etc.) includes the range of tolerances or errors that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. Moreover, the term "may" fully encompasses all the meanings of the term "able to," and vice versa.

[0032] Any implementation described as an "example" in this article is not necessarily to be interpreted as preferred or superior to other implementations.

[0033] In the description of various embodiments of this disclosure that describe positional relationships, for example, when the positional relationship between two parts is described as, for example, “above,” “under,” and “beside,” one or more other parts may be located between the two parts, unless more restrictive terms such as “exactly” or “directly” are used. For example, in the case where an element or layer is disposed “on” another element or layer, a third layer or element may be inserted therebetween.

[0034] The terms “first element,” “second element,” and / or “third element” should be understood as one of the first, second, and third elements, or any or all combinations of the first, second, and third elements. For example, A, B, and / or C can refer to only A; only B; only C; any or some combinations of A, B, and C; or all of A, B, and C.

[0035] The term “at least one” should be understood to include any and all combinations of one or more of the associated listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element, the first element, the second element, or the third element.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It should also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, the terms “part” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the functions described herein that would be understood by one of ordinary skill in the art.

[0037] Instead, these implementations may be provided to make this disclosure thorough and complete enough to help those skilled in the art to fully understand the scope of this disclosure.

[0038] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be joined or combined in part or in whole, and may interoperate and be technology-driven in various ways. Embodiments of this disclosure may be implemented independently of each other or may be implemented together in an interdependent relationship.

[0039] Various embodiments of this specification will be described in detail with reference to the accompanying drawings. All components of each display device / apparatus according to all embodiments of this disclosure are operatively connected and configured.

[0040] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0041] refer to Figure 1 The display device 100 according to the embodiments of the present disclosure may include a display panel 110 and a driver circuit for driving the display panel 110.

[0042] The driver circuit may include a data driver circuit 120 and a gating driver circuit 130, and may also include a controller 140 for controlling the data driver circuit 120 and the gating driver circuit 130.

[0043] Display panel 110 may include multiple sub-pixels SP connected to multiple data lines DL and multiple gate lines GL.

[0044] Display panel 110 may include a display area DA for displaying an image and a non-display area NDA located outside the display area DA. In display panel 110, multiple sub-pixels SP for displaying the image may be disposed in the display area DA. Driver circuits 120, 130, and 140 may be electrically connected to or mounted in the non-display area NDA. Pad portions for connecting integrated circuits or printed circuits may also be disposed in the non-display area NDA.

[0045] The data driver circuit 120 can be a circuit for driving multiple data lines DL, and can provide data signals to the multiple data lines DL. The gating driver circuit 130 can be a circuit for driving multiple gating lines GL, and can provide gating signals to the multiple gating lines GL.

[0046] The controller 140 can provide a data control signal DCS to the data driver circuit 120 to control the timing of its operation. The controller 140 can also provide a gating control signal GCS to the gating driver circuit 130 to control the timing of its operation.

[0047] The controller 140 can control the initiation of the scan operation based on the timing for each frame, converting input image data received from an external source (e.g., host system 150) into a data signal format usable by the data driver circuit 120, and providing the converted image data to the data driver circuit 120. The controller 140 can also control the execution of data-driven operations at appropriate times based on the scan timing.

[0048] Specifically, the controller 140 can receive various timing signals from the outside along with the input image data, such as vertical synchronization signal (VSYNC), horizontal synchronization signal (HSYNC), data enable signal (DE), and clock signal (CLK). The controller 140 can generate various control signals, such as data control signal DCS and gating control signal GCS, to control data driver circuit 120 and gating driver circuit 130, and can output them to the corresponding circuits.

[0049] The controller 140 can be implemented as a component separate from the data driver circuitry 120, or it can be integrated with the data driver circuitry 120 into a single integrated circuit.

[0050] The data driver circuit 120 can receive image data DATA from the controller 140 and provide data voltage to multiple data lines DL, thereby driving the multiple data lines DL. The data driver circuit 120 can also be referred to as a source driver circuit.

[0051] For example, the data driver circuit 120 can provide data voltage to multiple data channels that correspond to multiple data lines DL respectively.

[0052] The data driver circuit 120 may include one or more source driver integrated circuits (SDICs).

[0053] For example, each source driver integrated circuit (SDIC) can be connected to the display panel 110 via a tape-on-board (TAB) method, or via a chip-on-glass (COG) method or a chip-on-panel (COP) method. Alternatively, the SDIC can be implemented using a chip-on-film (COF) method and connected to the display panel 110.

[0054] The gating driver circuit 130 can output a gating signal with an on-state voltage level or a gating signal with an off-state voltage level under the control of the controller 140. The gating driver circuit 130 can sequentially provide gating signals with an on-state voltage level to multiple gating lines GL, thereby sequentially driving multiple gating lines GL.

[0055] The gate driver circuit 130 can be connected to the display panel 110 via a tape-on-board (TAB) method, or via a chip-on-glass (COG) method or a chip-on-panel (COP) method. Alternatively, the gate driver circuit 130 can be connected to the display panel 110 via a chip-on-film (COF) method. The gate driver circuit 130 can also be formed in the non-display area NDA of the display panel 110 as a gate-in-panel (GIP) type. The gate driver circuit 130 can be disposed on or connected to the substrate SUB. In other words, when the gate driver circuit 130 is of the GIP type, it can be disposed in the non-display area NDA of the substrate SUB. When the gate driver circuit 130 is of the COG or COF type, it can be connected to the substrate SUB.

[0056] For example, the substrate SUB can be a silicon substrate, which allows for more precise control of the drive voltage of the driver circuit.

[0057] However, the embodiments disclosed herein are not limited thereto, and the substrate SUB may also be a glass substrate or other types of substrates commonly used in display devices.

[0058] The gate driver circuit 130 can be configured with multiple stages. When the gate driver circuit 130 is implemented as a gate in panel (GIP) type, each of the multiple stages can be implemented using multiple GIP circuits.

[0059] At least one of the data driver circuit 120 and the gating driver circuit 130 may also be disposed in the display area DA. For example, at least one of the data driver circuit 120 and the gating driver circuit 130 may be configured not to overlap with the plurality of sub-pixels SP, or may partially or completely overlap with the plurality of sub-pixels SP.

[0060] The data driver circuit 120 can convert the image data DATA received from the controller 140 into analog data voltages, and can provide them to multiple data lines DL when a specific gating line GL is turned on by the gating driver circuit 130.

[0061] The data driver circuit 120 can be connected to one side of the display panel 110 (e.g., the top or bottom side). Depending on the driving method or panel design, the data driver circuit 120 can be connected to both sides of the display panel 110 (e.g., the top and bottom sides) or to two or more of the four sides of the display panel 110.

[0062] The gating driver circuit 130 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the driving method or panel design, the gating driver circuit 130 can be connected to both sides of the display panel 110 (e.g., the left and right sides) or two or more of the four sides of the display panel 110.

[0063] The controller 140 may be a timing controller commonly used in display technology, or it may be a control device that includes a timing controller and performs other control functions. Alternatively, the controller 140 may be a control device separate from the timing controller, or it may be a circuit included in the control device. The controller 140 may be implemented using various types of circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0064] The controller 140 can be mounted on a printed circuit board or flexible printed circuit and can be electrically connected to the data driver circuit 120 and the strobe driver circuit 130 via the printed circuit board or flexible printed circuit.

[0065] The display device 100 according to the embodiments of the present disclosure may be a display including a backlight unit, such as a liquid crystal display, or it may be a self-emissive display, such as an organic light-emitting diode (OLED) display, a quantum dot display, or a micro light-emitting diode (micro LED) display.

[0066] In the case where the display device 100 according to the embodiments of the present disclosure is an OLED display, each sub-pixel SP may include a self-emissive organic light-emitting diode (OLED) as a light-emitting device. In the case where the display device 100 is a quantum dot display, each sub-pixel SP may include a quantum dot composed of self-emissive semiconductor nanocrystals as a light-emitting device. In the case where the display device 100 is a micro-LED display, each sub-pixel SP may include a micro-LED made of inorganic materials and emitting its own light as a light-emitting device.

[0067] The display panel 110 according to embodiments of the present disclosure may have a top-emitting structure or a bottom-emitting structure, and in some cases may have a double-sided emitting structure.

[0068] Meanwhile, the display device 100 according to the embodiments of the present disclosure may include multiple MUX (multiplexer) levels on the display panel 110, and may be configured with a demultiplexer to control the connection between multiple data channels and multiple data lines DL through the switching operation of multiple MUX levels.

[0069] In other words, the demultiplexer can provide data voltages from the data driver circuit 120 to multiple channels to multiple data lines DL through switching operations.

[0070] According to embodiments of the present disclosure, the data driver circuit 120 can control the length of at least one of a first extension time and a second extension time of a plurality of MUX levels based on the bit switching count of the image data.

[0071] Figure 2 This is a diagram illustrating an implementation example of a display device 100 according to an embodiment of the present disclosure.

[0072] refer to Figure 2 In the display device 100 according to an embodiment of the present disclosure, the data driver circuit 120 can be implemented using a chip-on-film (COF) method selected from various methods such as TAB, COG, and COF, and the gate driver circuit 130 can be implemented in the form of a gate-in-panel (GIP) method selected from various methods such as TAB, COG, COF, and GIP. However, embodiments of the present disclosure are not limited thereto.

[0073] When the gate driver circuit 130 is implemented in GIP form, multiple gate driver integrated circuits (GDICs) included in the gate driver circuit 130 can be directly formed in the non-display area of ​​the display panel 110. In this case, each GDIC can receive various signals (e.g., clock signal, gate high signal, gate low signal, etc.) required to generate the scan signal through the gate drive related signal lines formed in the non-display area.

[0074] Similarly, one or more source driver integrated circuits (SDICs) included in the data driver circuit 120 may be mounted on at least one source film (SF), and one side of the source film SF may be electrically connected to the display panel 110. Furthermore, wiring for electrically connecting the SDICs and the display panel 110 may be provided on the upper part of the source film SF.

[0075] exist Figure 2 In the example, the display device 100 is illustrated as including a plurality of source films SF and a plurality of source driver integrated circuits SDIC disposed on each of the plurality of source films SF. However, embodiments of the present disclosure are not limited thereto, and the display device 100 may include a single source film SF and a single SDIC disposed thereon.

[0076] The display device 100 may include at least one source printed circuit board (SPCB) for electrically connecting at least one SDIC to other devices and a control printed circuit board (CPCB) for mounting control components and various electrical devices.

[0077] One side of the source film SF on which the SDIC is mounted can be connected to the source printed circuit board SPCB. For example, the source film SF including the SDIC can be electrically connected to the display panel 110 on one side and to the SPCB on the other side.

[0078] The control printed circuit board (CPCB) may have a controller 140 and a power management circuit 210 mounted thereon. The controller 140 can control the operation of the data driver circuit 120 and the gating driver circuit 130. The power management circuit 210 can supply drive voltage or current to the display panel 110, the data driver circuit 120 and the gating driver circuit 130, and can control the supplied voltage or current.

[0079] At least one SPCB and CPCB can be electrically connected via at least one connecting member. The connecting member can be, for example, a flexible printed circuit (FPC) or a flexible flat cable (FFC). Furthermore, the SPCB and CPCB can be integrated into a single printed circuit board.

[0080] The display device 100 may also include a setup board 230 electrically connected to a control printed circuit board (CPCB). The setup board 230 may also be referred to as a power board. The setup board 230 may include a main power management circuit 220 for managing the total power of the display device 100. The main power management circuit 220 may be linked to the power management circuit 210.

[0081] In the display device 100 configured as described above, the driving voltage can be generated by the setup board 230 and transmitted to the power management circuit 210 on the CPCB. The power management circuit 210 can transmit the driving voltage required for display driving or feature sensing to the SPCB via a flexible printed circuit (FPC) or a flexible flat cable (FFC). The driving voltage transmitted to the SPCB can be provided to specific sub-pixels (SPs) in the display panel 110 via an SDIC to perform light emission or sensing.

[0082] In this case, each sub-pixel SP disposed in the display panel 110 of the display device 100 may include a light-emitting device and circuit elements such as a driving transistor for driving the light-emitting device.

[0083] The type and number of circuit elements constituting each sub-pixel SP can vary depending on the provided functions and design scheme.

[0084] Figure 3 This is a diagram illustrating an example of a sub-pixel SP according to an embodiment of the present disclosure.

[0085] refer to Figure 3 The subpixel circuit SPC may include a driving transistor DRT for driving the light-emitting device ED, a scanning transistor SCT connected to a first node N1 of the driving transistor DRT, a sensing transistor SENT connected to a second node N2 of the driving transistor DRT, and a storage capacitor Cst for maintaining a constant voltage during a frame period.

[0086] The light-emitting device ED may include a pixel electrode PE and a common electrode CE, and may also include a light-emitting layer EL located between the pixel electrode PE and the common electrode CE.

[0087] The pixel electrode PE of the light-emitting device ED can be an electrode set separately for each sub-pixel SP, and the common electrode CE can be an electrode set together for all sub-pixels SP.

[0088] For example, the pixel electrode PE can be the anode, and the common electrode CE can be the cathode. Conversely, the pixel electrode PE can be the cathode, and the common electrode CE can be the anode.

[0089] The common electrode CE of the light-emitting device ED can be connected to the low-potential voltage line VSSL that provides the low-potential voltage EVSS.

[0090] For example, the light-emitting device ED can be an organic light-emitting diode (OLED), a light-emitting diode (LED), or a quantum dot light-emitting device.

[0091] The driving transistor DRT is a transistor used to drive the light-emitting device ED, and may include a first node N1, a second node N2 and a third node N3.

[0092] The first node N1 of the driving transistor DRT can be the gate node of the driving transistor DRT, and can be electrically connected to the source or drain node of the scanning transistor SCT.

[0093] The second node N2 of the driving transistor DRT can be the source or drain node of the driving transistor DRT, and can be electrically connected to the pixel electrode PE of the light-emitting device ED.

[0094] The third node N3 of the driving transistor DRT can be the drain or source node of the driving transistor DRT, and can be electrically connected to the high-potential voltage line VDDL that provides the high-potential power voltage EVDD.

[0095] The storage capacitor Cst can be connected between the first node N1 and the second node N2 of the driving transistor DRT.

[0096] The scanning transistor SCT is controlled by a strobe signal and can be connected between the first node N1 of the driving transistor DRT and the data line DL.

[0097] The scanning transistor SCT can be turned on by a gating signal at the on-voltage level provided from the gating line GL, and the data voltage VDATA provided from the data line DL can be transmitted to the first node N1 of the driving transistor DRT.

[0098] The sensing transistor SENT is controlled by a strobe signal and can be connected between the second node N2 of the driving transistor DRT and the sensing line SL.

[0099] In other words, the sensing transistor SENT can be turned on by a gating signal at the on-voltage level provided from the gating line GL, and the connection between the second node N2 of the driving transistor DRT and the sensing line SL can be controlled.

[0100] The sensing transistor SENT can be turned on by a gating signal at the on-voltage level, and the reference voltage Vref supplied from the sensing line SL can be transmitted to the second node N2 of the driving transistor DRT.

[0101] In addition, the sensing transistor SENT can be turned on by a gating signal at the on-voltage level, and the voltage of the second node N2 of the driving transistor DRT can be transmitted to the sensing line SL.

[0102] according to Figure 3 In the example, the scan transistor SCT and the sensing transistor SENT can be connected to the same gate line GL.

[0103] On the other hand, the scan transistor SCT and the sensing transistor SENT can be connected to different gating lines GL. In this case, the scan transistor SCT can receive a scan gating signal at the on-state voltage level from the scan gating line GL, and the sensing transistor SENT can receive a sensing gating signal at the on-state voltage level from the sensing gating line GL, which is another gating line.

[0104] Each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT can be an n-type transistor or a p-type transistor. In embodiments of this disclosure, for ease of illustration, each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT is shown as an n-type transistor.

[0105] When the scanning transistor SCT and the sensing transistor SENT are n-type transistors, the on-state voltage level of the strobe signal can be high.

[0106] Figure 3 The structure of the sub-pixel SP shown is only an example, and it can be modified in various ways to include one or more additional transistors or one or more additional capacitors.

[0107] Figure 4 This is a diagram illustrating a data driver circuit 120 according to an embodiment of the present disclosure.

[0108] refer to Figure 4 The data driver circuit 120 may include a shift register 410, a latch circuit 420, a bit counting circuit 430, a switch controller 440, a digital-to-analog converter 450, a gamma voltage circuit 460, and an output buffer 470.

[0109] The shift register 410 can receive image data from the controller 140 and provide it to the latch circuit 420.

[0110] For example, shift register 410 can generate a latch clock signal for timing the output image data DATA based on the data control signal DCS received from controller 140, and can provide the latch clock signal to latch circuit 420.

[0111] The latch circuit 420 can receive and latch image data DATA from the shift register 410.

[0112] For example, latch circuit 420 may include a first latch circuit and a second latch circuit.

[0113] The first latch circuit can latch the image data DATA received from the shift register 410 based on the latch clock signal, and can output the image data DATA latched in the first latch circuit to the second latch circuit.

[0114] The second latch circuit can latch the image data DATA received from the first latch circuit based on the latch clock signal, and can output the image data DATA latched in the second latch circuit to the bit counting circuit 430.

[0115] The bit counting circuit 430 can count the bit switching counts of the image data DATA output from the latch circuit 420.

[0116] Specifically, the image data DATA includes multiple data bit values ​​corresponding to multiple data lines DL, and the bit counting circuit 430 can count the bit switching counts corresponding to each of the n MUX stages (where n is a positive integer) included in the demultiplexer.

[0117] More specifically, the bit counting circuit 430 can count the number of "1" bits in the data bit values ​​of the first MUX level out of n MUX levels, as a bit switching count corresponding to the first MUX level.

[0118] In addition, the bit counting circuit 430 can count the number of changed bits between the (k-1)th MUX level and the kth MUX level (where k is a positive integer satisfying 2≤k≤n) in the n MUX levels, as the bit switching count corresponding to the kth MUX level.

[0119] Here, the changed bit can refer to at least one bit where the "0" bit value in the (k-1)th MUX level is changed to "1" in the kth MUX level, or the "1" bit value in the (k-1)th MUX level is changed to "0" in the kth MUX level.

[0120] For example, when the data bit value corresponding to the first MUX level is “01111010”, the bit counting circuit 430 can count the bit switching count of the first MUX level to “5”, and when the data bit value corresponding to the first MUX level is “10011000”, the bit counting circuit 430 can count it to “3”.

[0121] Furthermore, when the data bit value corresponding to the first MUX level is "01111010" and the data bit value corresponding to the second MUX level is "10111110", the bit counting circuit 430 can count "3" (the number of bits changed between the data bit values ​​of the first and second MUX levels) as the bit switching count for the second MUX level. When the data bit value corresponding to the third MUX level is "11110011", it can count "4" (the number of bits changed between the second and third MUX levels) as the bit switching count for the third MUX level.

[0122] The switch controller 440 can control the switching operation of the demultiplexer based on the bit switching count counted by the bit counting circuit 430. The demultiplexer controls the connection between multiple data channels and multiple data lines.

[0123] Specifically, the switch controller 440 can select an extension time corresponding to the bit switching count from a plurality of preset extension times, and can output a switch control signal SWC based on the selected extension time to a plurality of MUX stages included in a multiplexer.

[0124] For example, multiple preset extension times may include at least one of multiple first extension times and multiple second extension times, wherein the first extension time may correspond to the activation time at the MUX level, and the second extension time may correspond to the deactivation time at the MUX level.

[0125] For example, the switch controller 440 can select an extension time corresponding to the bit switching count of each of the multiple MUX levels from a plurality of preset extension times, and can output a switch control signal SWC based on the selected extension time.

[0126] According to the implementation, the switch controller 440 can select an extension time for at least one data channel among a plurality of data channels that corresponds to a preset period, and can output a switch control signal SWC based on the selected extension time.

[0127] For example, the switch controller 440 can select an extension time for each of at least two MUX levels connected to at least one data channel corresponding to a preset period in a plurality of MUX levels, and can output a switch control signal SWC based on the selected extension time.

[0128] In a more specific example, if the number of data channels is 2304 and the preset period is "60", the switch controller 440 can select an extension time for each of at least two MUX levels connected to each of the 60th, 120th, ... and 2280th channels, and can output a switch control signal SWC based on the selected extension time.

[0129] When the bit switching count of the image data DATA is equal to or greater than a first threshold (e.g., 3) and less than a second threshold (e.g., 6) that is greater than the first threshold, the switch controller 440 can select an extension time TYP of a first length from a plurality of extension times.

[0130] When the bit switching count of the image data DATA is less than the first threshold, the switch controller 440 can select a second length extension time MIN that is shorter than the first length from multiple extension times.

[0131] When the bit switching count of the image data DATA is equal to or greater than the second threshold, the switch controller 440 can select a third extension time MAX that is longer than the first extension time from a plurality of extension times.

[0132] For example, the first length of the extension time TYP can represent the normal extension time and can be predetermined within the range of 90% to 110% of the initial extension time; the second length of the extension time MIN can represent the minimum extension time and can be predetermined within the range of 70% to 90% of the initial extension time; and the third length of the extension time MAX can represent the maximum extension time and can be predetermined within the range of 110% to 130% of the initial extension time. However, the embodiments of this disclosure are not limited thereto.

[0133] The switch controller 440 can receive initial switch control signals for multiple MUX levels from the controller 140, and can generate a switch control signal SWC corresponding to each of the multiple MUX levels by controlling the initial extension time corresponding to the initial switch control signal based on a selected extension time.

[0134] When the bit switching count of image data DATA is equal to or greater than the first threshold and less than the second threshold, and the first length extension time TYP is set to 100% of the initial extension time, the switch controller 440 may output the initial switch control signal received from the controller 140 as the switch control signal SWC without controlling the extension time.

[0135] For example, in the display device 100 according to an embodiment of the present disclosure, the extension time of each of the plurality of MUX stages can be adaptively controlled according to the bit switching amount of image data DATA, so that the peak current switching in the plurality of MUX stages can be reduced and the ground bounce noise can be improved accordingly.

[0136] The digital-to-analog converter 450 can convert image data DATA output from the latch circuit 420 into data voltage VDATA based on the gamma grayscale voltage, wherein the gamma grayscale voltage can be supplied from the gamma voltage circuit 460.

[0137] The output buffer 470 can provide the data voltage VDATA output from the digital-to-analog converter 450 to the demultiplexer through multiple data channels.

[0138] For example, output buffer 470 can be an output amplifier that amplifies the data voltage VDATA output from digital-to-analog converter 450 and outputs it to multiple data channels.

[0139] Figure 5 This is a diagram illustrating an example implementation of a gamma voltage circuit 460 according to an embodiment of the present disclosure.

[0140] refer to Figure 5 The gamma voltage circuit 460 may include multiple resistor strings RST, multiple decoders DEC, input gamma string GMS1, output gamma string GMS2, ​​and multiple buffers.

[0141] The input gamma string GMS1 is a resistor string connected in series between the high-potential voltage VREG1 and the low-potential voltage VREG2. Each of the high-potential voltage VREG1 and the low-potential voltage VREG2 can be varied by the resistor string RST, which divides the grayscale generation voltage DDVDH, and the decoder DEC. Here, the grayscale generation voltage DDVDH can be varied according to the bit switching count of the image data DATA.

[0142] The output gamma string GMS2 is a series resistor string connected between the highest gamma reference voltage GMA10 and the lowest gamma reference voltage GMA1. These gamma reference voltages can be referred to as tapped gamma voltages because they represent the voltages at the taps of the output gamma string GMS2.

[0143] The highest gamma reference voltage GMA10 depends on a specific voltage division within the input gamma string GMS1. This voltage division can be changed by the decoder. The lowest gamma reference voltage GMA1 can also be changed by the resistor string RST that divides the grayscale generation voltage DDVDH and the decoder DEC.

[0144] The output gamma string GMS2 can include multiple tap grayscale points. The output gamma string GMS2 can generate multiple gamma voltages (e.g., V0 to V255) representing the voltage level of each grayscale by dividing the voltage between the gamma reference voltages at the tap grayscale points TAB.

[0145] Each of the tap grayscale points (TABs) can be connected to a resistor string (RST), a decoder (DEC), and a buffer. The resistor string (RST) can be connected between the gamma reference voltage of an adjacent upper tap grayscale point (TAB) and the low-level voltage (VREG2), and can divide the gamma reference voltage of the adjacent upper tap. The decoder can select a voltage divider corresponding to the gamma values ​​GM1 to GM9 stored in the gamma register memory of the data driver and apply the selected voltage to the buffer. The buffer can buffer the voltage divider and apply it to the tap grayscale point (TAB).

[0146] The gamma voltages V0 to V255 generated by the gamma voltage circuit 460 can be provided to the digital-to-analog converter 450, which can use the gamma voltages to convert the image data DATA from digital form to analog data voltage VDATA.

[0147] Specifically, when an image signal is provided to a pixel, the digital signal is converted into an analog voltage suitable for the sub-pixel SP. This voltage adjustment between grayscale values, taken into account visibility, is called gamma correction. Most gamma correction can be performed using a gamma voltage circuit 460 that includes a resistor string and a decoder.

[0148] Gamma correction can be performed at a specific point after the display device is driven by optical compensation, and the gamma value at that point can be written to the gamma register memory of the data driver. Optical compensation involves identifying decoder values ​​that satisfy the luminance or color coordinate target values ​​of each decoder DEC, and the values ​​between decoders—e.g., the values ​​between tap grayscale voltages—can be obtained by interpolation. The decoder values ​​can correspond to gamma values ​​GM1 to GM9 stored in the gamma register memory.

[0149] Figure 6 This is a diagram illustrating the demultiplexer included in a display device 100 according to an embodiment of the present disclosure.

[0150] refer to Figure 6 According to embodiments of the present disclosure, the data driver circuit 120 can be electrically connected to a demultiplexer DMUX comprising multiple MUX levels MUX1 to MUX5 via multiple data channels CH1, CH2 and CH3.

[0151] Multiple data channels CH1, CH2 and CH3 are exemplified as three channels, and the demultiplexer DMUX is exemplified as a 1-to-5 demultiplexer, but embodiments of this disclosure are not limited thereto.

[0152] For example, when the number of data lines DL in the display panel 110 is 3840 (RGB) and the demultiplexer DMUX is a 1-to-5 demultiplexer, the number of data channels can be 2304.

[0153] Specifically, the multiple data channels may include at least one first data channel CH1 corresponding to the first color, at least one second data channel CH2 corresponding to the second color, and at least one third data channel CH3 corresponding to the third color.

[0154] For example, the first color can be red, the second color can be green, and the third color can be blue. However, embodiments of this disclosure are not limited thereto, and the plurality of data channels may also include at least one fourth data channel corresponding to a fourth color (e.g., white).

[0155] according to Figure 6 For example, the digital-to-analog converter 450 may include a first digital-to-analog converter 451 for receiving image data corresponding to a first color, a second digital-to-analog converter 452 for receiving image data corresponding to a second color, and a third digital-to-analog converter 453 for receiving image data corresponding to a third color.

[0156] The output buffer 470 may include a first output buffer 471 connected to the first digital-to-analog converter 451, a second output buffer 472 connected to the second digital-to-analog converter 452, and a third output buffer 473 connected to the third digital-to-analog converter 453.

[0157] according to Figure 6 For example, the first output buffer 471 can be connected to the first data channel CH1 via the first data pad DP1, the second output buffer 472 can be connected to the second data channel CH2 via the second data pad DP2, and the third output buffer 473 can be connected to the third data channel CH3 via the third data pad DP3.

[0158] Each of the multiple MUX levels MUX1 to MUX5 in the demultiplexer DMUX can electrically connect the first data channel CH1 to the third data channel CH3 to the first data line DL1 to the fifth data line DL5 via a switch operation.

[0159] according to Figure 6 For example, the first MUX level MUX1 can electrically connect data channels CH1 to CH3 to the first data line DL1; the second MUX level MUX2 can electrically connect data channels CH1 to CH3 to the second data line DL2; and the third MUX level MUX3 can electrically connect the first data channel CH1 to the third data channel CH3 to the third data line DL3.

[0160] The fourth MUX level MUX4 can electrically connect the first data channel CH1 to the third data channel CH3 to the fourth data line DL4, and the fifth MUX level MUX5 can electrically connect the first data channel CH1 to the third data channel CH3 to the fifth data line DL5.

[0161] according to Figure 6 For example, each of the multiple MUX levels MUX1 to MUX5 may include a first switching element (e.g., S11, S21, S31, S41, S51) connected to a first data channel CH1, a second switching element (e.g., S12, S22, S32, S42, S52) connected to a second data channel CH2, and a third switching element (e.g., S13, S23, S33, S43, S53) connected to a third data channel CH3.

[0162] Specifically, in the first MUX level MUX1, the first switching element S11 can control the connection between the first data channel CH1 and the first-1 data line DL1-1 in the first data line DL1 through a switching operation; the second switching element S12 can control the connection between the second data channel CH2 in the first data line DL1 and the first-2 data line DL1-2 in the first data line DL1 through a switching operation; and the third switching element S13 can control the connection between the third data channel CH3 and the first-3 data line DL1-3 in the first data line DL1 through a switching operation.

[0163] In the second MUX level MUX2, the first switching element S21 can control the connection between the first data channel CH1 and the second-1 data line DL2-1 in the second data line DL2 through a switching operation; the second switching element S22 can control the connection between the second data channel CH2 and the second-2 data line DL2-2 in the second data line DL2 through a switching operation; and the third switching element S23 can control the connection between the third data channel CH3 and the second-3 data line DL2-3 in the second data line DL2 through a switching operation.

[0164] In the third MUX level MUX3, the first switching element S31 can control the connection between the first data channel CH1 and the third-1 data line DL3-1 in the third data line DL3 through switching operation; the second switching element S32 can control the connection between the second data channel CH2 and the third-2 data line DL3-2 in the third data line DL3 through switching operation; and the third switching element S33 can control the connection between the third data channel CH3 and the third-3 data line DL3-3 in the third data line DL3 through switching operation.

[0165] In the fourth MUX level MUX4, the first switching element S41 can control the connection between the first data channel CH1 and the fourth-1 data line DL4-1 in the fourth data line DL4 through switching operation; the second switching element S42 can control the connection between the second data channel CH2 and the fourth-2 data line DL4-2 in the fourth data line DL4 through switching operation; and the third switching element S43 can control the connection between the third data channel CH3 and the fourth-3 data line DL4-3 in the fourth data line DL4 through switching operation.

[0166] In the fifth MUX level MUX5, the first switching element S51 can control the connection between the first data channel CH1 and the fifth-1 data line DL5-1 in the fifth data line DL5 through switching operation; the second switching element S52 can control the connection between the second data channel CH2 and the fifth-2 data line DL5-2 in the fifth data line DL5 through switching operation; and the third switching element S53 can control the connection between the third data channel CH3 and the fifth-3 data line DL5-3 in the fifth data line DL5 through switching operation.

[0167] Each of the data lines DL1-1, DL2-1, DL3-1, DL4-1, and DL5-1 connected to the first switching elements S11, S21, S31, S41, and S51 can be connected to a sub-pixel of the first color among multiple sub-pixels. Each of the data lines DL1-2, DL2-2, DL3-2, DL4-2, and DL5-2 connected to the second switching elements S12, S22, S32, S42, and S52 can be connected to a sub-pixel of the second color among multiple sub-pixels. Each of the data lines DL1-3, DL2-3, DL3-3, DL4-3, and DL5-3 connected to the third switching elements S13, S23, S33, S43, and S53 can be connected to a sub-pixel of the third color among multiple sub-pixels.

[0168] Each of the multiple MUX levels, MUX1 to MUX5, can be connected to the switch controller 440 in the data driver circuit 120 via a different switch control line and can receive the switch control signal SWC.

[0169] For example, the first MUX level MUX1 can be connected to the switch controller 440 via the first switch control line and receive the first switch control signal; the second MUX level MUX2 can be connected to the switch controller 440 via the second switch control line and receive the second switch control signal; the third MUX level MUX3 can be connected to the switch controller 440 via the third switch control line and receive the third switch control signal; the fourth MUX level MUX4 can be connected to the switch controller 440 via the fourth switch control line and receive the fourth switch control signal; and the fifth MUX level MUX5 can be connected to the switch controller 440 via the fifth switch control line and receive the fifth switch control signal.

[0170] The first, second, and third switching elements included in any of the multiple MUX levels MUX1 to MUX5 can be connected to the switch controller 440 in the data driver circuit 120 via a common switch control line and can receive the switch control signal SWC.

[0171] For example, the first to third switching elements S11, S12, and S13 included in the first MUX level MUX1 can be connected to the switch controller 440 via the first switch control line and receive the same first switch control signal. Similarly, the switching elements S21 to S23 in the second MUX level MUX2 can be connected via the second switch control line and receive the second switch control signal, the switching elements S31 to S33 in MUX3 can be connected via the third switch control line and receive the third switch control signal, the switching elements S41 to S43 in the fourth MUX level MUX4 can be connected via the fourth switch control line and receive the fourth switch control signal, and the switching elements S51 to S53 in the fifth MUX level MUX5 can be connected via the fifth switch control line and receive the fifth switch control signal.

[0172] In other words, the extension time of each of the MUX levels MUX1 to MUX5 can be controlled individually, and the extension times can be the same or at least partially different from each other.

[0173] In addition, the extension times of the first to third switching elements contained in any of the MUX levels MUX1 to MUX5 can also be the same.

[0174] Specifically, each of the multiple MUX levels MUX1 to MUX5 can receive any one of the switching control signals corresponding to the first length of the extended time TYP, the second length of the extended time MIN, or the third length of the extended time MAX, based on the bit switching count corresponding to each of the multiple MUX levels MUX1 to MUX5.

[0175] For example, when the bit switching counts corresponding to the first MUX level MUX1 and the third MUX level MUX3 are within the range of a first threshold and a second threshold, the bit switching counts corresponding to the second MUX level MUX2 and the fourth MUX level MUX4 are less than the first threshold, and the bit switching count corresponding to the fifth MUX level MUX5 is equal to or greater than the second threshold, the first MUX level MUX1 to the third MUX level MUX3 can receive a switch control signal corresponding to a first-length extension time TYP, the second MUX level MUX2 and the fourth MUX level MUX4 can receive a switch control signal corresponding to a second-length extension time MIN, and the fifth MUX level MUX5 can receive a switch control signal corresponding to a third-length extension time MAX. The extension time of each of the multiple MUX levels MUX1 to MUX5 can be controlled based on the received switch control signals.

[0176] However, this is merely an example, and the extension time set in a display device is not limited to the three types mentioned above. For instance, the extension time based on a specific bit switching count standard can be set to four or more types.

[0177] Meanwhile, the first, second, and third switching elements included in any one of the multiple MUX levels MUX1 to MUX5 can be connected to the switch controller 440 in the data driver circuit 120 via different switch control lines, and can receive the switch control signal SWC.

[0178] For example, in the first MUX level MUX1, the first switching element S11 can be connected to the switch controller 440 via the first-1 switch control line of the first switch control line and receive the first-1 switch control signal; the second switching element S12 can be connected via the first-2 switch control line and receive the first-2 switch control signal of the first switch control line; and the third switching element S13 can be connected via the first-3 switch control line of the first switch control line and receive the first-3 switch control signal.

[0179] In the second MUX level MUX2, the first switching element S21 can be connected to the switch controller 440 via the second-1 switch control line in the second switch control line, and receives the second-1 switch control signal. The second switching element S22 can be connected to the switch controller 440 via the second-2 switch control line in the second switch control line, and receives the second-2 switch control signal. The third switching element S23 can be connected to the switch controller 440 via the second-3 switch control line in the second switch control line, and receives the second-3 switch control signal.

[0180] In the third MUX level MUX3, the first switching element S31 can be connected to the switch controller 440 via the third-1 switch control line in the third switch control line, and receives the third-1 switch control signal. The second switching element S32 can be connected to the switch controller 440 via the third-2 switch control line, and receives the third-2 switch control signal. The third switching element S33 can be connected to the switch controller 440 via the third-3 switch control line, and receives the third-3 switch control signal.

[0181] In the fourth MUX level MUX4, the first switching element S41 can be connected to the switch controller 440 via the fourth-1 switch control line in the fourth switch control line, and receives the fourth-1 switch control signal. The second switching element S42 can be connected to the switch controller 440 via the fourth-2 switch control line, and receives the fourth-2 switch control signal. The third switching element S43 can be connected to the switch controller 440 via the fourth-3 switch control line, and receives the fourth-3 switch control signal.

[0182] In the fifth MUX level MUX5, the first switching element S51 can be connected to the switch controller 440 via the fifth-1 switch control line in the fifth switch control line, and receives the fifth-1 switch control signal. The second switching element S52 can be connected to the switch controller 440 via the fifth-2 switch control line, and receives the fifth-2 switch control signal. The third switching element S53 can be connected to the switch controller 440 via the fifth-3 switch control line, and receives the fifth-3 switch control signal.

[0183] In other words, in any of the first to third switching elements contained in multiple MUX levels MUX1 to MUX5, the extension times of at least two switching elements may be the same or different.

[0184] Specifically, each of the first to third switching elements in any of the multiple MUX levels MUX1 to MUX5 can receive any one of the switching control signals corresponding to the first length extension time TYP, the second length extension time MIN, or the third length extension time MAX based on the bit switching count corresponding to each of the first to third switching elements in the corresponding MUX level.

[0185] At least one of the first switching elements S11, S21, S31, S41, S51, the second switching elements S12, S22, S32, S42, S52, and the third switching elements S13, S23, S33, S43, S53 in multiple MUX levels MUX1 to MUX5 can be a p-type transistor or an n-type transistor. Each switching element implemented as a transistor can receive a switching control signal SWC through its gate node.

[0186] Figures 7A to 8 This is a diagram illustrating an example of extended time in a control display device 100 according to an embodiment of the present disclosure.

[0187] Specifically, Figure 7A A timing diagram according to an embodiment is shown, wherein a first extended time SPT1 controls each of the plurality of MUX levels MUX1 to MUX5 during a single horizontal time (1H time). Figure 7B A timing diagram according to an embodiment is shown, wherein a second extended time SPT2 controls each of the multiple MUX levels MUX1 to MUX5 during a single horizontal time period. Figure 8 A timing diagram is shown based on the switching operations of the first to third switching elements included in each of the multiple MUX levels MUX1 to MUX5 during a single horizontal time period.

[0188] refer to Figure 7A and Figure 7B Each of the multiple MUX levels MUX1 to MUX5 can control at least one of the first extension time SPT1 and the second extension time SPT2 based on the switch control signal SWC received from the switch controller 440 during the activation time of the scan strobe signal SCAN, wherein the n MUX levels are activated sequentially.

[0189] Here, the activation time of the scan strobe signal SCAN can refer to the period during which the scan strobe signal SCAN is at a high level.

[0190] The first extended time SPT1 may include an initial deactivation time from the activation start point of the scan strobe signal SCAN to the activation start point of the first MUX level out of n MUX levels, at least one intermediate deactivation time between the activation end point of the (n-1)th MUX level and the activation start point of the nth MUX level, and a final deactivation time from the activation end point of the nth MUX level to the end point of the scan strobe signal. Here, the number of intermediate deactivation times can be (n-1).

[0191] The data driver circuit 120 can control the length of at least one of the initial deactivation time, at least one intermediate deactivation time, and the final deactivation time.

[0192] exist Figure 7A In the example, the initial deactivation time may include the first deactivation time SPT1-1, the intermediate deactivation times may include the second to fifth deactivation times SPT1-2 to SPT1-5, and the final deactivation time may include the sixth deactivation time SPT1-6.

[0193] In other words, in Figure 7AIn the example, the first extended time SPT1 may include a first deactivation time SPT1-1 from the activation start point of the scan strobe signal SCAN to the activation start point of the first MUX level MUX1, a second deactivation time SPT1-2 from the activation end point of MUX1 to the activation start point of MUX2, a third deactivation time SPT1-3 from the activation end point of MUX2 to the activation start point of MUX3, a fourth deactivation time SPT1-4 from the activation end point of MUX3 to the activation start point of MUX4, a fifth deactivation time SPT1-5 from the activation end point of MUX4 to the activation start point of MUX5, and a sixth deactivation time SPT1-6 from the activation end point of MUX5 to the end point of the scan strobe signal SCAN.

[0194] For example, the length of each of the first deactivation time SPT1-1 to the fifth deactivation time SPT1-5 can be equal to the length of the extension time corresponding to the bit switching count of each of the MUX levels MUX1 to MUX5. Here, each of the extension times corresponding to the bit switching count of the first MUX level MUX1 to the fifth MUX level MUX5 can include at least one of a first length extension time TYP, a second length extension time MIN, and a third length extension time MAX.

[0195] Alternatively, the length of each of the second deactivation time SPT1-2 to the sixth deactivation time SPT1-6 can be equal to the length of the extended time corresponding to the bit switching count of each of the MUX levels MUX1 to MUX5.

[0196] The second extended time SPT2 may include n activation times, each corresponding to one of the n MUX levels. The data driver circuit 120 can control the length of at least one of the n activation times.

[0197] For example, according to Figure 7B For example, the second extended time SPT2 may include a first activation time SPT2-1 from the activation start point to the activation end point of the first MUX level MUX1, a second activation time SPT2-2 from the activation start point to the activation end point of the second MUX level MUX2, a third activation time SPT2-3 from the activation start point to the activation end point of the third MUX level MUX3, a fourth activation time SPT2-4 from the activation start point to the activation end point of the fourth MUX level MUX4, and a fifth activation time SPT2-5 from the activation start point to the activation end point of the fifth MUX level MUX5.

[0198] For example, the length of each of the first activation time SPT2-1 to the fifth activation time SPT2-5 can be equal to the length of the extension time corresponding to the bit switching count of each of MUX1 to MUX5. Here, the extension time corresponding to the bit switching count of each of the first MUX level MUX1 to the fifth MUX level MUX5 can include at least one of the first length extension time TYP, the second length extension time MIN, and the third length extension time MAX.

[0199] The switch controller 440 can provide a switch control signal SWC, which controls the first extended time SPT1, to the multiple MUX levels MUX1 to MUX5 based on a bit switching count corresponding to each of the multiple MUX levels MUX1 to MUX5.

[0200] For example, the switch control signal SWC provided to each MUX level MUX1 to MUX5 can be a signal that controls the first deactivation time SPT1-1 to the fifth deactivation time SPT1-5 or the second deactivation time SPT1-2 to the sixth deactivation time SPT1-6 to one of the following: a first length extension time TYP, a second length extension time MIN, and a third length extension time MAX.

[0201] The switch controller 440 can also provide a switch control signal SWC, which controls the second extended time SPT2, to multiple MUX levels MUX1 to MUX5 based on the bit switching count corresponding to each MUX level.

[0202] For example, the switch control signal SWC provided to MUX1 to MUX5 of the MUX level can be a signal that controls the first activation time SPT2-1 to the fifth activation time SPT2-5 to one of the first length extension time TYP, the second length extension time MIN, and the third length extension time MAX.

[0203] The switch controller 440 can provide switch control signals SWC to multiple MUX levels MUX1 to MUX5 based on the bit switching count corresponding to each MUX level, wherein the first extension time SPT1 and the second extension time SPT2 are both controlled.

[0204] according to Figure 7A and Figure 7B In the example, when a high-level scan strobe signal SCAN[k] is applied through the k-th strobe line (where k is a positive integer), the scan transistor SCT included in at least one sub-pixel SP connected to the k-th strobe line can be turned on.

[0205] Additionally, the first MUX level MUX1 to the fifth MUX level MUX5 can supply data voltage VDATA to data lines DL1 to DL5 during the first activation time SPT2-1 to the fifth activation time SPT2-5 according to the switching operation based on the switch control signal SWC, wherein the extension time is controlled and received from the switch controller 440. As a result, the data voltage VDATA can be transmitted to the first node N1 of the driving transistor DRT included in at least one sub-pixel SP connected to the k-th gate line.

[0206] according to Figure 7A For example, when controlling the length of the first deactivation time SPT1-1 to the fifth deactivation time SPT1-5 or the second deactivation time SPT1-2 to the sixth deactivation time SPT1-6 based on the switch control signal SWC, the length of the first activation time SPT2-1 to the fifth activation time SPT2-5 can be controlled to be the same.

[0207] according to Figure 7B For example, when the lengths of the first activation time SPT2-1 to the fifth activation time SPT2-5 are controlled based on the switch control signal SWC, the lengths of the first deactivation time SPT1-1 to the sixth deactivation time SPT1-6 can be controlled to be the same.

[0208] However, the embodiments of this disclosure are not limited thereto, and the lengths of the first deactivation time SPT1-1 to the fifth deactivation time SPT1-5 or the second deactivation time SPT1-2 to the sixth deactivation time SPT1-6 and the first activation time SPT2-1 to the fifth activation time SPT2-5 can be controlled simultaneously based on the switch control signal SWC.

[0209] refer to Figure 8 The first MUX level MUX1 to the fifth MUX level MUX5 can receive a switch control signal SWC from the switch controller 440, wherein at least one of the first extension time SPT1 and the second extension time SPT2 is controlled, based on the bit switching count corresponding to each of the first MUX level MUX1 to the fifth MUX level MUX5, and can control the switching operation of the corresponding first switch element S11, S21, S31, S41, S51, second switch element S12, S22, S32, S42, S52 and third switch element S13, S23, S33, S43, S53 based on the switch control signal SWC.

[0210] according to Figure 8Examples include the first to third switching elements S11, S12 and S13 in any of the first MUX level MUX1 to the fifth MUX level MUX5 (e.g., MUX1) which may have a first extension time SPT1 and a second extension time SPT2 that are controlled to be the same as each other.

[0211] However, this disclosure is not limited thereto, and at least two of the first to third switching elements (e.g., S11, S12, S13) in any of the MUX stages (e.g., MUX1) may have at least one of a first extension time SPT1 and a second extension time SPT2 that are controlled to be different from each other.

[0212] Figures 9 to 11 This is a diagram illustrating an example of controlling the extended time based on the MUX switching count in a display device 100 according to an embodiment of the present disclosure.

[0213] More specifically, Figure 9 The timing diagram shows that MUX2 and MUX3 of the second MUX level (MUX1) to MUX5 of the first MUX level are deactivated (i.e., MUX switching count = 3); Figure 10 The timing diagram shows that MUX2 through MUX4 in the second MUX level are deactivated (i.e., MUX switching count = 2); and Figure 11 The timing diagram shows that the second MUX level MUX2 to the fifth MUX level MUX5 are deactivated (i.e., MUX switching count = 1).

[0214] Reference Figures 9 to 11 The switch controller 440 can output a switch control signal SWC to control at least one of the first MUX level MUX1 to the fifth MUX level MUX5 to deactivate during the activation time of the scan strobe signal (e.g., SCAN[k]).

[0215] In other words, the switch controller 440 can output a switch control signal SWC to control the activation time of at least one MUX level to "0" during the activation time of the scan strobe signal (e.g., scan [k]).

[0216] according to Figure 9In the example, when the image data DATA corresponding to the second MUX level MUX2 and the third MUX level MUX3 during the activation time of the previous scan strobe signal SCAN[k-1] is the same as the image data DATA corresponding to the second MUX level MUX2 and the third MUX level MUX3 during the activation time of the current scan strobe signal SCAN[k], the switch controller 440 can output a switch control signal SWC to control the second MUX level MUX2 and the third MUX level MUX3 to be deactivated during the activation time of the current scan strobe signal SCAN[k].

[0217] Even when at least one of the first MUX level MUX1 to the fifth MUX level MUX5 is deactivated, the switch controller 440 according to an exemplary embodiment of the present disclosure can still output a switch control signal SWC in which at least one of the first extension time SPT1 and the second extension time SPT2 is controlled, thereby controlling the switching operation of each of the plurality of first MUX level MUX1 to the fifth MUX level MUX5.

[0218] Even when at least one of the first MUX level MUX1 to the fifth MUX level MUX5 is deactivated, the display device 100 according to the embodiments of the present disclosure can easily control the first extension time SPT1 and the second extension time SPT2.

[0219] The switching control signal SWC provided to each of the plurality of first MUX levels MUX1 to fifth MUX levels MUX5 can be a signal for controlling at least one of the first deactivation times SPT1-1 to sixth deactivation times SPT1-6 and the first activation times SPT2-1 to fifth activation times SPT2-5 corresponding to the plurality of first MUX levels MUX1 to fifth MUX levels MUX5 to a corresponding extension time of a first length extension time TYP, a second length extension time MIN, and a third length extension time MAX.

[0220] according to Figure 9 In the example, the switch control signal SWC provided to each of the plurality of first MUX levels MUX1 to fifth MUX levels MUX5 can control the second and third activation times SPT2-2 and SPT2-3 to "0", thereby deactivating the second MUX level MUX2 and the third MUX level MUX3; control the first activation time SPT2-1 to an extended time MAX of a third length corresponding to the bit switching count of the first MUX level MUX1; and control the fourth activation time SPT2-4 and the fifth activation time SPT2-5 to an extended time TYP of a first length corresponding to the bit switching count of the fourth MUX level MUX4 and the fifth MUX level MUX5, respectively.

[0221] according to Figure 10 In the example, the switch control signal SWC provided to each of the plurality of first MUX levels MUX1 to fifth MUX levels MUX5 can control the second activation time SPT2-2 to the fourth activation time SPT2-4 to "0", thereby deactivating the second MUX levels MUX2 to the fourth MUX levels MUX4; control the first activation time SPT2-1 to an extended time MAX of a third length corresponding to the bit switching count of the first MUX level MUX1; and control the fifth activation time SPT2-5 to an extended time TYP of a first length corresponding to the bit switching count of the fifth MUX level MUX5.

[0222] according to Figure 11 For example, the switch control signal SWC provided to each of the multiple first MUX levels MUX1 to fifth MUX levels MUX5 can control the second activation time SPT2-2 to the fifth activation time SPT2-5 to "0", thereby deactivating the second MUX levels MUX2 to the fifth MUX levels MUX5, and control the first activation time SPT2-1 to an extended time MAX of a third length corresponding to the bit switching count of the first MUX level MUX1.

[0223] However, Figures 9 to 11 The timing diagrams shown are merely examples, and exemplary embodiments of this disclosure are not limited thereto. The length of the extended time (e.g., TYP, MIN, MAX) corresponding to each of the deactivation times SPT1-1 to SPT1-6 and the activation times SPT2-1 to SPT2-5 can be predetermined based on at least one of the bit switching counts of each of the first MUX levels MUX1 to the fifth MUX levels MUX5, the number of deactivation MUX levels, and the position of the deactivation MUX levels.

[0224] The display device according to an exemplary embodiment of the present disclosure can be described as follows.

[0225] A display device according to an exemplary embodiment of this disclosure may include: a display panel having a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels, and a demultiplexer; a data driver circuit that provides data voltages corresponding to image data to a plurality of data channels; and a controller that controls the data driver circuit and provides the image data to the data driver circuit. The demultiplexer may include a plurality of MUX stages, and the connection between the plurality of data channels and the plurality of data lines can be controlled by switching operations of the MUX stages. The data driver circuit may control the length of at least one of a first extension time and a second extension time of the MUX stages based on a bit switching count of the image data.

[0226] The data driver circuit can select an extension time corresponding to the bit switching count from multiple preset extension times for multiple MUX levels, and can output a switching control signal based on the selected extension time to the MUX level.

[0227] The data driver circuit can receive the initial switching control signal for the MUX level from the controller, and can generate the switching control signal by controlling the initial extension time corresponding to the initial switching control signal based on the selected extension time.

[0228] The first deactivation time may include: an initial deactivation time from the activation start point of the scan strobe signal to the activation start point of the first MUX level among the n MUX levels (where n is a positive integer) that are sequentially activated during the activation time of the scan strobe signal; at least one intermediate deactivation time between the activation start point of the (n-1)th MUX level and the activation end point of the nth MUX level; and a final deactivation time from the activation end point of the nth MUX level to the end point of the scan strobe signal.

[0229] The data driver circuit can control the length of at least one of the initial deactivation time, at least one intermediate deactivation time, and the final deactivation time.

[0230] The second extended time may include n activation times, each of which corresponds to a MUX level that is sequentially activated during the activation time of the scan strobe signal.

[0231] The data driver circuit can control the length of at least one of the n activation times.

[0232] When the bit switching count of the image data is equal to or greater than a first threshold and less than or greater than a second threshold, the data driver circuit can select a first extension time with a first length. When the bit switching count is less than the first threshold, the data driver circuit can select a second extension time shorter than the first extension time. When the bit switching count is equal to or greater than the second threshold, the data driver circuit can select a third extension time longer than the first extension time.

[0233] Image data may include multiple data bit values ​​corresponding to multiple data lines.

[0234] The bit switching count of the k-th MUX level (where k is a positive integer satisfying 2≤k≤n) in n MUX levels can correspond to the number of bits changed between the data bit values ​​of the (k-1)-th MUX level and the k-th MUX level.

[0235] The bit switching count of the first MUX level out of n MUX levels can be the number of "1" bits in the data bit values ​​of the first MUX level.

[0236] The data channels may include at least one first data channel corresponding to a first color, at least one second data channel corresponding to a second color, and at least one third data channel corresponding to a third color.

[0237] Each of the plurality of MUX levels may include a first switching element connected to a corresponding first data channel in the at least one first data channel, a second switching element connected to a corresponding second data channel in the at least one second data channel, and a third switching element connected to a corresponding third data channel in the at least one third data channel.

[0238] The first, second, and third switching elements included in any of the multiple MUX levels can be connected to the data driver circuit via a common switch control line and can receive switch control signals.

[0239] The first, second, and third switching elements included in any of the multiple MUX levels can be connected to the data driver circuit via different switch control lines and can receive switch control signals.

[0240] Each MUX level can be connected to the data driver circuit via a different switch control line and can receive switch control signals.

[0241] The data driver circuit can control at least one of the multiple MUX levels to be deactivated during the activation time of the scan strobe signal.

[0242] Multiple MUX levels may include at least one switching element implemented as a p-type transistor or an n-type transistor.

[0243] The data driver circuit according to embodiments of the present disclosure may include: a latch circuit that receives and latches image data from a controller; a bit counting circuit that counts bit switching counts of the image data output from the latch circuit; a switch controller that controls the length of at least one of a first extension time and a second extension time of a plurality of MUX levels in a demultiplexer for connections between a plurality of data channels and a plurality of data lines based on the bit switching counts; a digital-to-analog converter that converts the image data output from the latch circuit into a data voltage based on gamma grayscale voltage; and an output buffer that outputs the data voltage to the demultiplexer through the plurality of data channels.

[0244] The switch controller can select an extension time corresponding to the bit switching count from a number of preset extension times, and can output a switch control signal based on the selected extension time to multiple MUX stages included in the multiplexer.

[0245] The above description has been presented to enable any person skilled in the art to make and use the technical ideas of this disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the technical concept and scope of this disclosure. The above description and figures provide examples of the technical ideas of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of this disclosure.

[0246] Cross-reference to related applications

[0247] This application claims priority to Korean Patent Application No. 10-2024-0171275, filed in Korea on November 26, 2024, which is expressly incorporated herein by reference for all purposes, as if fully set forth herein.

Claims

1. A display device, the display device comprising: The display panel includes multiple gate lines, multiple data lines, multiple sub-pixels, and a demultiplexer; A data driver circuit that provides data voltages corresponding to image data to multiple data channels; as well as The controller controls the data driver circuit and provides the image data to the data driver circuit. The demultiplexer includes multiple multiplexer MUX stages, and the connection between the multiple data channels and the multiple data lines is controlled by the switching operations of the multiple MUX stages. The data driver circuit controls the length of at least one of the multiple preset extension times for the multiple MUX levels based on the bit switching count of the image data.

2. The display device according to claim 1, in, The data driver circuit selects an extension time corresponding to the bit switching count from the plurality of preset extension times, and outputs a switching control signal based on the selected extension time to the plurality of MUX stages.

3. The display device according to claim 2, in, The data driver circuit receives initial switching control signals for the plurality of MUX levels from the controller, and generates the switching control signals by controlling an initial extension time corresponding to the initial switching control signals according to the selected extension time.

4. The display device according to claim 1, in, The plurality of preset extension times include a first extension time, which includes: The initial deactivation time is from the activation start point of the scan gating signal to the activation start point of the first MUX level among the n MUX levels sequentially activated during the activation time of the scan gating signal, where n is a positive integer; At least one intermediate deactivation time, the at least one intermediate deactivation time being between the activation end point of the (n-1)th MUX level and the activation start point of the nth MUX level; and The final deactivation time, which is from the end of the activation at the nth MUX level to the end of the scan strobe signal, and The data driver circuit controls the length of at least one of the initial deactivation time, the at least one intermediate deactivation time, and the final deactivation time.

5. The display device according to claim 1, in, The plurality of preset extension times include a second extension time, which includes n activation times. Each of the n activation times corresponds to one of the n MUX levels sequentially activated during the activation time of the scan gating signal, where n is a positive integer. The data driver circuit controls the length of at least one of the n activation times.

6. The display device according to claim 2, in, When the bit switching count of the image data is equal to or greater than a first threshold and less than a second threshold, the data driver circuit selects an extension time with a first length from the plurality of preset extension times, wherein the second threshold is greater than the first threshold.

7. The display device according to claim 6, in, When the bit switching count of the image data is less than the first threshold, the data driver circuit selects a second length of extension time from the plurality of preset extension times, the second length being shorter than the first length, and When the bit switching count of the image data is equal to or greater than the second threshold, the data driver circuit selects a third length of extension time from the plurality of preset extension times, the third length being longer than the first length.

8. The display device according to claim 4, in, The image data includes multiple data bit values ​​corresponding to the multiple data lines, and The bit switching count of the k-th MUX level in the n MUX levels corresponds to the number of switching bits between the data bit values ​​of the (k-1)-th MUX level and the k-th MUX level, where k is a positive integer satisfying 2≤k≤n.

9. The display device according to claim 8, in, The bit switching count of the first MUX level out of the n MUX levels is the number of "1" bits in the data bit values ​​of the first MUX level.

10. The display device according to claim 2, in, The plurality of data channels include at least one first data channel corresponding to the first color, at least one second data channel corresponding to the second color, and at least one third data channel corresponding to the third color. Each of the plurality of MUX levels includes: A first switching element is connected to a corresponding first data channel in the at least one first data channel; A second switching element, the second switching element being connected to a corresponding second data channel in the at least one second data channel; and A third switching element is connected to a corresponding third data channel in the at least one third data channel.

11. The display device according to claim 10, in, The first, second, and third switching elements included in one of the plurality of MUX levels are connected to the data driver circuit via a common switching control line and receive the switching control signal.

12. The display device according to claim 10, in, The first, second, and third switching elements included in one of the plurality of MUX levels are connected to the data driver circuit via different switching control lines and receive the switching control signals.

13. The display device according to claim 2, in, Each of the plurality of MUX levels is connected to the data driver circuit via a different switch control line and receives the switch control signal.

14. The display device according to claim 1, in, The data driver circuit controls at least one of the plurality of MUX levels to be deactivated during the activation time of the scan strobe signal.

15. The display device according to claim 1, in, The plurality of MUX stages include at least one switching element of p-type transistors and n-type transistors.

16. A data driver circuit, the data driver circuit comprising: A latching circuit that receives and latches image data from the controller; A bit counting circuit that counts the bit switching counts of the image data output from the latch circuit; A switch controller, which controls the length of at least one of a plurality of preset extension times for a plurality of multiple multiplexer MUX levels within a demultiplexer based on the bit switching count, the demultiplexer controlling the connection between a plurality of data channels and a plurality of data lines; A digital-to-analog converter that converts the image data output from the latch circuit into a data voltage based on the gamma grayscale voltage; as well as An output buffer that outputs the data voltage to the demultiplexer through the plurality of data channels.

17. The data driver circuit according to claim 16, in, The switch controller selects an extension time corresponding to the bit switching count from the plurality of preset extension times, and outputs a switch control signal based on the selected extension time to the plurality of MUX levels.

18. A display device, the display device comprising: According to claim 16, the data driver circuit is configured to provide the data voltage corresponding to the image data to the plurality of data channels; The display panel includes multiple gate lines, multiple data lines, multiple sub-pixels, and the demultiplexer. as well as The controller is configured to control the data driver circuit and provide the image data to the data driver circuit.

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