Pixel circuits and display panels

Abstract

This application discloses a pixel circuit and a display panel. The pixel circuit includes: a driving module, a first voltage transmission module, a compensation module, a first storage module, a second storage module, and a second voltage transmission module; the compensation module is connected between the second terminal of the driving module and a control terminal; the first terminal of the first storage module is electrically connected to the control terminal of the driving module; the second storage module is connected between the first terminal of the driving module and the second terminal of the first storage module; the first voltage transmission module is used to conduct during the threshold compensation stage, transmitting a first reference voltage to the first terminal of the driving module; the compensation module is also used to conduct during the threshold compensation stage; the second voltage transmission module is used to transmit a data voltage to the first terminal of the second storage module during the data writing stage. This application embodiment can improve the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a pixel circuit and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display panels needs improvement. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above background, this application provides a pixel circuit and a display panel, which aims to improve the performance of the display panel.

[0005] This application provides a pixel circuit, including: a driving module, a first voltage transmission module, a compensation module, a first storage module, a second storage module, and a second voltage transmission module; The first voltage transmission module is connected to the first reference voltage; the first voltage transmission module is electrically connected to the first terminal of the drive module; The compensation module is connected between the second end of the drive module and the control end of the drive module; The first terminal of the first storage module is electrically connected to the control terminal of the drive module; The second storage module is connected between the first end of the drive module and the second end of the first storage module; the first end of the second storage module and the second end of the first storage module are electrically connected to the first end of the second voltage transmission module; the second voltage transmission module is connected to the data voltage. The first voltage transmission module is used to turn on during the threshold compensation stage to transmit the first reference voltage to the first terminal of the drive module, and the compensation module is used to turn on during the threshold compensation stage. The second voltage transmission module is used to transmit the data voltage to the first end of the second storage module during the data writing phase.

[0006] This application also provides a display panel, including: the pixel circuit provided in any embodiment of this application.

[0007] In the pixel circuit of this embodiment, the compensation module is connected between the second end of the driving module and the control end of the driving module; the first end of the first storage module is electrically connected to the control end of the driving module; the second end of the first storage module is connected to the second voltage transmission module; the second voltage transmission module receives the data voltage; the second storage module is connected between the first end of the driving module and the second end of the first storage module; the first end of the second storage module and the second end of the first storage module are electrically connected to the first end of the second voltage transmission module; the first voltage transmission module is turned on during the threshold compensation stage to transmit the first reference voltage to the first end of the driving module; the compensation module is turned on during the threshold compensation stage to transmit the voltage related to the first reference voltage and the threshold voltage of the driving module to the control end of the driving module; so that the threshold voltage can be stored in the first storage module; during the data writing stage, the second voltage transmission module transmits the data voltage to the first end of the second storage module to write the data voltage into the second storage module; the data voltage can be directly coupled to the control end of the driving module through the first storage module, so that there is no data voltage loss, which is beneficial to achieving high brightness and improving the display effect. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this application.

[0010] Figure 2 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0011] Figure 3 This is a timing waveform diagram of a write frame provided in an embodiment of this application.

[0012] Figure 4 This is a timing waveform diagram of a hold frame provided in an embodiment of this application.

[0013] Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0014] Figure 6 The timing waveform diagram of another write frame provided in the embodiment of this application.

[0015] Figure 7 This is a timing waveform diagram of another hold frame provided in an embodiment of this application.

[0016] Figure 8 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0017] Figure 9 The timing waveform diagram of another write frame provided in the embodiment of this application.

[0018] Figure 10 This is a timing waveform diagram of another hold frame provided in an embodiment of this application.

[0019] Figure 11 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0020] Figure 12 The timing waveform diagram of another write frame provided in the embodiment of this application.

[0021] Figure 13 This is a timing waveform diagram of another hold frame provided in an embodiment of this application.

[0022] Figure 14 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0023] Figure 15 This is a timing waveform diagram of another hold frame provided in an embodiment of this application.

[0024] Figure 16 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0025] Figure 17 This is a schematic diagram of the structure of another display panel provided in an embodiment of this application.

[0026] Figure 18 This is a flowchart of a display panel driving method provided in an embodiment of this application.

[0027] Figure 19 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0028] Figure 20 This is a schematic diagram of a pixel circuit in related technologies. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0031] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0032] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0033] For certain elements, terms such as "above" or "over" are sometimes used when describing the position of an element located in the Z direction, and "below" or "under" are used when describing the position of an element located in the opposite direction. Furthermore, when using terms such as "above," "over," "below," "under," or "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly adjacent, but also the state where the two elements are separated by gaps or other elements. Additionally, the terms "first," "second," and "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance or order. At least one may include one or more. At least part may include part or all. The first direction and the second direction intersect, for example, they may be perpendicular. At least one may include one or more. Connections may include direct connections or indirect connections.

[0034] This application provides a pixel circuit. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. The pixel circuit 200 includes: a driving module 10, a first voltage transmission module 20, a compensation module 30, a first storage module 40, a second storage module 50, and a second voltage transmission module 60.

[0035] The first voltage transmission module 20 is connected to the first reference voltage V1; the first voltage transmission module 20 is electrically connected to the first terminal S of the drive module 20. The compensation module 30 is connected between the second terminal D of the drive module 20 and the control terminal G of the drive module 20. The first end of the first storage module 40 is electrically connected to the control terminal G of the drive module 10; The second storage module 50 is connected between the first end of the drive module 10 and the second end of the first storage module 40; the first end of the second storage module 40 and the second end of the first storage module 40 are electrically connected to the first end of the second voltage transmission module 60 (which can be connected to the first node N1); the second voltage transmission module 60 receives the data voltage. The first voltage transmission module 20 is used to turn on during the threshold compensation stage T2 to transmit the first reference voltage V1 to the first terminal S of the drive module 10. The compensation module 30 is used to turn on during the threshold compensation stage T2 to transmit the voltage related to the first reference voltage V1 and the threshold voltage of the drive module 10 to the control terminal G of the drive module 10. The second voltage transmission module 60 is used to transmit the data voltage Vdata to the first end of the second storage module 40 during the data writing stage T3.

[0036] For example, the driving module 10 may include a driving transistor M1. The driving transistor M1 may include an N-type transistor or a metal-oxide-semiconductor transistor. The gate of the driving transistor M1 may serve as the control terminal G of the driving module 10, the first terminal (e.g., the source) of the driving transistor M1 may serve as the first terminal S of the driving module 10, and the second terminal (e.g., the drain) of the driving transistor M1 may serve as the second terminal D of the driving module 10. The threshold voltage Vth of the driving module 10 may be the threshold voltage of the driving transistor M1. The driving module 10 and the light-emitting element 100 may be connected in series between a first power line and a second power line. The first power line may be used to transmit a first power supply voltage VDD. The second power line may be used to transmit a second power supply voltage VSS. For example, the first storage module 40 and the second storage module 50 may be connected in series between the first terminal S and the control terminal G of the driving module 20. For example, one of the first power supply voltage VDD and the second power supply voltage VSS may be a high voltage, and the other a low voltage. For example, the first power supply voltage VDD may be a high voltage, such as a positive voltage, and the second power supply voltage VSS may be a low voltage, such as a negative voltage.

[0037] During the threshold compensation stage T2, the control terminal G of the drive module 10 discharges to the input terminal of the first reference voltage V1 via the conducting compensation module 30, the conducting drive module 10, and the conducting first voltage transmission module 20, which is to perform threshold compensation of the drive module 10 until the voltage difference between the control terminal G and the first terminal S of the drive module 10 is the threshold voltage of the drive module 10. The potential of the control terminal G and the second terminal D of the drive module 10 is the sum of the first reference voltage V1 and the threshold voltage Vth of the drive module 10. The threshold voltage Vth or the voltage related to the threshold voltage Vth can be stored in the first storage module 40, which means that the voltage related to the first reference voltage V1 and the threshold voltage Vth of the drive module 10 is transmitted to the control terminal G of the drive module 10. The duration of the threshold compensation stage T2 is adjustable, meaning the compensation time is adjustable and can be set as needed. For example, the duration of the threshold compensation stage T2 can be greater than or equal to N times the row scan time of a single-row pixel circuit, where N is greater than or equal to 2. The row scan time can be the interval between the start times of the data writing stages corresponding to adjacent row pixel circuits, thereby improving the compensation effect. The threshold compensation stages T2 corresponding to multiple row pixel circuits can overlap, thereby achieving multi-row compensation, which is beneficial for achieving high-frequency driving. For example, the first reference voltage V1 can be a DC voltage or a variable voltage.

[0038] During the data writing phase T3, the second voltage transmission module 60 can transmit the data voltage Vdata to the first terminal of the second storage module 40 to write the data voltage Vdata into the second storage module 50. This means storing the data voltage Vdata or a voltage related to Vdata into the second storage module 50. Therefore, the data voltage Vdata can be directly coupled to the control terminal G of the driver module 10 via the first storage module 40, thereby increasing the range of the data voltage Vdata without loss of range (compared to the method of coupling the data voltage to the control terminal of the driver module through a coupling module during the data writing phase, such as...). Figure 20 As shown, Figure 20 The pixel circuitry in the image suffers from a loss in data voltage range (the voltage at the control terminal of the driving module is related to the capacitance ratio of the coupling module and the storage module), which is beneficial for achieving high brightness. Simultaneously, during the data writing phase T3, the second voltage transmission module 60 transmits the data voltage Vdata to the second terminal of the first storage module 40. Within the same write frame, the threshold compensation phase T2 can precede the data writing phase T3. For example, the compensation module 30 can be turned off during the data writing phase T3. For example, the second voltage transmission module 60 can be electrically connected to the data line Data. The data line Data can be used to transmit the data voltage Vdata.

[0039] During the light-emitting phase, the driving module 10 generates a driving current to drive the light-emitting element 100 to emit light based on the voltage difference between its control terminal G and its first terminal S. Through threshold compensation, the magnitude of the driving current generated by the driving module 10 during the light-emitting phase is independent of the threshold voltage Vth of the driving module 10, but is related to the data voltage Vdata. During the light-emitting phase, the first storage module 40 and the second storage module 50 are connected in series to maintain the voltage difference between the control terminal G and the first terminal S of the driving module 20, thereby ensuring that the driving module 10 generates a stable driving current.

[0040] In the pixel circuit of this embodiment, the compensation module 30 is connected between the second terminal D of the driving module 20 and the control terminal G of the driving module 20; the first terminal of the first storage module 40 is electrically connected to the control terminal G of the driving module 10; the second terminal of the first storage module 40 is connected to the second voltage transmission module 60; the second voltage transmission module 60 receives the data voltage; the second storage module 50 is connected between the first terminal of the driving module 10 and the second terminal of the first storage module 40; the first terminal of the second storage module 40 is electrically connected to the first terminal of the second voltage transmission module 60; the first voltage transmission module 20 is turned on during the threshold compensation stage T2, transmitting the first reference voltage. V1 is transmitted to the first terminal S of the driving module 10. The compensation module 30 is turned on during the threshold compensation stage T2 so that the voltage related to the first reference voltage V1 and the threshold voltage of the driving module 10 is transmitted to the control terminal G of the driving module 10. This allows the threshold voltage Vth to be stored in the first storage module 40. During the data writing stage T3, the second voltage transmission module 60 transmits the data voltage Vdata to the first terminal of the second storage module 40 so as to write the data voltage Vdata into the second storage module 50. The data voltage Vdata can be directly coupled to the control terminal G of the driving module 10 through the first storage module 40, thus eliminating data voltage loss, which is beneficial for achieving high brightness and improving the display effect.

[0041] Figure 2 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Optionally, based on the above embodiment, the second voltage transmission module 60 is connected to a second reference voltage V2, and the second voltage transmission module 60 is used to transmit the second reference voltage V2 to the second terminal of the first storage module 40 during the threshold compensation stage T2.

[0042] For example, the second voltage transmission module 60 can access the data voltage Vdata and the second reference voltage V2 through the same terminal in a time-division manner. For example, the second voltage transmission module 60 includes a fourth transistor M4, and the data voltage Vdata and the second reference voltage V2 are transmitted to the second terminal of the first storage module 40 through the same transistor M4 in a time-division manner. For example, the data line Data can be used to transmit the data voltage Vdata and the second reference voltage V2 in a time-division manner.

[0043] For example, the first reference voltage V1 and the second reference voltage V2 may be the same or different. For example, if the first reference voltage V1 and the second reference voltage V2 are the same, they can be transmitted through the same signal line, thereby reducing the number of signal lines and simplifying wiring. Alternatively, the first reference voltage V1 and the second reference voltage V2 may be transmitted through different signal lines.

[0044] For example, the second reference voltage V2 can be a DC voltage or a variable voltage.

[0045] For example, the first reference voltage V1 and the second reference voltage V2 are the same, both being the voltage Vini. During the threshold compensation stage T2, the voltage at the second terminal of the first storage module 40 is Vini, and the voltage at the control terminal G of the drive module 10 is Vini + Vth. That is, the voltage at the first terminal of the first storage module 40 is Vini + Vth. Therefore, the voltage difference between the first terminal and the second terminal of the first storage module 40 is Vth, meaning the threshold voltage Vth can be stored in the first storage module 40. For example, during the data writing stage T3, the voltage at the control terminal G of the drive module 10 is Vdata + Vth.

[0046] For example, the first reference voltage V1 and the second reference voltage V2 are different. In the threshold compensation stage T2, the voltage at the second terminal of the first storage module 40 is V2, and the voltage at the control terminal G of the drive module 10 is V1 + Vth. That is, the voltage at the first terminal of the first storage module 40 is V1 + Vth. Therefore, the voltage difference between the first terminal and the second terminal of the first storage module 40 is V1 + Vth - V2. In other words, the voltage (V1 + Vth - V2) related to the threshold voltage Vth can be stored in the first storage module 40. For example, in the data writing stage T3, the voltage at the control terminal G of the drive module 10 is Vdata + Vth + V1 - V2.

[0047] See Figure 2 Optionally, the second voltage transmission module 60 includes a first voltage transmission unit 61 and a second voltage transmission unit 62. The first voltage transmission unit 61 is electrically connected to the first terminal of the second storage module 40. The first voltage transmission unit 61 receives the data voltage and is used to transmit the data voltage Vdata to the first terminal of the second storage module 40 during the data writing phase T3. For example, during the data writing phase T3, the first voltage transmission unit 61 transmits the data voltage Vdata to the first terminal of the second storage module 40, the second terminal of the first storage module 40, and the first node N1. During the data writing phase T3, the second voltage transmission unit 62 is turned off.

[0048] The second voltage transmission unit 62 is electrically connected to the second terminal of the first storage module 40. The second voltage transmission unit 62 is connected to the second reference voltage V2. The second voltage transmission unit 62 is used to conduct during the threshold compensation stage T2 and transmit the second reference voltage V2 to the second terminal of the first storage module 40.

[0049] For example, during the threshold compensation phase T2, the second voltage transmission unit 62 transmits the second reference voltage V2 to the second terminal of the first storage module 40, the first terminal of the second storage module 40, and the first node N1. During the threshold compensation phase T2, the first voltage transmission unit 61 is turned off. For example, the first voltage transmission unit 61 may include a fourth transistor M4, and the second voltage transmission unit 62 may include a third transistor M3. The data voltage Vdata and the second reference voltage V2 can be transmitted to the first node N1 (i.e., the second terminal of the first storage module 40 or the first terminal of the second storage module 40) in a time-division manner through different voltage transmission units or different transistors.

[0050] Optionally, the control terminal of the second voltage transmission unit 62 and the control terminal of the compensation module 30 can be connected to the same gate signal and / or the same gate line (e.g., the first gate line, which can transmit the first gate signal EMB1), thereby reducing the number of signal lines and simplifying wiring. The switching states of the second voltage transmission unit 62 and the compensation module 30 can be the same, that is, they can be turned on and off at the same time.

[0051] Optionally, the transistors in the second voltage transmission unit 62 and the transistors in the compensation module 30 have the same channel type. The channel type may include N-type or P-type.

[0052] Optionally, the compensation module 30 includes an N-type transistor. For example, the compensation module 30 includes a metal-oxide-semiconductor transistor, thereby reducing leakage current at the control terminal G of the drive module 10. In other embodiments, the compensation module 30 includes a P-type transistor.

[0053] For example, N-type transistors include metal-oxide transistors, which may include IGZO (indium gallium zinc oxide) transistors. For example, P-type transistors may include polysilicon transistors.

[0054] For example, the compensation module 30 includes a second transistor M2. Alternatively, both the third transistor M3 and the second transistor M2 are N-type transistors.

[0055] For example, the first voltage transmission unit 61 or the fourth transistor M4 includes an N-type transistor or a P-type transistor. See also Figure 2 Optionally, the pixel circuit further includes a first light-emitting control module 80, which is connected between the second terminal of the second storage module 50 and the first terminal of the driving module 10. For example, the first light-emitting control module 80 is turned off during the threshold compensation stage T2. For example, the first light-emitting control module 80 is turned off during the data writing stage T3. For example, the first light-emitting control module 80 is turned on during the light-emitting stages T4 / T6, so that the driving current generated by the driving module 10 flows to the light-emitting element 100 to drive the light-emitting element 100 to emit light.

[0056] For example, the first light-emitting control module 80 may include a sixth transistor M6.

[0057] Optionally, see Figure 2 The pixel circuit also includes a first initialization module 70, the first end of the first initialization module 70 is electrically connected to the second end of the second storage module 50, the first end of the second storage module 50 is electrically connected to the second end of the first storage module 40, and the first initialization module 70 is connected to a first initialization voltage Vref; For example, the first initialization module 70 is used to transmit the first initialization voltage Vref to the second terminal of the second storage module 50 during the data writing phase T3 and / or the threshold compensation phase T2.

[0058] For example, the driving current I generated by the driving module 10 during the light-emitting phase is related to the difference (Vdata-Vref) between the data voltage Vdata and the first initialization voltage Vref. Alternatively, the driving current I generated by the driving module 10 during the light-emitting phase is related to the square of the difference (Vdata-Vref) between the data voltage Vdata and the first initialization voltage Vref. 2 Related.

[0059] In the data writing stage T3, the voltage at the first terminal of the second storage module 50 is Vdata, and the voltage at the second terminal of the second storage module 50 is Vref. Therefore, the voltage difference between the first terminal and the second terminal of the second storage module 50 is Vdata-Vref.

[0060] When the first reference voltage V1 and the second reference voltage V2 are the same, both being voltage Vini, during the light-emitting phases T4 / T6, the voltage difference between the control terminal G and the first terminal S of the driving module 10 is Vdata - Vref + Vth, and the driving current generated by the driving module 10... Where μ is the carrier mobility of driving transistor M0, Cox is the channel capacitance per unit area of ​​driving transistor M0, and W / L is the channel width-to-length ratio of driving transistor M0. For example, if driving transistor M0 is an N-type transistor, μ is the electron mobility of driving transistor M0. For example, if driving transistor M0 is a P-type transistor, μ is the hole mobility of driving transistor M0.

[0061] When the first reference voltage V1 and the second reference voltage V2 are different, during the light-emitting stages T4 / T6, the voltage difference between the control terminal G and the first terminal S of the driving module 10 is Vdata-Vref+Vth+V1-V2, and the driving current generated by the driving module 10 is... .

[0062] Optionally, see Figure 2 The first terminal of the first initialization module 70 is electrically connected to the first terminal of the light-emitting element 100.

[0063] For example, the light-emitting element 100 may include a light-emitting diode, such as an organic light-emitting diode. For example, one of the first and second terminals of the light-emitting element 100 may be an anode, and the other a cathode. For example, the first terminal of the light-emitting element 100 may be an anode, and the second terminal may be a cathode. The second terminal of the light-emitting element 100 may be connected to a second power supply voltage VSS.

[0064] For example, the first initialization module 70 is used in the first initialization phase T1 to transmit a first initialization voltage Vref to a first terminal of the light-emitting element 100 and / or a second terminal of the second storage module 50. For example, in the first initialization phase T1, the first initialization module 70 is turned on, transmitting the first initialization voltage Vref to the second terminal of the second storage module 50 to initialize the second terminal of the second storage module 50. For example, in the first initialization phase T1, the first initialization module 70 is turned on, transmitting the first initialization voltage Vref to the first terminal of the light-emitting element 100 to initialize the first terminal of the light-emitting element 100.

[0065] For example, see Figure 2The second voltage transmission module 60 is used in the first initialization phase T1 to transmit the second reference voltage V2 to the second terminal of the first storage module 40 and / or the first terminal of the second storage module 50, that is, to transmit the second reference voltage V2 to the second terminal of the first storage module 40 and / or the first terminal of the second storage module 50, so as to initialize the second terminal of the first storage module 40 and / or the first terminal of the second storage module 50. For example, see Figure 2 The second voltage transmission unit 62 is used to turn on during the first initialization phase T1, transmitting the second reference voltage V2 to the second terminal of the first storage module 40 and / or the first terminal of the second storage module 50 to initialize the second terminal of the first storage module 40 and / or the first terminal of the second storage module 50. For example, during the first initialization phase T1, the first voltage transmission unit 61 is turned off.

[0066] Optionally, see Figure 2 The control terminals of the first initialization module 70 and the first light-emitting control module 80 are connected to the same gate signal and / or the same gate line (e.g., a light-emitting control signal line, which can transmit the light-emitting control signal and may be a third gate signal EM) to reduce the number of signal lines and simplify wiring. The switching states of the first initialization module 70 and the first light-emitting control module 80 can be opposite; for example, when the first initialization module 70 is on, the first light-emitting control module 80 is off; when the first light-emitting control module 80 is on, the first initialization module 70 is off.

[0067] For example, in the first initialization phase T1, the first light-emitting control module 80 is turned off.

[0068] For example, the transistors in the first initialization module 70 and the transistors in the first light-emitting control module 80 have different channel types.

[0069] For example, the first initialization module 70 may include a ninth transistor M9.

[0070] Optionally, the first initialization module 70 includes an N-type transistor or a P-type transistor. For example, the ninth transistor M9 is an N-type transistor and the sixth transistor M6 is a P-type transistor; or, the ninth transistor M9 is a P-type transistor and the sixth transistor M6 is an N-type transistor.

[0071] For example, the first reference voltage V1 is higher than or equal to the first initialization voltage Vref.

[0072] For example, the first reference voltage V1 is higher than the first initialization voltage Vref. With this setting, the difference between the first power supply voltage VDD and the first reference voltage V1 is less than the difference between the first power supply voltage VDD and the first initialization voltage Vref, which reduces the discharge time of the control terminal of the drive module, i.e., reduces the duration of the threshold compensation stage, thus facilitating high-frequency drive. For example, by setting one of the first voltage transmission module and the first initialization module, the first initialization voltage Vref and the first reference voltage V1 can be transmitted to the first terminal of the drive module 10 and / or the second terminal of the second storage module 50 through the same module or transistor. Optionally, the first reference voltage V1 is equal to the first initialization voltage Vref.

[0073] Compared to setting one of the first voltage transmission module and the first initialization module to transmit the first initialization voltage Vref and the first reference voltage V1 to the first terminal of the driving module 10 and / or the second terminal of the second storage module 50 through the same module or transistor, by setting the first voltage transmission module and the first initialization module separately, the data voltage range and the uniformity of low grayscale display can be flexibly adjusted.

[0074] For example, the first initialization voltage Vref is higher than the second power supply voltage VSS. For example, the difference between the first initialization voltage Vref and the second power supply voltage VSS is less than the turn-on voltage of the light-emitting element 100, which can prevent the light-emitting element 100 from emitting light in the first initialization phase T1 and / or the second initialization phase T5.

[0075] Optionally, see Figure 2 The pixel circuit also includes a third voltage transmission module 90, which is electrically connected to the second terminal D of the driving module 10, and the third voltage transmission module 90 is connected to the first power supply voltage VDD. The third voltage transmission module 90 is used in the first initialization phase T1 to transmit the first power supply voltage VDD to the control terminal G of the drive module 10 via the conducting compensation module 30, so as to initialize the control terminal G of the drive module 10.

[0076] The pixel circuit is configured with a write frame, which includes a first initialization phase T1, a threshold compensation phase T2, and a data writing phase T3. For example, in the write frame, the first initialization phase T1 precedes the data writing phase T3, and / or, in the write frame, the first initialization phase T1 precedes the threshold compensation phase T2.

[0077] For example, the third voltage transmission module 90 is used to transmit the first power supply voltage VDD to the second terminal D of the drive module 10 during the light emission stages T4 / T6.

[0078] For example, the third voltage transmission module 90 is turned off during the threshold compensation phase T2 and / or the data writing phase T3.

[0079] For example, the first power supply voltage VDD is higher than the first reference voltage V1. This setting allows the drive module 10 to be turned on during the data writing phase T3, writing a voltage related to the first reference voltage V1 and the threshold voltage of the drive module 10 to the control terminal G of the drive module 10. For example, the difference between the first power supply voltage VDD and the first reference voltage V1 is greater than the threshold voltage of the drive module 10.

[0080] Optionally, see Figure 2 The third voltage transmission module 90 includes a fourth voltage transmission unit 91 and a fifth voltage transmission unit 92. The fourth voltage transmission unit 91 is electrically connected to the second terminal D of the drive module 10. The fourth voltage transmission unit 91 is used to turn on during the first initialization phase T1 and transmit the first power supply voltage VDD to the control terminal of the drive module 10 via the turned-on compensation module 30. The fifth voltage transmission unit 92 is electrically connected to the second terminal D of the driving module 10; the fifth voltage transmission unit 92 is connected to the first power supply voltage VDD, and the fifth voltage transmission unit 92 is used to conduct during the light emission stage T4 / T6 to transmit the first power supply voltage VDD to the second terminal D of the driving module 10.

[0081] For example, the fourth voltage transmission unit 91 may include a seventh transistor M7. The seventh transistor M7 may include an N-type transistor or a P-type transistor. The fifth voltage transmission unit 92 may include a fifth transistor M5.

[0082] Optionally, see Figure 2 The control terminal of the fifth voltage transmission unit 92 and the control terminal of the first light-emitting control module 80 are connected to the same gate signal and / or connected to the same gate line (e.g., a light-emitting control signal line, which can transmit the light-emitting control signal, and can be the third gate signal EM), thereby reducing the number of signal lines and simplifying wiring. The switching states of the fifth voltage transmission unit 92 and the first light-emitting control module 80 can be the same, for example, simultaneously on and simultaneously off.

[0083] Optionally, see Figure 2 The transistors in the first light-emitting control module 80 and the transistors in the fifth voltage transmission unit 92 have the same channel type, such as P-type transistors or N-type transistors. For example, the sixth transistor M6 and the fifth transistor M5 are both P-type transistors, or the sixth transistor M6 and the fifth transistor M5 are both N-type transistors.

[0084] For example, the transistors in the first light-emitting control module 80 and the fifth voltage transmission unit 92 are both P-type transistors, which can reduce power consumption. The difference between the high level and low level of the gate signal of a P-type transistor is less than the difference between the high level and low level of the gate signal of an N-type transistor. Therefore, the transistors in the first light-emitting control module 80 and the fifth voltage transmission unit 92 are both P-type transistors, which can reduce power consumption.

[0085] Optionally, see Figure 2 The control terminal of the fifth voltage transmission unit 92 and the control terminal of the first initialization module 70 are connected to the same gate signal and / or the same gate line (e.g., a light emission control signal line, which can transmit the light emission control signal, and can be the third gate signal EM), thereby reducing the number of signal lines and simplifying wiring. The switching states of the first initialization module 70 and the fifth voltage transmission unit 92 can be opposite. For example, when the first initialization module 70 is on, the fifth voltage transmission unit 92 is off; when the fifth voltage transmission unit 92 is on, the first initialization module 70 is off.

[0086] For example, see Figure 2 The transistors in the first initialization module 70 and the transistors in the fifth voltage transmission unit 92 have different channel types. For example, the ninth transistor M9 is an N-type transistor and the fifth transistor M5 is a P-type transistor; or, the ninth transistor M9 is a P-type transistor and the fifth transistor M5 is an N-type transistor.

[0087] Optionally, the power supply voltages connected to the four voltage transmission units 91 and the fifth voltage transmission unit 92 are the same, or connected to the same power supply line, thereby reducing the number of signal lines and simplifying wiring.

[0088] In other embodiments, the fourth voltage transmission unit 91 and the fifth voltage transmission unit 92 are connected to different power supply voltages or different power lines. For example, the fourth voltage transmission unit 91 is connected to a second type of first power supply voltage VDD2, and the fifth voltage transmission unit 92 is connected to a first type of first power supply voltage VDD1. The fourth voltage transmission unit 91 is used to turn on during the first initialization phase T1, transmitting the second type of first power supply voltage VDD2 to the control terminal of the driving module 10 via the turned-on compensation module 30. The fifth voltage transmission unit 92 is used to turn on during the light emission phases T4 / T6, transmitting the first type of first power supply voltage VDD1 to the second terminal D of the driving module 10.

[0089] Figure 3 This is a timing waveform diagram of a write frame provided in an embodiment of this application. Figure 4 This is a timing waveform diagram of a hold frame provided in an embodiment of this application. Figure 3 and Figure 4 Applicable to Figure 2 The pixel circuit shown. See also Figure 2 and Figure 3 Optionally, the conduction pulse of the gate signal EMB1 connected to the control terminal of the compensation module 30 (or the control terminal of the second voltage transmission unit 62) and the conduction pulse of the gate signal EMB2 connected to the control terminal of the first voltage transmission module 20 have the same pulse width W1. That is, the control terminal of the compensation module 30 (or the control terminal of the second voltage transmission unit 62) and the control terminal of the first voltage transmission module 20 can share the same gate driving circuit, such as the first gate driving circuit, thereby reducing the bezel width. The first gate driving circuit can be located in the non-display area of ​​the display panel.

[0090] For example, see Figure 2 and Figure 3 In the same write frame, the turn-on pulse of the gate signal EMB2 connected to the control terminal of the first voltage transmission module 20 lags behind the turn-on pulse of the gate signal EMB1 connected to the control terminal of the compensation module 30 (or the control terminal of the second voltage transmission unit 62). That is, in the same pixel circuit, the shift register connected to the control terminal of the first voltage transmission module 20 is the subsequent stage of the shift register connected to the control terminal of the compensation module 30 (or the control terminal of the second voltage transmission unit 62).

[0091] For example, see Figure 2 and Figure 3 The transistors in the compensation module 30 and the transistors in the first voltage transmission module 20 have the same channel type. The first voltage transmission module 20 may include an eighth transistor M8. For example, both the second transistor M2 and the eighth transistor M8 are N-type transistors, or both the second transistor M2 and the eighth transistor M8 are P-type transistors.

[0092] See Figure 2 Optionally, the first storage module 40 includes a first capacitor Cst1. The first terminal of the first capacitor Cst1 can serve as the first terminal of the first storage module 40, and the second terminal of the first capacitor Cst1 can serve as the second terminal of the first storage module 40. For example, the second storage module 50 includes a second capacitor Cst2. The first terminal of the second capacitor Cst2 can serve as the first terminal of the second storage module 50, and the second terminal of the second capacitor Cst2 can serve as the second terminal of the second storage module 50. For example, the ratio of the first capacitor Cst1 to the second capacitor Cst2, Cst1 / Cst2, is greater than or equal to 0.9:1 and less than or equal to 1:0.9. For example, Cst1 / Cst2 can be 0.9:1, 0.925:1, 0.95:1, 0.975:1, 1, 1:0.925, 1:0.95, 1:0.975, or 1:0.9, etc. For example, the first capacitor Cst1 and the second capacitor Cst2 are equal.

[0093] When the pixel circuit refresh rate is the first refresh rate, only write frames are set. When the pixel circuit refresh rate is the second refresh rate, both write frames and hold frames can be set. Hold frames do not include the threshold compensation stage T2 and / or the data write stage T3. The first refresh rate is higher than the second refresh rate.

[0094] For example, the pixel circuit is configured with a write frame and a hold frame, the hold frame including a second initialization phase T5. A first initialization module 70 is used in the second initialization phase T5 to transmit a first initialization voltage Vref to a first terminal of the light-emitting element 100 and / or a second terminal of the second storage module 50. For example, in the second initialization phase T5, the compensation module 20 and / or the second voltage transmission module 60 are turned off. For example, in the second initialization phase T5, the first voltage transmission unit 61 is turned off. For example, in the second initialization phase T5, the second voltage transmission unit 62 is turned off. For example, in the second initialization phase T5, the compensation module 20 and the third voltage transmission module 90 are turned off. For example, in the second initialization phase T5, the first voltage transmission module 20 is turned off. For example, in the second initialization phase T5, the first light-emitting control module 80 is turned off.

[0095] See Figure 2 The control terminal of the compensation module 30 (which can be the gate of the second transistor M2) is connected to the first gate signal EMB1. The control terminal of the second voltage transmission unit 62 (which can be the gate of the third transistor M3) is connected to the first gate signal EMB1. The control terminal of the first voltage transmission module 20 (which can be the gate of the eighth transistor M8) is connected to the second gate signal EMB2. The control terminal of the first initialization module 70 (which can be the gate of the ninth transistor M9) is connected to the third gate signal EM. The control terminal of the first light emission control module 80 (which can be the gate of the sixth transistor M6) is connected to the third gate signal EM. The control terminal of the fifth voltage transmission unit 92 (which can be the gate of the fifth transistor M5) is connected to the third gate signal EM. The control terminal of the first voltage transmission unit 61 (which can be the gate of the fourth transistor M4) is connected to the fourth gate signal S2. The control terminal of the fourth voltage transmission unit 91 (which can be the gate of the seventh transistor M7) is connected to the fifth gate signal S1.

[0096] See Figure 2The first terminal of the eighth transistor M8 is connected to the first reference voltage V1 or to the first voltage line. The second terminal of the eighth transistor M8 is connected to the first terminal of the driving transistor M1. The second transistor M2 is connected between the second terminal and the gate of the driving transistor M1. The first terminal of the first capacitor Cst1 is connected to the gate of the driving transistor M1. The second terminal of the first capacitor Cst1 is connected to the first terminal of the second capacitor Cst2. The second terminal of the second capacitor Cst2 is connected to the second terminal of the ninth transistor M9. The first terminal of the ninth transistor M9 is connected to the first initialization voltage Vref or to the first initialization signal line. The second terminal of the ninth transistor M9 is connected to the first terminal of the light-emitting element 100. The sixth transistor M6 is connected to the first terminal of the driving transistor M1 and the light-emitting element 100. The first terminal of the third transistor M3 is connected to the first reference voltage V1 or the first voltage line, and the second terminal of the third transistor M3 is connected to the first terminal of the second capacitor Cst2 (or the second terminal of the first capacitor Cst1). The first terminal of the third transistor M3 is connected to the first reference voltage V1 or the first voltage line, and the second terminal of the third transistor M3 is connected to the first terminal of the second capacitor Cst2 (or the second terminal of the first capacitor Cst1). The first terminal of the fifth transistor M5 is connected to the first power supply voltage VDD or the first power line, and the second terminal of the fifth transistor M5 is connected to the second terminal of the driving transistor M1. The first terminal of the seventh transistor M7 is connected to the first power supply voltage VDD or the first power line, and the second terminal of the seventh transistor M7 is connected to the second terminal of the driving transistor M1.

[0097] See Figure 2 The driving transistors M1, M2, M3, M4, M8, and M9 are all N-type transistors. The fifth transistor M5, M6, and M7 are all P-type transistors.

[0098] See Figures 2 to 4 The working process of the pixel circuit is described below. For example, the light emission stage may include a first light emission stage T4 for writing frames and a second light emission stage T6 for holding frames. The write frame may include a first initialization stage T1, a threshold compensation stage T2, a data writing stage T3, and a first light emission stage T4. The holding frame may include a second initialization stage T5 and a second light emission stage T6.

[0099] During at least a portion of the first initialization phase T1, the first gate signal EMB1 may be at an on level, for example, a high level; the second gate signal EMB2 may be at an off level, for example, a low level; the third gate signal EM may be at a high level; the fourth gate signal S2 may be at an off level, for example, a low level; and the fifth gate signal S1 may be at an on level, for example, a low level. The first initialization module 70 (which may be the ninth transistor M9) is turned on, transmitting the first initialization voltage Vref to the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2) to initialize the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2). The second voltage transmission unit 62 (which may be the third transistor M3) is turned on, transmitting the second reference voltage V2 to the second terminal of the first storage module 40 (which may be the second terminal of the first capacitor Cst1), the first terminal of the second storage module 50 (which may be the first terminal of the second capacitor Cst2), and the first node N1 to initialize the second terminal of the first storage module 40, the first terminal of the second storage module 50, and the first node. The compensation module 30 (which may be the second transistor M2) and the fourth voltage transmission unit 91 (which may be the seventh transistor M7) are turned on, transmitting the first power supply voltage VDD or VDD1 through the turned-on fourth voltage transmission unit 91 (which may be the seventh transistor M7) and compensation module 30 (which may be the second transistor M2) to the control terminal G (the gate of the driving transistor M1) of the driving module 10 to initialize the control terminal G (the gate of the driving transistor M1) of the driving module 10. The first voltage transmission module 20 (which may be the eighth transistor M8), the first voltage transmission unit 61 (which may be the fourth transistor M4), the fifth voltage transmission unit 92 (which may be the fifth transistor M5), and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned off.

[0100] During at least a portion of the threshold compensation phase T2, the first gate signal EMB1 may be at an on level, for example, a high level; the second gate signal EMB2 may be at an on level, for example, a high level; the third gate signal EM may be at a high level; the fourth gate signal S2 may be at an off level, for example, a low level; and the fifth gate signal S1 may be at an off level, for example, a high level. The first voltage transmission module 20 (which may be the eighth transistor M8) and the compensation module 30 (which may be the second transistor M2) are turned on. The control terminal G of the driving module 10 (which may be the gate of the driving transistor M1) discharges to the power supply corresponding to the first reference voltage V1 through the turned-on first voltage transmission module 20 (which may be the eighth transistor M8), the driving module 10 (which may be the driving transistor M1), and the compensation module 30 (which may be the second transistor M2), i.e., threshold compensation is performed until the potential of the control terminal G and the second terminal D (which may be the gate and the second terminal of the driving transistor M1) of the driving module 10 is V1 + Vth. The first initialization module 70 (which may be the ninth transistor M9) is turned on, transmitting the first initialization voltage Vref to the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2). The second voltage transmission unit 62 (which may be the third transistor M3) is turned on, transmitting the second reference voltage V2 to the second terminal of the first storage module 40 (which may be the second terminal of the first capacitor Cst1), the first terminal of the second storage module 50 (which may be the first terminal of the second capacitor Cst2), and the first node N1. The first voltage transmission unit 61 (which may be the fourth transistor M4), the fourth voltage transmission unit 91 (which may be the seventh transistor M7), the fifth voltage transmission unit 92 (which may be the fifth transistor M5), and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned off. The voltage at the first terminal S of the driving module 10 (which may be the first terminal of the driving transistor M1) is the first reference voltage V1.

[0101] During at least a portion of the data writing phase T3, the first gate signal EMB1 may be at an off level, such as a low level; the second gate signal EMB2 may be at an on level, such as a high level; the third gate signal EM may be at a high level; the fourth gate signal S2 may be at an on level, such as a high level; and the fifth gate signal S1 may be at an off level, such as a high level. The first voltage transmission unit 61 (which may be the fourth transistor M4) is turned on, transmitting the data voltage Vdata on the data line Data to the second terminal of the first storage module 40 (which may be the second terminal of the first capacitor Cst1), the first terminal of the second storage module 50 (which may be the first terminal of the second capacitor Cst2), and the first node N1. The first initialization module 70 (which may be the ninth transistor M9) is turned on, transmitting the first initialization voltage Vref to the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2). The first voltage transmission module 20 (which may be the eighth transistor M8) is turned on, transmitting the first reference voltage V1 to the first terminal S of the driving module 10 (which may be the first terminal of the driving transistor M1). The compensation module 30 (which may be the second transistor M2), the second voltage transmission unit 62 (which may be the third transistor M3), the fourth voltage transmission unit 91 (which may be the seventh transistor M7), the fifth voltage transmission unit 92 (which may be the fifth transistor M5), and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned off.

[0102] During at least a portion of the first light-emitting stage T4, the first gate signal EMB1 may be at a turn-off level, for example, a low level VGL; the second gate signal EMB2 may be at a turn-off level, for example, a low level VGL; the third gate signal EM may be at a low level; the fourth gate signal S2 may be at a turn-off level, for example, a low level VGL; and the fifth gate signal S1 may be at a turn-off level, for example, a high level VGH. The fifth voltage transmission unit 92 (which may be the fifth transistor M5) and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned on, and the driving current generated by the driving module 10 (which may be the driving transistor M1) can drive the light-emitting element 100 to emit light. The first initialization module 70 (which may be the ninth transistor M9), the second voltage transmission unit 62 (which may be the third transistor M3), the compensation module 30 (which may be the second transistor M2), the fourth voltage transmission unit 91 (which may be the seventh transistor M7), the first voltage transmission module 20 (which may be the eighth transistor M8), and the first voltage transmission unit 61 (which may be the fourth transistor M4) are turned off.

[0103] During at least a portion of the second initialization phase T5, the first gate signal EMB1 may be at a shutdown level, for example, a low level; the second gate signal EMB2 may be at a shutdown level, for example, a low level; the third gate signal EM may be at a high level; the fourth gate signal S2 may be at a shutdown level, for example, a low level; and the fifth gate signal S1 may be at a shutdown level, for example, a high level. The first initialization module 70 (which may be the ninth transistor M9) is turned on, transmitting the first initialization voltage Vref to the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2) to initialize the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2). The second voltage transmission unit 62 (which may be the third transistor M3), the compensation module 30 (which may be the second transistor M2), the fourth voltage transmission unit 91 (which may be the seventh transistor M7), the first voltage transmission module 20 (which may be the eighth transistor M8), the first voltage transmission unit 61 (which may be the fourth transistor M4), the fifth voltage transmission unit 92 (which may be the fifth transistor M5), and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned off.

[0104] During at least a portion of the second light-emitting stage T6, the first gate signal EMB1 may be at a turn-off level, for example, a low level; the second gate signal EMB2 may be at a turn-off level, for example, a low level; the third gate signal EM may be at a low level; the fourth gate signal S2 may be at a turn-off level, for example, a low level; and the fifth gate signal S1 may be at a turn-off level, for example, a high level. The fifth voltage transmission unit 92 (which may be the fifth transistor M5) and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned on, and the driving current generated by the driving module 10 (which may be the driving transistor M1) can drive the light-emitting element 100 to emit light. The first initialization module 70 (which may be the ninth transistor M9), the second voltage transmission unit 62 (which may be the third transistor M3), the compensation module 30 (which may be the second transistor M2), the fourth voltage transmission unit 91 (which may be the seventh transistor M7), the first voltage transmission module 20 (which may be the eighth transistor M8), and the first voltage transmission unit 61 (which may be the fourth transistor M4) are turned off.

[0105] Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 6 The timing waveform diagram of another write frame provided in the embodiment of this application. Figure 7 This is a timing waveform diagram of another hold frame provided in an embodiment of this application. Figure 6 and Figure 7 Applicable to Figure 5 The pixel circuit shown. Alternatively, see... Figures 5-7The pulse width W2 of the turn-off pulse of the gate signal EM1 connected to the control terminal of the third voltage transmission module 90 and the turn-off pulse of the gate signal EM2 connected to the control terminal of the first light emission control module 80 (or the turn-on pulse of the gate signal EM2 connected to the control terminal of the first initialization module 70) is the same. This configuration allows the control terminals of the third voltage transmission module 90 and the first light emission control module 80 (or the first initialization module 70) to share the same gate driving circuit, such as a second gate driving circuit, thereby reducing the bezel width. The second gate driving circuit can be located in the non-display area of ​​the display panel.

[0106] In the same write frame or the same hold frame, the turn-off pulse of the gate signal (e.g., the sixth gate signal EM1) connected to the control terminal of the third voltage transmission module 90 (which may be the gate of the fifth transistor M5) lags behind the turn-off pulse of the gate signal EM2 connected to the control terminal of the first light emission control module 80 (or the turn-on pulse of the gate signal EM2 connected to the control terminal of the first initialization module 70). That is, in the same pixel circuit, the shift register connected to the control terminal of the third voltage transmission module 90 is the subsequent stage of the shift register connected to the control terminal of the first light emission control module 80 (or the control terminal of the first initialization module 70).

[0107] See Figures 5-7 The third voltage transmission module 90 may include only one voltage transmission unit, such as a fifth voltage transmission unit 92, but not a fourth voltage transmission unit 91. The first power supply voltage VDD can be transmitted through one voltage transmission unit during the first initialization stage T1 and the light emission stage T4 / T6, thereby reducing the number of transistors in the pixel circuit and improving pixel resolution.

[0108] Optionally, see Figures 5-7 During the first initialization phase T1 and the light emission phases T4 / T6, the first power supply voltage VDD is transmitted to the second terminal D of the driving module 10 through the same transistor (e.g., the fifth transistor M5) in the third voltage transmission module 90.

[0109] Figures 5-7 Technical solutions and Figures 2-4 The technical solutions are similar in principle, the difference being the structure of the third voltage transmission module 90 and the gate signal it receives. See also... Figures 5-7 The working process of the pixel circuit will be introduced.

[0110] During at least a portion of the first initialization phase T1, the first gate signal EMB1 may be at an on level, for example, a high level; the second gate signal EMB2 may be at an off level, for example, a low level; the third gate signal EM (which may be EM2) may be at a high level; the fourth gate signal S2 may be at an off level, for example, a low level; and the sixth gate signal EM1 may be at an on level, for example, a low level. The first initialization module 70 (which may be the ninth transistor M9) is turned on, transmitting the first initialization voltage Vref to the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2) to initialize the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2). The second voltage transmission unit 62 (which may be the third transistor M3) is turned on, transmitting the second reference voltage V2 to the second terminal of the first storage module 40 (which may be the second terminal of the first capacitor Cst1), the first terminal of the second storage module 50 (which may be the first terminal of the second capacitor Cst2), and the first node N1 to initialize the second terminal of the first storage module 40, the first terminal of the second storage module 50, and the first node. The compensation module 30 (which may be the second transistor M2) and the third voltage transmission module 90 (which may be the fifth voltage transmission unit 92 or the fifth transistor M5) are turned on, transmitting the first power supply voltage VDD or VDD1 through the turned-on fifth voltage transmission unit 92 (which may be the fifth transistor M5) and compensation module 30 (which may be the second transistor M2) to the control terminal G (the gate of the driving transistor M1) of the driving module 10 to initialize the control terminal G (the gate of the driving transistor M1) of the driving module 10. The first voltage transmission module 20 (which may be the eighth transistor M8), the first voltage transmission unit 61 (which may be the fourth transistor M4), and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned off.

[0111] During at least a portion of the threshold compensation phase T2, the first gate signal EMB1 may be at an on level, for example, a high level; the second gate signal EMB2 may be at an on level, for example, a high level; the third gate signal EM (which may be EM2) may be at a high level; the fourth gate signal S2 may be at an off level, for example, a low level; and the sixth gate signal EM1 may be at an off level, for example, a high level. The first voltage transmission module 20 (which may be the eighth transistor M8) and the compensation module 30 (which may be the second transistor M2) are turned on. The control terminal G of the driving module 10 (which may be the gate of the driving transistor M1) discharges to the power supply corresponding to the first reference voltage V1 through the turned-on first voltage transmission module 20 (which may be the eighth transistor M8), the driving module 10 (which may be the driving transistor M1), and the compensation module 30 (which may be the second transistor M2), i.e., threshold compensation is performed until the potential of the control terminal G and the second terminal D (which may be the gate and the second terminal of the driving transistor M1) of the driving module 10 is V1+Vth. The first initialization module 70 (which may be the ninth transistor M9) is turned on, transmitting the first initialization voltage Vref to the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2). The second voltage transmission unit 62 (which may be the third transistor M3) is turned on, transmitting the second reference voltage V2 to the second terminal of the first storage module 40 (which may be the second terminal of the first capacitor Cst1), the first terminal of the second storage module 50 (which may be the first terminal of the second capacitor Cst2), and the first node N1. The first voltage transmission unit 61 (which may be the fourth transistor M4), the third voltage transmission module 90 (which may be the fifth voltage transmission unit 92, which may be the fifth transistor M5), and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned off. The voltage at the first terminal S of the driving module 10 (which may be the first terminal of the driving transistor M1) is the first reference voltage V1.

[0112] During at least a portion of the data writing phase T3, the first gate signal EMB1 may be at an off level, such as a low level; the second gate signal EMB2 may be at an on level, such as a high level; the third gate signal EM (which may be EM2) may be at a high level; the fourth gate signal S2 may be at an on level, such as a high level; and the sixth gate signal EM1 may be at an off level, such as a high level. The first voltage transmission unit 61 (which may be the fourth transistor M4) is turned on, transmitting the data voltage Vdata on the data line Data to the second terminal of the first storage module 40 (which may be the second terminal of the first capacitor Cst1), the first terminal of the second storage module 50 (which may be the first terminal of the second capacitor Cst2), and the first node N1. The first initialization module 70 (which may be the ninth transistor M9) is turned on, transmitting the first initialization voltage Vref to the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2). The first voltage transmission module 20 (which may be the eighth transistor M8) is turned on, transmitting the first reference voltage V1 to the first terminal S of the driving module 10 (which may be the first electrode of the driving transistor M1). The compensation module 30 (which may be the second transistor M2), the second voltage transmission unit 62 (which may be the third transistor M3), the third voltage transmission module 90 (which may be the fifth voltage transmission unit 92, which may be the fifth transistor M5), and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned off.

[0113] During at least a portion of the first light-emitting stage T4, the first gate signal EMB1 may be at an off level, for example, a low level; the second gate signal EMB2 may be at an off level, for example, a low level; the third gate signal EM (which may be EM2) may be at a low level; the fourth gate signal S2 may be at an off level, for example, a low level; and the sixth gate signal EM1 may be at an on level, for example, a low level. The third voltage transmission module 90 (which may be the fifth voltage transmission unit 92, which may be the fifth transistor M5) and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned on, and the driving current generated by the driving module 10 (which may be the driving transistor M1) can drive the light-emitting element 100 to emit light. The first initialization module 70 (which may be the ninth transistor M9), the second voltage transmission unit 62 (which may be the third transistor M3), the compensation module 30 (which may be the second transistor M2), the first voltage transmission module 20 (which may be the eighth transistor M8), and the first voltage transmission unit 61 (which may be the fourth transistor M4) are turned off.

[0114] During at least a portion of the second initialization phase T5, the first gate signal EMB1 may be at a shutdown level, for example, a low level; the second gate signal EMB2 may be at a shutdown level, for example, a low level; the third gate signal EM (which may be EM2) may be at a high level; the fourth gate signal S2 may be at a shutdown level, for example, a low level; and the sixth gate signal EM1 may be at a shutdown level, for example, a high level. The first initialization module 70 (which may be the ninth transistor M9) is turned on, transmitting the first initialization voltage Vref to the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2) to initialize the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2). The second voltage transmission unit 62 (which may be the third transistor M3), the compensation module 30 (which may be the second transistor M2), the fourth voltage transmission unit 91 (which may be the seventh transistor M7), the first voltage transmission module 20 (which may be the eighth transistor M8), the first voltage transmission unit 61 (which may be the fourth transistor M4), the third voltage transmission module 90 (which may be the fifth voltage transmission unit 92, which may be the fifth transistor M5), and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned off.

[0115] During at least a portion of the second light-emitting stage T6, the first gate signal EMB1 may be at an off level, for example, a low level; the second gate signal EMB2 may be at an off level, for example, a low level; the third gate signal EM (which may be EM2) may be at a low level; the fourth gate signal S2 may be at an off level, for example, a low level; and the sixth gate signal EM1 may be at an on level, for example, a low level. The third voltage transmission module 90 (which may be the fifth voltage transmission unit 92, which may be the fifth transistor M5) and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned on, and the driving current generated by the driving module 10 (which may be the driving transistor M1) can drive the light-emitting element 100 to emit light. The first initialization module 70 (which may be the ninth transistor M9), the second voltage transmission unit 62 (which may be the third transistor M3), the compensation module 30 (which may be the second transistor M2), the fourth voltage transmission unit 91 (which may be the seventh transistor M7), the first voltage transmission module 20 (which may be the eighth transistor M8), and the first voltage transmission unit 61 (which may be the fourth transistor M4) are turned off.

[0116] Figure 8 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Optionally, based on the above embodiments, see [link to related documentation]. Figure 8The second voltage transmission module 60 also includes a third voltage transmission unit 63. The first end of the first voltage transmission unit 61 and the first end of the second voltage transmission unit 62 are electrically connected to the first end of the third voltage transmission unit 63. The second end of the first storage module 40 and the first end of the second storage module 50 are electrically connected to the second end of the third voltage transmission unit 63. The third voltage transmission unit 63 is used to be turned on during the threshold compensation stage T2 and the data writing stage T3.

[0117] Specifically, during the threshold compensation phase T2, the second voltage transmission unit 62 and the third voltage transmission unit 63 are turned on, transmitting the second reference voltage V2 to the second terminal of the first storage module 40 via the turned-on second voltage transmission unit 62 and the third voltage transmission unit 63. During the data writing phase T3, the first voltage transmission unit 61 and the third voltage transmission unit 63 are turned on, transmitting the data voltage Vdata to the first terminal (and / or the second terminal of the first storage module 40) via the turned-on first voltage transmission unit 61 and the third voltage transmission unit 63.

[0118] For example, the third voltage transmission unit 63 includes a tenth transistor M10. The third voltage transmission unit 63 may include only one transistor. Compared to directly connecting the first voltage transmission unit 61 and the second voltage transmission unit 62 (i.e., two transistors) to the first node N (or the second terminal of the first storage module 40), by setting the third voltage transmission unit 63, the parasitic capacitance between the data voltage Vdata on the data line Data and the control terminal G of the drive module 10 and / or the first node N1 can be reduced, thereby reducing signal crosstalk. The tenth transistor M10 may include a P-type transistor or an N-type transistor.

[0119] For example, the third voltage transmission unit 63 is used to be turned on during the first initialization phase T1. During the first initialization phase T1, the second voltage transmission unit 62 and the third voltage transmission unit 63 are turned on, and the second reference voltage V2 is transmitted to the second terminal (and / or the second terminal of the first storage module 40) of the first storage module 40 through the turned-on second voltage transmission unit 62 and the third voltage transmission unit 63.

[0120] For example, during the second initialization phase T5, the third voltage transmission unit 63 is turned on. For example, during the light-emitting phases T4 / T6, the third voltage transmission unit 63 is turned off. When the third voltage transmission unit 63 is on, the tenth transistor M10 can be turned on. When the third voltage transmission unit 63 is off, the tenth transistor M10 can be turned off.

[0121] Figure 9 The timing waveform diagram of another write frame provided in the embodiment of this application. Figure 10 This is a timing waveform diagram of another hold frame provided in an embodiment of this application. Figure 9 and Figure 10Applicable to Figure 8 The pixel circuit shown.

[0122] Figures 8-10 Technical solutions and Figures 5-7 The technical solutions work on similar principles, the difference being... Figures 8-10 The technical solution adds a third voltage transmission unit 63. Figures 8-10 The working process of the pixel circuit corresponding to the technical solution can be found in the following reference. Figures 5-7 The working process of the pixel circuit corresponding to the technical solution will not be described in detail here.

[0123] also, Figures 8-10 The fourth transistor M4 in the technical solution and Figures 5-7 The fourth transistor M4 in the technical solution has a different channel type, and is also about to... Figures 5-7 In the technical solution, swapping the high and low levels of the gate signal S2 of the fourth transistor M4 can provide... Figures 8-10 The gate signal S2 of the fourth transistor M4 in the technical solution.

[0124] Optionally, see Figure 8 The control terminals of the third voltage transmission unit 63 and the first light-emitting control module 80 are connected to the same gate signal and / or the same gate line (which can be used to transmit the third gate signal EM / EM2) to reduce the number of signal lines and simplify wiring. For example, the switching states of the third voltage transmission unit 63 and the first light-emitting control module 80 can be opposite; for example, when the third voltage transmission unit 63 is on, the first light-emitting control module 80 is off; when the first light-emitting control module 80 is on, the third voltage transmission unit 63 is off.

[0125] For example, see Figure 8 The transistors in the third voltage transmission unit 63 and the transistors in the first light-emitting control module 80 have different channel types. For example, see... Figure 8 The third voltage transmission unit 63 or the tenth transistor M10 includes an N-type transistor, and the first light-emitting control module 80 or the sixth transistor M6 includes a P-type transistor. Alternatively, the third voltage transmission unit 63 or the tenth transistor M10 includes a P-type transistor, and the first light-emitting control module 80 or the sixth transistor M6 includes an N-type transistor.

[0126] Optionally, see Figure 8 The control terminals of the third voltage transmission unit 63 and the first initialization module 70 are connected to the same gate signal and / or the same gate line (which can be used to transmit the third gate signal EM / EM2) to reduce the number of signal lines and simplify wiring. For example, the switching states of the third voltage transmission unit 63 and the first initialization module 70 can be the same, that is, they can be turned on and off at the same time.

[0127] For example, see Figure 8 The transistors in the third voltage transmission unit 63 and the transistors in the first initialization module 70 have the same channel type. For example, the third voltage transmission unit or the tenth transistor M10 includes a P-type transistor, and the first initialization module 70 or the ninth transistor M9 includes a P-type transistor. Alternatively, see... Figure 8 The third voltage transmission unit or the tenth transistor M10 includes an N-type transistor, and the first initialization module 70 or the ninth transistor M9 includes an N-type transistor.

[0128] Figure 11 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Optionally, based on the above embodiments, see [link to related documentation]. Figure 11 The control terminals of the first initialization module 70 and the first voltage transmission module 20 are connected to the same gate signal and / or the same gate line (which can transmit the seventh gate signal S3) to reduce the number of signal lines and simplify wiring. For example, the switching states of the first initialization module 70 and the first voltage transmission module 20 can be the same, that is, they are simultaneously turned on and simultaneously turned off.

[0129] For example, see Figure 11 The transistors in the first initialization module 70 and the transistors in the first voltage transmission module 20 have the same channel type. For example, see... Figure 11 The first voltage transmission module 20 or the eighth transistor M8 includes a P-type transistor, and the first initialization module 70 or the ninth transistor M9 includes a P-type transistor. The eighth transistor M8 and the ninth transistor M9 share a gate line and are both polysilicon transistors, which is beneficial for improving pixel resolution (PPI). Alternatively, the first voltage transmission module 20 or the eighth transistor M8 includes an N-type transistor, and the first initialization module 70 or the ninth transistor M9 includes an N-type transistor.

[0130] For example, see Figures 11-13 In the first initialization phase T1, the first initialization module 70 is turned off. In the second initialization phase T5, the first initialization module 70 is turned on.

[0131] For example, see Figures 11-13 During the holding frame, in the second initialization phase T5, the first voltage transmission module 20 is turned on to transmit the first reference voltage V1 to the first terminal of the drive module (which may be the first pole of the drive transistor M1) to initialize the first terminal of the drive module (which may be the first pole of the drive transistor M1).

[0132] Figure 12 The timing waveform diagram of another write frame provided in the embodiment of this application. Figure 13 This is a timing waveform diagram of another hold frame provided in an embodiment of this application. Figure 12 and Figure 13 Applicable to Figure 11 The pixel circuit shown.

[0133] Figures 11-13 Technical solutions and Figures 5-7 The technical solutions work on similar principles, the difference being... Figures 11-13 In the technical solution, the first initialization module 70 and the first voltage transmission module 20 are connected to the same gate signal. (See also...) Figures 11-13 The working process of the pixel circuit will be introduced.

[0134] During at least a portion of the first initialization phase T1, the first gate signal EMB1 may be at an on level, for example, a high level; the seventh gate signal S3 may be at an off level, for example, a high level; the third gate signal EM (which may be EM2) may be at an off level, for example, a high level; the fourth gate signal S2 may be at an off level, for example, a low level; and the sixth gate signal EM1 may be at an on level, for example, a low level. The second voltage transmission unit 62 (which may be the third transistor M3) is turned on, transmitting the second reference voltage V2 to the second terminal of the first storage module 40 (which may be the second terminal of the first capacitor Cst1), the first terminal of the second storage module 50 (which may be the first terminal of the second capacitor Cst2), and the first node N1 to initialize the second terminal of the first storage module 40 (which may be the second terminal of the first capacitor Cst1), the first terminal of the second storage module 50 (which may be the first terminal of the second capacitor Cst2), and the first node. The compensation module 30 (which may be the second transistor M2) and the third voltage transmission module 90 (which may be the fifth voltage transmission unit 92, or the fifth transistor M5) are turned on, transmitting the first power supply voltage VDD or VDD1 through the turned-on fifth voltage transmission unit 92 (which may be the fifth transistor M5) and compensation module 30 (which may be the second transistor M2) to the control terminal G (gate of the driving transistor M1) of the driving module 10, thereby initializing the control terminal G (gate of the driving transistor M1) of the driving module 10. The first voltage transmission module 20 (which may be the eighth transistor M8), the first voltage transmission unit 61 (which may be the fourth transistor M4), and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned off. The first initialization module 70 (which may be the ninth transistor M9) is turned off.

[0135] During at least a portion of the threshold compensation phase T2, the first gate signal EMB1 may be at an on level, for example, a high level; the seventh gate signal S3 may be at an on level, for example, a low level; the third gate signal EM (which may be EM2) may be at an off level, for example, a high level; the fourth gate signal S2 may be at an off level, for example, a low level; and the sixth gate signal EM1 may be at an off level, for example, a high level. The first voltage transmission module 20 (which may be the eighth transistor M8) and the compensation module 30 (which may be the second transistor M2) are turned on. The control terminal G of the driving module 10 (which may be the gate of the driving transistor M1) discharges to the power supply corresponding to the first reference voltage V1 through the turned-on first voltage transmission module 20 (which may be the eighth transistor M8), the driving module 10 (which may be the driving transistor M1), and the compensation module 30 (which may be the second transistor M2), i.e., threshold compensation is performed until the potential of the control terminal G and the second terminal D (which may be the gate and the second terminal of the driving transistor M1) of the driving module 10 is V1+Vth. The first initialization module 70 (which may be the ninth transistor M9) is turned on, transmitting the first initialization voltage Vref to the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2). The second voltage transmission unit 62 (which may be the third transistor M3) is turned on, transmitting the second reference voltage V2 to the second terminal of the first storage module 40 (which may be the second terminal of the first capacitor Cst1), the first terminal of the second storage module 50 (which may be the first terminal of the second capacitor Cst2), and the first node N1. The first voltage transmission unit 61 (which may be the fourth transistor M4), the third voltage transmission module 90 (which may be the fifth voltage transmission unit 92, which may be the fifth transistor M5), and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned off. The voltage at the first terminal S of the driving module 10 (which may be the first terminal of the driving transistor M1) is the first reference voltage V1.

[0136] During at least a portion of the data writing phase T3, the first gate signal EMB1 may be at an off level, for example, a low level; the seventh gate signal S3 may be at an on level, for example, a low level; the third gate signal EM (which may be EM2) may be at an off level, for example, a high level; the fourth gate signal S2 may be at an on level, for example, a high level; and the sixth gate signal EM1 may be at an off level, for example, a high level. The first voltage transmission unit 61 (which may be the fourth transistor M4) is turned on, transmitting the data voltage Vdata on the data line Data to the second terminal of the first storage module 40 (which may be the second terminal of the first capacitor Cst1), the first terminal of the second storage module 50 (which may be the first terminal of the second capacitor Cst2), and the first node N1. The first initialization module 70 (which may be the ninth transistor M9) is turned on, transmitting the first initialization voltage Vref to the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2). The first voltage transmission module 20 (which may be the eighth transistor M8) is turned on, transmitting the first reference voltage V1 to the first terminal S of the driving module 10 (which may be the first electrode of the driving transistor M1). The compensation module 30 (which may be the second transistor M2), the second voltage transmission unit 62 (which may be the third transistor M3), the third voltage transmission module 90 (which may be the fifth voltage transmission unit 92, which may be the fifth transistor M5), and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned off.

[0137] During at least a portion of the first light-emitting stage T4, the first gate signal EMB1 may be at an off level, for example, a low level; the seventh gate signal S3 may be at an off level, for example, a high level; the third gate signal EM (which may be EM2) may be at an on level, for example, a low level; the fourth gate signal S2 may be at an off level, for example, a low level; and the sixth gate signal EM1 may be at an on level, for example, a low level. The third voltage transmission module 90 (which may be the fifth voltage transmission unit 92, which may be the fifth transistor M5) and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned on, and the driving current generated by the driving module 10 (which may be the driving transistor M1) can drive the light-emitting element 100 to emit light. The first initialization module 70 (which may be the ninth transistor M9), the second voltage transmission unit 62 (which may be the third transistor M3), the compensation module 30 (which may be the second transistor M2), the first voltage transmission module 20 (which may be the eighth transistor M8), and the first voltage transmission unit 61 (which may be the fourth transistor M4) are turned off.

[0138] During at least a portion of the second initialization phase T5, the first gate signal EMB1 may be at an off level, for example, a low level; the seventh gate signal S3 may be at an on level, for example, a low level; the third gate signal EM (which may be EM2) may be at an off level, for example, a high level; the fourth gate signal S2 may be at an off level, for example, a low level; and the sixth gate signal EM1 may be at an off level, for example, a high level. The first initialization module 70 (which may be the ninth transistor M9) is turned on, transmitting the first initialization voltage Vref to the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2) to initialize the first terminal of the light-emitting element 100 and the second terminal of the second storage module 50 (which may be the second terminal of the second capacitor Cst2). The first voltage transmission module 20 (which may be the eighth transistor M8) is turned on, transmitting the first reference voltage V1 to the first terminal of the driving module (which may be the first terminal of the driving transistor M1) to initialize the first terminal of the driving module (which may be the first terminal of the driving transistor M1). The second voltage transmission unit 62 (which may be the third transistor M3), the compensation module 30 (which may be the second transistor M2), the fourth voltage transmission unit 91 (which may be the seventh transistor M7), the first voltage transmission unit 61 (which may be the fourth transistor M4), the third voltage transmission module 90 (which may be the fifth voltage transmission unit 92, which may be the fifth transistor M5), and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned off.

[0139] During at least a portion of the second light-emitting stage T6, the first gate signal EMB1 may be at an off level, for example, a low level; the seventh gate signal S3 may be at an off level, for example, a high level; the third gate signal EM (which may be EM2) may be at an on level, for example, a low level; the fourth gate signal S2 may be at an off level, for example, a low level; and the sixth gate signal EM1 may be at an on level, for example, a low level. The third voltage transmission module 90 (which may be the fifth voltage transmission unit 92, which may be the fifth transistor M5) and the first light-emitting control module 80 (which may be the sixth transistor M6) are turned on, and the driving current generated by the driving module 10 (which may be the driving transistor M1) can drive the light-emitting element 100 to emit light. The first initialization module 70 (which may be the ninth transistor M9), the second voltage transmission unit 62 (which may be the third transistor M3), the compensation module 30 (which may be the second transistor M2), the fourth voltage transmission unit 91 (which may be the seventh transistor M7), the first voltage transmission module 20 (which may be the eighth transistor M8), and the first voltage transmission unit 61 (which may be the fourth transistor M4) are turned off.

[0140] Figure 14 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Optionally, based on the above embodiments, see [link to related documentation]. Figure 14The control terminals of the first initialization module 70 and the first voltage transmission unit 61 are connected to the same gate signal and / or the same gate line (which can transmit the fourth gate signal S2) to reduce the number of signal lines and simplify wiring. For example, the switching states of the first initialization module 70 and the first voltage transmission unit 61 can be the same, that is, they can be turned on and off at the same time.

[0141] For example, see Figure 11 The transistors in the first initialization module 70 and the transistors in the first voltage transmission unit 61 have the same channel type. For example, see... Figure 11 The first voltage transmission unit 61 or the fourth transistor M4 includes a P-type transistor, and the first initialization module 70 or the ninth transistor M9 includes a P-type transistor. Alternatively, the first voltage transmission unit 61 or the fourth transistor M4 includes an N-type transistor, and the first initialization module 70 or the ninth transistor M9 includes an N-type transistor.

[0142] Figure 15 This is a timing waveform diagram of another hold frame provided in an embodiment of this application. Figure 9 and Figure 15 Applicable to Figure 14 The pixel circuit shown.

[0143] Figure 9 , Figures 14-15 Technical solutions and Figures 8-10 The technical solutions work on similar principles, the difference being... Figure 9 , Figures 14-15 The first initialization module 70 and the first voltage transmission unit 61 of the technical solution are connected to the same gate signal. Figure 9 , Figures 14-15 The working process of the pixel circuit corresponding to the technical solution can be found in the following reference. Figures 8-10 The working process of the pixel circuit corresponding to the technical solution is not described here. See [link to technical solution]. Figure 9 , Figures 14-15The first initialization module 70 is turned off in the first initialization phase T1 and turned on in the second initialization phase T5. In the second initialization phase T5, the first voltage transmission unit 61 and the third voltage transmission unit 63 are turned on, disconnecting the driver chip from the data line. Alternatively, the driver chip may not transmit voltage to the data line, and the output terminal of the driver chip connected to the data line may be in a high-impedance state or a floating state to reduce power consumption without affecting the potential of the second terminal (or the first terminal or the first node N1) of the first storage module 40. Alternatively, in the second initialization phase T5, the first voltage transmission unit 61 and the third voltage transmission unit 63 are turned on, transmitting the data voltage to the second terminal (or the first terminal or the first node N1) of the first storage module 40. This improves the stability of the potential of the first node N1 of the holding frame, enhances the display effect, and reduces power consumption since there is no threshold compensation stage for the holding frame. Figure 14 Alternatively, the third voltage transmission unit 63 may not be provided.

[0144] The pixel circuit may include some or all of the following components: driving module 10, first voltage transmission module 20, compensation module 30, first storage module 40, second storage module 50, second voltage transmission module 60, third voltage transmission module 90, first light emission control module 80, and first initialization module 70, which can be configured as needed.

[0145] This application provides a display panel. Figure 16 This is a schematic diagram of a display panel provided in an embodiment of this application. The display panel 300 may include the pixel circuit 200 provided in any of the above embodiments, which has the beneficial effects of the pixel circuit in any of the embodiments of this application, and will not be described again here.

[0146] Optionally, see Figure 16 The display panel includes a first gate driving circuit 400, which includes multiple cascaded first shift registers 401. The control terminals of the compensation module 30 (or the second voltage transmission unit 62) and the first voltage transmission module 20 in the same pixel circuit are connected to the output terminals of different first shift registers 401. This configuration simplifies the circuit and reduces the bezel width. For example, the control terminal of the compensation module 30 (or the control terminal of the second voltage transmission unit 62) is connected to the output terminal of the first shift register 401 via a first gate line L1 (which can transmit the first gate signal EMB1), and the control terminal of the first voltage transmission module 20 is connected to the output terminal of the first shift register 401 via a second gate line L2 (which can transmit the second gate signal EMB2).

[0147] Figure 17 This is a schematic diagram of another display panel provided in an embodiment of this application. Optionally, see... Figure 17 When the pixel circuit also includes a third voltage transmission module 90, the display panel includes a second gate driving circuit 500. The second gate driving circuit 500 includes multiple cascaded second shift registers 501. The control terminals of the third voltage transmission module 90 and the first light emission control module 80 (or the first initialization module 70) in the same pixel circuit 200 are connected to the output terminals of different second shift registers 501. This configuration simplifies the circuit and reduces the bezel width. For example, the control terminal of the third voltage transmission module 90 is connected to the output terminal of the second shift register 501 via a third gate line L3 (which can transmit the sixth gate signal EM1), and the control terminal of the first light emission control module 80 (or the first initialization module 70) is connected to the output terminal of the second shift register 501 via a fourth gate line L4 (which can transmit the third gate signal EM2).

[0148] Optionally, the display panel 300 includes gate lines (e.g., L1, L2, L3, L4), and the pixel circuits 200 are electrically connected to the gate lines (e.g., gate lines L1, L2, L3, L4, etc.). The gate lines extend along a first direction X, and each row of pixel circuits 200 includes multiple pixel circuits 200 arranged along the first direction X. For example, the turn-on pulses of the gate signal EMB1 at the control terminal of the compensation module 30 of the multi-row pixel circuits 200 overlap; and / or, the threshold compensation stages T2 of the multi-row pixel circuits 200 overlap, thereby achieving multi-row compensation, which is beneficial for achieving high-frequency driving.

[0149] For example, multiple gate lines are arranged along a second direction Y. The first direction X intersects the second direction Y, for example, perpendicularly. For example, multiple data lines may extend along the second direction Y and be arranged along the first direction X.

[0150] This application provides a driving method for driving pixel circuits. Figure 18 This is a flowchart illustrating a driving method for a display panel according to an embodiment of this application. See also... Figure 18 The driving method for this pixel circuit includes: Step S110: In the threshold compensation stage, the first voltage transmission module is turned on to transmit the first reference voltage to the first terminal of the drive module, and the compensation module is turned on to transmit the voltage related to the first reference voltage and the threshold voltage of the drive module to the control terminal of the drive module. Step S120: During the data writing stage, the compensation module is turned off, and the second voltage transmission module transmits the data voltage to the second end of the first storage module.

[0151] The pixel circuit driving method of this application embodiment is used to drive the pixel circuit 200 of any embodiment of this application, and has the beneficial effects of the pixel circuit of any embodiment of this application, which will not be repeated here. This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0152] Figure 19 This is a schematic diagram of a display device provided in an embodiment of this application. This application also provides a display device 1, including the display panel provided in any embodiment of this application.

[0153] For example, the display device includes a photosensitive element and a display panel provided in any embodiment of this application. The photosensitive element is used to receive light transmitted through the light-transmitting area. The photosensitive element may include one or more of a camera, a fingerprint recognition module, an ambient light sensor, an infrared sensor, etc.

[0154] Display devices include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablets, e-readers, televisions, access control systems, smart landlines, consoles, laptops, wearable devices, in-vehicle displays, and other devices with display functions.

[0155] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0156] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A pixel circuit, characterized in that, include: The module comprises a drive module, a first voltage transmission module, a compensation module, a first storage module, a second storage module, and a second voltage transmission module. The first voltage transmission module is connected to the first reference voltage; The first voltage transmission module is electrically connected to the first terminal of the drive module; The compensation module is connected between the second end of the drive module and the control end of the drive module; The first end of the first storage module is electrically connected to the control end of the drive module; The second storage module is connected between the first end of the drive module and the second end of the first storage module; the first end of the second storage module and the second end of the first storage module are electrically connected to the first end of the second voltage transmission module. The second voltage transmission module receives the data voltage; The first voltage transmission module is used to turn on during the threshold compensation stage to transmit the first reference voltage to the first terminal of the drive module, and the compensation module is used to turn on during the threshold compensation stage. The second voltage transmission module is used to transmit the data voltage to the first end of the second storage module during the data writing phase.

2. The pixel circuit according to claim 1, characterized in that, The second voltage transmission module is connected to the second reference voltage, and the second voltage transmission module is used to transmit the second reference voltage to the second end of the first storage module during the threshold compensation stage. Preferably, the second voltage transmission module includes a first voltage transmission unit and a second voltage transmission unit. The first voltage transmission unit is electrically connected to the first end of the second storage module. The first voltage transmission unit receives the data voltage and is used to turn on during the data writing phase to transmit the data voltage to the first end of the second storage module. The second voltage transmission unit is electrically connected to the second terminal of the first storage module. The second voltage transmission unit is connected to the second reference voltage. The second voltage transmission unit is used to turn on during the threshold compensation stage to transmit the second reference voltage to the second terminal of the first storage module. Preferably, the first reference voltage and the second reference voltage are the same or different.

3. The pixel circuit according to claim 2, characterized in that, The control terminal of the second voltage transmission unit and the control terminal of the compensation module are connected to the same gate signal and / or the same gate line; Preferably, the transistors in the second voltage transmission unit and the transistors in the compensation module have the same channel type; Preferably, the compensation module includes an N-type transistor.

4. The pixel circuit according to claim 2 or 3, characterized in that, The second voltage transmission module further includes a third voltage transmission unit, wherein a first terminal of the first voltage transmission unit is electrically connected to a first terminal of the second voltage transmission unit, and a first terminal of the second storage module is electrically connected to a second terminal of the third voltage transmission unit; the third voltage transmission unit is used to be turned on during the threshold compensation stage and the data writing stage. Preferably, the pixel circuit further includes a first light-emitting control module, which is connected between the second end of the second storage module and the first end of the driving module. The control terminal of the third voltage transmission unit and the control terminal of the first light-emitting control module are connected to the same gate signal and / or connected to the same gate line. Preferably, the transistors in the third voltage transmission unit and the transistors in the first light-emitting control module have different channel types; Preferably, the third voltage transmission unit includes an N-type transistor, and the first light-emitting control module includes a P-type transistor.

5. The pixel circuit according to claim 4, characterized in that, The second voltage transmission module is used to transmit the second reference voltage to the second terminal of the first storage module and / or the first terminal of the second storage module during the first initialization phase. The second voltage transmission unit is used to turn on during the first initialization phase to transmit the second reference voltage to the second terminal of the first storage module and / or the first terminal of the second storage module; The third voltage transmission unit is used to be turned on during the first initialization phase; Preferably, the first voltage transmission unit includes an N-type transistor or a P-type transistor.

6. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a first initialization module, a first terminal of the first initialization module is electrically connected to the second terminal of the second storage module, and the first initialization module is connected to a first initialization voltage. The first initialization module is used to transmit the first initialization voltage to the second terminal of the second storage module during the data writing phase and / or the threshold compensation phase. Preferably, the first end of the first initialization module is electrically connected to the first end of the light-emitting element; Preferably, the first initialization module is used to turn on during the first initialization phase to transmit the first initialization voltage to the first end of the light-emitting element and / or the second end of the second storage module; Preferably, the pixel circuit further includes a first light-emitting control module, which is connected between the second end of the second storage module and the first end of the driving module. Preferably, the first light-emitting control module is turned off during the first initialization phase, the threshold compensation phase, and the data writing phase; the first light-emitting control module is turned on during the light-emitting phase.

7. The pixel circuit according to claim 6, characterized in that, The control terminal of the first initialization module and the control terminal of the first light-emitting control module are connected to the same gate signal and / or connected to the same gate line; the transistors in the first initialization module and the transistors in the first light-emitting control module have different channel types; Preferably, the first initialization module includes an N-type transistor or a P-type transistor.

8. The pixel circuit according to claim 6, characterized in that, The control terminals of the first initialization module and the first voltage transmission module are connected to the same gate signal and / or the same gate line; the transistors in the first initialization module and the transistors in the first voltage transmission module have the same channel type. Preferably, the first initialization module includes an N-type transistor or a P-type transistor.

9. The pixel circuit according to claim 6, characterized in that, The first reference voltage is higher than the first initialization voltage; Preferably, the second terminal of the light-emitting element is connected to a second power supply voltage, and the first initialization voltage is higher than the second power supply voltage; Preferably, the pixel circuit is provided with a write frame and a hold frame, the write frame includes a first initialization phase, a threshold compensation phase and a data writing phase, and the hold frame includes a second initialization phase; The first initialization module is used to transmit the first initialization voltage to the first terminal of the light-emitting element and / or the second terminal of the second storage module during the second initialization phase. The second voltage transmission module is used to transmit the second reference voltage to the second terminal of the first storage module and / or the first terminal of the second storage module during the first initialization phase. During the second initialization phase, the compensation module and / or the second voltage transmission module are turned off; Preferably, the control terminal of the first initialization module and the control terminal of the first voltage transmission module are connected to the same gate signal and / or connected to the same gate line. During the second initialization phase, the first voltage transmission module is turned on, and during the first initialization phase, the first initialization module is turned off. Preferably, the driving current generated by the driving module during the light-emitting stage is related to the difference between the data voltage and the first initialization voltage.

10. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a third voltage transmission module, which is electrically connected to the second terminal of the driving module and is connected to a first power supply voltage. The third voltage transmission module is used to transmit the first power supply voltage to the control terminal of the drive module via the turned-on compensation module during the first initialization phase. Preferably, the second voltage transmission module is used to transmit the second reference voltage to the second terminal of the first storage module and / or the first terminal of the second storage module during the first initialization phase; Preferably, in a write frame, the first initialization phase precedes the data write phase, and / or, in a write frame, the first initialization phase precedes the threshold compensation phase; Preferably, the third voltage transmission module is used to transmit the first power supply voltage to the second terminal of the driving module during the light emission stage; Preferably, the first power supply voltage is higher than the first reference voltage.

11. The pixel circuit according to claim 10, characterized in that, The third voltage transmission module includes a fourth voltage transmission unit and a fifth voltage transmission unit, and the fourth voltage transmission unit is electrically connected to the second terminal of the drive module. The fourth voltage transmission unit is used to be turned on during the first initialization phase, and to transmit the first power supply voltage to the control terminal of the drive module via the turned-on compensation module. The fifth voltage transmission unit is electrically connected to the second terminal of the driving module; the fifth voltage transmission unit is connected to the first power supply voltage, and the fifth voltage transmission unit is used to turn on during the light emission stage to transmit the first power supply voltage to the second terminal of the driving module. Preferably, the pixel circuit further includes a first light-emitting control module, which is connected between the second end of the second storage module and the first end of the driving module. The control terminal of the fifth voltage transmission unit and the control terminal of the first light-emitting control module are connected to the same gate signal and / or the same gate line. The transistors in the first light-emitting control module and the transistors in the fifth voltage transmission unit have the same channel type.

12. The pixel circuit according to claim 10, characterized in that, The pixel circuit further includes a first light-emitting control module, which is connected between the second terminal of the second storage module and the first terminal of the driving module. The turn-off pulse of the gate signal accessed to the control terminal of the third voltage transmission module has the same pulse width as the turn-off pulse of the gate signal accessed to the control terminal of the first light-emitting control module. In the same write frame or the same hold frame, the turn-off pulse of the gate signal accessed by the control terminal of the third voltage transmission module lags behind the turn-off pulse of the gate signal accessed by the control terminal of the first light emission control module. Preferably, during the first initialization phase and the light-emitting phase, the first power supply voltage is transmitted to the second terminal of the driving module through the same transistor in the third voltage transmission module.

13. The pixel circuit according to claim 1, characterized in that, The conduction pulse of the gate signal input to the control terminal of the compensation module has the same pulse width as the conduction pulse of the gate signal input to the control terminal of the first voltage transmission module. In the same write frame, the turn-on pulse of the gate signal accessed by the control terminal of the first voltage transmission module lags behind the turn-on pulse of the gate signal accessed by the control terminal of the compensation module. Preferably, the transistors in the compensation module and the transistors in the first voltage transmission module have the same channel type; Preferably, the driving module includes an N-type transistor; and / or, the driving module includes a metal-oxide-semiconductor transistor. Preferably, the compensation module is used to be turned off during the data writing phase; in the write frame, the threshold compensation phase is performed before the data writing phase. Preferably, the first storage module includes a first capacitor, the second storage module includes a second capacitor, and the ratio of the first capacitor to the second capacitor is greater than or equal to 0.9:1 and less than or equal to 1:0.

9.

14. A display panel, characterized in that, include: The pixel circuit as described in any one of claims 1-13.

15. The display panel according to claim 14, characterized in that, The display panel includes a first gate driving circuit, which includes multiple cascaded first shift registers. The control terminal of the compensation module and the control terminal of the first voltage transmission module in the same pixel circuit are connected to the output terminals of different first shift registers. Preferably, when the pixel circuit further includes a third voltage transmission module, the display panel includes a second gate driving circuit, the second gate driving circuit includes a plurality of cascaded second shift registers, and the control terminal of the third voltage transmission module and the control terminal of the first light emission control module in the same pixel circuit are connected to the output terminals of different second shift registers; Preferably, the display panel includes gate lines, the pixel circuits are electrically connected to the gate lines, the gate lines extend along a first direction, and each row of the pixel circuits includes a plurality of pixel circuits arranged along the first direction; The gate signal turn-on pulses of the control terminal of the compensation module of the multiple rows of pixel circuits overlap, and / or the threshold compensation stages of the multiple rows of pixel circuits overlap.

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