Display devices and their driving methods

Abstract

This application relates to a display device and a driving method thereof. A display device includes a display panel, a first gating driving circuit, and a second gating driving circuit. The display panel includes a first screen block and a second screen block. The first gating driving circuit provides a scan output to a first gating line of the first screen block, and the second gating driving circuit provides a scan output to a second gating line of the second screen block. The first screen block includes a first high-frequency region where first image data is updated at a first refresh rate and a first low-frequency region where second image data is updated at a second refresh rate lower than the first refresh rate. The second screen block includes a second high-frequency region where third image data is updated at a third refresh rate and a second low-frequency region where fourth image data is updated at a fourth refresh rate lower than the third refresh rate.

Description

Technical Field

[0001] This disclosure relates to display devices and driving methods thereof, and more specifically, for example, but not limited to, display devices and driving methods thereof capable of reducing power consumption. Background Technology

[0002] Display devices are used in a variety of technological fields, such as portable terminals, home televisions (TVs), outdoor industrial / advertising displays, and automotive displays. As the screen size and resolution of display devices increase, energy-saving technologies for stable power supply are an important issue.

[0003] The descriptions provided in this Background section should not be assumed to be prior art simply because they are mentioned in or associated with this section. The Background section may include information describing one or more aspects of the subject matter art. Summary of the Invention

[0004] The inventors of this application have newly recognized that conventional energy-saving technologies control the entire screen using the same method regardless of the video content, and are therefore limited in terms of power consumption reduction. To overcome the aforementioned limitations of related technologies, this disclosure provides a display device and its driving method that can drive multiple partitioned screen blocks at independent data refresh rates based on video content.

[0005] Another aspect of this disclosure is to provide a display device and a driving method thereof that can reduce power consumption.

[0006] Additional advantages, aspects, and features of this disclosure will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon reviewing the following, or may be learned from practice of this disclosure. Various aspects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description and claims, and in the accompanying drawings.

[0007] To achieve these and other objectives and in accordance with the purposes of this disclosure, as implemented and broadly described herein, a display device may include: a display panel including a first screen block and a second screen block; a first gating drive circuit configured to provide a scan output to a first gating line of the first screen block; and a second gating drive circuit configured to provide a scan output to a second gating line of the second screen block, wherein the first screen block includes a first high-frequency region and a first low-frequency region, in the first high-frequency region, first image data is updated at a first data refresh rate, in the first low-frequency region, second image data is updated at a second data refresh rate less than the first data refresh rate, and the second screen block includes a second high-frequency region and a second low-frequency region, in the second high-frequency region, third image data is updated at a third data refresh rate, and in the second low-frequency region, fourth image data is updated at a fourth data refresh rate less than the third data refresh rate.

[0008] In another aspect of this disclosure, a driving method for a display device including a first screen block and a second screen block may include: providing a scan output to a first gate line of the first screen block; and providing a scan output to a second gate line of the second screen block, wherein the first screen block includes a first high-frequency region and a first low-frequency region, wherein in the first high-frequency region, first image data is updated at a first data refresh rate, and in the first low-frequency region, second image data is updated at a second data refresh rate less than the first data refresh rate, and wherein the second screen block includes a second high-frequency region and a second low-frequency region, wherein in the second high-frequency region, third image data is updated at a third data refresh rate, and in the second low-frequency region, fourth image data is updated at a fourth data refresh rate less than the third data refresh rate.

[0009] According to an example implementation of this disclosure, a display device and its driving method are capable of driving multiple divided screen blocks at independent data refresh rates based on video content.

[0010] According to exemplary embodiments of this disclosure, display devices and their driving methods can further reduce power consumption compared to conventional energy-saving technologies.

[0011] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0012] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the various principles of the disclosure. In the drawings:

[0013] Figure 1 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure;

[0014] Figure 2 This is a diagram illustrating the equivalent circuit of a pixel according to an exemplary embodiment of the present disclosure;

[0015] Figure 3A This is a diagram illustrating example drive waveforms for pixels in a refresh frame;

[0016] Figure 3B This is a diagram illustrating an example drive waveform for skipping pixels in a frame;

[0017] Figure 4 This is a diagram illustrating an example of multiple screen blocks being driven at independent refresh rates;

[0018] Figure 5 and Figure 6 This is achieved by synchronizing the timing of the masking process with the scan output and skipping the data refresh operation. Figure 4 A diagram showing the multi-refresh-rate driven scenario;

[0019] Figure 7 and Figure 8 This is a diagram illustrating the drive waveform and stage connection configuration of the gating drive circuit that masks the scan output from the time of the input mask scan clock.

[0020] Figure 9 and Figure 10 This is a diagram illustrating the driving waveform and circuit configuration of the fifth gating stage at the start of the scan output masking;

[0021] Figures 11A to 11D This is a diagram illustrating an example operation sequence for the fifth gating level that implements scan output masking based on scan clock masking;

[0022] Figure 12 This is a diagram illustrating an example configuration of a gating drive circuit that performs scan output masking from a predetermined time based on a scan clock masking method and changes the carry transfer direction to the forward and reverse directions;

[0023] Figures 13A to 13C This is a diagram used to describe a multi-refresh-rate drive based on forward carry transmission according to an exemplary embodiment of this disclosure;

[0024] Figures 14A to 14C This is a diagram used to describe a multi-refresh-rate drive based on reverse carry transfer according to an exemplary embodiment of this disclosure;

[0025] Figure 15 This is a diagram illustrating an extended example of multi-refresh-rate driving based on forward and reverse carry transfers; and

[0026] Figure 16 This is a diagram illustrating an example connection configuration between a clock masking control circuit, a level shifter, and a gating stage.

[0027] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative dimensions and illustrations of these elements may be exaggerated. Detailed Implementation

[0028] In the following description, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are illustrated. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the disclosure will be thorough and complete and will fully convey the concept of the disclosure to those skilled in the art. Wherever possible, unless otherwise specified, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as is known in the art, except for steps and / or operations that need to occur in a particular order. Similar reference numerals refer to similar elements throughout. The names of corresponding elements used in the following description may be chosen solely for ease of writing and may therefore differ from the names used in actual products.

[0029] The advantages and features of this disclosure, and methods of implementing them, will be illustrated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the exemplary aspects set forth herein. Rather, these exemplary embodiments are provided so that this disclosure may be thorough and complete, and fully convey the concept of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the appended claims.

[0030] Furthermore, numerous specific details are set forth in the following detailed description of this disclosure in order to provide a sufficiently thorough understanding of this disclosure. However, it will be understood that this disclosure can be practiced without these specific details. In other instances, known methods, processes, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of this disclosure.

[0031] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to describe various embodiments of this disclosure are merely exemplary, and this disclosure is not limited thereto. Similar reference numerals refer to similar elements throughout. The same elements are designated by the same reference numerals throughout this specification. As used herein, the terms “comprising,” “having,” “including,” etc., indicate that additional components may be added, unless more restrictive terms such as “only” are used. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Any implementation described herein as an “example” is not necessarily to be construed as more preferred or advantageous than other implementations.

[0032] Even if not explicitly stated, the elements in the various embodiments of this disclosure should be interpreted as including margins of error.

[0033] When describing positional relationships, for example, when using terms such as "above," "over," "below," "above," "below," "below," "near," "adjacent," "next to," "beside," or "adjoining" to describe the positional relationship between two components, one or more other components may be located between the two components, unless more restrictive terms such as "immediately," "directly," or "closely" are used. For example, when a structure is described as being "above," "over," "below," "above," "below," "below," "near," "adjacent," "beside," or "adjoining" another structure, this description should be interpreted to include situations where these structures are in contact with each other and situations where a third structure is positioned or inserted between them. Furthermore, the terms "left side," "right side," "top," "bottom," "downward," "upward," "upper part," "lower part," etc., refer to any frame of reference.

[0034] When describing temporal relationships, such as when time sequence is described as “after,” “next,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “only,” “directly,” or “immediately” are used.

[0035] When a component or layer is referred to as being "on" or "connected to" another component or layer, it should be understood that this means the component or layer may be directly on or directly connected to the other component or layer, or that there may be an intermediate component or layer. Furthermore, when a component is referred to as being "on" or "below" another component, it should be understood that this means the components may be configured to be in direct contact with each other, or may be configured not to be in direct contact with each other.

[0036] The term “at least one” should be understood to include any and all combinations of one or more of the relevant listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element, the first element, the second element, or the third element.

[0037] It will be understood that although the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another and do not limit the nature, order, sequence, or number of elements. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0038] In the following description, detailed descriptions will be omitted where it is determined that such descriptions of known functions or configurations would unnecessarily obscure the essential points of this disclosure. Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0039] Features of the various embodiments of this disclosure may be partially or wholly linked or combined with each other, and may interoperate with each other and be technically driven in various ways, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be implemented independently of each other, or may be implemented together in an interdependent manner.

[0040] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant field, and shall not be interpreted as having an overly idealized or overly formal meaning, unless expressly defined herein. For example, the terms “component” or “unit” may be applied, for example, to a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the described functions, as would be understood by one of ordinary skill in the art.

[0041] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, all components of each display device according to all embodiments of the present disclosure are operatively connected and configured. For ease of description, the scale of each element shown in the drawings differs from the actual scale; therefore, the description is not limited to the scales shown in the figures.

[0042] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0043] Reference Figure 1 The display device according to the embodiments of this disclosure can be described as an organic light-emitting display device, but this disclosure is not limited thereto, and the display device of this disclosure can also be implemented as a quantum dot display device, a micro light-emitting diode (LED) display device, or a miniature light-emitting diode (LED) display device. The display panel 100 may include a screen for reproducing an input image. The screen may include a pixel array that displays pixel data (hereinafter referred to as "image data") DATA of the input image.

[0044] The screen may include at least a first screen block AA1 and a second screen block AA2 that are driven separately. The first screen block AA1 and the second screen block AA2 may be electrically disconnected or separated from each other. One side of the first screen block AA1 and one side of the second screen block AA2 may be in contact with each other and have a boundary therebetween. A first data driving circuit 110A may be disposed on the opposite side of the first screen block AA1. A second data driving circuit 110B may be disposed on the opposite side of the second screen block AA2. The screen block of this disclosure may also be referred to as a display area block or a display driving block, and this disclosure is not limited thereto.

[0045] The first screen block AA1 may include a first data line DL1, a first gating line GL1 intersecting the first data line DL1, and a first pixel. The first pixel may be arranged in the first screen block AA1 in a matrix form defined by the intersection between the first data line DL1 and the first gating line GL1 to configure a first pixel array. Based on the position of the first pixels emitting the same color light, the first pixels may be arranged in the first screen block AA1 in various types such as striped and diamond patterns.

[0046] The second screen block AA2 may include a second data line DL2, a second gating line GL2 intersecting the second data line DL2, and second pixels. The second pixels may be arranged in the second screen block AA2 in a matrix form defined by the intersection between the second data line DL2 and the second gating line GL2 to configure a second pixel array. Based on the position of the second pixels emitting the same color light, the second pixels may be arranged in various types in the second screen block AA2, such as striped or diamond-shaped arrangements.

[0047] The first screen block AA1 and the second screen block AA2 may not share data lines DL1 and DL2, and furthermore, they may not share gating lines GL1 and GL2. The first data line DL1 in the first screen block AA1 and the second data line DL2 in the second screen block AA2 may be physically and electrically disconnected from each other. Similarly, the first gating line GL1 in the first screen block AA1 and the second gating line GL2 in the second screen block AA2 may be physically and electrically disconnected from each other.

[0048] The pixel PIX included in the first frame block AA1 and the second frame block AA2 may include R pixels that generate red (R) light, G pixels that generate green (G) light, and B pixels that generate blue (B) light to achieve various color combinations. The pixel PIX may also include W pixels that generate white (W) light. RGB pixels or RGBW pixels can be configured with a single pixel.

[0049] Each pixel in the first frame block AA1 and the second frame block AA2 can be implemented using a pixel circuit connected to the data line DL and the gate line GL via a thin-film transistor (TFT). The pixel circuit may include a light-emitting device, a driving transistor, one or more switching transistors, and a capacitor. The light-emitting device can be implemented as an organic light-emitting diode (OLED) in which an organic compound layer is disposed between a cathode and an anode. The driving current applied to the light-emitting device can be controlled based on the gate-source voltage of the driving transistor. The gate-source voltage of the driving transistor can be determined by the data voltage corresponding to the image data DATA.

[0050] The pixel circuitry can sample the threshold voltage of the driving transistor midway through a pixel programming operation performed within a frame period. This sampled threshold voltage can be reflected in the gate-source voltage of the driving transistor (hereinafter referred to as Vgs), thus preventing or reducing drive current distortion due to changes in the threshold voltage of the driving transistor. In other words, changes in the threshold voltage of the driving transistor can be reflected and therefore compensated for in the gate-source voltage of the driving transistor, so the drive current will not be affected by such threshold voltage changes.

[0051] Pixel circuits can be implemented as hybrid types. In hybrid pixel circuits, the semiconductor layers of some transistors may include low-temperature polysilicon (hereinafter referred to as LTPS), while the semiconductor layers of other transistors may include oxide semiconductors.

[0052] The timing controller 130 can receive video data DATA and timing signals synchronized with the video data DATA from a host system (not shown). The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical synchronization signal Vsync defines a vertical time period (i.e., one frame period). The horizontal synchronization signal Hsync defines a horizontal time period (i.e., one frame period). The data enable signal DE defines the time for transmitting video data DATA within either the vertical or horizontal time period.

[0053] The timing controller 130 can generate a first source timing control signal DDC1 for controlling the operation timing of the first data drive circuit 110A and a first gating timing control signal GDC1 for controlling the operation timing of the first gating drive circuit 120A based on the timing signals Vsync, Hsync and DE received from the host system.

[0054] The timing controller 130 can generate a second source timing control signal DDC2 for controlling the operation timing of the second data drive circuit 110B and a second gating timing control signal GDC2 for controlling the operation timing of the second gating drive circuit 120B based on the timing signals Vsync, Hsync and DE received from the host system.

[0055] The display panel driver circuit can be connected to the timing controller 130 via an interface circuit.

[0056] The display panel driving circuit may include a first data driving circuit 110A and a first gating driving circuit 120A for driving the first screen block AA1, and a second data driving circuit 110B and a second gating driving circuit 120B for driving the second screen block AA2.

[0057] The first data driving circuit 110A can drive the first data line DL1 of the first screen block AA1, and the first gating driving circuit 120A can drive the first gating line GL1 of the first screen block AA1. The second data driving circuit 110B can drive the second data line DL2 of the second screen block AA2, and the second gating driving circuit 120B can drive the second gating line GL2 of the second screen block AA2.

[0058] The first data driving circuit 110A can be implemented using multiple driver integrated circuits (ICs). The first data driving circuit 110A can be provided with image data DATA and a first source timing control signal DDC1 from the timing controller 130. The first data driving circuit 110A can generate a first data voltage corresponding to the image data DATA, and can output the first data voltage to the first data line DL1 based on the first source timing control signal DDC1.

[0059] The second data driving circuit 110B can be implemented using multiple driver ICs. The second data driving circuit 110B can be provided with image data DATA and a second source timing control signal DDC2 from the timing controller 130. The second data driving circuit 110B can generate a second data voltage corresponding to the image data DATA, and can output the second data voltage to the second data line DL2 based on the second source timing control signal DDC2.

[0060] The first gating drive circuit 120A and the second gating drive circuit 120B can be directly formed in the border area outside the screen blocks AA1 and AA2 of the display panel 100. The screen blocks AA1 and AA2 can be included in the display area of ​​the display panel 100, and the first gating drive circuit 120A and the second gating drive circuit 120B can be disposed in the border area or non-display area adjacent to the display area of ​​the display panel 100.

[0061] The first gating drive circuit 120A can generate a pulse-type first gating signal based on the first gating timing control signal GDC1 provided from the timing controller 130, and can output the first gating signal to the first gating line GL1 (e.g., by progressive scan). The pulse-type first gating signal may include one or more scan signals and a light emission control signal.

[0062] The second gating drive circuit 120B can generate a pulse-type second gating signal based on the second gating timing control signal GDC2 provided from the timing controller 130, and can output the second gating signal to the second gating line GL2 (e.g., by progressive scan). The pulse-type second gating signal may include one or more scan signals and a light emission control signal.

[0063] Figure 2 This is a diagram illustrating the equivalent circuit of a pixel PIX according to an embodiment of the present disclosure.

[0064] Reference Figure 2 A pixel PIX can be implemented using a pixel circuit, which includes an OLED light-emitting device, a driving transistor DT, multiple switching transistors (e.g., first to seventh switching transistors) T1 to T7, and a capacitor CST.

[0065] The driving transistor DT, switching transistors T1 to T7, and capacitor CST can control the driving current flowing in the OLED to drive the OLED. Each of the driving transistor DT and switching transistors T1 to T7 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0066] Each of the second transistor T2 through the sixth transistor T6 and the driving transistor DT can be implemented as a PMOS type, comprising a semiconductor layer of LTPS with good response characteristics. On the other hand, the first transistor T1 and the seventh transistor T7, which are directly connected to the gate electrode of the driving transistor DT, can be implemented as NMOS type, comprising a semiconductor layer of oxide with good cutoff characteristics.

[0067] The turn-on voltage of a PMOS transistor can be a low gate voltage, and the turn-off voltage of a PMOS transistor can be a high gate voltage. On the other hand, the turn-on voltage of an NMOS transistor can be a high gate voltage, and the turn-off voltage of an NMOS transistor can be a low gate voltage.

[0068] An OLED (Optical Display Panel) device may include an anode (or pixel electrode), a cathode (or common electrode), and an organic compound layer disposed therebetween (consisting of a common layer and an emissive layer). The anode of the OLED device may be connected to a fourth node N4, and the cathode of the OLED device may be connected to a second source voltage ELVSS.

[0069] The driving transistor DT may include a gate electrode connected to a first node N1, a source electrode connected to a second node N2, and a drain electrode connected to a third node N3. The driving transistor DT can generate a driving current based on the voltage of the first node N1 (or the data voltage stored in the capacitor CST), and can apply the driving current to the light-emitting device OLED.

[0070] The first switching transistor T1 may include a gate electrode for receiving a first scan signal SCAN1, a drain electrode connected to a third node N3, and a source electrode connected to a first node N1. The first switching transistor T1 can be turned on in response to the first scan signal SCAN1, and can short-circuit the gate and drain electrodes of the driving transistor DT to each other. Therefore, when the first switching transistor T1 is turned on, the driving transistor DT can operate like a diode.

[0071] The second switching transistor T2 may include a gate electrode for receiving the second scan signal SCAN2, a source electrode for receiving the data voltage Vdata, and a drain electrode connected to the second node N2. The second switching transistor T2 can be turned on in response to the second scan signal SCAN2 and can transmit the data voltage Vdata to the second node N2.

[0072] The capacitor CST can be connected between the first node N1 and the input terminal of the first source voltage ELVDD. The capacitor CST can maintain the voltage of the first node N1.

[0073] The third switching transistor T3 and the fourth switching transistor T4 can be connected between the first source voltage ELVDD and the light-emitting diode OLED, and can form a current movement path through which the driving current generated by the driving transistor DT flows.

[0074] The third switching transistor T3 may include a source electrode connected to the input terminal of the first source voltage ELVDD, a drain electrode connected to the second node N2, and a gate electrode for receiving the light emission control signal EM. The fourth switching transistor T4 may include a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode for receiving the light emission control signal EM.

[0075] The third switching transistor T3 and the fourth switching transistor T4 can be turned on in response to the light emission control signal EM. When the third switching transistor T3 and the fourth switching transistor T4 are turned on, the light-emitting device OLED can receive driving current from the driving transistor DT and emit light with a brightness corresponding to the driving current.

[0076] The fifth switching transistor T5 may include a source electrode connected to the input terminal of the OBS voltage Vobs, a drain electrode connected to the second node N2, and a gate electrode for receiving the third scan signal SCAN3. The fifth switching transistor T5 can be turned on in response to the third scan signal SCAN3 and can apply the OBS voltage Vobs to the second node N2.

[0077] The sixth switching transistor T6 may include a source electrode connected to the input terminal of the anode reset voltage VAR, a drain electrode connected to the fourth node N4, and a gate electrode for receiving the third scan signal SCAN3. The sixth switching transistor T6 can be turned on in response to the third scan signal SCAN3 and can transmit the anode reset voltage VAR to the fourth node N4.

[0078] The seventh switching transistor T7 may include a source electrode connected to the input terminal of the initialization voltage Vini, a drain electrode connected to the first node N1, and a gate electrode for receiving the fourth scan signal SCAN4. The seventh switching transistor T7 can be turned on in response to the fourth scan signal SCAN4 and can apply the initialization voltage Vini to the first node N1.

[0079] Pixel circuitry can be driven at multiple refresh rates. With multiple refresh rate driving, data refresh operations can be skipped synchronously with the scan output masking timing. One or more skip frames can be provided between adjacent refresh frames, during which data refresh operations are skipped. The refresh rate can be determined based on the number of skip frames.

[0080] The pixel circuit can perform data refresh operations, including pixel initialization and data programming, within a refresh frame. During the data refresh operation, the light-emitting device can be turned off, and at this time, an anode reset operation can be performed to initialize the light-emitting device to its anode reset voltage.

[0081] The pixel circuit can omit (or skip) the data refresh operation in the skip frame, and the data refresh condition Vgs (drive current) set in the previous refresh frame can be fully maintained. The pixel circuit can perform an anode reset operation to turn off the light-emitting device in the skip frame. Therefore, the duration for which the light-emitting device is on in the skip frame can be substantially equal to the duration for which the light-emitting device is on in the refresh frame.

[0082] In each of the refresh and skip frames, the pixel circuitry can perform an on-bias stress (OBS) operation on the driving transistors during the anode reset operation. The OBS operation can be used to prevent or reduce image quality defects caused by the hysteresis characteristics of the driving transistors.

[0083] Figure 3A This is a diagram illustrating the driving waveform of pixels in a refresh frame.

[0084] Reference Figure 3A The first OBS period Tobs1, the initialization period Ti, the programming period Ts, the second OBS period Tobs2, and the luminescence period Te can be arranged in chronological order in the refresh frame.

[0085] The second scan signal SCAN2 can define a programming period Ts that provides the data voltage Vdata. The programming period Ts can be the on-level (Lon) period of the second scan signal SCAN2.

[0086] The third scan signal SCAN3 can be defined as a first OBS period Tobs1 before the programming period Ts and a second OBS period Tobs2 after the programming period Ts and before the emission period Te. The first OBS period Tobs1 and the second OBS period Tobs2 can each be the on-level (Lon) period of the third scan signal SCAN3.

[0087] The fourth scan signal SCAN4 can define an initialization period Ti that is positioned between the first OBS period Tobs1 and the programming period Ts. The initialization period Ti can be the on-level (Lon) period of the fourth scan signal SCAN4.

[0088] The light emission control signal EM can define the light emission period Te following the second OBS period Tobs2. The light emission period Te can be the on-level (Lon) period of the light emission control signal EM.

[0089] During the first OBS period Tobs1, the OBS voltage Vobs can be applied to the second node N2. Based on the OBS voltage Vobs, the drain-source channel of the driving transistor DT can be opened to the maximum extent, and the driving transistor DT can maintain a stronger saturation state. Therefore, the hysteresis characteristic of the driving transistor DT can be recovered before data programming.

[0090] During the first OBS period Tobs1, the anode reset voltage Var can be applied to the fourth node N4, so that the residual charge in the parasitic capacitor formed between the anode and cathode of the OLED can be reset.

[0091] During the initialization period Ti, the first node N1 can be initialized to the initialization voltage Vini, and as the first switching transistor T1 is turned on, the driving transistor DT can operate like a diode.

[0092] During the programming period Ts, as the first switching transistor T1 and the second switching transistor T2 are turned on, the threshold voltage sampling operation and the data programming operation can be performed sequentially or simultaneously.

[0093] During the second OBS period Tobs2, the OBS voltage Vobs can be applied to the second node N2. Based on the OBS voltage Vobs, the drain-source channel of the driving transistor DT can be opened to the maximum extent, and the driving transistor DT can maintain a stronger saturation state. Therefore, the hysteresis characteristic of the driving transistor DT can be recovered again before emission.

[0094] During the second OBS period Tobs2, the anode reset voltage VAR can be applied to the fourth node N4, so that the residual charge in the parasitic capacitor of the OLED can be reset again.

[0095] During the emission period Te, a drive current can be supplied to the OLED from the drive transistor DT. The drive current can be based on Vgs of the drive transistor DT, which is set during the programming period Ts. The drive current can be independent of the threshold voltage of the drive transistor DT and can be associated with the data voltage Vdata.

[0096] Figure 3B This is a diagram illustrating the driving waveform of pixels skipped in a frame.

[0097] Reference Figure 3B The third OBS period (Tobs3), the fourth OBS period (Tobs4), and the luminous period (Te) can be arranged in chronological order within the skip frames.

[0098] The illumination control signal EM can define the illumination period Te of the skip frame. The illumination period Te can be the on-level (Lon) period of the illumination control signal EM. The on-level (Lon) period of the illumination control signal EM in the skip frame can be basically the same as that in the refresh frame.

[0099] The third scan signal SCAN3 can be further defined as the third OBS period Tobs3 and the fourth OBS period Tobs4, which are sequentially arranged before the emission period Te in the skip frame. In the skip frame, the third OBS period Tobs3 and the fourth OBS period Tobs4 can each be the on-level (Lon) period of the third scan signal SCAN3. The on-level (Lon) period of the third scan signal SCAN3 in the skip frame can be substantially the same as that in the refresh frame.

[0100] Furthermore, initialization and programming periods may not be required in skip frames.

[0101] For this purpose, the outputs of the first scan signal SCAN1 and the fourth scan signal SCAN4 can be skipped in the skip frame. Furthermore, the output of the third scan signal SCAN3 can be skipped.

[0102] Figure 4 This is a diagram illustrating an example of driving multiple screen blocks with independent refresh rates.

[0103] Reference Figure 4 A frame can be divided into a first frame block AA1 and a second frame block AA2, which are driven independently.

[0104] The first image block AA1 can be driven based on the first scan output and its corresponding image data.

[0105] The first image block AA1 may include a first high-frequency region AR11 and a first low-frequency region AR12. In the first high-frequency region AR11, first image data is updated at a first data refresh rate H-FR, and in the first low-frequency region AR12, second image data is updated at a second data refresh rate L-FR, which is less than the first data refresh rate H-FR.

[0106] Within the same frame, depending on the scanning direction of the first image block AA1, the scanning output timing of the gating line corresponding to the first high-frequency region AR11 can be earlier than the scanning output timing of the gating line corresponding to the first low-frequency region AR12, but this disclosure is not limited thereto. Furthermore, within a predetermined time, the number of scanning output masks on the gating line of the first low-frequency region AR12 can be greater than the number of scanning output masks on the gating line of the first high-frequency region AR11.

[0107] The second screen block AA2 can be driven based on the second scan output and its corresponding image data.

[0108] The second image block AA2 may include a second high-frequency region AR21 and a second low-frequency region AR22. In the second high-frequency region AR21, third image data is updated at a third data refresh rate H-FR', and in the second low-frequency region AR22, fourth image data is updated at a fourth data refresh rate L-FR' which is less than the third data refresh rate H-FR'.

[0109] Within the same frame, depending on the scanning direction of the second screen block AA2, the scanning output timing of the gating line corresponding to the second high-frequency region AR21 can be earlier than the scanning output timing of the gating line corresponding to the second low-frequency region AR22, but this disclosure is not limited thereto. Furthermore, within a predetermined time, the number of scanning output masks on the gating line of the second low-frequency region AR22 can be greater than the number of scanning output masks on the gating line of the second high-frequency region AR21.

[0110] Furthermore, the first data refresh rate H-FR and the third data refresh rate H-FR' can be equal to or different from each other. Additionally, the second data refresh rate L-FR and the fourth data refresh rate L-FR' can be equal to or different from each other.

[0111] Figure 5 and Figure 6 This is achieved by synchronizing the timing of the masking process with the scan output and skipping the data refresh operation. Figure 4 A diagram illustrating the multi-refresh-rate driven scenario.

[0112] Reference Figure 5 The first high-frequency region AR11 of the first image block AA1 can update the first image data A at a period of 240Hz, and the first low-frequency region AR12 of the first image block AA1 can update the second image data B at a period of 1Hz. The refresh operation of the first high-frequency region AR11 can be synchronized with the scan output timing of each frame from the first frame to the 240th frame. On the other hand, the refresh operation of the first low-frequency region AR12 can be synchronized with the scan output timing of the first frame, and then the synchronization with the scan output masking timing of the second frame to the 240th frame can be omitted. The first high-frequency region AR11 can be a region of interest (ROI), and the first low-frequency region AR12 can be a background region.

[0113] Reference Figure 5The second high-frequency region AR21 of the second image block AA2 can update the third image data C at a period of 240Hz, and the second low-frequency region AR22 of the second image block AA2 can update the fourth image data D at a period of 1Hz. The refresh operation of the second high-frequency region AR21 can be synchronized with the scan output timing of each frame from the first frame to the 240th frame. On the other hand, the refresh operation of the second low-frequency region AR22 can be synchronized with the scan output timing of the first frame, and then the synchronization with the scan output masking timing of the second frame to the 240th frame can be omitted. The second high-frequency region AR21 can be a Region of Interest (ROI), and the second low-frequency region AR22 can be a background region.

[0114] Reference Figure 6 The first high-frequency region AR11 of the first image block AA1 can update the first image data A at a period of 240Hz, and the first low-frequency region AR12 of the first image block AA1 can update the second image data B at a period of 1Hz. The refresh operation of the first high-frequency region AR11 can be synchronized with the scan output timing of each frame from the first frame to the 240th frame. On the other hand, the refresh operation of the first low-frequency region AR12 can be synchronized with the scan output timing of the first frame, and then the synchronization with the scan output masking timing of the second frame to the 240th frame can be omitted. The first high-frequency region AR11 can be a region of interest (ROI), and the first low-frequency region AR12 can be a background region.

[0115] Reference Figure 6 The second high-frequency region AR21 of the second frame block AA2 can update the third image data C at a period of 120Hz, and the second low-frequency region AR22 of the second frame block AA2 can update the fourth image data D at a period of 60Hz. The refresh operation of the second high-frequency region AR21 can be synchronized with the scan output timing of each frame from the first odd-numbered frames to the 120th odd-numbered frames, and can also be synchronized with the scan output masking timing of other frames (e.g., even-numbered frames). On the other hand, the refresh operation of the second low-frequency region AR22 can be synchronized with the scan output timing of each frame in the (4k-3)th frame (where k can be 1 to 60), and can omit the synchronization with the scan output masking timing of other frames. It should be noted that refresh rates of 240Hz, 120Hz, 60Hz, and 1Hz are described by way of example only, and other possible refresh rates can also be implemented in this disclosure.

[0116] Figure 7 and Figure 8 This is a diagram illustrating the drive waveform and stage connection configuration of the gating drive circuit that masks the scan output starting from the input mask scan clock time.

[0117] Figure 7 The gating drive circuit can be Figure 1 Each of the first gating drive circuit 120A and the second gating drive circuit 120B. For example, Figure 1 Each of the first gating drive circuit 120A and the second gating drive circuit 120B can be as follows: Figure 7 That's how it was achieved.

[0118] Reference Figure 7 and Figure 8 The gating drive circuit may include multiple gating stages GIP1 to GIP8 that are cascaded together.

[0119] The gating drive circuit may include: the (4k-3)th gating stages GIP1 and GIP5 (where k can be a positive integer), which generate a scan output corresponding to the first odd clock CLK1_O; the (4k-2)th gating stages GIP2 and GIP6, which generate a scan output corresponding to the second odd clock CLK2_O, whose phase is different from that of the first odd clock CLK1_O; the (4k-1)th gating stages GIP3 and GIP7, which generate a scan output corresponding to the first even clock CLK1_E, whose phase is the same as that of the first odd clock CLK1_O; and the 4kth gating stages GIP4 and GIP8, which generate a scan output corresponding to the second even clock CLK2_E, whose phase is the same as that of the second odd clock CLK2_O. Figure 8 As can be seen, the phase difference between the first odd-numbered clock CLK1_O and the second odd-numbered clock CLK2_O is 180 degrees, and the phase difference between the first even-numbered clock CLK1_E and the second even-numbered clock CLK2_E is also 180 degrees. In other words, the phases of the first odd-numbered clock CLK1_O and the second odd-numbered clock CLK2_O are opposite to each other, and the phases of the first even-numbered clock CLK1_E and the second even-numbered clock CLK2_E are also opposite to each other.

[0120] GIP1 can be operationally enabled based on an externally input start signal VST, and can generate a scan output SRO1 corresponding to a first odd-numbered clock CLK1_O. The scan output SRO1 of GIP1 can be input to GIP2 as a first carry signal Carry1. GIP2 can be operationally enabled based on the first carry signal Carry1, and can generate a scan output SRO2 corresponding to a second odd-numbered clock CLK2_O. In this way, the scan output SRO7 of GIP7 can be input to GIP8 as a seventh carry signal Carry7. GIP8 can be operationally enabled based on the seventh carry signal Carry7, and can generate a scan output SRO8 corresponding to a second even-numbered clock CLK2_E.

[0121] On the other hand, when the first odd clock CLK1_O is input in a masked state in time synchronization with the scan output SRO5 of GIP5, the scan outputs SRO5 to SRO8 of GIP5 to GIP8 can be skipped. The scan output SRO5 of GIP5 can be skipped by the masked first odd clock CLK1_O, and the scan outputs SRO6, SRO7, and SRO8 of GIP6, GIP7, and GIP8 can be skipped by the carry signals Carry5, Carry6, and Carry7 at the cutoff level.

[0122] Figure 9 This is a diagram illustrating the circuit configuration of the fifth gate stage GIP5, which initiates the scan output masking.

[0123] Reference Figure 9 The fifth gate stage GIP5 may include elements such as T11, T12, T13, T14, Tbv, T16, T17, CQ, CQB, and CQ'. Each of T11, T12, T13, T14, Tbv, T16, and T17 may be implemented as a PMOS transistor, but this disclosure is not limited thereto.

[0124] T16 can be the first output buffer (pull-down buffer). The gate of T16 can be connected to the Q node, its source can be connected to the gating low voltage VGL, and its drain can be connected to the output node NO.

[0125] T17 can be a second output buffer (pull-up buffer). The gate of T17 can be connected to the QB node, its source can be connected to the output node NO, and its drain can be connected to the gating high voltage VGH.

[0126] The gate of T11 can be connected to the input of the first odd clock CLK1_O, its source can be connected to the input of Carry4, and its drain can be connected to the source of Tbv.

[0127] The gate of T12 can be connected to the input of Carry4, its source can be connected to the Q' node, and its drain can be connected to the gating high voltage VGH.

[0128] The gate of T13 can be connected to the Q' node, its source can be connected to the input of the first odd clock CLK1_O, and its drain can be connected to the QB node.

[0129] The gate of T14 can be connected to the input of Carry4, its source can be connected to the QB node, and its drain can be connected to the gating high voltage VGH.

[0130] The gate of Tbv can be connected to the gating voltage VGL, its source can be connected to the drain of T11, and its drain can be connected to the Q node. Furthermore, each of CQ, CQB, and CQ' can be implemented as a capacitor, with CQ connected between the Q node and the output node NO, CQB connected between the QB node and the gating high voltage VGH, and CQ' connected between the Q' node and the CQ' node.

[0131] Figure 10 This is a diagram illustrating the operation waveform of the fifth gating stage when the scan output masking begins. Figures 11A to 11D This is a diagram illustrating the operation sequence of the fifth gating level based on scan clock masking to achieve scan output masking.

[0132] Reference Figure 10 and Figure 11A During periods ① and ②, T12, T13, T11, and T17 can be cut off, while T14, Tbv, and T16 can be turned on. During periods ① and ②, the scan output SRO5 can be the gate low voltage VGL.

[0133] Reference Figure 10 and Figure 11B During period ③, T13, T11, and T17 can be cut off, while T12, T14, Tbv, and T16 can be turned on. During period ③, the scan output SRO5 can be the gate low voltage VGL.

[0134] Reference Figure 10 and Figure 11C During period ④, T13 and T17 can be turned off, and T12, T14, T11, Tbv, and T16 can be turned on. During period ④, the scan output SRO5 can be the gate low voltage VGL.

[0135] Reference Figure 10 and Figure 11D During period ⑤, T13, T11, and T17 can be cut off, while T12, T14, Tbv, and T16 can be turned on. During period ⑤, the scan output SRO5 can be the gate low voltage VGL.

[0136] As a result, during periods ② and ③, based on the masking of the first odd-numbered clock CLK1_O, the scan output SRO5 can be used as the low-voltage VGL output. In other words, during periods ② and ③, the scan output SRO5 can be masked as the low-voltage VGL output instead of being used as the high-voltage VGH output.

[0137] Figure 12 This is a diagram illustrating the configuration of a gating drive circuit that performs scan output masking from a predetermined time and changes the carry transfer direction to the forward and reverse directions based on a scan clock masking method.

[0138] Figure 12 The gating drive circuit can be Figure 1 Each of the first gating drive circuit 120A and the second gating drive circuit 120B. For example, Figure 1 Each of the first gating drive circuit 120A and the second gating drive circuit 120B can be as follows: Figure 12 That's how it was achieved.

[0139] Reference Figure 12 The gating drive circuit may include multiple gating stages GIP1 to GIP8 that are cascaded together.

[0140] The gating drive circuit may include: the (4k-3)th gating stages GIP1 and GIP5 (where k can be a positive integer), which generate a scan output corresponding to the first odd clock CLK1_O; the (4k-2)th gating stages GIP2 and GIP6, which generate a scan output corresponding to the second odd clock CLK2_O, whose phase is different from that of the first odd clock CLK1_O; the (4k-1)th gating stages GIP3 and GIP7, which generate a scan output corresponding to the first even clock CLK1_E, whose phase is the same as that of the first odd clock CLK1_O; and the 4kth gating stages GIP4 and GIP8, which generate a scan output corresponding to the second even clock CLK2_E, whose phase is the same as that of the second odd clock CLK2_O.

[0141] The gating drive circuit may also include multiple first carry transfer switches SW_T that are enabled only in a positive carry shift drive. A positive carry shift drive can represent a drive in which the carry signal is transferred from the upper side to the lower side.

[0142] Each of the multiple first carry transfer switches SW_T can be connected between the scan outputs SRO1 and SRO5 of the (4k-3)th gating stages GIP1 and GIP5 and the positive carry inputs CR1_T and CR5_T of the (4k-2)th gating stages GIP2 and GIP6.

[0143] Each of the multiple first carry transfer switches SW_T can be connected between the scan outputs SRO2 and SRO6 of the (4k-2)th gating stages GIP2 and GIP6 and the positive carry inputs CR2_T and CR6_T of the (4k-1)th gating stages GIP3 and GIP7.

[0144] Each of the multiple first carry transfer switches SW_T can be connected between the scan outputs SRO3 and SRO7 of the (4k-1)th gating stages GIP3 and GIP7 and the positive carry inputs CR3_T and CR7_T of the 4kth gating stages GIP4 and GIP8.

[0145] In the forward carry shift drive, GIP1 can be operationally enabled based on the first start signal VST_T and can output a scan output SRO1 corresponding to the first odd clock CLK1_O. The scan output SRO1 of GIP1 can be input to GIP2 as the first forward carry signal CR1_T. GIP2 can be operationally enabled based on the first forward carry signal CR1_T and can generate a scan output SRO2 corresponding to the second odd clock CLK2_O. In this way, the scan output SRO7 of GIP7 can be input to GIP8 as the seventh forward carry signal CR7_T. GIP8 can be operationally enabled based on the seventh forward carry signal CR7_T and can generate a scan output SRO8 corresponding to the second even clock CLK2_E.

[0146] In addition, the gating drive circuit may also include multiple second carry transfer switches SW_B that are enabled only in the reverse carry shift drive. The reverse carry shift drive can represent a drive in which the carry signal is transferred from the bottom to the top.

[0147] Each of the multiple second carry transfer switches SW_B can be connected between the scan outputs SRO8 and SRO4 of the 4kth gating stages GIP8 and GIP4 and the reverse carry inputs CR7_B and CR3_B of the (4k-1)th gating stages GIP7 and GIP3.

[0148] Each of the multiple second carry transfer switches SW_B can be connected between the scan outputs SRO7 and SRO3 of the (4k-1)th gating stages GIP7 and GIP3 and the reverse carry inputs CR6_B and CR2_B of the (4k-2)th gating stages GIP6 and GIP2.

[0149] Each of the multiple second carry transfer switches SW_B can be connected between the scan outputs SRO6 and SRO2 of the (4k-2)th gating stages GIP6 and GIP2 and the reverse carry inputs CR5_B and CR1_B of the (4k-3)th gating stages GIP5 and GIP1.

[0150] In the reverse carry shift drive, GIP8 can be operationally enabled based on the second start signal VST_B, and outputs a scan output SRO8 corresponding to the second even clock CLK2_E. The scan output SRO8 of GIP8 can be input to GIP7 as the seventh reverse carry signal CR7_B. GIP7 can be operationally enabled based on the seventh reverse carry signal CR7_B, and generates a scan output SRO7 corresponding to the first even clock CLK1_E. In this way, the scan output SRO2 of GIP2 can be input to GIP1 as the first reverse carry signal CR1_B. GIP1 can be operationally enabled based on the first reverse carry signal CR1_B, and generates a scan output SRO1 corresponding to the first odd clock CLK1_O.

[0151] Figures 13A to 13C It is a diagram used to describe multi-refresh-rate drives based on forward carry transfer.

[0152] Reference Figure 13A The first high-frequency region of the first frame block AA1 can update the first image data at a period of 240Hz, and the first low-frequency region of the first frame block AA1 can update the second image data at a period of 1Hz. For this purpose, the first gating drive circuit can perform a positive carry shift drive to transmit a positive carry signal from the center of the frame CEN toward the upper edge of the frame Edg1.

[0153] Reference Figure 13A The second high-frequency region of the second screen block AA2 can update the third image data at a period of 120Hz, and the second low-frequency region of the second screen block AA2 can update the fourth image data at a period of 60Hz. For this purpose, the second gating drive circuit can perform a positive carry shift drive to transmit the positive carry signal from the center of the screen CEN toward the lower edge of the screen Edg2.

[0154] In either the first or second gating drive circuit, when the first odd clock CLK1_O is input in a masked state in time synchronization with the scan output SRO5 of GIP5, the scan outputs SRO5 to SRO8 of GIP5 to GIP8 can be skipped. The scan output SRO5 of GIP5 can be skipped by the masked first odd clock CLK1_O, and the scan outputs SRO6, SRO7, and SRO8 of GIP6, GIP7, and GIP8 can be skipped by the cutoff levels CR5_T, CR6_T, and CR7_T.

[0155] Figures 14A to 14C It is a diagram used to describe multi-refresh-rate drives based on reverse carry transfer.

[0156] Reference Figure 14AThe first high-frequency region of the first screen block AA1 can update the first image data at a period of 120Hz, and the first low-frequency region of the first screen block AA1 can update the second image data at a period of 10Hz. For this purpose, the first gating drive circuit can perform a reverse carry shift drive to transmit the reverse carry signal from the upper edge of the screen Edg1 toward the center of the screen CEN.

[0157] Reference Figure 14A The second high-frequency region of the second screen block AA2 can update the third image data at a period of 60Hz, and the second low-frequency region of the second screen block AA2 can update the fourth image data at a period of 1Hz. For this purpose, the second gating drive circuit can perform a reverse carry shift drive to transmit the reverse carry signal from the bottom of the screen Edg2 toward the center of the screen CEN.

[0158] In either the first or second gating drive circuit, when the second even-numbered clock CLK2_E is input in a masked state in time synchronization with the scan output SRO4 of GIP4, the scan outputs SRO4 to SRO1 of GIP4 to GIP1 can be skipped. The scan output SRO4 of GIP4 can be skipped by the masked second even-numbered clock CLK2_E, and the scan outputs SRO3, SRO2, and SRO1 of GIP3, GIP2, and GIP1 can be skipped by the cutoff levels CR3_B, CR2_B, and CR1_B.

[0159] Figure 15 This is a diagram illustrating an extended example of multi-refresh-rate driven technology based on forward and reverse carry transfers.

[0160] Reference Figure 15 The frequency range can be divided from high frequency to low frequency, depending on the starting position of the scan for each case.

[0161] like Figure 15 As shown in Case 1, the first gating drive circuit can perform a forward carry shift drive to transmit a forward carry signal from the center CEN of the first screen block AA1 toward the upper edge Edg1 of the first screen block AA1, and the second gating drive circuit can perform a reverse carry shift drive to transmit a reverse carry signal from the lower edge Edg2 of the first screen block AA1 toward the center CEN of the first screen block AA1.

[0162] In case 1, based on the scan & skip drive of the first gating drive circuit, the area near the center CEN of the first screen block AA1 can be the high-frequency area H-FR, and the area near the upper edge Edg1 of the first screen block AA1 can be the low-frequency area L-FR.

[0163] In case 1, based on the scan & skip drive of the second gating drive circuit, the area near the lower edge of the screen Edg2 in the second screen block AA2 can be the high-frequency area H-FR, and the area near the center of the screen CEN in the second screen block AA2 can be the low-frequency area L-FR.

[0164] like Figure 15 As shown in Case 2, the first gating drive circuit can perform a reverse carry shift drive to transmit the reverse carry signal from the upper side Edg1 of the first screen block AA1 toward the center CEN of the first screen block AA1, and the second gating drive circuit can perform a forward carry shift drive to transmit the forward carry signal from the center CEN of the second screen block AA2 toward the lower side Edg2 of the second screen block AA2.

[0165] In case 2, based on the scan & skip drive of the first gating drive circuit, the area near the upper edge Edg1 of the first screen block AA1 can be the high-frequency region H-FR, and the area near the center CEN of the first screen block AA1 can be the low-frequency region L-FR.

[0166] In case 2, based on the scan & skip drive of the second gating drive circuit, the area near the center CEN of the second screen block AA2 can be the high-frequency area H-FR, and the area near the bottom Edg2 of the second screen block AA2 can be the low-frequency area L-FR.

[0167] It should be noted that although the display area of ​​the display panel is shown in the figure as being divided into two screen blocks, the display area of ​​the display panel may also be divided into three or more screen blocks, and this disclosure is not limited thereto.

[0168] Figure 16 This is a diagram illustrating the connection configuration between the clock masking control circuit, the level shifter, and the gating stage.

[0169] Reference Figure 16 The clock masking control circuit CM can analyze the first image data to be input to the first screen block. Therefore, it can set the area with relatively large changes in the image data as the first high-frequency area and the area with relatively small changes in the image data as the first low-frequency area.

[0170] The clock masking control circuit CM can generate a first control signal CTR1 corresponding to the scan output masking timing of the first high-frequency region, and a second control signal CTR2 corresponding to the scan output masking timing of the first low-frequency region. In this case, the number of clock masking frequencies for the second control signal CTR2 can be greater than the number of clock masking frequencies for the first control signal CTR1. The first control signal CTR1 may not include a clock masking period, and only the second control signal CTR2 may include a clock masking period.

[0171] The level shifter LS converts the first control signal CTR1, which is at a transistor-to-transistor logic (TTL) level, into a boost level between the gating high voltage VGH and the gating low voltage VGL to generate the first clock signal CLK1. The first clock signal CLK1 can be input to the corresponding gating stage GIP.

[0172] The level shifter LS converts the TTL-level second control signal CTR2 into a boost level between the gating high voltage VGH and the gating low voltage VGL to generate the second clock signal CLK2. The second clock signal CLK2 can be input to the corresponding gating stage GIP.

[0173] In this case, the number of clock masking frequencies for the second clock signal CLK2 can be greater than the number of clock masking frequencies for the first clock signal CLK1. The first clock signal CLK1 may not include clock masking periods, and only the second clock signal CLK2 may include clock masking periods.

[0174] This disclosure allows for the driving of segmented frame blocks at independent data refresh rates based on video content. It can mask the scan clock at desired timing to skip GIP output, thus enabling the driving of frame blocks at different data refresh rates. The scan clock masking method of this disclosure allows for the segmentation of frequency regions from high to low relative to the scan start position. Because image data updates cease in the low-frequency region, power consumption can be reduced proportionally. This disclosure allows for the independent driving of multiple frame regions based on video content to achieve energy savings.

[0175] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0176] Although this disclosure has been specifically shown and described with reference to its exemplary embodiments, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the technical concept and scope of this disclosure as defined by the appended claims.

Claims

1. A display device, the display device comprising: The display panel includes a first screen block and a second screen block; A first gating drive circuit is configured to provide a scan output to a first gating line of the first screen block; as well as A second gating drive circuit is configured to provide scan output to a second gating line of the second screen block. The first image block includes a first high-frequency region and a first low-frequency region. In the first high-frequency region, first image data is updated at a first data refresh rate. In the first low-frequency region, second image data is updated at a second data refresh rate lower than the first data refresh rate. The second image block includes a second high-frequency region and a second low-frequency region. In the second high-frequency region, the third image data is updated at a third data refresh rate. In the second low-frequency region, the fourth image data is updated at a fourth data refresh rate that is lower than the third data refresh rate.

2. The display device according to claim 1, wherein, In the same frame, The scan output timing corresponding to the gating line of the first high-frequency region is earlier than the scan output timing corresponding to the gating line of the first low-frequency region, and The scan output timing corresponding to the gating line of the second high-frequency region is earlier than the scan output timing corresponding to the gating line of the second low-frequency region.

3. The display device according to claim 2, wherein, During the scheduled time, The number of scan output masks on the gating line in the first low-frequency region is greater than the number of scan output masks on the gating line in the first high-frequency region, and The number of scan output masks on the gating line in the second low-frequency region is greater than the number of scan output masks on the gating line in the second high-frequency region.

4. The display device according to claim 1, wherein, The first gating drive circuit includes: The (4k-3)th gating stage is configured to generate a scan output corresponding to the first odd clock, where k is a positive integer; The (4k-2)th gating stage is configured to generate a scan output corresponding to a second odd clock having a phase different from that of the first odd clock. The (4k-1)th gating stage is configured to generate a scan output corresponding to a first even clock having the same phase as the first odd clock; and The 4kth gating stage is configured to generate a scan output corresponding to a second even clock having the same phase as the second odd clock. Wherein, at least one of the first odd clock, the first even clock, the second odd clock, and the second even clock has a clock masking period in at least one predetermined frame.

5. The display device according to claim 4, further comprising a plurality of first carry transfer switches that are enabled only in the forward carry shift drive. in, Each of the plurality of first carry transfer switches: Connect the scan output of the (4k-3)th gating stage to the positive carry input of the (4k-2)th gating stage. Connect the scan output of the (4k-2)th gating stage to the positive carry input of the (4k-1)th gating stage, or Connect between the scan output of the (4k-1)th gating stage and the positive carry input of the 4kth gating stage.

6. The display device according to claim 4, further comprising a plurality of second carry transfer switches enabled only in the reverse carry shift drive. in, Each of the plurality of second carry transfer switches: Connect the scan output of the 4kth gating stage and the inverse carry input of the (4k-1)th gating stage. Connect between the scan output of the (4k-1)th gating stage and the reverse carry input of the (4k-2)th gating stage, or Connect between the scan output of the (4k-2)th gating stage and the reverse carry input of the (4k-3)th gating stage.

7. The display device according to claim 1, wherein, The second gating drive circuit includes: The (4k-3)th gating stage is configured to generate a scan output corresponding to the first odd clock, where k is a positive integer; The (4k-2)th gating stage is configured to generate a scan output corresponding to a second odd clock having a phase later than that of the first odd clock. The (4k-1)th gating stage is configured to generate a scan output corresponding to a first even clock having the same phase as the first odd clock; and The 4kth gating stage is configured to generate a scan output corresponding to a second even clock having the same phase as the second odd clock. Wherein, at least one of the first odd clock, the first even clock, the second odd clock, and the second even clock has a clock masking period in at least one predetermined frame.

8. The display device according to claim 7, further comprising a plurality of first carry transfer switches enabled only in forward carry shift drive. in, Each of the plurality of first carry transfer switches: Connect the scan output of the (4k-3)th gating stage to the positive carry input of the (4k-2)th gating stage. Connect the scan output of the (4k-2)th gating stage to the positive carry input of the (4k-1)th gating stage, or Connect between the scan output of the (4k-1)th gating stage and the positive carry input of the 4kth gating stage.

9. The display device according to claim 7, further comprising a plurality of second carry transfer switches enabled only in the reverse carry shift drive. in, Each of the plurality of second carry transfer switches: Connect the scan output of the 4kth gating stage and the inverse carry input of the (4k-1)th gating stage. Connect between the scan output of the (4k-1)th gating stage and the reverse carry input of the (4k-2)th gating stage, or Connect between the scan output of the (4k-2)th gating stage and the reverse carry input of the (4k-3)th gating stage.

10. The display device according to claim 1, further comprising a clock masking control circuit, the clock masking control circuit being configured to generate, based on first image data to be input to the first screen block, a first control signal corresponding to the scan output masking timing of the first high-frequency region and a second control signal corresponding to the scan output masking timing of the first low-frequency region, and based on second image data to be input to the second screen block, to generate a third control signal corresponding to the scan output masking timing of the second high-frequency region and a fourth control signal corresponding to the scan output masking timing of the second low-frequency region.

11. The display device according to claim 1, wherein, The first gate line of the first screen block and the second gate line of the second screen block are electrically disconnected from each other.

12. The display device according to claim 1, further comprising: A first data driving circuit is configured to provide first image data to a first data line of the first screen block. as well as A second data driving circuit is configured to provide second image data to a second data line of the second screen block. The first data line and the second data line are electrically disconnected from each other.

13. The display device according to claim 1, wherein, The first frame block and the second frame block are in contact with each other and there is a boundary between the first frame block and the second frame block.

14. A display device, the display device comprising: The display panel includes a first screen block and a second screen block; A first gating drive circuit is configured to provide a scan output to a first gating line of the first screen block; as well as A second gating drive circuit is configured to provide scan output to a second gating line of the second screen block. The first screen block and the second screen block are driven by the first gating drive circuit and the second gating drive circuit at independent data refresh rates.

15. A driving method for a display device, the display device comprising a first screen block and a second screen block, the driving method comprising the following steps: Provide scan output to the first gate line of the first screen block; as well as Provide scan output to the second gate line of the second screen block. The first image block includes a first high-frequency region and a first low-frequency region. In the first high-frequency region, first image data is updated at a first data refresh rate. In the first low-frequency region, second image data is updated at a second data refresh rate lower than the first data refresh rate. The second image block includes a second high-frequency region and a second low-frequency region. In the second high-frequency region, the third image data is updated at a third data refresh rate. In the second low-frequency region, the fourth image data is updated at a fourth data refresh rate that is lower than the third data refresh rate.

16. The driving method according to claim 15, wherein, In the same frame, The scan output timing corresponding to the gating line of the first high-frequency region is earlier than the scan output timing corresponding to the gating line of the first low-frequency region, and The scan output timing corresponding to the gating line of the second high-frequency region is earlier than the scan output timing corresponding to the gating line of the second low-frequency region.

17. The driving method according to claim 16, wherein, During the scheduled time, The number of scan output masks on the gating line in the first low-frequency region is greater than the number of scan output masks on the gating line in the first high-frequency region, and The number of scan output masks on the gating line in the second low-frequency region is greater than the number of scan output masks on the gating line in the second high-frequency region.

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