Data caching circuit and chip

By using a shift register chain to replace the traditional FIFO memory, the circuit control logic is simplified, the problem of high control logic complexity in the prior art is solved, resource utilization and operating frequency are improved, and the probability of design errors is reduced.

CN122090897APending Publication Date: 2026-05-26OPEN SECURITY RES INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
OPEN SECURITY RES INC
Filing Date
2026-01-13
Publication Date
2026-05-26

AI Technical Summary

Technical Problem

Existing FIFO memories have high control logic complexity in data processing circuits, and complex read/write pointer comparison and address decoding logic, resulting in high design difficulty, low resource utilization, and long timing paths, which limits the operating frequency.

Method used

A shift register chain-based FIFO is used instead of the traditional read-write pointer-based FIFO memory. The empty/full state of the shift register chain is determined by the count value, simplifying the circuit control logic and avoiding complex read-write pointer comparison and address decoding logic.

Benefits of technology

It reduces the probability of circuit design errors, simplifies code implementation, improves resource utilization and operating frequency, reduces chip area, and ensures data read/write speed and timing stability.

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Abstract

This application discloses a data caching circuit and chip. The data caching circuit is configured in a memory controller, which is connected to both a memory and a processing unit. The data caching circuit includes a shift register chain. The data caching circuit determines a count value based on a write enable signal generated by the memory controller and a read enable signal generated by the processing unit. The count value indicates the fullness or emptiness of the shift register chain. When the write enable signal is valid and the count value indicates that the shift register chain is not full, the circuit reads first algorithm data from the memory and writes the first algorithm data into the shift register chain in response to a data read instruction sent by the processing unit. When the read enable signal is valid and the count value indicates that the shift register chain is not empty, the circuit determines a target shift register in the shift register chain based on the count value and outputs the target algorithm data in the target shift register to the processing unit. This application can reduce the complexity of the circuit control logic.
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