Semiconductor memory devices and their operation methods

Abstract

This application relates to a semiconductor memory device and a method of operating the same. A semiconductor memory device and a method of operating the semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory blocks; peripheral circuitry configured to perform programming, reading, or erasing operations on the plurality of memory blocks; and control logic configured to set the level of a drain select line operating voltage or a source select line operating voltage corresponding to each memory block based on the number of erase write (EW) cycles or the number of read operations performed on each memory block, and to control the peripheral circuitry to perform programming, reading, or erasing operations based on the set drain select line operating voltage or the set source select line operating voltage.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to electronic devices, and more specifically, to a semiconductor memory device and a method of operating the semiconductor memory device. Background Technology

[0002] A storage device is a device that stores data under the control of a host device such as a computer, smartphone, or smart tablet. Depending on the device used to store data, a storage device includes devices that store data on a disk (e.g., a hard disk drive (HDD)) and devices that store data in semiconductor memory (especially non-volatile memory) (e.g., solid-state drives (SSDs) and memory cards).

[0003] Storage devices may include memory devices for storing data and memory controllers for controlling the memory devices. Memory devices may be volatile or non-volatile memory. Non-volatile memory includes read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Summary of the Invention

[0004] Various embodiments of this disclosure relate to a semiconductor memory device capable of adjusting the operating voltage to improve reliability by predicting changes in the threshold voltage of a selected transistor, and a method of manufacturing the semiconductor memory device.

[0005] According to embodiments of this disclosure, a semiconductor memory device may include: a memory cell array including a plurality of memory blocks; peripheral circuitry configured to perform programming, reading, or erasing operations on the plurality of memory blocks; and control logic configured to set the level of a drain select line operating voltage or a source select line operating voltage corresponding to each memory block based on the number of erase write (EW) cycles or the number of read operations for each memory block, and to control the peripheral circuitry to perform programming, reading, or erasing operations based on the set drain select line operating voltage or the set source select line operating voltage.

[0006] According to embodiments of this disclosure, a method of operating a semiconductor memory device may include the following steps: receiving a command corresponding to a selected memory block among a plurality of memory blocks; checking the number of erase write (EW) cycles or the number of read operations of the selected memory block; setting a drain select line operating voltage or a source select line operating voltage of the selected memory block based on the number of EW cycles or the number of read operations of the selected memory block; and performing a programming operation, a read operation, or an erase operation corresponding to the command by using the set drain select line operating voltage or source select line operating voltage.

[0007] According to embodiments of the present disclosure, a semiconductor memory device may include: a memory cell array including a plurality of memory blocks; peripheral circuitry configured to perform programming operations, read operations, erase operations, or select transistor monitoring operations on the plurality of memory blocks; and control logic configured to control the peripheral circuitry to periodically perform select transistor monitoring operations on each memory block, and to set the level of the drain select line operating voltage or the source select line operating voltage for programming operations, read operations, or erase operations based on the number of failure bits corresponding to each memory block obtained as a result of the select transistor monitoring operations.

[0008] According to embodiments of the present disclosure, a method of operating a semiconductor memory device may include the following steps: performing a first selection transistor monitoring operation on a selected memory block among a plurality of memory blocks; based on the result of the first selection transistor monitoring operation, detecting the number of selection transistors among the drain selection transistors and source selection transistors included in the selected memory block whose threshold voltages are greater than a first monitoring read voltage, so as to count a first number of failure bits; and setting a drain selection line operating voltage or a source selection line operating voltage corresponding to the selected memory block based on the counted number of first failure bits. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating a data processing system including a semiconductor memory device according to an embodiment of the present disclosure;

[0010] Figure 2 This is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure;

[0011] Figure 3 It is shown Figure 2 A diagram illustrating the implementation of the control logic;

[0012] Figure 4 It is shown Figure 2 A graph of the storage blocks;

[0013] Figure 5 This is a diagram illustrating an implementation of a three-dimensional storage block;

[0014] Figure 6 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure;

[0015] Figure 7 This is a diagram illustrating a method for setting the drain select line operating voltage or the source select line operating voltage based on the number of EW cycles or the number of read operations according to an embodiment of this disclosure.

[0016] Figure 8 It is shown Figure 2 A diagram of another implementation of the control logic;

[0017] Figure 9 This is a flowchart illustrating a method of operating a semiconductor memory device according to another embodiment of the present disclosure;

[0018] Figure 10 This is a threshold voltage distribution diagram illustrating a selective transistor monitoring operation method according to an embodiment of the present disclosure;

[0019] Figure 11 This is a diagram illustrating a method for setting the drain select line operating voltage or the source select line operating voltage based on the number of failure bits according to an embodiment of the present disclosure.

[0020] Figure 12 This is a threshold voltage distribution diagram illustrating another selective transistor monitoring operation method according to an embodiment of the present disclosure;

[0021] Figure 13 This is a diagram illustrating a method for setting the drain select line operating voltage or the source select line operating voltage based on the number of failure bits according to an embodiment of the present disclosure; and

[0022] Figure 14 This is a block diagram illustrating the configuration of a storage device according to another embodiment of the present disclosure. Detailed Implementation

[0023] The specific structural or functional descriptions disclosed herein are merely illustrative for describing implementations based on the concepts of this disclosure. Implementations based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the specific implementations set forth herein.

[0024] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, so that those skilled in the art can realize the technical spirit of the present disclosure.

[0025] Figure 1 This is a block diagram illustrating a data processing system 1000 including a semiconductor memory device 100 according to an embodiment of the present disclosure.

[0026] Reference Figure 1 The data processing system 1000 may include a host 1300 and a storage device. The storage device may include a memory device 1100 and a controller 1200. The memory device 1100 may include a plurality of semiconductor memory devices 100. The semiconductor memory devices 100 may be grouped into n memory device groups, where n is a natural number greater than 1. According to an embodiment, the controller 1200, the memory device 1100, and the host 1300 may be configured as a single device or separate devices.

[0027] exist Figure 1 In the diagram, n memory device groups are shown communicating with controller 1200 via first channel CH1 to nth channel CHn, respectively. Individual semiconductor memory devices 100 will be described later. Figure 2 describe.

[0028] Each of the n memory device groups is configured to communicate with controller 1200 via a common channel. Controller 1200 is configured to control the semiconductor memory device 100 of memory device 1100 via channels CH1 to CHn.

[0029] Controller 1200 is coupled between host 1300 and memory device 1100. Controller 1200 is configured to access memory device 1100 in response to requests from host 1300. For example, controller 1200 is configured to control read, write, erase, and background operations of memory device 1100 in response to a host command Host_CMD received from host 1300. In a write operation, host 1300 may send data and address along with the host command Host_CMD; in a read operation, address may be sent along with the host command Host_CMD. Controller 1200 is configured to provide an interface between memory device 1100 and host 1300. Controller 1200 is configured to drive firmware for controlling memory device 1100.

[0030] The host 1300 may include portable electronic devices such as computers, PDAs, PMPs, MP3 players, cameras, camcorders, and mobile phones. The host 1300 can use the host command Host_CMD to request write operations, read operations, erase operations, etc., from the storage device. The host 1300 can send the host command Host_CMD corresponding to the write command, data, and address to the controller 1200 for write operations on the storage device 1100, and can send the host command Host_CMD corresponding to the read command and address to the controller 1200 for read operations. The address can be a logical address.

[0031] The controller 1200 and the memory device 1100 may be integrated into a single semiconductor device. In one embodiment, the controller 1200 and the memory device 1100 may be integrated into a single semiconductor device to form a memory card. For example, the controller 1200 and the memory device 1100 may be integrated into a single semiconductor device to form a memory card, such as a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash memory card (CF), a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), and a universal flash memory device (UFS).

[0032] The controller 1200 and the memory device 1100 may be integrated into a semiconductor device to form a semiconductor drive (SSD). The semiconductor drive SSD may include the semiconductor memory device 100 configured to store data therein.

[0033] In another embodiment, the data processing system 1000 may be provided as one of the components of various electronic devices (such as computers, UMPCs (Ultra-Mobile PCs), workstations, netbooks, PDAs (Personal Digital Assistants), portable computers, network tablets, wireless phones, mobile phones, smartphones, e-books, PMPs (Portable Multimedia Players), portable game consoles, navigation devices, black boxes, digital cameras, 3D televisions, digital audio recorders, digital audio players, digital image recorders, digital image players, digital video recorders, digital video players, devices capable of transmitting and receiving information in a wireless environment, various electronic devices constituting a home network, various electronic devices constituting a computer network, various electronic devices constituting a remote information network, RFID devices), or as one of the components constituting a computing system.

[0034] In implementations, the storage device or memory device 1100 can be implemented in various forms of packaging. For example, the storage device or memory device 1100 can be packaged and mounted in ways such as PoP (PoP), Ball Grid Array (BGA), Chip Scale Package (CSP), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Waffle Die Package, Wafer Form Die, Chip on Board (COB), Ceramic Dual In-line Package (CERDIP), Metric Quad Flat Package (MQFP), Thin Quad Flat Package (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System Package (SIP), Multi-Chip Package (MCP), Wafer Scale Fabrication Package (WFP), Wafer Scale Processed Stacked Package (WSP), etc.

[0035] Figure 2 This is a diagram illustrating a semiconductor memory device 100 according to an embodiment of the present disclosure.

[0036] Reference Figure 2 The semiconductor memory device 100 may include a memory cell array 10 for storing data. The semiconductor memory device 100 may include peripheral circuitry 200 configured to perform programming operations to store data in the memory cell array 10, reading operations to output the stored data, and erasing operations to erase the stored data. Figure 1 The controller 1200 controls the control logic 300 of the peripheral circuit 200.

[0037] The memory cell array 10 may include memory blocks MB1 to MBk 11, where k is a natural number greater than 1. Local lines LL and bit lines BL1 to BLm may be connected to each of the memory blocks MB1 to MBk 11, where m is a natural number greater than 1. For example, the local line LL may include a first select line, a second select line, and multiple word lines disposed between the first and second select lines. Additionally, the local line LL may include dummy lines disposed between the first select line and the word line, and between the second select line and the word line. The first select line may be a source select line, and the second select line may be a drain select line. For example, the local line LL may include a word line, a drain select line, a source select line, and a source line SL. For example, the local line LL may also include dummy lines. For example, the local line LL may also include pipelines. The local lines LL may be individually connected to memory blocks MB1 to MBk 11, and the bit lines BL1 to BLm may be collectively connected to memory blocks MB1 to MBk 11. The memory blocks MB1 to MBk 11 may have a two-dimensional or three-dimensional structure. For example, in a storage block 11 with a two-dimensional structure, memory cells can be arranged in a direction parallel to the substrate. For example, in a storage block 11 with a three-dimensional structure, memory cells can be stacked in a direction perpendicular to the substrate.

[0038] The peripheral circuitry 200 can be configured to perform programming, reading, and erasing operations on the selected memory block 11 under the control of the control logic 300. Additionally, the peripheral circuitry 200 can be configured to perform monitoring operations on the drain-select transistors and source-select transistors included in the selected memory block 11 under the control of the control logic 300. For example, the peripheral circuitry 200 may include a voltage generation circuitry 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input / output circuitry 250, a pass / fail determination unit 260, and a source line driver 270.

[0039] The voltage generation circuit 210 can generate various operating voltages Vop for monitoring programming, reading, erasing operations, and selecting transistors in response to the operation signal OP_CMD. Additionally, the voltage generation circuit 210 can generate source select line operating voltages applied to the source select line of the selected memory block and drain select line operating voltages applied to the drain select line, both in response to the operation signal OP_CMD. The voltage generation circuit 210 can adjust the levels of the drain select line operating voltage and the source select line operating voltage according to the control logic 300. Furthermore, the voltage generation circuit 210 can selectively discharge the local line LL in response to the operation signal OP_CMD.

[0040] For example, voltage generation circuit 210 can generate programming voltage, verification voltage, pass voltage, monitoring read voltage, drain select line operation voltage and source select line operation voltage under the control of control logic 300.

[0041] The row decoder 220 can send an operating voltage Vop to the local line LL connected to the selected memory block 11 in response to the control signal AD_signals. For example, the row decoder 220 can selectively apply the operating voltage (e.g., programming voltage, verification voltage, pass voltage, monitoring read voltage, etc.) generated by the voltage generation circuit 210 to the word lines in the local line LL in response to the control signal AD_signals. In addition, the row decoder 220 can apply the drain select line operating voltage and the source select line operating voltage generated by the voltage generation circuit 210 to the drain select line and the source select line in the local line LL in response to the control signal AD_signals.

[0042] The line decoder 220 can apply the programming voltage generated by the voltage generation circuit 210 to the selected word line in the local line LL in response to the control signal AD_signals during the programming voltage application operation, and can also apply the pass voltage generated by the voltage generation circuit 210 to the remaining unselected word lines. Additionally, during the read operation, the line decoder 220 can apply the read voltage generated by the voltage generation circuit 210 to the selected word line in the local line LL in response to the control signal AD_signals, and apply the pass voltage generated by the voltage generation circuit 210 to the remaining unselected word lines. Furthermore, during the monitoring operation of the selection transistor, the line decoder 220 can apply the monitoring read voltage generated by the voltage generation circuit 210 to the selected drain select line or selected source select line in the local line LL in response to the control signal AD_signals, and apply the pass voltage generated by the voltage generation circuit 210 to the word line and the unselected drain select line or unselected source select line.

[0043] Page buffer group 230 may include multiple page buffers PB1 to PBm 231 connected to bit lines BL1 to BLm. Page buffers PB1 to PBm 231 may operate in response to the page buffer control signal PBSIGNALS. For example, page buffers PB1 to PBm 231 may temporarily store data to be programmed during a programming operation, or may sense the voltage or current of bit lines BL1 to BLm during a read operation, verification operation, or monitoring operation on a selected transistor. Each of page buffers PB1 to PBm 231 may detect a failure bit by sensing the voltage or current of bit lines BL1 to BLm during a monitoring operation on a selected transistor, and may output failure bit information FB to control logic 300.

[0044] The column decoder 240 can transfer data between the input / output circuitry 250 and the page buffer group 230 in response to the column address CADD. For example, the column decoder 240 can exchange data with the page buffer 231 via the data line DL or with the input / output circuitry 250 via the column line CL.

[0045] The input / output circuit 250 can output from... Figure 1 The controller 1200 receives internal commands CMD and addresses ADD and sends them to the control logic 300, or can exchange data DATA with the column decoder 240.

[0046] During a read operation, the pass / fail determination unit 260 can generate a reference current in response to the enable bit VRY_BIT<#>, compare the sensed voltage VPB received from the page buffer group 230 with the reference voltage generated by the reference current, and output a pass signal PASS or a failure signal FAIL.

[0047] The source line driver 270 is connected to the memory cells included in the memory cell array 10 via the source line SL, and can control the voltage applied to the source line SL. The source line driver 270 can receive the source line control signal CTRL_SL from the control logic 300, and can control the source line voltage applied to the source line SL based on the source line control signal CTRL_SL.

[0048] Control logic 300 can control peripheral circuitry 200 by outputting operation signal OP_CMD, control signal AD_signals, page buffer control signal PBSIGNALS, and enable bit VRY_BIT<#> in response to internal command CMD and address ADD. Additionally, control logic 300 can determine whether the verification operation passed or failed by responding to the PASS signal or the FAIL signal.

[0049] In an implementation, control logic 300 may count the number of erase write (EW) cycles or read operations of the selected memory block, and may adjust and set the level of the drain select line operating voltage or source select line operating voltage applied to the drain select line or source select line of the selected memory block based on the counted number of EW cycles or the counted number of read operations. For example, when the counted number of EW cycles or read operations of the selected memory block exceeds a set number (i.e., a reference number), control logic 300 may control voltage generation circuit 210 to raise and reset the level of the drain select line operating voltage or source select line operating voltage applied to the drain select line or source select line of the selected memory block, and generate a reset drain select line operating voltage or reset source select line operating voltage during various operations of the selected memory block (e.g., programming operations, read operations, or erase operations).

[0050] In another embodiment, control logic 300 can control peripheral circuitry 200 to perform monitoring operations on the selection transistors included in each of the memory blocks MB1 to MBk 11 at regular intervals. It can receive failure bits FB obtained as a result of the monitoring operation on the selected transistors, count the received failure bits FB, and adjust and set the level of the drain select line operating voltage or source select line operating voltage applied to the drain select line or source select line of the selected memory block based on the number of counted failure bits FB. For example, when the number of failure bits FB obtained as a result of the monitoring operation on the selection transistors included in the selected memory block is greater than a set number of bits (i.e., a reference number), control logic 300 can control voltage generation circuitry 210 to raise and reset the level of the drain select line operating voltage or source select line operating voltage applied to the drain select line or source select line of the selected memory block, and can generate a reset drain select line operating voltage or source select line operating voltage during various operations of the selected memory block (e.g., programming operation, read operation, or erase operation).

[0051] Figure 3 It is shown Figure 2 A diagram illustrating the implementation of the control logic 300.

[0052] Reference Figure 3 The control logic 300 may include a counter 310 and a selection line operating voltage setting circuit 320.

[0053] Counter 310 can Figure 2The counter 310 counts and stores the number of EW cycles or read operations for each of the storage blocks MB1 to MBk 11. Additionally, the counter 310 can output a first count signal E / W_Count or a second count signal Read_Count corresponding to each of the storage blocks MB1 to MBk 11 based on the stored number of EW cycles or read operations. The first count signal E / W_Count corresponds to the counted number of EW cycles for the storage block, and the second count signal Read_Count corresponds to the calculated number of read operations for the storage block.

[0054] The select line operating voltage setting circuit 320 can receive a first count signal E / W_Count or a second count signal Read_Count corresponding to each of the memory blocks MB1 to MBk 11 from the counter 310, and can set the drain select line operating voltage or source select line operating voltage corresponding to each of the memory blocks MB1 to MBk 11 based on the received first count signal E / W_Count and the received second count signal Read_Count.

[0055] For example, the select line operation voltage setting circuit 320 can determine the number of EW cycles or the number of read operations of the memory block based on the received first count signal E / W_Count or the received second count signal Read_Count, and can set the drain select line operation voltage or source select line operation voltage corresponding to the memory block by comparing the determined number of EW cycles or the determined number of read operations with the determined set number of memory blocks. For example, when it is determined that the number of EW cycles or the number of read operations of the memory block is equal to or less than the first set number, the select line operation voltage setting circuit 320 can maintain the drain select line operation voltage or source select line operation voltage at the initial voltage level, and when the number of EW cycles or the number of read operations of the memory block exceeds the first set number and is determined to be equal to or less than the second set number greater than the first set number, a new drain select line operation power or a new source select line operation power can be set by increasing the first offset voltage at the initial voltage level. Additionally, when the number of EW cycles or read operations of the memory block exceeds the second set number, the selection line operation voltage setting circuit 320 can set a new drain selection line operation voltage or source selection line operation voltage that is increased by a second offset voltage greater than the first offset voltage from the initial voltage level.

[0056] The select line operating voltage setting circuit 320 can perform the operation of setting the drain select line operating voltage or the source select line operating voltage for each of the memory blocks MB1 to MBk 11.

[0057] The line selection voltage setting circuit 320 can output line selection voltage information DSL_SSL_inf, which includes information about the level of the set drain-select line selection voltage or the level of the set source-select line selection voltage. The line selection voltage information DSL_SSL_inf can be sent to... Figure 2 The voltage generation circuit 210 can adjust the levels of the drain select line operating voltage and the source select line operating voltage based on the select line operating voltage information DSL_SSL_inf.

[0058] Figure 4 It is shown Figure 2 The diagram of storage block 11.

[0059] Reference Figure 4 Multiple word lines WL1 to WL16, arranged parallel to each other between the first and second select lines, can be connected to memory block 11. The first select line can be the source select line SSL, and the second select line can be the drain select line DSL. More specifically, memory block 11 may include multiple memory strings ST connected between bit lines BL1 to BLm and the source line SL. Bit lines BL1 to BLm can be individually connected to memory strings ST, and the source line SL can be collectively connected to memory strings ST. Since memory strings ST can be configured to be identical to each other, the memory string ST connected to the first bit line BL1 will be described in detail as an example.

[0060] A memory string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells F1 to F16, and a drain selection transistor DST. A memory string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and may include more than the number of memory cells F1 to F16 shown in the figure.

[0061] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST included in different memory strings ST can be connected to the source select line SSL, the gate of the drain select transistor DST can be connected to the drain select line DSL, and the gate of memory cells F1 to F16 can be connected to word lines WL1 to WL16. A group of memory cells included in different memory strings ST that are connected to the same word line can be referred to as a physical page PPG. Therefore, memory block 11 can include as many physical pages PPG as word lines WL1 to WL16.

[0062] A memory cell can store 1 bit of data; this method is often referred to as the Single-Level Cell (SLC) method. In these cases, a physical page (PPG) can store one logical page (LPG) of data. A logical page (LPG) of data can include the number of data bits equal to the number of cells included in a physical page (PPG). Alternatively, a memory cell can store two or more bits of data. This method is often referred to as the Multi-Level Cell (MLC) method. In these cases, a physical page (PPG) can store two or more logical page (LPG) data.

[0063] Figure 5 This is a diagram illustrating an implementation of a three-dimensional storage block.

[0064] Reference Figure 5 The memory cell array 10 may include memory blocks MB1 to MBk 11. Memory block 11 may include multiple memory strings ST11 to ST1m and ST21 to ST2m. Each of the memory strings ST11 to ST1m and ST21 to ST2m may extend in the vertical direction (Z direction). In memory block 11, m memory strings may be arranged in the row direction (X direction). Although for the sake of description, Figure 5 Two memory strings are shown arranged in the column direction (Y direction), but three or more memory strings may be arranged in the column direction (Y direction).

[0065] Each of the memory strings ST11 to ST1m and ST21 to ST2m may include at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, and at least one drain selection transistor DST.

[0066] The source select transistors SST of each memory string ST can be connected between the source line SL and memory cells MC1 to MCn. The source select transistors SST of memory strings ST arranged in the same row can be connected to the same source select line SSL. The source select transistors SST of memory strings ST11 to ST1m arranged in the first row can be connected to the first source select line SSL1. The source select transistors SST of memory strings ST21 to ST2m arranged in the second row can be connected to the second source select line SSL2. In another embodiment, the source select transistors SST of memory strings ST11 to ST1m and ST21 to ST2m can be connected to a single source select line.

[0067] The first memory cells MC1 to the nth memory cell MCn of each memory string ST can be connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the first memory cells MC1 to the nth memory cell MCn can be connected to the first word line WL1 to the nth word line WLn, respectively.

[0068] In this implementation, at least one of the first memory cell MC1 to the nth memory cell MCn can be used as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the memory string ST can be stably controlled. Therefore, the reliability of the data stored in memory block 11 can be improved.

[0069] The drain select transistors (DSTs) of each memory string ST can be connected between the bit line and memory cells MC1 to MCn. The drain select transistors (DSTs) of memory strings ST arranged in the row direction can be connected to drain select lines extending in the row direction. The drain select transistors (DSTs) of memory strings ST11 to ST1m in the first row can be connected to the first drain select line DSL1. The drain select transistors (DSTs) of memory strings ST21 to ST2m in the second row can be connected to the second drain select line DSL.

[0070] Figure 6 This is a flowchart illustrating a method of operating a semiconductor memory device 100 according to an embodiment of the present disclosure.

[0071] Figure 7 This is a diagram illustrating a method for setting the drain select line operating voltage or the source select line operating voltage based on the number of EW cycles or the number of read operations according to an embodiment of this disclosure.

[0072] The following will refer to Figures 2 to 7 A method for operating a semiconductor memory device 100 according to an embodiment of the present disclosure is described.

[0073] In operation S610, the semiconductor memory device 100 may receive a command CMD for a selected memory block (e.g., memory block MB1). In this embodiment, the command can be executed from outside the semiconductor memory device 100. Figure 1 The controller 1200 receives the command CMD and address ADD corresponding to the programming operation, read operation, or erase operation.

[0074] In operation S620, the number of EW cycles or the number of read operations of the selected storage block MB1 can be checked.

[0075] For example, counter 310 of control logic 300 can output a first count signal E / W_Count or a second count signal Read_Count corresponding to the number of EW cycles or read operations of the selected memory block MB1. Selection line operation voltage setting circuit 320 of control logic 300 can check the number of EW cycles or read operations of the selected memory block MB1 based on the received first count signal E / W_Count or second count signal Read_Count.

[0076] In operation S630, the number of EW cycles or the number of read operations of the selected storage block MB1 can be compared with the set number.

[0077] For example, the selection line operation voltage setting circuit 320 can compare the number of EW cycles or the number of read operations of the selected memory block MB1 with a set number, and can determine whether the number of EW cycles or the number of read operations of the selected memory block MB1 is equal to or less than the set number, or whether the number of EW cycles and the number of read operations of the selected memory block MB1 exceeds the set number.

[0078] In operation S630, when it is determined that the number of EW cycles or read operations of the selected memory block MB1 exceeds a set number (if so), in operation S640, the selection line operation voltage setting circuit 320 can reset the drain selection line operation voltage or source selection line operation voltage corresponding to the selected memory block MB1. For example, the selection line operation voltage setting circuit 320 can set a new drain selection line operation voltage or source selection line operation voltage that is increased by an offset voltage relative to the initial voltage level.

[0079] In operation S630, when the number of EW cycles or the number of read operations of the selected memory block MB1 is equal to or less than the set number (if not), the selection line operation voltage setting circuit 320 can maintain the initially set drain selection line operation voltage or source selection line operation voltage without resetting the drain selection line operation voltage or source selection line operation voltage.

[0080] Reference Figure 7 When the number of EW cycles or read operations α of the selected memory block is equal to or less than the first set number (i.e., the first reference number) A, the drain selection line operating voltage V can be set. DSL Or source selection line operating voltage V SSL To maintain the initial voltage level int_V.

[0081] Additionally, when the number of EW cycles or read operations α of the selected memory block exceeds a first set number A and is equal to or less than a second set number (i.e., the second reference number) B, the drain select line operating voltage V can be reset by increasing a first offset voltage ΔV relative to the initial voltage level int_V. DSL Or source selection line operating voltage V SSL Additionally, when the number of EW cycles or read operations α of the selected memory block exceeds the second set number B, the drain select line operating voltage V can be reset by increasing the initial voltage level int_V by a second offset voltage 2ΔV. DSL Or source selection line operating voltage V SSL .

[0082] In operation S650, the peripheral circuit 200 can perform an operation corresponding to the command CMD on the selected memory block MB1 under the control of the control logic 300, namely, a read operation, a programming operation, or an erase operation.

[0083] The voltage generation circuit 210 can generate various operating voltages Vop for read, program, or erase operations in response to the operation signal OP_CMD, and can generate operating voltages by adjusting the levels of the drain select line operating voltage and the source select line operating voltage based on the select line operating voltage information DSL_SSL_inf generated by the select line operating voltage setting circuit 320. The line decoder 220 can send the operating voltage Vop to the local line LL connected to the selected memory block MB1 in response to the control signal AD_signals. For example, the line decoder 220 can apply the drain select line operating voltage and the source select line operating voltage generated by the voltage generation circuit 210 to the drain select line and the source select line of the selected memory block MB1 in response to the line decoder control signal AD_signal.

[0084] According to the embodiments of this disclosure described above, the drain select line operating voltage applied to the gate of the drain select transistor or the source select line operating voltage applied to the gate of the source select transistor can be adjusted based on the number of EW cycles or the number of read operations of the selected memory block. Therefore, even when the threshold voltage of the drain select transistor or the source select transistor increases due to the increase in the number of EW cycles or the number of read operations, the drain select transistor or the source select transistor can operate stably with the adjusted drain select line operating voltage or source select line operating voltage, thereby improving the reliability of the semiconductor memory device 100.

[0085] Figure 8 It is shown Figure 2 A diagram of another implementation of the control logic 300.

[0086] The control logic 300 may include a selection transistor monitoring and control circuit 330, a failure bit counter 340, and a selection line operating voltage setting circuit 350.

[0087] Selecting the transistor monitoring and control circuit 330 can generate and output the operation signal OP_CMD, the control signal AD_signals, the source line control signal CTRL_SL, and the page buffer control signal PBSIGNALS for control purposes. Figure 2The peripheral circuitry 200 performs monitoring operations on the selection transistors of each of the memory blocks MB1 to MBk11 at regular intervals. For example, the selection transistor monitoring control circuitry 330 can generate and output operation signals OP_CMD, control signals AD_signals, source line control signals CTRL_SL, and page buffer control signals PBSIGNALS in response to a time signal T that is enabled at regular intervals for control. Figure 2 The peripheral circuit 200 performs monitoring operations.

[0088] Monitoring the select transistors can be performed by scanning the threshold voltages of the drain and source select transistors included in the selected memory block to detect the operation of a drain or source select transistor whose threshold voltage is higher than the monitored read voltage level. Among the drain and source select transistors included in the selected memory block, the drain and source select transistors with threshold voltages higher than the monitored read voltage can each be detected as a failure bit (FB).

[0089] The failure bit counter 340 can receive failure bits FB as a result of monitoring the selection transistor of the peripheral circuit 200, count the received failure bits FB, and output the failure bit count signal FB_Count.

[0090] The select line operating voltage setting circuit 350 can receive the failure bit count signal FB_Count corresponding to each of the memory blocks MB1 to MBk 11 from the failure bit counter 340, and can set the drain select line operating voltage or source select line operating voltage corresponding to each of the memory blocks MB1 to MBk 11 based on the received failure bit count signal FB_Count.

[0091] For example, the selection line operating voltage setting circuit 350 can determine the number of failure bits of the memory block based on the received failure bit count signal FB_Count, and can set the drain selection line operating voltage or source selection line operating voltage corresponding to the memory block by comparing the determined number of failure bits of the memory block with a set number of bits. For example, when it is determined that the number of failure bits of the memory block is equal to or less than a first set number of bits, the selection line operating voltage setting circuit 350 can maintain the drain selection line operating voltage or source selection line operating voltage at the initial voltage level, and when it is determined that the number of failure bits of the memory block exceeds the first set number of bits and is equal to or less than a second set number of bits (which is greater than the first set number of bits), the selection line operating voltage setting circuit 350 can set a new drain selection line operating voltage or a new source selection line operating voltage that is increased by a first offset voltage at the initial voltage level. Additionally, when it is determined that the number of failed bits in the memory block exceeds the second set number of bits (which is greater than the first set number of bits), the select line operation voltage setting circuit 350 can set a new drain select line operation voltage or source select line operation voltage that is increased by a second offset voltage (which is greater than the first offset voltage) from the initial voltage level.

[0092] The select line operating voltage setting circuit 350 can perform the above-described operation of setting the drain select line operating voltage or the source select line operating voltage for each of the memory blocks MB1 to MBk 11.

[0093] The line selection voltage setting circuit 350 can output line selection voltage information DSL_SSL_inf, which includes information about the level of the set drain-select line selection voltage or the level of the set source-select line selection voltage. The line selection voltage information DSL_SSL_inf can be sent to... Figure 2 The voltage generation circuit 210 can adjust the levels of the drain select line operating voltage and the source select line operating voltage based on the select line operating voltage information DSL_SSL_inf.

[0094] Figure 9 This is a flowchart illustrating a method of operating a semiconductor memory device 100 according to another embodiment of the present disclosure.

[0095] Figure 10 This is a threshold voltage distribution diagram illustrating a selection transistor monitoring operation method according to an embodiment of the present disclosure.

[0096] Figure 11 This is a diagram illustrating a method for setting the drain select line operating voltage or the source select line operating voltage based on the number of failure bits according to an embodiment of the present disclosure.

[0097] The following will refer to Figures 2 to 5 as well as Figures 8 to 11 A method for operating a semiconductor memory device 100 according to another embodiment of the present disclosure is described.

[0098] In operation S910, the semiconductor memory device 100 can perform a selection transistor monitoring operation on each of the memory blocks MB1 to MBk11 at regular intervals.

[0099] For example, the selection transistor monitoring control circuit 330 can generate and output operation signals OP_CMD, control signals AD_signals, source line control signals CTRL_SL, and page buffer control signals PBSIGNALS in response to a time signal T that is enabled at regular intervals for control purposes. Figure 2 The peripheral circuit 200 performs monitoring operations.

[0100] The peripheral circuit 200 can perform a selection transistor monitoring operation on each of the memory blocks MB1 to MBk11 in response to the operation signal OP_CMD, the control signal AD_signals, the source line control signal CTRL_SL, and the page buffer control signal PBSIGNALS.

[0101] For example, voltage generation circuit 210 can generate a monitoring read voltage applied to a selected drain select line or a selected source select line, as well as a pass voltage applied to an unselected drain select line, an unselected source select line, and a word line.

[0102] The line decoder 220 can apply a monitoring read voltage to a selected drain select line or a selected source select line, and can apply a pass voltage to the remaining unselected drain select lines, unselected source select lines, and word lines.

[0103] During a specific period after the semiconductor memory device 100 is manufactured, the threshold voltage changes of the drain select transistor and the source select transistor can be relatively small. The activation of the time signal T can be prevented during the set initial period, so that select transistor monitoring can be skipped during the set initial period, and select transistor monitoring operations can be performed at regular intervals after the initial period.

[0104] In operation S920, each of the page buffers PB1 to PBm 231 can detect a failure bit FB. For example, each of the page buffers PB1 to PBm 231 can sense the voltage or current of bit lines BL1 to BLm during monitoring of the select transistor to detect a drain-select transistor or source-select transistor whose threshold voltage is higher than the monitored read voltage, in order to generate and output the failure bit FB. Figure 10The threshold voltage distributions of the drain-select transistor (DST) and source-select transistor (SST) shown in the diagram indicate that some drain-select transistors or source-select transistors with threshold voltages exceeding the normal range can be detected as failure bits (FB).

[0105] The failure bit counter 340 can receive failure bits FB as a result of monitoring the selection transistor of the peripheral circuit 200, and can count the received failure bits FB.

[0106] In operation S930, the selection line operation voltage setting circuit 350 can compare the counted number of failure bits with the set number of bits.

[0107] For example, the selection line operation voltage setting circuit 350 can compare the number of failure bits of each of the memory blocks MB1 to MBk 11 with the set number of bits, and can determine whether the number of failure bits of each of the memory blocks MB1 to MBk 11 is equal to or less than the set number of bits or exceeds the set number of bits.

[0108] In operation S930, when it is determined that the number of failure bits of the memory block exceeds the set number of bits (if so), in operation S940, the selection line operating voltage setting circuit 350 can reset the drain selection line operating voltage or source selection line operating voltage corresponding to the memory block. For example, the selection line operating voltage setting circuit 350 can set a new drain selection line operating voltage or source selection line operating voltage that is increased by an offset voltage relative to the initial voltage level.

[0109] In operation S930, when the number of failure bits of the memory block is equal to or less than the set number of bits (if not), the select line operating voltage setting circuit 350 can maintain the initially set drain select line operating voltage or source select line operating voltage without resetting the drain select line operating voltage or source select line operating voltage corresponding to the memory block.

[0110] Reference Figure 11 When the number of failure bits (FB) of the storage block is equal to or less than the first set number of bits (i.e., the first reference number) C, the drain select line operating voltage or the source select line operating voltage can be set to maintain the initial voltage level int_V.

[0111] Additionally, when the number of failure bits (FB) in a memory block exceeds a first set number of bits (C) and is equal to or less than a second set number of bits (i.e., the first reference number) (D), the drain select line operating voltage or the source select line operating voltage can be reset by increasing a first offset voltage (ΔV) relative to the initial voltage level (int_V). Furthermore, when the number of failure bits (FB) in a memory block exceeds the second set number of bits (D), the drain select line operating voltage (V) can be reset by increasing a second offset voltage (2ΔV) relative to the initial voltage level (int_V). DSL Or source selection line operating voltage.

[0112] The operation of setting the drain select line operating voltage or source select line operating voltage corresponding to each of the memory blocks MB1 to MBk11 can be performed sequentially.

[0113] According to another embodiment of this disclosure, the drain select line operating voltage applied to the gate of the drain select transistor or the source select line operating voltage applied to the gate of the source select transistor can be adjusted based on the number of failure bits in the memory block. Therefore, the drain select transistor or the source select transistor can operate stably, thereby improving the reliability of the semiconductor memory device 100.

[0114] Figure 12 This is a threshold voltage distribution diagram illustrating another selective transistor monitoring operation method according to an embodiment of the present disclosure.

[0115] Figure 13 This is a diagram illustrating a method for setting the drain select line operating voltage or the source select line operating voltage based on the number of failure bits according to an embodiment of the present disclosure.

[0116] Reference Figure 2 , Figure 8 , Figure 12 and Figure 13 The peripheral circuit 200 can use multiple monitoring read voltages (e.g., a first monitoring read voltage Level_A, a second monitoring read voltage Level_B greater than the first monitoring read voltage Level_A, and a third monitoring read voltage Level_C greater than the second monitoring read voltage Level_B) to sequentially perform the threshold voltage monitoring operation of the selection transistor.

[0117] For example, in a threshold voltage monitoring operation using a select transistor with a first monitoring read voltage Level_A, voltage generation circuit 210 can generate a first monitoring read voltage Level_A to be applied to a selected drain select line or a selected source select line, and a pass voltage to be applied to an unselected drain select line, an unselected source select line, and a word line.

[0118] The line decoder 220 can apply a first monitoring read voltage Level_A to the selected drain select line or the selected source select line, and can apply a pass voltage to the remaining unselected drain select line, unselected source select line, and word line.

[0119] Each of the page buffers PB1 to PBm 231 can detect the failed bit FB by sensing the voltage or current of bit lines BL1 to BLm during threshold voltage monitoring operation using the select transistor with the first monitoring read voltage Level_A.

[0120] Subsequently, during the threshold voltage monitoring operation using the selection transistor with the second monitoring read voltage Level_B, the voltage generation circuit 210 can generate the second monitoring read voltage Level_B, and the row decoder 220 can apply the second monitoring read voltage Level_B to a selected drain select line or a selected source select line. Each of the page buffers PB1 to PBm 231 can sense the voltage or current of bit lines BL1 to BLm during the threshold voltage monitoring operation using the selection transistor with the second monitoring read voltage Level_B to detect the failure bit FB.

[0121] Subsequently, during the threshold voltage monitoring operation using the selection transistor with the third monitoring read voltage Level_C, the voltage generation circuit 210 can generate the third monitoring read voltage Level_C, and the row decoder 220 can apply the third monitoring read voltage Level_C to the selected drain select line or the selected source select line. Each of the page buffers PB1 to PBm 231 can detect the failed bit FB by sensing the voltage or current of the bit lines BL1 to BLm during the threshold voltage monitoring operation using the selection transistor with the third monitoring read voltage Level_C.

[0122] The failure bit counter 340 can count the number of failure bits FB received during the threshold voltage monitoring operation of the selected transistor using the first monitoring read voltage Level_A, the number of failure bits FB received during the threshold voltage monitoring operation of the selected transistor using the second monitoring read voltage Level_B, and the number of failure bits FB received during the threshold voltage monitoring operation of the selected transistor using the third monitoring read voltage Level_C.

[0123] When the number of failed bits (FB) received and counted during the threshold voltage monitoring operation of the select transistor using the first monitoring read voltage Level_A is equal to or less than the set number of bits (i.e., the reference number) β, the select line operating voltage setting circuit 350 can maintain the drain select line operating voltage or the source select line operating voltage at the initial voltage level int_V. On the other hand, when the number of failed bits (FB) received and counted during the threshold voltage monitoring operation of the select transistor using the first monitoring read voltage Level_A exceeds the set number of bits β, the drain select line operating voltage or the source select line operating voltage is increased by a first voltage ΔV1 relative to the initial voltage level int_V to set a new drain select line operating voltage or source select line operating voltage.

[0124] Furthermore, when the number of failed bits (FB) received and counted during the threshold voltage monitoring operation of the selection transistor using the second monitoring read voltage Level_B is equal to or less than the set number of bits β, the selection line operation voltage setting circuit 350 can maintain the drain selection line operation voltage or the source selection line operation voltage at the initial voltage level int_V. On the other hand, when the number of failed bits (FB) received and counted during the threshold voltage monitoring operation of the selection transistor using the second monitoring read voltage Level_B exceeds the set number of bits β, the drain selection line operation voltage or the source selection line operation voltage increases relative to the initial voltage level int_V by a second voltage ΔV2 greater than the first voltage ΔV1, thereby setting a new drain selection line operation voltage or source selection line operation voltage.

[0125] Additionally, when the number of failed bits (FB) received and counted during the threshold voltage monitoring operation of the selection transistor using the third monitoring read voltage Level_C is equal to or less than the set number of bits β, the selection line operation voltage setting circuit 350 can maintain the drain selection line operation voltage or the source selection line operation voltage at the initial voltage level int_V. On the other hand, when the number of failed bits (FB) received and counted during the threshold voltage monitoring operation of the selection transistor using the third monitoring read voltage Level_C exceeds the set number of bits β, the drain selection line operation voltage or the source selection line operation voltage increases relative to the initial voltage level int_V by a third voltage ΔV3 greater than the second voltage ΔV2, to set a new drain selection line operation voltage or source selection line operation voltage.

[0126] Figure 14 This is a block diagram illustrating the configuration of a storage device 2000 according to another embodiment of the present disclosure.

[0127] Reference Figure 14 The storage device 2000 may include a semiconductor memory device 1100 and a controller 1200.

[0128] Semiconductor memory device 1100 can be used to store data information of various data types, such as text, graphics, software code, etc. Semiconductor memory device 1100 can be compared with reference to... Figure 2 The semiconductor memory devices described are the same. The structure and operation of semiconductor memory device 1100 are the same as those described above, therefore its detailed description will be omitted.

[0129] The controller 1200 can be coupled to the host and the memory device 1100, and can be configured to access the memory device 1100 in response to requests from the host. For example, the controller 1200 can be configured to control read operations, write operations, erase operations, and background operations of the memory device 1100.

[0130] The controller 1200 may include random access memory (RAM) 1210, central processing unit (CPU) 1220, host interface 1230, ECC circuit (ECC) 1240, memory interface 1250, etc.

[0131] RAM 1210 can be used as operating memory for CPU 1220, cache memory between memory device 1100 and host, buffer memory between memory device 1100 and host, etc. For reference, RAM 1210 can be replaced with static random access memory (SRAM), read-only memory (ROM), etc.

[0132] CPU 1220 can be configured to control the overall operation of controller 1200. For example, CPU 1220 can be configured to operate firmware (e.g., flash translation layer (FTL)) stored in RAM 1210.

[0133] The host interface 1230 can be configured to interface with a host. For example, the controller 1200 can communicate with the host via at least one of various communication standards or interfaces such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, and proprietary protocols.

[0134] ECC circuit 1240 can be configured to use error correction codes to detect and correct errors included in data read from memory device 1100.

[0135] The memory interface 1250 can be configured to interface with the memory device 1100. For example, the memory interface 1250 may include a NAND interface or a NOR interface.

[0136] For reference, controller 1200 may also include a buffer memory (not shown) for temporarily storing data. The buffer memory can be used to temporarily store data sent to an external device via host interface 1230 or to temporarily store data sent from memory device 1100 via memory interface 1250. Additionally, controller 1200 may also include a ROM for storing code data for interfacing with the host device.

[0137] As described above, since the storage device 2000 includes a semiconductor memory device 1100 with improved integration and improved characteristics, the integration and characteristics of the storage device 2000 can also be improved.

[0138] According to embodiments of this disclosure, a semiconductor memory device can adjust its operating voltage by predicting changes in the threshold voltage of a selected transistor, thereby improving the reliability of the semiconductor memory device.

[0139] While embodiments of the present disclosure have been shown and described with reference to specific implementations and accompanying drawings, the disclosed embodiments are not intended to be limiting. Furthermore, it should be noted that those skilled in the art, in light of this disclosure, will recognize that these embodiments can be implemented in various ways through substitutions, alterations, and modifications without departing from the spirit and / or scope of this disclosure and the following claims. Moreover, these embodiments can be combined to form additional embodiments.

[0140] Cross-references to related applications

[0141] This application claims priority to Korean Patent Application No. 10-2024-0170730, filed on November 26, 2024, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A memory cell array, comprising multiple memory blocks; Peripheral circuitry that performs programming, reading, or erasing operations on the plurality of memory blocks; as well as Control logic, the control logic: The level of the drain select line operating voltage or the source select line operating voltage corresponding to each memory block is set based on the number of erase write (EW) cycles or read operations performed on each memory block. The peripheral circuit is controlled to perform the programming operation, the read operation, or the erase operation based on the set drain select line operating voltage or the set source select line operating voltage.

2. The semiconductor memory device according to claim 1, in, The control logic includes: A counter that counts the number of EW cycles or the number of read operations for each memory block; and The select line operation voltage setting circuit compares the number of EW cycles or the number of read operations with a reference number, and sets the level of the drain select line operation voltage or the source select line operation voltage based on the comparison result.

3. The semiconductor memory device according to claim 2, wherein, When the number of EW cycles or the number of read operations is equal to or less than the reference number, the select line operation voltage setting circuit sets the level of the drain select line operation voltage or the level of the source select line operation voltage to the initial voltage level.

4. The semiconductor memory device according to claim 3, wherein, When the number of EW cycles or the number of read operations exceeds the reference number, the select line operation voltage setting circuit sets the level of the drain select line operation voltage or the source select line operation voltage to a level that is increased by an offset voltage relative to the initial voltage level.

5. The semiconductor memory device according to claim 2, in, When the number of EW cycles or the number of read operations is equal to or less than the first reference number, the select line operating voltage setting circuit sets the level of the drain select line operating voltage or the source select line operating voltage to the initial voltage level, and Wherein, when the number of EW cycles or the number of read operations exceeds the first reference number and is equal to or less than the second reference number, the select line operation voltage setting circuit sets the level of the drain select line operation voltage or the level of the source select line operation voltage to a first level relative to the initial voltage level plus a first offset voltage, wherein the second reference number is greater than the first reference number.

6. The semiconductor memory device according to claim 5, wherein, When the number of EW cycles or the number of read operations exceeds the second reference number, the select line operation voltage setting circuit sets the level of the drain select line operation voltage or the level of the source select line operation voltage to a second level relative to the initial voltage level, which is increased by a second offset voltage, and the second offset voltage is greater than the first offset voltage.

7. A method of operating a semiconductor memory device, the method comprising the following steps: Receive commands corresponding to the selected storage block among multiple storage blocks; Check the number of erase writes or read operations performed on the selected storage block; The drain select line operating voltage or source select line operating voltage of the selected memory block is set based on the number of EW cycles or the number of read operations of the selected memory block. as well as The programming, reading, or erasing operation corresponding to the command is performed by using the set drain select line operating voltage or source select line operating voltage.

8. The method according to claim 7, wherein, The steps for setting the drain select line operating voltage or the source select line operating voltage include the following steps: Compare the number of EW cycles or the number of read operations with a reference number; Based on a comparison result showing that the number of EW cycles or the number of read operations is equal to or less than the reference number, the level of the drain select line operating voltage or the source select line operating voltage is set to an initial voltage level; and Based on a comparison result showing that the number of EW cycles or the number of read operations exceeds the reference number, the level of the drain select line operating voltage or the level of the source select line operating voltage is set to a first level relative to the initial voltage level by adding an offset voltage.

9. The method according to claim 7, wherein, The steps for setting the drain select line operating voltage or the source select line operating voltage include the following steps: Compare the number of EW cycles or the number of read operations with a first reference number and a second reference number that is greater than the first reference number; Based on a comparison result showing that the number of EW cycles or the number of read operations exceeds the first reference number and is equal to or less than the second reference number, the level of the drain select line operating voltage or the level of the source select line operating voltage is set to a first level relative to the initial voltage level by an increase of a first offset voltage; and Based on the comparison result that the number of EW cycles or the number of read operations exceeds the second reference number, the level of the drain select line operating voltage or the level of the source select line operating voltage is set to a second level relative to the initial voltage level by adding a second offset voltage, wherein the second offset voltage is greater than the first offset voltage.

10. A semiconductor memory device, the semiconductor memory device comprising: A memory cell array, comprising multiple memory blocks; Peripheral circuitry that performs programming, reading, erasing, or selection transistor monitoring operations on the plurality of memory blocks; as well as Control logic, which controls the peripheral circuitry: The selection transistor monitoring operation is performed periodically on each memory block, and The level of the drain select line operating voltage or the source select line operating voltage for the programming operation, the read operation, or the erase operation is set based on the number of failure bits corresponding to each memory block obtained as a result of the selection transistor monitoring operation.

11. The semiconductor memory device according to claim 10, in, The peripheral circuit: The selection transistor monitoring operation is performed periodically for each of the plurality of memory blocks; and When the selected transistor monitoring operation is performed, the selected transistors whose threshold voltages are greater than the monitoring read voltage among the drain selected transistors and source selected transistors included in the selected memory block are detected, so as to output failure bit information corresponding to each detected selected transistor.

12. The semiconductor memory device according to claim 11, in, The control logic includes: A failure bit counter that receives failure bit information from the peripheral circuitry to count the number of failure bits in the selected memory block; and A selection line operation voltage setting circuit is used to set the level of the drain selection line operation voltage or the source selection line operation voltage of the selected memory block based on the number of failure bits.

13. The semiconductor memory device according to claim 12, wherein, When the number of failure bits is equal to or less than the reference number, the select line operating voltage setting circuit sets the level of the drain select line operating voltage or the level of the source select line operating voltage to the initial voltage level.

14. The semiconductor memory device according to claim 13, wherein, When the number of failure bits exceeds the reference number, the select line operation voltage setting circuit sets the level of the drain select line operation voltage or the level of the source select line operation voltage to a first level relative to the initial voltage level, which is increased by an offset voltage.

15. The semiconductor memory device according to claim 12, wherein, When the number of failure bits is equal to or less than the first reference number, the select line operation voltage setting circuit sets the level of the drain select line operation voltage or the level of the source select line operation voltage to the initial voltage level.

16. The semiconductor memory device according to claim 15, wherein, When the number of failure bits exceeds the first reference number and is equal to or less than the second reference number, the select line operation voltage setting circuit sets the level of the drain select line operation voltage or the level of the source select line operation voltage to a first level relative to the initial voltage level plus a first offset voltage, wherein the second reference number is greater than the first reference number.

17. The semiconductor memory device of claim 16, wherein, When the number of failure bits exceeds the second reference number, the select line operating voltage sets the level of the drain select line operating voltage or the level of the source select line operating voltage to a second level relative to the initial voltage level, which is increased by a second offset voltage, wherein the second offset voltage is greater than the first offset voltage.

18. The semiconductor memory device according to claim 10, in, The selection transistor monitoring operation includes a first monitoring operation based on a first monitoring read voltage, a second monitoring operation based on a second monitoring read voltage greater than the first monitoring read voltage, and a third monitoring operation based on a third monitoring read voltage greater than the second monitoring read voltage. The peripheral circuit includes: During the first monitoring operation, a selection transistor whose threshold voltage is greater than the first monitoring read voltage is detected among the drain selection transistor and source selection transistor included in the selected memory block, so as to output failure bit information for the first monitoring operation. During the second monitoring operation, a selection transistor whose threshold voltage among the drain selection transistor and the source selection transistor included in the selected memory block is greater than the second monitoring read voltage is detected, and a failure bit information for the second monitoring operation is output; and During the third monitoring operation, a selection transistor whose threshold voltage is greater than the third monitoring read voltage among the drain selection transistor and the source selection transistor included in the selected memory block is detected, so as to output failure bit information for the third monitoring operation.

19. The semiconductor memory device of claim 18, wherein, The control logic includes: A failure bit counter that receives failure bit information from the peripheral circuitry to count the number of failure bits corresponding to each of the first monitoring operation, the second monitoring operation, and the third monitoring operation; and A selection line operation voltage setting circuit is used to set the level of the drain selection line operation voltage or the source selection line operation voltage of the selected memory block based on the number of failure bits corresponding to the first monitoring operation, the number of failure bits corresponding to the second monitoring operation, and the number of failure bits corresponding to the third monitoring operation.

20. The semiconductor memory device of claim 19, wherein, The selection line operating voltage setting circuit: When the number of failure bits corresponding to the first monitoring operation is equal to or less than the reference number, the level of the drain select line operating voltage or the level of the source select line operating voltage is set to the initial voltage level. and When the number of failure bits corresponding to the first monitoring operation exceeds a reference number, the level of the drain select line operating voltage or the level of the source select line operating voltage is set to a first level relative to the initial voltage level by an additional first offset voltage.

21. The semiconductor memory device of claim 20, wherein, The selection line operating voltage setting circuit: When the number of failure bits corresponding to the second monitoring operation is equal to or less than the reference number, the level of the drain select line operating voltage or the level of the source select line operating voltage is set to the initial voltage level. and When the number of failure bits corresponding to the second monitoring operation exceeds the reference number, the level of the drain select line operating voltage or the level of the source select line operating voltage is set to a second level relative to the initial voltage level by an additional second offset voltage, wherein the second offset voltage is greater than the first offset voltage.

22. The semiconductor memory device of claim 21, wherein, The selection line operating voltage setting circuit: When the number of failure bits corresponding to the third monitoring operation is equal to or less than the reference number, the level of the drain select line operating voltage or the level of the source select line operating voltage is set to the initial voltage level. and When the number of failure bits corresponding to the third monitoring operation exceeds the reference number, the level of the drain select line operating voltage or the level of the source select line operating voltage is set to a third level relative to the initial voltage level by adding a third offset voltage, wherein the third offset voltage is greater than the second offset voltage.

23. The semiconductor memory device according to claim 10, in, The control logic includes a selection transistor monitoring control circuit that controls the peripheral circuitry to periodically perform the selection transistor monitoring operation. The selected transistor monitoring and control circuit skips the selected transistor monitoring operation during a set initial time period, and controls the peripheral circuit to periodically perform the selected transistor monitoring operation after the initial time period.

24. A method of operating a semiconductor memory device, the method comprising the following steps: Perform a first selection transistor monitoring operation on the selected memory block among multiple memory blocks; Based on the result of the first selection transistor monitoring operation, the number of selection transistors in the selected memory block whose threshold voltage is greater than the first monitoring read voltage is detected, so as to count the number of first failure bits. as well as The drain select line operating voltage or source select line operating voltage corresponding to the selected memory block is set based on the number of the first failure bits counted.

25. The method of claim 24, further comprising the step of: Based on the determination that the number of first failure bits counted is equal to or less than the reference number, the level of the drain select line operating voltage or the level of the source select line operating voltage is set to the initial voltage level.

26. The method of claim 25, further comprising the step of: Based on the determination that the number of first failure bits counted exceeds the reference number, the level of the drain select line operating voltage or the level of the source select line operating voltage is set to a level that is increased by an offset voltage relative to the initial voltage level.

27. The method of claim 24, further comprising the step of: Perform a second selection transistor monitoring operation on the selected memory block; Based on the result of the second selection transistor monitoring operation, the number of selection transistors in the drain selection transistor and the source selection transistor whose threshold voltage is greater than the second monitoring read voltage is detected, so as to count the number of second failure bits, wherein the second monitoring read voltage is greater than the first monitoring read voltage; as well as The drain select line operating voltage or the source select line operating voltage corresponding to the selected memory block is set based on the number of second failure bits counted.

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