Duty cycle correction device and duty cycle correction method thereof

Abstract

This invention provides a duty cycle correction device and a duty cycle correction method. A duty cycle adjustment circuit adjusts the duty cycle of the input clock signal to output a clock signal. An integrator circuit generates an integral signal based on the output clock signal. A correction control circuit periodically controls the duty cycle adjustment circuit to adjust the duty cycle by the amount of adjustment based on the logic level changes of the integral signal.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a duty cycle correction device and a duty cycle correction method thereof. Background Technology

[0002] Duty cycle correction devices are used to correct the duty cycle of a signal, maintaining it at a default percentage, thereby improving system signal quality and ensuring normal system operation. Therefore, providing a duty cycle correction device that can quickly and accurately correct the signal's duty cycle is a very important issue. Summary of the Invention

[0003] This invention relates to a duty cycle correction device and a duty cycle correction method, which can quickly and accurately correct the duty cycle of a signal.

[0004] According to an embodiment of the present invention, the duty cycle correction device includes a duty cycle adjustment circuit, an integrator circuit, and a correction control circuit. The duty cycle adjustment circuit adjusts the duty cycle of the input clock signal to output an output clock signal. The integrator circuit is coupled to the duty cycle adjustment circuit and generates an integral signal based on the output clock signal. The correction control circuit is coupled to both the integrator circuit and the duty cycle adjustment circuit, and periodically controls the duty cycle adjustment circuit to adjust the duty cycle by the amount of adjustment based on the logic level change of the integral signal.

[0005] In one embodiment of the present invention, when the logic level of the integral signal changes more than n times during the default period, the correction control circuit controls the duty cycle adjustment circuit to reduce the adjustment amount.

[0006] In one embodiment of the present invention, n is an integer greater than 1, which can be a fixed value or vary with the needs of different stages.

[0007] In one embodiment of the present invention, the aforementioned correction control circuit includes a multiplier circuit, an adder circuit, and a control circuit. The multiplier circuit is coupled to an integrator circuit and provides a product value based on the integrated signal. A first input terminal of the adder circuit is coupled to the multiplier circuit, and a second input terminal is coupled to its output terminal. The output terminal of the adder circuit is coupled to a duty cycle adjustment circuit, outputting a control code to the duty cycle adjustment circuit to control the adjustment of the duty cycle by an appropriate amount. The control circuit is coupled to both the multiplier circuit and the adder circuit, periodically controlling the multiplier circuit to adjust the product value based on changes in the logic level of the integrated signal, and controlling the adder circuit to add or subtract the product value using the control code based on the logic level of the integrated signal, thereby controlling the duty cycle adjustment circuit to adjust the duty cycle by the appropriate amount.

[0008] In one embodiment of the present invention, the control circuit reacts to the product value being less than or equal to the default product value and then stops adjusting the product value.

[0009] In one embodiment of the present invention, the integrator circuit includes a differential signal conversion circuit, a first comparator, a first resistor, a second resistor, a first capacitor, a second capacitor, and a second comparator. The differential signal conversion circuit is coupled to the output of the duty cycle adjustment circuit, converting the output clock signal into a differential signal. The first resistor is coupled between the differential signal conversion circuit and the positive input of the first comparator. The second resistor is coupled between the differential signal conversion circuit and the negative input of the first comparator. The first capacitor is coupled between the positive input of the first comparator and ground. The second capacitor is coupled between the negative input of the first comparator and ground. The positive and negative inputs of the second comparator are respectively coupled to the negative and positive outputs of the first comparator. The output of the second comparator is coupled to a correction control circuit and is used to output an integrated signal.

[0010] In one embodiment of the present invention, the duty cycle correction device further includes a delay circuit coupled between the duty cycle adjustment circuit and the integrator circuit.

[0011] This invention also provides a duty cycle correction method for a duty cycle correction device. The duty cycle correction device includes a duty cycle adjustment circuit that adjusts the duty cycle of an input clock signal to output an output clock signal. The duty cycle correction method includes the following steps: providing the output clock signal to an integrator circuit to generate an integrated signal; and periodically controlling the duty cycle adjustment circuit to adjust the duty cycle by an adjustment amount based on the logic level change of the integrated signal.

[0012] In one embodiment of the present invention, the duty cycle correction method of the above-described duty cycle correction device includes the following steps: determining whether the logic level of the integral signal changes more than n times during the default period. When the logic level of the integral signal changes more than n times during the default period, controlling the duty cycle adjustment circuit to reduce the adjustment amount.

[0013] In one embodiment of the present invention, n is an integer greater than 1.

[0014] In one embodiment of the present invention, the duty cycle correction method of the above-described duty cycle correction device includes the following steps: Periodically adjusting the provided product value according to the logic level change of the integral signal; adding or subtracting the product value to a control code according to the logic level of the integral signal; and outputting the control code to the duty cycle adjustment circuit to control the duty cycle adjustment circuit to adjust the duty cycle by an appropriate amount.

[0015] In one embodiment of the present invention, the duty cycle correction method of the above-mentioned duty cycle correction device includes stopping the adjustment of the product value when the reaction product value is less than or equal to the default product value.

[0016] Based on the above, the integrator circuit of this embodiment generates an integral signal based on the output clock signal of the duty cycle adjustment circuit. The correction control circuit periodically controls the duty cycle adjustment circuit to adjust the duty cycle based on the logic level changes of the integral signal. This allows for rapid and accurate correction of the duty cycle of the output clock signal, thereby improving the signal quality of the system using the duty cycle correction device and ensuring normal system operation. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a duty cycle correction device according to an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of a duty cycle correction device according to another embodiment of the present invention;

[0019] Figure 3 This is an operation timing diagram of a duty cycle correction device according to an embodiment of the present invention;

[0020] Figure 4 This is a flowchart of a duty cycle correction method for a duty cycle correction device according to an embodiment of the present invention;

[0021] Figure 5 This is a flowchart of a duty cycle correction method for a duty cycle correction device according to another embodiment of the present invention;

[0022] Figure 6 This is a flowchart of a duty cycle correction method for a duty cycle correction device according to another embodiment of the present invention. Detailed Implementation

[0023] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0024] Figure 1 This is a schematic diagram of a duty cycle correction device according to an embodiment of the present invention. Please refer to... Figure 1 The duty cycle correction device 100 includes a duty cycle adjustment circuit 102, an integrator circuit 104, and a correction control circuit 106. The integrator circuit 104 is coupled to the duty cycle adjustment circuit 102 and the correction control circuit 106, and the correction control circuit 106 is also coupled to the duty cycle adjustment circuit 102.

[0025] The duty cycle adjustment circuit 102 adjusts the duty cycle of the input clock signal CLK1 to output the output clock signal CLK2. The integrator circuit 104 generates an integral signal S1 based on the output clock signal CLK2. The correction control circuit 106 can periodically control the duty cycle adjustment circuit 102 to adjust the duty cycle of the input clock signal CLK1 based on the logic level changes of the integral signal S1. For example, when the logic level of the integral signal S1 changes more than n times within the default period, the correction control circuit 106 can control the duty cycle adjustment circuit 102 to reduce the adjustment amount, where n is an integer greater than 1. The number of logic level changes can be, for example, counting the number of times a logic level changes from high to low and from low to high, or only counting the number of times a logic level changes from high to low, or only counting the number of times a logic level changes from low to high. This allows for quick and accurate correction of the duty cycle of the output clock signal, improving the signal quality of the system using the duty cycle correction device and ensuring normal system operation.

[0026] Furthermore, the duty cycle correction device 100 can be implemented as follows: Figure 2 As shown. In Figure 2 In this embodiment, the duty cycle correction device 100 may further include a delay circuit 202, which is coupled between the duty cycle adjustment circuit 102 and the integrator circuit 104. The delay circuit 202 can delay the output of the output clock signal CLK2, and it can be implemented, for example, using multiple buffers. Furthermore, the delay circuit 202 can also output the output clock signal CLK2 through buffer BF1, but this is not a limitation; in other embodiments, the delay circuit 202 may also directly output the output clock signal CLK2.

[0027] The integrator circuit 104 may include a differential signal conversion circuit 204, comparators 206 and 208, resistors R1 and R2, and capacitors C1 and C2. The differential signal conversion circuit 204 is coupled to the delay circuit 202 and is coupled to the positive and negative input terminals of the comparator 206 through resistors R1 and R2. Further, the differential signal conversion circuit 204 may include multiple first inverters connected in series between the delay circuit 202 and resistor R1, and multiple second inverters connected in series between the delay circuit 202 and resistor R2. The number of first inverters may be even, for example, and the number of second inverters may be odd, but this is not a limitation. For example, in other embodiments, the number of first inverters may be odd, and the number of second inverters may be even. Capacitor C1 is coupled between the positive input terminal of the comparator 206 and ground, and capacitor C2 is coupled between the negative input terminal of the comparator 206 and ground. The positive and negative input terminals of comparator 208 are coupled to the negative and positive output terminals of comparator 206, respectively, and the output terminal of comparator 208 is coupled to the correction control circuit 106.

[0028] In this embodiment, the correction control circuit 106 may include a multiplier circuit 210, an adder circuit 212, and a control circuit 214. The multiplier circuit 210 is coupled to the integrator circuit 104, the adder circuit 210, and the control circuit 214. The adder circuit 212 is also coupled to the control circuit 214 and the duty cycle adjustment circuit 102. In addition, one input terminal and one output terminal of the adder circuit 212 are coupled.

[0029] The differential signal conversion circuit 204 converts the output clock signal CLK2 into a differential signal. In this embodiment, the differential signal includes two clock signals with opposite phases. The differential signal is converted into an integral signal S1 via resistors R1 and R2, capacitors C1 and C2, comparator 206, and comparator 208, and then output to the multiplier circuit 210. Further, as... Figure 2 As shown, when the duty cycle of the output clock signal CLK2 is larger, the output voltage "+" terminal of comparator 206 (as shown by output curve VO1) will approach the high voltage logic level VH. Conversely, when the duty cycle of the output clock signal CLK2 is smaller, the output voltage "-" terminal of comparator 206 (as shown by voltage curve VO2) will approach the low voltage logic level VL. Comparator 208 can generate an integral signal S1 based on the output voltage of comparator 206. When the output voltage of comparator 206 corresponds to output curve VO1, comparator 208 generates an integral signal S1 at a high voltage logic level (as shown by output curve VO2). Figure 2 As shown), when the output voltage of comparator 206 corresponds to the output curve VO2, comparator 208 generates a low-voltage logic level integration signal S1. Multiplier circuit 210 can provide the product value based on the integration signal S1. For example, ... Figure 3 As shown, the multiplier circuit 210 can provide different product values ​​M at different stages. The product value M can be, for example, 8, 4, 2, or 1, but is not limited to these. The adder circuit 212 outputs control code CD1 to the duty cycle adjustment circuit 102 to control the duty cycle adjustment circuit 102 to adjust the duty cycle of the input clock signal CLK1. The control circuit 214 can periodically control the multiplier circuit 210 to adjust the product value M according to the logic level change of the integral signal S1, and control the adder circuit 212 to add or subtract the product value M from the control code CD1 according to the logic level of the integral signal S1, thereby controlling the duty cycle adjustment circuit 102 to adjust the duty cycle of the input clock signal CLK1.

[0030] For example, in Figure 3In this embodiment, the control circuit 214 can perform a counting operation (e.g., counting the rising edge of the base clock signal) to generate a count value, which is reset when it accumulates to a default value (e.g., 3, but not limited thereto). The control circuit 214 can control the adder circuit 212 to add or subtract the product value M from the control code CD1 based on the logic level of the integral signal S1. For example, when the integral signal S1 is at a high logic level, the product value M is subtracted from the control code CD1, and when the integral signal S1 is at a low logic level, the product value M is added to the control code CD1. However, this is not a limitation; in other embodiments, it can also be set that when the integral signal S1 is at a high logic level, the product value M is added to the control code CD1, and when the integral signal S1 is at a low logic level, the product value M is subtracted from the control code CD1.

[0031] Furthermore, the control circuit 214 can periodically determine whether it is necessary to control the multiplier circuit 210 to adjust the product value M based on the logic level changes of the integral signal S1, for example, in Figure 3 In this embodiment, the control circuit 214 can determine the period during which the integral signal S1 is applied based on the count value (i.e., the default period). Figure 3 In this embodiment, the logic level changes during the period from 0 to 3 determine whether the multiplier circuit 210 needs to be adjusted to increase the product value M. Furthermore, the control circuit 214 can determine whether to adjust the product value M by judging the number of logic level changes of the integral signal S1 within each period defined by the count value. For example, it can be set to adjust the product value M when the number of logic level changes of the integral signal S1 within each period defined by the count value is greater than 1.

[0032] like Figure 3 As shown, assuming the product value M equals 8 when entering stage A, during period T1, control circuit 214 continuously controls adder circuit 212 to subtract the product value M from control code CD1, responding to the integral signal S1 being at a high logic level. Since the number of logic level changes of integral signal S1 during period T1 is less than 1, control circuit 214 does not control multiplier circuit 210 to adjust the product value M. During period T2, integral signal S1 changes between high and low logic levels 4 times, and control circuit 214 responds to the logic level changes of integral signal S1 by controlling adder circuit 212 to add or subtract the product value M from control code CD1. Since the number of logic level changes of integral signal S1 during period T2 is greater than 1, control circuit 214 enters stage B, controlling multiplier circuit 210 to reduce the product value M to 4. Similarly, during the period T3~T5, the logic level of the integral signal S1 changes more than once each time, so the control circuit 214 continuously controls the multiplier circuit 210 to reduce the product value M.

[0033] Furthermore, the control circuit 214 can determine whether the product value M is less than or equal to the default product value. When the product value M is less than or equal to the default value, it indicates that the duty cycle is close to the target duty cycle, and the control circuit 214 can end the adjustment of the product value M, that is, stop adjusting the duty cycle. For example, in Figure 3 In this embodiment, the default product value can be set to 1. After the period T5 ends, the control circuit 214 enters stage E and stops adjusting the product value M.

[0034] Figure 4 This is a flowchart of a duty cycle correction method for a duty cycle correction device according to an embodiment of the present invention. The duty cycle correction device includes a duty cycle adjustment circuit, which uses an adjusted duty cycle of the input clock signal to output an output clock signal. The duty cycle correction method of the duty cycle correction device may include at least the following steps: First, the output clock signal is provided to an integrator circuit to generate an integrated signal (step S402). Then, the duty cycle adjustment circuit is periodically controlled to adjust the adjustment amount of the duty cycle based on the logic level change of the integrated signal (step S404).

[0035] Furthermore, the method of periodically adjusting the duty cycle based on the logic level changes of the integral signal can be as follows: Figure 5 As shown, after step S402, it is determined whether the logic level of the integral signal changes more than n times during the default period (step S502), where n is an integer greater than 1. If the number of changes is greater than n, the duty cycle adjustment circuit is controlled to reduce the adjustment amount (step S504). If the number of changes is less than n, the duty cycle adjustment circuit is not controlled to reduce the adjustment amount (step S506).

[0036] In some embodiments, the adjustment amount of the duty cycle can be implemented, for example, by adjusting the product value generated based on the integral signal. Figure 6In this embodiment, the provided product value can be periodically adjusted according to the logic level changes of the integral signal (step S602). For example, when the logic level of the integral signal changes more than n times within the default period, the provided product value can be reduced. Then, the control code is added to or subtracted from the product value according to the logic level of the integral signal (step S604). For example, when the integral signal is at a high logic level, the control code is subtracted from the product value, and when the integral signal is at a low logic level, the control code is added to the product value. However, this is not a limitation; in other embodiments, it can also be set that when the integral signal is at a high logic level, the control code is added to the product value, and when the integral signal is at a low logic level, the control code is subtracted from the product value. Afterward, the adjusted control code is output to the duty cycle adjustment circuit to control the duty cycle adjustment circuit to adjust the duty cycle adjustment amount (step S606). Furthermore, when the product value is adjusted to be less than or equal to the default product value, the adjustment of the product value can be stopped (step S608), that is, the adjustment of the duty cycle adjustment amount is stopped.

[0037] In summary, the integrator circuit of this invention generates an integral signal based on the output clock signal of the duty cycle adjustment circuit, and the correction control circuit periodically controls the duty cycle adjustment circuit to adjust the duty cycle based on the logic level changes of the integral signal. This allows for rapid and accurate correction of the duty cycle of the output clock signal, thereby improving the signal quality of systems using duty cycle correction devices and ensuring normal system operation.

[0038] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A duty cycle correction device, characterized in that, include: The duty cycle adjustment circuit adjusts the duty cycle of the input clock signal to output the output clock signal. An integrator circuit, coupled to the duty cycle adjustment circuit, generates an integral signal based on the output clock signal; as well as A correction control circuit, coupled to the integrator circuit and the duty cycle adjustment circuit, periodically controls the duty cycle adjustment circuit to adjust the duty cycle by the amount of adjustment based on the logic level change of the integral signal.

2. The duty cycle correction device according to claim 1, characterized in that, When the logic level of the integral signal changes more than n times during the default period, the correction control circuit controls the duty cycle adjustment circuit to reduce the adjustment amount.

3. The duty cycle correction device according to claim 2, characterized in that, n is an integer greater than 1.

4. The duty cycle correction device according to claim 1, characterized in that, The correction control circuit includes: A multiplier circuit, coupled to the integrator circuit, provides a product value based on the integration signal; An adder circuit, wherein a first input terminal is coupled to the multiplier circuit, a second input terminal and an output terminal are coupled to the adder circuit, and the output terminal of the adder circuit is coupled to the duty cycle adjustment circuit, outputting a control code to the duty cycle adjustment circuit to control the duty cycle adjustment circuit to adjust the duty cycle by the adjustment amount; and A control circuit, coupled to the multiplier circuit and the adder circuit, periodically controls the multiplier circuit to adjust the product value according to the logic level change of the integral signal, and controls the adder circuit to add or subtract the product value to the control code according to the logic level of the integral signal, so as to control the duty cycle adjustment circuit to adjust the adjustment amount of the duty cycle.

5. The duty cycle correction device according to claim 4, characterized in that, The control circuit stops adjusting the product value when the product value is less than or equal to the default product value.

6. The duty cycle correction device according to claim 1, characterized in that, The integrator circuit includes: A differential signal conversion circuit is coupled to the output terminal of the duty cycle adjustment circuit to convert the output clock signal into a differential signal; First comparator; The first resistor is coupled between the differential signal conversion circuit and the positive input terminal of the first comparator; The second resistor is coupled between the differential signal conversion circuit and the negative input terminal of the first comparator; The first capacitor is coupled between the positive input terminal of the first comparator and ground; The second capacitor is coupled between the negative input terminal of the first comparator and the ground; and The second comparator has its positive and negative input terminals coupled to the negative and positive output terminals of the first comparator, respectively. The output terminal of the second comparator is coupled to the correction control circuit and outputs the integral signal.

7. The duty cycle correction device according to claim 1, characterized in that, Also includes: The delay circuit is coupled between the duty cycle adjustment circuit and the integrator circuit.

8. A duty cycle correction method for a duty cycle correction device, characterized in that, The duty cycle correction device includes a duty cycle adjustment circuit, which adjusts the duty cycle of the input clock signal to output an output clock signal. The duty cycle correction method of the duty cycle correction device includes: The output clock signal is provided to the integrator circuit to generate an integrated signal; and The duty cycle adjustment circuit is periodically controlled to adjust the duty cycle based on the logic level changes of the integral signal.

9. The duty cycle correction method of the duty cycle correction device according to claim 8, characterized in that, include: Determine whether the logic level of the integral signal changes more than n times during the default period; as well as When the logic level of the integral signal changes more than n times during the default period, the duty cycle adjustment circuit is controlled to reduce the adjustment amount.

10. The duty cycle correction method of the duty cycle correction device according to claim 9, characterized in that, n is an integer greater than 1.

11. The duty cycle correction method of the duty cycle correction device according to claim 8, characterized in that, include: The provided product value is periodically adjusted based on the logic level changes of the integral signal; The control code is added to or subtracted from the product value based on the logic level of the integral signal; as well as The control code is output to the duty cycle adjustment circuit to control the duty cycle adjustment circuit to adjust the duty cycle by the adjustment amount.

12. The duty cycle correction method of the duty cycle correction device according to claim 11, characterized in that, include: If the product value is less than or equal to the default product value, the adjustment of the product value is stopped.

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