Carrier communication circuits, chips and systems

Abstract

This application discloses a carrier communication circuit, chip, and system. The carrier communication circuit includes: a low-voltage power supply line, a signal modulation circuit, a power bus, and a signal demodulation circuit. One end of the signal modulation circuit is connected to the low-voltage power supply line, and the other end is connected to the power bus. The signal modulation circuit receives an external input signal and a carrier signal, and modulates the input signal into a first modulation signal. One end of the signal demodulation circuit is connected to the power bus, and the other end is connected to the low-voltage power supply line. The signal demodulation circuit demodulates the second modulation signal received from the power bus into an output signal. The technical solution provided by this application can achieve bidirectional data communication between devices without changing the connection status of the device's power supply line.

Description

Technical Field

[0001] This application belongs to the field of carrier communication technology, and in particular relates to a carrier communication circuit, chip and system. Background Technology

[0002] With the rapid development of technology and the significant improvement in people's quality of life, home appliances are increasingly moving towards intelligence, which places more stringent demands on the performance of communication and control circuits. Taking the signal interaction between the master and slave devices as an example, the current signal interaction methods between the master and slave devices generally involve two major categories: power and signal. Most circuit designs adopt three-wire or four-wire designs, resulting in a large number of wire harnesses between the master and slave devices, which greatly increases the difficulty of equipment installation and maintenance. Summary of the Invention

[0003] This application provides an implementation scheme that differs from related technologies to solve the technical problem of a large number of wiring harnesses between the host and slave devices in related technologies.

[0004] In a first aspect, this application provides a carrier communication circuit, comprising: a low-voltage power supply line, a signal modulation circuit, a power bus, and a signal demodulation circuit; wherein:

[0005] One end of the signal modulation circuit is connected to the low-voltage power supply line, and the other end of the signal modulation circuit is connected to the power bus. The signal modulation circuit is used to receive external input signals and carrier signals, and modulate the input signals into a first modulation signal.

[0006] One end of the signal demodulation circuit is connected to the power bus, and the other end of the signal demodulation circuit is connected to the low-voltage power line. The signal demodulation circuit is used to demodulate the second modulation signal received from the power bus into an output signal.

[0007] Secondly, this application provides a carrier communication chip, including the carrier communication circuit as described in the first aspect.

[0008] Thirdly, this application provides a carrier communication device, including a master device and a slave device connected via a power bus and a ground wire, wherein:

[0009] The host device includes: a host MCU; a first carrier communication circuit or a first carrier communication chip connected to the host MCU; and a first power supply circuit connected to the host MCU and the first carrier communication circuit or the first carrier communication chip, wherein the first power supply circuit is used to supply power to the host MCU and the first carrier communication circuit or the first carrier communication chip, the first carrier communication circuit being the carrier communication circuit as described in the first aspect, and the first carrier communication chip being the carrier communication chip as described in the second aspect.

[0010] The slave device includes: a slave MCU; a second carrier communication circuit or a second carrier communication chip connected to the slave MCU; and a second power supply circuit connected to the slave MCU and the second carrier communication circuit or the second carrier communication chip, the second power supply circuit being used to supply power to the slave MCU and the second carrier communication circuit or the second carrier communication chip, the second carrier communication circuit being a carrier communication circuit as described in the first aspect, and the second carrier communication chip being a carrier communication chip as described in the second aspect.

[0011] The carrier communication circuit provided in this application includes: a low-voltage power supply line, a signal modulation circuit, a power bus, and a signal demodulation circuit; wherein: one end of the signal modulation circuit is connected to the low-voltage power supply line, and the other end of the signal modulation circuit is connected to the power bus; the signal modulation circuit is used to receive an externally input signal and a carrier signal, and modulate the input signal into a first modulation signal; one end of the signal demodulation circuit is connected to the power bus, and the other end of the signal demodulation circuit is connected to the low-voltage power supply line; the signal demodulation circuit is used to demodulate the second modulation signal received from the power bus into an output signal. This allows for bidirectional power supply and data transmission between the host device and the slave device using the power bus, significantly reducing costs compared to three-wire and four-wire systems. Especially for existing power supply lines of the devices, the circuit provided in this application can achieve bidirectional data communication between devices without changing the existing power supply line connection status. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0013] Figure 1 This is a first structural schematic diagram of a carrier communication circuit 10 provided in an embodiment of this application;

[0014] Figure 2 This is a schematic diagram of the second structure of the carrier communication circuit 10 provided in the embodiments of this application;

[0015] Figure 3 This is a schematic diagram of the signal modulation circuit 12 provided in an embodiment of this application;

[0016] Figure 4 Waveform diagram of the carrier communication circuit 10 provided in the embodiments of this application;

[0017] Figure 5 This is a schematic diagram of the structure of logic gate 12 provided in an embodiment of this application;

[0018] Figure 6 This is a schematic diagram of the signal demodulation circuit 13 provided in an embodiment of this application;

[0019] Figure 7 This is a schematic diagram of the structure of the carrier communication device 70 provided in the embodiments of this application;

[0020] Figure 8 This is a schematic diagram of the structure of a carrier communication system provided in an embodiment of this application. Detailed Implementation

[0021] The embodiments of this application are described in detail below, with examples of these embodiments illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0022] As home appliances become increasingly intelligent, the communication and control between master and slave devices are facing greater demands. Current communication methods between master and slave devices generally require both power and signal transmission, typically using three- or four-wire systems with numerous wiring harnesses. However, most existing product circuits only have power supply lines, lacking communication lines. Since the data transmission between electronic components in home appliances is generally limited, adding extra communication lines increases costs and complicates wiring and installation.

[0023] To address this technical problem, this application provides a carrier communication circuit, chip, and system to solve the technical problem of a large number of wire harnesses between the host and slave in related technologies.

[0024] The technical solution of this application and how it solves the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0025] Figure 1 This is a schematic diagram of the structure of a carrier communication circuit 10 provided for an exemplary embodiment of this application.

[0026] like Figure 1 As shown, this application proposes a carrier communication circuit 10, which includes: a low-voltage power line VDDL 11, a signal modulation circuit 12, a signal demodulation circuit 13, and a power bus VBUS 14; wherein:

[0027] One end of the signal modulation circuit 12 is connected to the low-voltage power supply line 11, and the other end of the signal modulation circuit 12 is connected to the power bus VBUS14. The signal modulation circuit 12 is used to receive the external input signal TX signal and carrier signal. The carrier signal can be the CLK signal, and modulate the TX signal into the first modulation signal.

[0028] One end of the signal demodulation circuit 13 is connected to the power bus VBUS14, and the other end of the signal demodulation circuit 13 is connected to the low-voltage power line VDDL11. The signal demodulation circuit 13 is used to demodulate the second modulation signal received from the power bus VBUS14 into the output signal RX signal.

[0029] The TX signal and carrier signal operate in the low-voltage power domain corresponding to the low-voltage power line VDDL11.

[0030] Specifically, the carrier communication circuit 10 in this embodiment includes a signal modulation circuit 12 and a signal demodulation circuit 13, which can transmit and receive data to realize communication between the device including the carrier communication circuit 10 and other communication nodes, such as the communication between the wired controller and the indoor unit in an air conditioning system.

[0031] The signal modulation circuit 12 is connected to the power bus VBUS14 and can convert the TX signal containing communication data into a first modulation signal through a carrier signal. Then, the first modulation signal is output to the power bus VBUS14 so that the first modulation signal containing communication data can be sent to other communication nodes through the power bus VBUS14 to complete the transmission of communication information.

[0032] The signal demodulation circuit 13 is connected to the power bus VBUS14. The signal demodulation circuit 13 can receive the second modulation signal sent by other communication nodes through the power bus VBUS14. The signal demodulation circuit 13 demodulates the second modulation signal to generate a level signal RX signal that can be recognized by the subsequent control circuit, so as to complete the reception of communication information.

[0033] Therefore, this embodiment uses a modulation and demodulation process for carrier communication, enabling bidirectional data transmission between devices without changing the connection status of the device power supply line. Power supply and bidirectional data transmission are completed through the power bus VBUS14. Furthermore, the carrier communication circuit provided in this embodiment has a simple circuit design, convenient and quick wiring between devices, and can also reduce implementation costs.

[0034] In some embodiments, the signal modulation circuit 12 includes logic gate 121, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, and a fourth MOSFET M4. (See also...) Figure 2 or Figure 3 , Figure 2This is a second structural schematic diagram of the carrier communication circuit 10 provided in an embodiment of this application. Figure 3 This is a schematic diagram of the signal modulation circuit 12 provided in an embodiment of this application, wherein:

[0035] Logic gate 121 is used to couple the externally input TX signal and carrier signal. The output of logic gate 121 is connected to the gate of the first MOS transistor M1 and the gate of the fourth MOS transistor M4.

[0036] The source of the first MOSFET M1 is connected to the low-voltage power supply line VDDL11, and the drain of the first MOSFET M1 is connected to the gate of the second MOSFET M2, the drain of the second MOSFET M2, the gate of the third MOSFET M3, and the drain of the fourth MOSFET M4, respectively.

[0037] The gate of the second MOSFET M2 is also connected to the gate of the third MOSFET M3 and the drain of the fourth MOSFET M4.

[0038] The drain of the third MOSFET M3 is connected to the power bus VBUS14;

[0039] The sources of the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 are all grounded.

[0040] In some embodiments, the TX signal is active low, meaning that when the TX signal is low, the carrier signal is enabled, and when the TX signal is high, the carrier signal is deactivated.

[0041] Please see Figure 4 , Figure 4 This is a waveform diagram of the carrier communication circuit 10 provided in the embodiments of this application. Figure 4 The waveform curves from top to bottom are: the waveform curve of the TX signal, the waveform curve of the carrier signal, the waveform curve of the signal on the power bus VBUS14, and the waveform curve of the RX signal. It can be seen that when the TX signal is low, there is a modulation signal on the power bus VBUS14.

[0042] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of logic gate 121 provided in an embodiment of this application.

[0043] Specifically, logic gate 121 first inverts the TX signal, then performs NAND logic processing on the inverted TX signal and the carrier signal. The TX signal and the carrier signal control whether the signal modulation circuit 12 draws load current from the power bus VBUS14.

[0044] Specifically, the input of logic gate 121 is connected to the TX signal and the carrier signal, and the output is connected to the gates of the first MOSFET M1 and the fourth MOSFET M4. The output of logic gate 121 is a control signal, which controls the on and off states of the first MOSFET M1 and the fourth MOSFET M4. When the control signal is low, the fourth MOSFET M4 is off, the gate voltages of the second MOSFET M2 and the third MOSFET M3 are not pulled low, the first MOSFET M1 is on, current flows through the third MOSFET M3, and the second MOSFET M2 is on and draws load current from the power bus VBUS14 to drive the load circuit. When the control signal is high, the first MOSFET M1 is off, the fourth MOSFET M4 is on, the gate voltages of the second MOSFET M2 and the third MOSFET M3 are pulled low, and no current flows through the second MOSFET M2 and the third MOSFET M3. Therefore, when the TX signal is low, the carrier signal generates a modulation signal on the power bus VBUS14; when the TX signal is high, the carrier signal cannot be sent to the power bus VBUS14.

[0045] The third MOSFET M3 and the second MOSFET M2 form a current mirror. The ratio of the currents in the third MOSFET M3 and the second MOSFET M2 is equal to the ratio of their areas.

[0046] In some embodiments, the signal modulation circuit 12 further includes a first resistor R1, and the source of the first MOS transistor M1 is connected to the low-voltage power supply line VDDL11 through the first resistor R1.

[0047] The first resistor R1 is used to set the current of the second MOSFET M2, which in turn determines the current of the third MOSFET M3. By adjusting the value of the first resistor R1, the amplitude of the modulation signal can be controlled.

[0048] Please see Figure 2 or Figure 6 , Figure 6 This is a schematic diagram of the signal demodulation circuit 13 provided in an embodiment of this application.

[0049] In some embodiments, the signal demodulation circuit 13 includes a first bipolar transistor Q1, a second bipolar transistor Q2, and a coupling filter module 131.

[0050] The input terminal of the coupling filter module 131 is connected to the power bus VBUS14, the output terminal of the coupling filter module 131 is connected to the base of the first bipolar transistor Q1, the collector of the first bipolar transistor Q1 is connected to the base of the second bipolar transistor Q2, the collector of the second bipolar transistor Q2 is connected to the low-voltage power line VDDL11, the collector of the second bipolar transistor Q2 is the output port of the RX signal, and the emitters of both the first bipolar transistor Q1 and the second bipolar transistor Q2 are grounded.

[0051] Specifically, the first bipolar transistor Q1 receives a modulation signal (such as the first modulation signal or the second modulation signal in the above embodiment) from the power bus VBUS14 through the coupling filter module 131. The modulation signal is demodulated by the first bipolar transistor Q1 and the second bipolar transistor Q2 to obtain the level signal RX signal that can be recognized by the subsequent control circuit.

[0052] like Figure 2 or Figure 6 As shown, the collector of the first bipolar transistor Q1 is also connected to the high-voltage power supply VCC, which is obtained by decoupling the power bus VBUS14.

[0053] In some embodiments, the coupling filter module 131 includes a second resistor RF and a feedforward capacitor CF; wherein:

[0054] The second resistor RF is connected in series with the feedforward capacitor CF. One end of the second resistor RF is connected to the power bus VBUS14, and the other end of the second resistor RF is connected to the feedforward capacitor CF. The other end of the feedforward capacitor CF is connected to the base of the first bipolar transistor Q1. The base of the first bipolar transistor Q1 serves as the first capacitor port CAP1.

[0055] Specifically, the feedforward capacitor CF couples the modulation signal on the power bus VBUS14 to the base of the first bipolar transistor Q1, while blocking the DC component and allowing only the AC signal to pass. The feedforward capacitor CF and the second resistor RF together identify the high-frequency modulation signal on the power bus VBUS14 and couple the identified high-frequency modulation signal to the base of the first bipolar transistor Q1 for demodulation. The first capacitor port CAP1 (i.e., the base of the first bipolar transistor Q1) is the input port for the demodulated signal, receiving the modulation signal from the power bus VBUS14 after being coupled and filtered by the second resistor RF and the feedforward capacitor CF.

[0056] In some embodiments, the signal demodulation circuit 13 further includes a third resistor R3, which is connected in parallel with the coupling filter module 131, and the power bus VBUS14 is connected to the base of the first bipolar transistor Q1 through the third resistor R3.

[0057] Specifically, the third resistor R3 is connected between the power bus VBUS14 and the base of the first bipolar transistor Q1. The third resistor R3 is used to set the DC bias of the first bipolar transistor Q1.

[0058] In some embodiments, the signal demodulation circuit 13 further includes a fourth resistor R4; wherein:

[0059] The collector of the second bipolar transistor Q2 is connected to the low-voltage power supply line VDDL11 through the fourth resistor R4.

[0060] Specifically, the fourth resistor R4 is a load resistor that provides a pull-up function for the RX signal, ensuring that when the second bipolar transistor Q2 is turned off, the RX signal can be reliably pulled high to the level of the low-voltage power supply line VDDL11, and the subsequent control circuit recognizes the RX signal as a high-level state.

[0061] In some embodiments, the signal demodulation circuit 13 further includes a fifth resistor R5, a sixth resistor R6, and a filter capacitor CD; wherein:

[0062] The collector of the first bipolar transistor Q1 is connected to the base of the second bipolar transistor Q2 through the fifth resistor R5 and the sixth resistor R6 in series.

[0063] The common terminal of the fifth resistor R5 and the sixth resistor R6 is connected to one end of the filter capacitor CD, serving as the second capacitor port CAP2;

[0064] The other end of the filter capacitor CD is grounded.

[0065] Specifically, the filter capacitor CD is connected to the common terminal of the fifth resistor R5 and the sixth resistor R6, and plays a filtering role. More specifically, the filter capacitor CD is used to filter out the high-frequency part of the signal after the first bipolar transistor Q1 demodulates and detects and identifies the TX signal from the signal modulation circuit 13.

[0066] In some embodiments, the signal demodulation circuit 13 further includes a seventh resistor R7, and the collector of the first bipolar transistor Q1 is connected to the high-voltage power supply VCC through the seventh resistor R7.

[0067] Specifically, the seventh resistor R7 is the load resistor of the first bipolar transistor Q1, connected to the high-voltage power supply VCC, and provides a pull-up function for the modulation signal.

[0068] The carrier communication circuit provided in this application includes: a low-voltage power supply line, a signal modulation circuit, a power bus, and a signal demodulation circuit; wherein: one end of the signal modulation circuit is connected to the low-voltage power supply line, and the other end of the signal modulation circuit is connected to the power bus, and the signal modulation circuit is used to modulate the input signal into a first modulation signal according to the control signal output by the logic gate; one end of the signal demodulation circuit is connected to the power bus, and the other end of the signal demodulation circuit is connected to the low-voltage power supply line, and the signal demodulation circuit is used to demodulate the second modulation signal received from the power bus into an output signal. This allows for bidirectional power supply and data transmission between the host device and the slave device using the power bus, significantly reducing costs compared to three-wire and four-wire systems. Especially for existing power supply lines of the device, the carrier communication circuit provided in this application can realize bidirectional data communication functionality of the device without changing the existing power supply line connection status.

[0069] This application also provides a carrier communication chip, which includes the carrier communication circuit provided in any of the above embodiments.

[0070] In this embodiment, a carrier communication chip including a carrier communication circuit is provided. This carrier communication chip replaces discrete devices such as transistors and resistors or other integrated circuits, which can greatly simplify the complexity of the circuit, reduce the area of ​​the printed circuit board (PCB), save costs, and facilitate the miniaturization of subsequent products.

[0071] This application embodiment also provides a carrier communication system, which includes a master device and a slave device connected via a power bus VBUS and a ground line, wherein:

[0072] The host device includes: a host MCU; a first carrier communication circuit or a first carrier communication chip connected to the host MCU; and a first power supply circuit connected to the host MCU and the first carrier communication circuit or the first carrier communication chip. The first power supply circuit is used to supply power to the host MCU and the first carrier communication circuit or the first carrier communication chip. The first carrier communication circuit is the carrier communication circuit provided in any of the above embodiments, and the first carrier communication chip is the carrier communication chip provided in the above embodiments.

[0073] The slave device includes: a slave MCU; a second carrier communication circuit or a second carrier communication chip connected to the slave MCU; and a second power supply circuit connected to the slave MCU and the second carrier communication circuit or the second carrier communication chip. The second power supply circuit is used to supply power to the slave MCU and the second carrier communication circuit or the second carrier communication chip. The second carrier communication circuit is the carrier communication circuit provided in any of the above embodiments, and the second carrier communication chip is the carrier communication chip provided in the above embodiments.

[0074] In some embodiments, the carrier communication system may be, for example, an air conditioning system, such as a host device being a wired controller in the air conditioning system and a slave device being an indoor unit in the air conditioning system.

[0075] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a carrier communication device 70 provided in an embodiment of this application. The carrier communication device 70 includes a power supply circuit 710, an input circuit 720, an output circuit 730, and a control circuit 740. The power supply circuit 710 is connected to the ground wire and the power bus. The power supply circuit 710 can be an LDO / DCDC integrated circuit composed of a low dropout linear regulator (LDO) and a DC-to-DC converter (DCDC) to power the carrier communication device 70. The input circuit 720 can include the signal modulation circuit 12 in the carrier communication circuit of the above embodiment. The input circuit 720 is used to modulate the received input signal. The output circuit 730 can include the signal demodulation circuit 13 in the above embodiment to demodulate the received modulated signal to obtain the original signal. The control circuit 740 is used to control the input circuit 720 and the output circuit 730.

[0076] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a carrier communication system provided in an embodiment of this application. The carrier communication system includes a host device 81 and a slave device 82. Both the host device 81 and the slave device 82 are equipped with the carrier communication chip provided in the above embodiment. Therefore, the host device 81 and the slave device 82 can complete power supply and bidirectional data transmission through the power bus.

[0077] In some embodiments, both the first power supply circuit in the host device and the second power supply circuit in the slave device can be LDO / DCDC integrated circuits, used to convert the high-voltage power supply VCC decoupled from the power bus VBUS into a low voltage suitable for MCU operation.

[0078] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A carrier communication circuit, characterized by, The utility model relates to a signal modulation and demodulation circuit, including: Low voltage power line, signal modulation circuit, power bus, signal demodulation circuit, wherein: One end of the signal modulation circuit is connected with the low voltage power line, the other end of the signal modulation circuit is connected with the power bus, the signal modulation circuit is used for receiving external input input signal and carrier signal, and the input signal is modulated into first modulation signal; One end of the signal demodulation circuit is connected with the power bus, the other end of the signal demodulation circuit is connected with the low voltage power line, and the signal demodulation circuit is used for demodulating second modulation signal received from the power bus into output signal.

2. The carrier communication circuit according to claim 1, characterized by The signal modulation circuit includes logic gate, first MOS tube, second MOS tube, third MOS tube and fourth MOS tube, wherein: The logic gate is used for coupling the input signal and the carrier signal, and the output end of the logic gate is connected to the gate of the first MOS tube and the gate of the fourth MOS tube; The source of the first MOS tube is connected with the low voltage power line, and the drain of the first MOS tube is connected with the gate of the second MOS tube, the drain of the second MOS tube, the gate of the third MOS tube and the drain of the fourth MOS tube respectively; The gate of the second MOS tube is also connected with the gate of the third MOS tube and the drain of the fourth MOS tube; The drain of the third MOS tube is connected with the power bus; The source of the second MOS tube, the source of the third MOS tube and the source of the fourth MOS tube are grounded.

3. The carrier communication circuit according to claim 2, characterized by The signal modulation circuit further includes a first resistor, and the source of the first MOS tube is connected with the low voltage power line through the first resistor.

4. The carrier communication circuit according to claim 1, characterized by The signal demodulation circuit includes first bipolar transistor, second bipolar transistor and coupling filter module, wherein: The input end of the coupling filter module is connected with the power bus, the output end of the coupling filter module is connected with the base of the first bipolar transistor, the collector of the first bipolar transistor is connected with the base of the second bipolar transistor, the collector of the second bipolar transistor is connected with the low voltage power line, the collector of the second bipolar transistor is the output port of the output signal, and the emitters of the first bipolar transistor and the second bipolar transistor are grounded.

5. The carrier communication circuit according to claim 4, characterized by The coupling filter module includes a second resistor and a feedforward capacitor, wherein: The second resistor is connected with the feedforward capacitor in series, one end of the second resistor is connected with the power bus, the other end of the second resistor is connected with the feedforward capacitor, the other end of the feedforward capacitor is connected with the base of the first bipolar transistor, and the base of the first bipolar transistor is a first capacitor port.

6. The carrier communication circuit according to claim 4, wherein The signal demodulation circuit further includes a third resistor, and the third resistor is connected with the coupling filter module in parallel, and the power bus is connected to the base of the first bipolar transistor through the third resistor.

7. The carrier communication circuit according to claim 4, characterized by The signal demodulation circuit further includes a fourth resistor, wherein: The collector of the second bipolar transistor is connected to the low voltage power line through the fourth resistor.

8. The carrier communication circuit according to claim 4, characterized by The signal demodulation circuit further comprises a fifth resistor, a sixth resistor and a filter capacitor; wherein: the collector of the first bipolar transistor is connected to the base of the second bipolar transistor through the fifth resistor and the sixth resistor in series; the common end of the fifth resistor and the sixth resistor is connected to one end of the filter capacitor as a second capacitor port; the other end of the filter capacitor is grounded.

9. A carrier communication chip, comprising: The carrier communication circuit comprises the carrier communication circuit according to any one of claims 1-8.

10. A carrier communication system, characterized by The master device and the slave device are connected through a power bus and a ground wire, wherein: the master device comprises a master micro control unit (MCU), a first carrier communication circuit or a first carrier communication chip connected to the master MCU, and a first power supply circuit connected to the master MCU and the first carrier communication circuit or the first carrier communication chip, the first power supply circuit being used for supplying power to the master MCU and the first carrier communication circuit or the first carrier communication chip, the first carrier communication circuit being the carrier communication circuit according to any one of claims 1-8, and the first carrier communication chip being the carrier communication chip according to claim 9; the slave device comprises a slave MCU, a second carrier communication circuit or a second carrier communication chip connected to the slave MCU, and a second power supply circuit connected to the slave MCU and the second carrier communication circuit or the second carrier communication chip, the second power supply circuit being used for supplying power to the slave MCU and the second carrier communication circuit or the second carrier communication chip, the second carrier communication circuit being the carrier communication circuit according to any one of claims 1-8, and the second carrier communication chip being the carrier communication chip according to claim 9.

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