A software switch cache acceleration method and related apparatus based on FPGA

Abstract

This application provides a software switch caching acceleration method and related apparatus based on FPGA, belonging to the field of network packet processing technology. The method includes: compiling a caching rule set into a decision tree forest using a decision tree construction algorithm, the decision tree forest comprising multiple decision trees of equal depth; mapping the decision tree forest to multiple parallel tree pipelines, the tree pipelines running on the FPGA, each tree pipeline corresponding to a decision tree, and each pipeline stage corresponding to a node layer of the decision tree; broadcasting a preset data packet to all tree pipelines for parallel processing; for each tree pipeline, guiding the preset data packet to traverse each pipeline stage until the preset data packet reaches the target leaf node of the decision tree; performing parallel rule matching on the preset data packet at the target leaf node of each decision tree to obtain the target caching rule matching the preset data packet, thereby accelerating flow table caching classification.

Description

Technical Field

[0001] This application relates to the field of network packet processing technology, and in particular to an FPGA-based software switch caching acceleration method and related apparatus. Background Technology

[0002] Software switches are the de facto standard virtual switching components for cloud platforms and data centers, and their performance directly determines the throughput and latency of the entire network system. To improve service deployment flexibility, existing software switches generally adopt a multi-table pipeline architecture, achieving hop-by-hop matching and table-by-table decision-making for data packets through a design where each table corresponds to a single service action. However, this architecture incurs significant performance overhead and is difficult to adapt to the performance requirements of high-speed network environments. To alleviate this performance bottleneck, software switches typically introduce caching mechanisms to accelerate data packet classification processing. This involves caching frequently matched flow rules into a large single flow table, and by quickly looking up this single flow table, the processing overhead of the multi-table pipeline can be effectively reduced. The flow table cache classifier, as the core functional component for implementing flow table cache classification in software switches, is responsible for quickly classifying and matching data packets and is crucial for the effective implementation of the aforementioned caching mechanism. However, flow table cache classifiers often rely on simple hardware offloading techniques, which have limited scalability when facing dynamic, large-scale flow table application scenarios. Summary of the Invention

[0003] The main objective of this application is to propose a software switch cache acceleration method and apparatus based on FPGA, which aims to accelerate flow table cache classification.

[0004] To achieve the above objectives, a first aspect of this application proposes a software switch cache acceleration method based on FPGA, the method comprising:

[0005] The cache rule set of the software switch is obtained, and the cache rule set is compiled into a decision tree forest through a decision tree construction algorithm, wherein the decision tree forest includes multiple decision trees of the same depth; The decision tree forest is mapped to multiple parallel tree pipelines, wherein the tree pipelines run on an FPGA, each tree pipeline corresponds to a decision tree, and each pipeline stage of the tree pipeline corresponds to a node layer of the decision tree. Broadcast the preset data packets to all tree pipelines for parallel processing; For each tree pipeline, the preset data packet is guided to traverse each pipeline stage of the tree pipeline until the preset data packet reaches the target leaf node of the decision tree; Parallel rule matching is performed on the preset data packet at the target leaf node of each decision tree to obtain the target caching rule that matches the preset data packet.

[0006] In some embodiments, compiling the cache rule set into a decision tree forest using a decision tree construction algorithm includes: The HyperSplit algorithm is used to recursively split the current cache rule set into two balanced subsets at each level node; When the number of rules for a node is less than or equal to a preset threshold, the node is pushed down layer by layer to the maximum depth layer to become a leaf node; During the splitting process, rules that need to be copied in multiple decision tree branches and rules that exceed the maximum rule capacity of leaf nodes are removed to obtain the remaining rule set; For the remaining rule set, the steps using the HyperSplit algorithm are repeated until all remaining rule sets have been processed, resulting in the decision tree forest.

[0007] In some embodiments, mapping the decision tree forest to multiple parallel tree pipelines includes: Generate a hardware configuration file for each decision tree, wherein the hardware configuration file includes pipeline configuration information of the decision tree and node data structure of each node in each node layer of the decision tree; For each decision tree, the tree pipeline corresponding to the decision tree is determined according to the pipeline configuration information, and each node layer of the decision tree is mapped to the pipeline level corresponding to the tree pipeline. The pipeline level includes a node RAM, which is used to store the node data structure of the node layer.

[0008] In some embodiments, mapping each node layer of the decision tree to the corresponding pipeline level of the tree pipeline includes: If the node data structure is an internal node structure, then the node data structure is stored in internal memory; If the node data structure is a leaf node structure, then the node data structure is stored in the leaf memory, wherein the internal memory and the leaf memory are different memory blocks on the FPGA.

[0009] In some embodiments, the internal node structure includes field identifiers, field values, and pointers; The field identifier is used to specify the header fields of the data packets to be inspected; The field value is a comparison value used to make branch decisions; The pointer points to the address of the next child node in the pipeline hierarchy.

[0010] In some embodiments, the leaf node structure includes a rule validity bit, a field value, and a field length; The valid rule bits are bitmasks used to indicate valid rules in leaf nodes; The field values ​​are used to indicate the complete matching condition specifications for each rule on each field; The field length is used to indicate the prefix length corresponding to each field.

[0011] In some embodiments, the pipeline stage includes node RAM and node logic units, and guiding the preset data packet to traverse each pipeline stage of the tree pipeline until the preset data packet reaches the target leaf node of the decision tree includes: The node logic unit reads the node data structure from the node RAM, compares the node data structure with the header of the preset data packet, determines the address of the corresponding node in the node RAM of the next pipeline stage based on the comparison result, and directs the preset data packet to the node corresponding to the address. The process of repeatedly reading the node data structure from the node RAM through the node logic unit, comparing the node data structure with the header of the preset data packet, determining the address of the corresponding node in the node RAM of the next pipeline stage based on the comparison result, and directing the preset data packet to the node corresponding to the address is repeated until the preset data packet reaches the target leaf node of the decision tree.

[0012] In some embodiments, the method further includes: When the cache rule set is updated, the structural changes of the decision tree forest are calculated by an online rule update agent, a memory access sequence is generated, and the target pipeline level is determined. The memory access sequence includes an address and data to be written. The target pipeline-level update engine determines whether the target node corresponding to the address is located in the local node RAM. If the target node is located in the local node RAM, the node data structure of the target node is updated according to the data to be written.

[0013] In some embodiments, updating the node data structure of the target node based on the data to be written includes: Insert the write command to perform the update into the gap between packet processing cycles; During the interval, the memory port of the local node RAM is switched from read mode to write mode based on the write instruction, so as to update the node data structure of the target node according to the data to be written.

[0014] In some embodiments, the method further includes: Pre-configure an empty pipeline; When the decision tree forest space is insufficient, causing the insertion of a new rule to fail, the new rule is placed in the empty pipeline.

[0015] To achieve the above objectives, a second aspect of this application provides an FPGA-based software switch cache acceleration device, the device comprising: The tree building module is used to obtain the cache rule set of the software switch and compile the cache rule set into a decision tree forest through a decision tree building algorithm, wherein the decision tree forest includes multiple decision trees of the same depth; An FPGA resource mapping module is used to map the decision tree forest to multiple parallel tree pipelines, wherein the tree pipelines run on the FPGA, each tree pipeline corresponds to a decision tree, and each pipeline level of the tree pipeline corresponds to a node layer of the decision tree; The data packet broadcast module is used to broadcast preset data packets to all tree pipelines for parallel processing; The data packet traversal module is used to guide the preset data packet to traverse each pipeline stage of the tree pipeline for each tree pipeline until the preset data packet reaches the target leaf node of the decision tree; The matching module is used to perform parallel rule matching on the preset data packet at the target leaf node of each decision tree to obtain the target caching rule that matches the preset data packet.

[0016] This application proposes an FPGA-based software switch cache acceleration method and related apparatus. It obtains the cache rule set of the software switch and compiles it into a decision tree forest using a decision tree construction algorithm. This transforms a complete set of flow rules into a series of compact, balanced, and independent decision trees, enabling classification of a large-scale rule set based on multiple parallel trees. The core of the cache classification acceleration is a hardware-accelerated classifier on the FPGA. This classifier consists of multiple parallel pipelines, each pipeline stage corresponding to a node layer of the decision tree. This multi-pipeline parallel processing architecture is the foundation for ensuring system scalability and performance improvement. This architecture allows for parallel processing of multiple decision trees generated by the software algorithm, thereby accelerating flow table cache classification. To achieve fast packet classification and matching, preset packets are broadcast to all tree pipelines for parallel processing. For each tree pipeline, the preset packets are guided to traverse each pipeline stage until they reach the target leaf node of the decision tree. Parallel rule matching is performed on the preset packets at each target leaf node to obtain the target cache rule matching the preset packets, thus accelerating the flow table cache classification task. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall architecture of the software switch caching acceleration system provided in the embodiments of this application; Figure 2This is a flowchart of the FPGA-based software switch cache acceleration method provided in the embodiments of this application; Figure 3 yes Figure 2 The flowchart of step S210 in the process; Figure 4 This is a schematic diagram illustrating the process of constructing a decision tree using the MegaTree algorithm provided in this application embodiment; Figure 5 This is a schematic diagram of the multi-pipeline parallel processing architecture provided in the embodiments of this application; Figure 6 This is a schematic diagram of the internal structure of a single tree pipeline provided in an embodiment of this application; Figure 7 yes Figure 2 The flowchart of step S220 in the text; Figure 8 yes Figure 7 The flowchart of step S720 in the process; Figure 9 This is a schematic diagram of the storage organization of the hardware node data structure provided in the embodiments of this application; Figure 10 yes Figure 2 The flowchart of step S220 in the text; Figure 11 This is a schematic diagram of the architecture of the intermediate layer module provided in the embodiments of this application; Figure 12 This is a schematic diagram of the architecture of the leaf layer module provided in an embodiment of this application; Figure 13 This is another flowchart of the FPGA-based software switch cache acceleration method provided in the embodiments of this application; Figure 14 yes Figure 13 The flowchart of step S1330 in the text; Figure 15 This is another flowchart of the FPGA-based software switch cache acceleration method provided in the embodiments of this application; Figure 16 This is a complete example flowchart of rule processing and hardware configuration provided in the embodiments of this application; Figure 17 This is a schematic diagram of the non-blocking interleaved dynamic update mechanism provided in the embodiments of this application; Figure 18 This is a schematic diagram of the structure of the FPGA-based software switch cache acceleration device provided in the embodiments of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0021] With the increasing demands on network infrastructure from cloud computing and big data analytics, Software-Defined Networking (SDN) technology has been widely adopted. Software switches, as de facto virtual switches in cloud platforms and data centers, directly impact the throughput and latency characteristics of the entire network system. To provide service flexibility, existing software switches typically employ a multi-table pipeline architecture. While this architecture improves service flexibility, it incurs significant performance overhead, making it difficult to meet the performance requirements of high-speed network environments. Therefore, software switches commonly employ caching mechanisms to accelerate packet classification processing, caching frequently matching flow rules in a large, single flow table to reduce the processing overhead of multi-table pipelines through fast lookups. The flow table cache classifier is the core component of flow table cache classification in software switches, responsible for quickly classifying and matching packets. However, the flow table cache classifier suffers from the following technical problems: 1. Poor scalability: Existing flow table cache classifiers use the classic algorithm based on tuple space search. As the rule dimension and number of rules increase, the number of generated tuples grows exponentially, leading to the "tuple explosion" problem, which severely restricts the scalability of the system.

[0022] 2. High CPU (Central Processing Unit) resource consumption: Continuous packet classification, flow entry management, and cache maintenance operations consume a lot of CPU and memory resources, causing resource contention, reducing the host system capacity, and affecting the overall system performance.

[0023] 3. Poor dynamic update performance: For large-scale, dynamically changing rule sets, existing methods struggle to support efficient dynamic rule updates while maintaining high classification throughput. Traditional FPGA (Field-Programmable Gate Array)-based acceleration solutions either do not support dynamic rule updates or the update operation severely impacts classification performance.

[0024] 4. Insufficient Hardware Acceleration Solutions: Existing FPGA-based acceleration solutions mainly fall into two categories: RTC (Run-to-Completion) architecture and pure pipelined architecture. While RTC architecture offers good flexibility, it suffers from low lookup efficiency and uncertain latency; pure pipelined architecture, while boasting high throughput, struggles to support incremental rule updates. None of the existing acceleration solutions are specifically designed for the characteristics of flow table caching.

[0025] Therefore, there is an urgent need for a hardware acceleration solution that can provide high classification throughput, support efficient dynamic rule updates, and is specifically optimized for large single tables in software switch caching.

[0026] Based on this, this application provides an FPGA-based software switch cache acceleration method and related apparatus, applicable to flow table cache classification acceleration scenarios in software switches such as Open vSwitch (OVS) and Vector Packet Processing (VPP). It aims to design an efficient hardware acceleration solution for large single tables in software switches, ensuring high classification throughput while supporting efficient and low-impact dynamic rule updates, and overcoming the problems of poor scalability and high resource consumption in existing solutions.

[0027] Please see Figure 1The FPGA-based software switch cache acceleration system provided in this application adopts a heterogeneous acceleration framework co-designed by CPU and FPGA, providing hardware eddy current boosters to accelerate the core cache large single table. Taking the OVS software switch as an example, the FPGA-based software switch cache acceleration system provided in this application includes two main components: a software OpenvSwitch layer and a cache acceleration device. The software OpenvSwitch layer receives user-configured OpenFlow rules and processes them through an OpenFlow pipeline. The software OpenvSwitch layer has built-in micro-single table classifiers and large single table classifiers, which together constitute the software flow classifier. When complex flow table cache classification tasks need to be processed, the software flow classifier offloads the task to the hardware classification accelerator through a flow offload mechanism. The cache acceleration device is the core component of this application and runs on the FPGA. The FPGA can be directly made into a SmartNIC, or it can be used as an additional acceleration chip to enhance traditional NICs. The caching acceleration device receives the stream rule set and update stream rules, constructs a decision tree forest and hardware configuration file through a stream classifier, and generates hardware write commands for online rule updates through an online rule update agent. The hardware classification accelerator contains multiple parallel pipelines, such as pipeline 1, pipeline 2, ..., pipeline N. Each pipeline contains multiple levels, including stage 0, stage 1, ..., stage M, and leaf nodes, forming a deep multi-level processing architecture.

[0028] Data packets in the input packet queue are directed to these pipelines, where their headers are processed in parallel. The hardware classification accelerator efficiently traverses a pre-loaded decision tree structure, matches flow rules for packets, and outputs a classification result, which is then used for packet forwarding decisions to forward packets to the corresponding output packet queue.

[0029] Figure 2 This is an optional flowchart of the FPGA-based software switch cache acceleration method provided in the embodiments of this application. Figure 2 The method may include, but is not limited to, steps S210 to S250.

[0030] Step S210: Obtain the cache rule set of the software switch, and compile the cache rule set into a decision tree forest using a decision tree construction algorithm, wherein the decision tree forest includes multiple decision trees of the same depth; Step S220: Map the decision tree forest to multiple parallel tree pipelines, wherein the tree pipelines run on the FPGA, each tree pipeline corresponds to a decision tree, and each pipeline level of the tree pipeline corresponds to a node layer of the decision tree. Step S230: Broadcast the preset data packet to all tree pipelines for parallel processing; Step S240: For each tree pipeline, guide the preset data packet to traverse each pipeline level of the tree pipeline until the preset data packet reaches the target leaf node of the decision tree; Step S250: Perform parallel rule matching on the preset data packet at the target leaf node of each decision tree to obtain the target caching rule that matches the preset data packet.

[0031] Existing flow table cache classifiers employ classic algorithms based on tuple space search to perform flow table cache classification tasks. As the rule dimension and number of rules increase, the number of generated tuples grows exponentially, leading to a tuple explosion problem that severely restricts system scalability. To address the poor scalability of flow table cache classifiers, this application's embodiment obtains the cache rule set of a software switch. On the CPU side, a flow classifier builds an agent to preprocess the cache rule set. A hardware-friendly decision tree construction algorithm is used to compile the cache rule set into a hardware-optimized decision tree forest data structure. The software switch can be OVS, VPP, etc., and the cache rule set contains multiple cache rules. These cache rules represent packet loss or backpressure strategies employed by the software switch when the cache is insufficient. The decision tree construction algorithm is the MegaTree algorithm, which aims to transform a complete set of flow rules into a series of compact, balanced, and independent decision trees. The decision tree forest consists of multiple decision trees, each with the same depth. By balancing the depth of the generated decision trees, the maximum depth of all trees is made as consistent as possible. This consistency is crucial for achieving predictable low-latency traversal in a parallel hardware pipeline, ensuring that these decision trees can be processed efficiently in parallel by FPGA hardware and preventing any single tree from becoming a processing bottleneck.

[0032] Please see Figure 3 In some embodiments, step S210 may include, but is not limited to, steps S310 to S340: Step S310: Using the HyperSplit algorithm, the current cache rule set is recursively divided into two balanced subsets at each layer node; Step S320: When the number of rules for a node is less than or equal to a preset threshold, the node is pushed down layer by layer to the maximum depth layer to become a leaf node. Step S330: During the splitting process, rules that need to be copied in multiple decision tree branches and rules that exceed the maximum rule capacity of leaf nodes are removed to obtain the remaining rule set; Step S340: For the remaining rule set, repeat the steps using the HyperSplit algorithm until all remaining rule sets have been processed, resulting in a decision tree forest.

[0033] In step S310 of some embodiments, the HyperSplit algorithm is used as the basis for recursively splitting the cache rule set. At each level node, the HyperSplit algorithm selects a dimension-threshold pair that produces the most balanced split, as the optimal split dimension d and split threshold t, and splits the current cache rule set into two balanced subsets, namely the left subset and the right subset. The HyperSplit algorithm performs subset partitioning based on a non-overlapping partitioning mechanism, which means that the same rule cannot appear in both the left and right subsets at the same time.

[0034] It should be noted that the inherent non-overlapping nature of cached rules significantly reduces rule duplication during tree construction, enabling the effective classification of large-scale rule sets using only multiple constructed parallel decision trees.

[0035] In step S320 of some embodiments, the segmentation process continues until the number of rules in a certain node is less than or equal to a preset threshold. At this point, the node is pushed down layer by layer to the maximum depth layer, becoming a leaf node containing the final subset of rules. This ensures that all leaf nodes are located at the same depth layer of the decision tree, thereby guaranteeing a fixed latency characteristic and facilitating subsequent pipeline-level synchronization and result merging. The remaining node layers can be filled using bubbles or no-operations to push nodes down layer by layer. The preset threshold is a pre-set threshold for the number of rules and can be set according to actual conditions; no specific limitation is made here.

[0036] In step S330 of some embodiments, the MegaTree algorithm involves two key iterative operations: non-overlapping splitting and rule eviction. A rule is evictioned under two conditions: (1) splitting the rule results in rule duplication; (2) adding the rule to a leaf node results in the leaf node exceeding its maximum rule capacity. Due to rule duplication or reaching the maximum rule capacity limit, some cached rules cannot be placed in the current decision tree. In this embodiment, rules that need to be copied in multiple decision tree branches and rules that exceed the maximum rule capacity of the leaf node are evictioned to obtain the remaining rule set. The rule eviction mechanism ensures that all rules in the current tree are unique, avoids rule duplication, and forms a compact and efficient tree structure.

[0037] In step S340 of some embodiments, steps S310 to S330 are performed on the remaining rule sets to construct multiple decision trees until all remaining rule sets have been processed, forming a decision tree forest.

[0038] Through steps S310 to S340 above, a hardware-friendly decision tree can be constructed, realizing the transformation from rule explosion to tree-based parallelism and improving system scalability.

[0039] Please see Figure 4Starting from the root node, a decision tree is built from top to bottom. For a given complete set of flow rules, at each level of the node, an optimal split dimension and split threshold are selected to split the rule set into a left subset and a right subset. When the node depth reaches the maximum depth, further splitting stops, and the node is marked as a leaf node. During the splitting process, if a rule is to be copied to multiple subtrees or the target leaf node has reached its maximum rule capacity, that rule is removed, resulting in a remaining set of flow rules to be processed in the next tree. This process is repeated to build N decision trees until there are no remaining flow rules, meaning all rules have been processed. It should be noted that the construction of each tree is independent and can be performed in parallel. After the decision tree is built, the cached rules in the leaf nodes can be updated with flow rules to obtain the updated results.

[0040] The flow table cache classifier performs continuous packet classification, flow entry management, and cache maintenance operations, which consumes a large amount of CPU and memory resources, causing resource contention, reducing the host system capacity, and affecting the overall system performance. To address the high resource consumption of flow table cache classification tasks, this application introduces an FPGA. Through a heterogeneous acceleration framework co-designed by CPU and FPGA, a hardware eddy current booster-like acceleration is provided for the large single-table cache of the software switch, overcoming the problems of poor scalability and high resource consumption in existing solutions while ensuring high classification throughput.

[0041] In step S220 of some embodiments, on the FPGA side, the decision tree forest constructed in step S110 is mapped to multiple parallel tree pipelines. Each tree pipeline is a deep pipeline engine running in parallel on the FPGA. Each tree pipeline corresponds to a decision tree, and each tree pipeline has a fixed number of pipeline stages, equal to the maximum configuration depth of the decision tree, ensuring that the clock cycles required for each data packet to pass through the tree pipeline are exactly the same and have a constant and deterministic latency. Each pipeline stage of the tree pipeline corresponds to a node layer of the decision tree. Each pipeline stage includes node RAM (Random Access Memory), node logic unit, and update engine. The node layer includes a root node layer, internal node layers, and leaf node layers. The internal node layer is the node layer located between the root node layer and the leaf node layer in the decision tree.

[0042] Please see Figure 5The FPGA acceleration engine employs a multi-pipeline parallel processing architecture. On the FPGA side, a top-level classifier is built, comprising N identical tree pipelines, each specifically processing one decision tree in the decision tree forest. An update interface establishes connections between the online rule update agent and the tree pipelines, forming dedicated update paths that support dynamic rule updates. A search interface searches for cached rules in the decision trees that match data packets. On the CPU side, operation commands are input, including data types and operations. Data types can be data packets or rules, and operations can include search, delete, and insert. A command separation module separates the operation commands into update and search instructions, sending update instructions to the update interface of specific tree pipelines to update node data for those pipelines. Search instructions are sent in parallel to the search interface of each tree pipeline to search for rules matching data packets, yielding search results for each decision tree. A multiplexer selects the first non-empty search result from the search results of multiple decision trees as the final search result, obtaining the target cached rule matching the data packet.

[0043] Please see Figure 6 The tree pipeline is divided into multiple stages, each stage being a pipeline level. Each pipeline level in the tree pipeline mirrors the corresponding node level. There is a one-to-one correspondence between the node levels and pipeline levels in the decision tree; for example, the root node matches stage 0, the first-level nodes match stage 1, the second-level nodes match stage 2, and leaf nodes match leaf nodes. The pipeline level at the root node level includes an update engine, registers, and node logic units. Except for the root node level, each node level's corresponding pipeline level includes an update engine, node RAM, and node logic units.

[0044] Please see Figure 7 In some embodiments, step S220 may include, but is not limited to, steps S710 to S720: Step S710: Generate a hardware configuration file for each decision tree, wherein the hardware configuration file includes pipeline configuration information of the decision tree and node data structure of each node in each node layer of the decision tree. Step S720: For each decision tree, determine the tree pipeline corresponding to the decision tree according to the pipeline configuration information, and map each node layer of the decision tree to the pipeline level corresponding to the tree pipeline. The pipeline level includes node RAM, which is used to store the node data structure of the node layer.

[0045] In step S710 of some embodiments, on the CPU side, an agent built by the stream classifier generates a corresponding hardware configuration file for each decision tree. The hardware configuration file includes pipeline configuration information for the decision tree and node data structures for each node in each node layer of the decision tree. The pipeline configuration information is used to indicate the tree pipeline corresponding to the decision tree. The node data structures are used to describe the business logic and information actually carried by the node.

[0046] In step S720 of some embodiments, for each decision tree, the tree pipeline corresponding to the decision tree is determined according to the pipeline configuration information, and the node data structure of each node in each node layer of the decision tree is stored in the node RAM of the corresponding pipeline level of the node layer.

[0047] The node RAM is a true dual-port RAM module. Each of the two independent read ports of the node RAM serves a complete and independent tree pipeline, allowing the two independent tree pipelines to share the same RAM. This allows two data packets to be processed simultaneously and asynchronously through the same set of rules, doubling the throughput without increasing memory usage. Given the scarcity of FPGA memory, this is a crucial advantage.

[0048] Through steps S710 to S720, each tree pipeline is dedicated to processing one decision tree in the decision tree forest, thus accelerating the classification of large single tables in the cache.

[0049] Please see Figure 8 In some embodiments, step S720 may include, but is not limited to, step S810 or step S820: Step S810: If the node data structure is an internal node structure, then store the node data structure in internal memory. Step S820: If the node data structure is a leaf node structure, then the node data structure is stored in the leaf memory, where the internal memory and the leaf memory are different memory blocks on the FPGA.

[0050] In step S810 of some embodiments, the nodes in the decision tree include a root node, internal nodes, and leaf nodes. The node data structure is divided into two categories: internal node structure and leaf node structure. An internal node is a node located between the root node and a leaf node, and its data structure contains the decision logic for data packet traversal. If the node data structure is an internal node structure, it is stored in internal memory.

[0051] In step S820 of some embodiments, the leaf node structure is the node data structure of the leaf node. If the node data structure is a leaf node structure, then the leaf node structure is stored in the leaf memory. The internal memory and the leaf memory are different memory blocks on the FPGA.

[0052] Steps S810 to S820 above, by separating internal nodes and leaf nodes into different memory blocks, enable parallel access and efficient resource utilization on the FPGA.

[0053] In step S230 of some embodiments, a preset data packet is broadcast to all N tree pipelines for parallel processing.

[0054] Design hardware-optimized node data structures to support high-speed parallel access and efficient memory utilization. See also... Figure 9 The node data structures of multiple internal nodes (node ​​0, node 1, ..., node m, etc.) located in the same node layer are stored in the intermediate layer memory block, while the node data structures of multiple leaf nodes (leaf 0, leaf 1, ..., leaf n, etc.) located in the same node layer are stored in the leaf layer memory block. By separating internal nodes and leaf nodes into different memory blocks, parallel access and efficient FPGA resource utilization can be achieved.

[0055] Each internal node's internal node structure includes three key fields: a field identifier, a field value, and a pointer. This compact structure facilitates single-cycle decisions at each pipeline level. The field identifier specifies the packet header field to be inspected, such as the source IP or destination IP. The field value is a comparison value used to make branching decisions; for example, a threshold of 7 determines whether a packet is routed to the left or right child node based on the comparison result. The pointer points to the address of the next child node in the pipeline hierarchy, i.e., the address of the next pipeline level child node.

[0056] Each leaf node's structure is designed to store multiple rules in a single memory address, supporting parallel rule matching. Each leaf node contains multiple rules (rule[0] to rule[j]) and includes rule validity bits, field values, and field lengths. That is, the leaf node structure includes multiple rules, rule validity bits for each rule, field values, and field lengths. The rule validity bits are bitmasks used to indicate valid rules in the leaf node, i.e., which rule entries in the leaf node are valid. The field values ​​indicate the complete matching condition specification for each rule across k fields. The field length is the prefix length corresponding to each field, supporting wildcard matching. Figure 9 As shown, Leaf 1 sets multiple field values ​​including field value [0] to field value [k] and the field length of each field (field length [0] to field length [k]).

[0057] By optimizing the hardware node structure, high-speed parallel access and efficient memory utilization are achieved, while maintaining scalability to accommodate diverse OVS rule sets. Furthermore, this complete representation of the hardware node structure is maintained in software, enabling dynamic updates and regeneration of hardware configuration files when rule sets change.

[0058] Please see Figure 10 In some embodiments, step S240 may include, but is not limited to, steps S1010 to S1020: Step S1010: Read the node data structure of the node from the node RAM through the node logic unit, compare the node data structure with the header of the preset data packet, determine the address of the corresponding node in the node RAM of the next pipeline stage according to the comparison result, and direct the preset data packet to the node corresponding to the address. Step S1020: Repeat the steps of reading the node data structure from the node RAM through the node logic unit, comparing the node data structure with the header of the preset data packet, determining the address of the corresponding node in the node RAM of the next pipeline stage based on the comparison result, and directing the preset data packet to the node corresponding to the address, until the preset data packet reaches the target leaf node of the decision tree.

[0059] In step S1010 of some embodiments, such as Figure 6 As shown, after a data packet is input into the tree pipeline, the node data structure of the node is read from the node RAM by the node logic unit of the current pipeline level. The node data structure obtained from the node RAM is compared with the header of the input data packet. Based on the comparison result, the address of the node in the node RAM of the next pipeline level is determined, and the data packet is directed to the node corresponding to the address.

[0060] In step S1020 of some embodiments, all leaf nodes are located at the maximum depth layer (maxDepth layer) of the decision tree. Each data packet must traverse the entire maxDepth pipeline level, that is, the data packet needs to go through the internal node traversal of maxDepth-1 level and the leaf node matching of level 1 to complete the classification. Step S1010 is repeated until the data packet reaches the target leaf node of the decision tree.

[0061] Through the above steps S1010 to S1020, it is ensured that each data packet has a fixed delay characteristic when passing through the tree pipeline.

[0062] like Figure 11 As shown, each intermediate layer module implements an internal node of the decision tree. This module receives configuration data (address) and packet headers, and processes them through multi-level comparison logic. Specifically, it selects from the input packet headers... , , , , , The multiplexer identifies the packet header fields to be inspected from among multiple fields based on their identifiers. A comparator then performs parallel comparisons of these packet header fields with the field values ​​configured in the node's RAM. Another multiplexer generates the address of the next node based on the comparison result. If the comparison result indicates that the packet is routed to the left child node, the address pointed to by the pointer is output. If the comparison result indicates that the packet is routed to the right child node, an offset is added to the pointer, and the address pointed to by the offset pointer is output. The intermediate layer module ensures deterministic latency through its pipelined design, while the write enable control signal supports dynamic rule updates, minimizing the impact on packet processing.

[0063] In step S250 of some embodiments, when a data packet arrives at the target leaf node of the decision tree, the node logic unit triggers multiple parallel matching units to perform parallel rule matching on the data packet. The cache rules in the flow table cache classifier do not overlap, and each data packet finds at most one matching cache rule in the parallel decision tree. In the multi-tree merging stage, a simple selector (MUX) is used to select a cache rule that matches the data packet from the matching results of multiple decision trees as the target cache rule, without requiring complex priority parsing logic. The target cache rule is used to make forwarding decisions for the data packet. It should be noted that if no tree pipeline finds a cache rule that matches the data packet, a no-match flag is output, and the data packet will fall back to the software pipeline for further processing.

[0064] Please see Figure 12 , Figure 12 The design of the leaf module is illustrated. The leaf module terminates tree traversal and produces the final classification result. The leaf module has multiple matching units that evaluate different rule conditions in parallel and select the appropriate output from valid matches via a multiplexer. A dedicated update interface supports online updates to the rule set.

[0065] For large-scale, dynamically changing rule sets, existing solutions struggle to support efficient dynamic rule updates while maintaining high classification throughput. Traditional FPGA-based acceleration solutions either don't support dynamic updates or the update operation severely impacts classification performance, resulting in poor dynamic rule update performance. Existing FPGA-based acceleration solutions mainly fall into two categories: RTC architecture and pure pipelined architecture. While RTC architecture offers good flexibility, it suffers from low lookup efficiency and uncertain latency; pure pipelined architecture, while offering high throughput, struggles to support incremental rule updates. Furthermore, existing acceleration solutions are not specifically designed for the characteristics of flow table caching. To address the issues of poor dynamic rule update performance and insufficient hardware acceleration solutions, this application proposes a hardware acceleration solution that supports efficient dynamic rule updates and is specifically optimized for large single-table caching in software switches.

[0066] Please see Figure 13 In some embodiments, the method may also include, but is not limited to, steps S1310 to S1330: Step S1310: When the cache rule set is updated, the structure change of the decision tree forest is calculated by the online rule update agent, a memory access sequence is generated, and the target pipeline level is determined. The memory access sequence includes the address and the data to be written. Step S1320: Determine whether the target node corresponding to the address is located in the local node RAM through the target pipeline-level update engine; Step S1330: If the target node is located in the local node RAM, the node data structure of the target node is updated according to the data to be written.

[0067] In step S1310 of some embodiments, an online rule update agent is set up on the CPU side. This agent manages incremental rule updates. Updates include operations such as insertion, deletion, and modification. Based on the principle of no rule duplication, each rule is stored only once in a node of a single tree. This ensures that any rule insertion, deletion, or modification only affects a local point in the data structure, ensuring high packet classification throughput even during the most frequent cache updates. The MegaTree algorithm can identify the specific trees and nodes affected by the update and recalculate the necessary branches within microseconds to generate the corresponding hardware configuration update. Specifically, when the cache rule set is updated, the necessary changes to the MegaTree structure are calculated by the online rule update agent, generating the corresponding memory access sequence and determining the target pipeline stage affected by the update. The memory access sequence includes the address of the node affected by the update and the data to be written.

[0068] In step S1320 of some embodiments, the update mechanism operates through a dedicated path connecting the online rule update agent and the hardware pipeline. This dedicated update path directly sends update commands to the target pipeline level of the affected specific pipeline, achieving precise target location without interfering with unrelated processing elements. The update engine of the target pipeline level receives the update command through an update interface and determines whether the target node corresponding to the address is located in the local node RAM of the target pipeline level.

[0069] In step S1330 of some embodiments, if the target node is located in the local node RAM, the node data structure of the target node is updated according to the data to be written, without blocking the data packet processing path.

[0070] Through steps S1310 to S1330, update operations can be seamlessly integrated into the normal packet processing flow without pipeline bubbles or pause penalties. Each update typically involves modifying only a few nodes, so the impact on overall throughput is negligible. The latency and throughput impacts are bounded and predictable, making it ideal for large-scale, dynamic cloud environments.

[0071] Please see Figure 14 In some embodiments, step S1330 may include, but is not limited to, steps S1410 to S1420: Step S1410: Insert the write instruction to perform the update into the gap between data packet processing cycles; In step S1420, during the gap, the memory port of the local node RAM is switched from read mode to write mode based on the write instruction, so as to update the node data structure of the target node according to the data to be written.

[0072] In step S1410 of some embodiments, the core of the update mechanism lies in the interleaving of write operations with normal packet processing. The system strategically inserts write instructions to perform updates into the gaps between packet processing cycles to utilize idle memory port bandwidth to complete rule updates without pausing any pipeline.

[0073] In step S1420 of some embodiments, this interleaved execution mechanism is designed so that port B (the second port) of the node RAM can switch to write mode to perform update operations at specific intervals while serving read requests for a pipeline. Specifically, during the interval, port B of the local node RAM switches from read mode to write mode based on a write instruction to update the node data structure of the target node according to the data to be written, and then immediately resumes normal read service, making the entire process transparent to packet processing.

[0074] like Figure 11 and Figure 12 As shown, when it is necessary to update the node data structure, the memory write enable is controlled according to the write enable and the pipeline stage, and the RAM data is written to the node RAM to realize the update of the node data.

[0075] Steps S1410 to S1420 above employ a non-blocking staggered update mechanism, which supports dynamic rule updates while ensuring high classification throughput.

[0076] Please see Figure 15 In some embodiments, the method may also include, but is not limited to, steps S1510 to S1520: Step S1510: Pre-configure an empty pipeline; Step S1520: When the decision tree forest space is insufficient and the insertion of a new rule fails, place the new rule in an empty pipeline.

[0077] In step S1510 of some embodiments, a fault-tolerance mechanism is set up to ensure reliable classifier construction and rule updates, thus ensuring system availability. An empty pipeline is pre-configured as a guaranteed placement location.

[0078] In step S1520 of some embodiments, when a new rule fails to be inserted due to insufficient space in the existing tree, whether during the initial tree construction or during subsequent dynamic updates, the new rule can be placed in this reserved empty pipeline, thereby maintaining system availability without interrupting packet processing.

[0079] Steps S1510 to S1520 above can maintain system availability without interrupting data packet processing by setting up a fault tolerance mechanism.

[0080] Please see Figure 16 , Figure 16 A concrete example is presented to trace the entire process of stream rules from software data structures to hardware pipeline configuration. This example demonstrates how the MegaTree algorithm transforms a set of rules into an optimized decision tree structure, and how this structure can be deployed on an FPGA for high-speed classification.

[0081] The complete process of this application embodiment includes: the CPU receives the stream rule set and compiles it into a fixed-depth decision tree forest using the MegaTree algorithm; a hardware configuration file (node ​​data structure mapping, pipeline configuration information, address mapping table) is generated for each decision tree in the decision tree forest, and the node data structure is loaded into the FPGA's BRAM (Block Random Access Memory), configuring pipeline parameters and result merging logic; the packet header is broadcast to all tree pipelines for parallel processing, each pipeline traverses to the leaf node level at a fixed depth for rule matching, and the first non-empty matching result is selected as the final classification result during the merging stage; when the rule set changes, the online rule update agent calculates the affected node changes and updates the hardware configuration during packet processing intervals through a non-blocking interleaved update mechanism to maintain processing continuity.

[0082] like Figure 16As shown in the first layer, the MegaTree algorithm starts with a set of rules {R1, R2, R3, R4, R5, R6, R7, R8, R9, R10}. It applies the HyperSplit method with non-overlapping splitting and rule removal strategies to build a balanced decision tree. The flow rule set is recursively split into left and right subsets based on the value of field X until the maximum depth is reached, thus building the first tree. For example, at the root node, rules are split based on the field value 7, with rules less than or equal to 7 assigned to the left subset and rules greater than 7 assigned to the right subset. During the splitting process, rules that need to be replicated in multiple decision tree branches (such as R5 and R4) and rules exceeding the rule capacity of leaf nodes (such as R8) are removed and deferred to the next iteration. For the removed rules, the removed rules are recursively split based on the values ​​of fields X and Y until the maximum depth is reached, thus building the second tree. Since all rules have been processed, the tree building process ends. The kick-out mechanism ensures the reasonable distribution of conflict rules and eliminates duplicates in leaf nodes.

[0083] like Figure 16 The second layer, as shown, illustrates the software representation of the decision tree. Each node in the tree is implemented as a structured data element, containing field identifiers (such as field X, field Y), comparison values ​​(such as 3, 11), and pointers to child nodes. The root node and internal nodes (intermediate nodes) perform branch decisions, while leaf nodes store the actual rules to be applied when data packets arrive during traversal. This complete representation is maintained in software to allow for dynamic updates and regeneration of hardware profiles when the rule set changes.

[0084] like Figure 16 The third layer, as shown, demonstrates hardware instantiation, directly mapping the software decision tree to a multi-stage parallel processing pipeline architecture. The first tree module implements the first tree across multiple pipeline stages. The root module (stage 0) stores the comparison value (7) of the root node in a register for immediate access, while the intermediate layer module (stage 1) stores internal node data in block RAM. The leaf layer module (final stage) contains the actual rules distributed across different memory locations. The parallel second tree module demonstrates the system's ability to process multiple trees simultaneously. This modular design allows each stage to contribute to the classification decision as packets flow through the pipeline stages until the final rule match is identified in the leaf stage.

[0085] This application's embodiments achieve a sustained classification throughput of over 500 MPPS (Million Packets Per Second) on a 100K rule set through a multi-pipeline parallel processing architecture and a hardware-optimized decision tree structure, far exceeding the classification performance of existing solutions, thus achieving high classification throughput. Furthermore, the use of decision tree forests and multi-tree parallel processing architecture effectively handles large-scale, high-dimensional rule sets, avoiding the tuple explosion problem of traditional tuple space search, and exhibiting strong scalability. Simultaneously, a non-blocking interleaved update mechanism is employed, achieving microsecond-level incremental rule updates with an update throughput of 300-500 KUPS (Thousands of Updates Per Second), while the impact of update operations on classification performance is negligible, thus enabling efficient dynamic rule updates. This application's embodiments, through a fixed-depth pipeline design, ensure that the processing latency of each data packet is deterministic, which is crucial for real-time network applications. Furthermore, the hardware resource consumption of this embodiment is significantly lower than existing solutions, using only approximately 27,000 LUTs (Look-Up Tables) and approximately 49,000 registers, far lower than other FPGA acceleration solutions of similar scale, with resource utilization controlled within 3-4%. The node data structure and memory organization method of this embodiment are specifically designed for FPGA hardware characteristics, fully utilizing the FPGA's parallel processing capabilities and on-chip memory resources. The hardware eddy current booster, serving as a software switch cache, can be seamlessly integrated with existing software switch architectures, achieving high system integration and transparent acceleration of flow table caching classification tasks.

[0086] Through the implementation of the above-described FPGA-based software switch caching acceleration method, the embodiments of this application achieve the following performance on a Xilinx Virtex UltraScale+ FPGA: (1) Classification throughput: A sustained classification throughput of approximately 500 MPPS was achieved across 12 different 100K rule sets, demonstrating excellent and consistent performance. The rule sets included Access Control List (ACL) rule sets, Firewall (FW) rule sets, Inter-Process Communication (IPC) rule sets, etc.

[0087] (2) Update throughput: Under the extreme condition of temporarily disabling a pipeline, the system concentrates all hardware and software resources on continuous update operations, achieving an update throughput of 300-500 KUPS. This performance index is significantly higher than the actual OVS system's requirements for flow table update performance.

[0088] (3) Resource utilization: CLB LUTs (Configurable Logic Block Look-Up Tables): 3.23%-3.54%; CLB Registers (Configurable Logic Block Registers): 2.05%-2.32%; BRAM (Block Random Access Memory): 29.17%-31.71%; LUTRAM (Look-Up Table Random Access Memory): 0.21%-0.39%; Maximum operating frequency: 250.38 MHz-254.39 MHz, the maximum operating frequency exceeds the target frequency, the target frequency is 250 MHz.

[0089] (4) Performance advantages: It achieves a throughput increase of 2.9-11 times, while reducing LUT utilization by 47-95%. It is the first decision tree-based FPGA accelerator specifically designed for software switch flow table cache classifier offloading, and also the first solution to achieve microsecond-level incremental rule updates in a pipeline architecture.

[0090] Please see Figure 17 This application employs a non-blocking interleaved update mechanism for rule updates, with an online rule update agent connected to the hardware pipeline via a dedicated path. When a rule update occurs, such as inserting rule 11, inserting rule 12, or deleting rule 7, the online rule update agent calculates the necessary changes to the MegaTree structure and generates the corresponding memory access sequence. For example, when inserting rule 11, the online rule update agent calculates that the second leaf node of the first tree has changed, generates a memory access sequence, and includes the data to be written (rule 11) and the address (the address of the second leaf node), determining that the affected pipeline stage is the leaf layer module of the first tree module. This process is completed within microseconds, and the update instruction is directly sent to the affected pipeline stage to update the node data structure stored in the RAM of that pipeline stage node, achieving precise target positioning. Because the update operation is seamlessly integrated into the normal packet processing flow, there are no pipeline bubbles or pause penalties. Each update typically involves modifying only a few nodes, so the impact on overall throughput is negligible, and the latency and throughput impacts are bounded and predictable.

[0091] The embodiments of this application are applicable to the following application scenarios: (1) Cloud computing data centers: providing high-performance packet classification acceleration for software switches such as Open vSwitch, and improving virtual network performance. (2) SDN networks: supporting large-scale SDN network environments with dynamic rule updates to meet flexible business needs. (3) Edge computing: reducing CPU load and improving overall system performance through hardware acceleration in edge computing scenarios. (4) 5G networks: supporting high-performance packet processing requirements in NFV (Network Functions Virtualization) scenarios in 5G networks.

[0092] Please see Figure 18 This application also provides an FPGA-based software switch cache acceleration device, which can implement the above-mentioned FPGA-based software switch cache acceleration method. The FPGA-based software switch cache acceleration device includes: The tree building module 1810 is used to obtain the cache rule set of the software switch and compile the cache rule set into a decision tree forest through the decision tree building algorithm. The decision tree forest includes multiple decision trees of the same depth. The FPGA resource mapping module 1820 is used to map the decision tree forest to multiple parallel tree pipelines, wherein the tree pipelines run on the FPGA, each tree pipeline corresponds to a decision tree, and each pipeline level of the tree pipeline corresponds to a node layer of the decision tree. The packet broadcast module 1830 is used to broadcast preset data packets to all tree pipelines for parallel processing. The data packet traversal module 1840 is used to guide the preset data packet to traverse each pipeline level of the tree pipeline for each tree pipeline until the preset data packet reaches the target leaf node of the decision tree. The matching module 1850 is used to perform parallel rule matching on the preset data packets at the target leaf node of each decision tree to obtain the target caching rules that match the preset data packets.

[0093] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0094] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0095] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0096] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0097] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0098] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0099] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0100] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0101] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0102] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0103] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A software switch cache acceleration method based on FPGA, characterized in that, The method includes: The cache rule set of the software switch is obtained, and the cache rule set is compiled into a decision tree forest through a decision tree construction algorithm, wherein the decision tree forest includes multiple decision trees of the same depth; The decision tree forest is mapped to multiple parallel tree pipelines, wherein the tree pipelines run on an FPGA, each tree pipeline corresponds to a decision tree, and each pipeline stage of the tree pipeline corresponds to a node layer of the decision tree. Broadcast the preset data packets to all tree pipelines for parallel processing; For each tree pipeline, the preset data packet is guided to traverse each pipeline stage of the tree pipeline until the preset data packet reaches the target leaf node of the decision tree; Parallel rule matching is performed on the preset data packet at the target leaf node of each decision tree to obtain the target caching rule that matches the preset data packet.

2. The method according to claim 1, characterized in that, The process of compiling the cache rule set into a decision tree forest using a decision tree construction algorithm includes: The HyperSplit algorithm is used to recursively split the current cache rule set into two balanced subsets at each level node; When the number of rules for a node is less than or equal to a preset threshold, the node is pushed down layer by layer to the maximum depth layer to become a leaf node; During the splitting process, rules that need to be copied in multiple decision tree branches and rules that exceed the maximum rule capacity of leaf nodes are removed to obtain the remaining rule set; For the remaining rule set, the steps using the HyperSplit algorithm are repeated until all remaining rule sets have been processed, resulting in the decision tree forest.

3. The method according to claim 1, characterized in that, The process of mapping the decision tree forest to multiple parallel tree pipelines includes: Generate a hardware configuration file for each decision tree, wherein the hardware configuration file includes pipeline configuration information of the decision tree and node data structure of each node in each node layer of the decision tree; For each decision tree, the tree pipeline corresponding to the decision tree is determined according to the pipeline configuration information, and each node layer of the decision tree is mapped to the pipeline level corresponding to the tree pipeline. The pipeline level includes a node RAM, which is used to store the node data structure of the node layer.

4. The method according to claim 3, characterized in that, The step of mapping each node layer of the decision tree to the corresponding pipeline level of the tree pipeline includes: If the node data structure is an internal node structure, then the node data structure is stored in internal memory; If the node data structure is a leaf node structure, then the node data structure is stored in the leaf memory, wherein the internal memory and the leaf memory are different memory blocks on the FPGA.

5. The method according to claim 4, characterized in that, The internal node structure includes field identifiers, field values, and pointers; The field identifier is used to specify the header fields of the data packets to be inspected; The field value is a comparison value used to make branch decisions; The pointer points to the address of the next child node in the pipeline hierarchy.

6. The method according to claim 4, characterized in that, The leaf node structure includes rule validity bits, field values, and field lengths; The valid rule bits are bitmasks used to indicate valid rules in leaf nodes; The field values ​​are used to indicate the complete matching condition specifications for each rule on each field; The field length is used to indicate the prefix length corresponding to each field.

7. The method according to claim 3, characterized in that, The pipeline stage includes node RAM and node logic units. Guiding the preset data packet to traverse each pipeline stage of the tree pipeline until the preset data packet reaches the target leaf node of the decision tree includes: The node logic unit reads the node data structure from the node RAM, compares the node data structure with the header of the preset data packet, determines the address of the corresponding node in the node RAM of the next pipeline stage based on the comparison result, and directs the preset data packet to the node corresponding to the address. The process of repeatedly reading the node data structure from the node RAM through the node logic unit, comparing the node data structure with the header of the preset data packet, determining the address of the corresponding node in the node RAM of the next pipeline stage based on the comparison result, and directing the preset data packet to the node corresponding to the address is repeated until the preset data packet reaches the target leaf node of the decision tree.

8. The method according to any one of claims 1 to 7, characterized in that, The method further includes: When the cache rule set is updated, the structural changes of the decision tree forest are calculated by an online rule update agent, a memory access sequence is generated, and the target pipeline level is determined. The memory access sequence includes an address and data to be written. The target pipeline-level update engine determines whether the target node corresponding to the address is located in the local node RAM. If the target node is located in the local node RAM, the node data structure of the target node is updated according to the data to be written.

9. The method according to claim 8, characterized in that, The step of updating the node data structure of the target node based on the data to be written includes: Insert the write command to perform the update into the gap between packet processing cycles; During the interval, the memory port of the local node RAM is switched from read mode to write mode based on the write instruction, so as to update the node data structure of the target node according to the data to be written.

10. The method according to any one of claims 1 to 7, characterized in that, The method further includes: Pre-configure an empty pipeline; When the decision tree forest space is insufficient, causing the insertion of a new rule to fail, the new rule is placed in the empty pipeline.

11. A software switch cache acceleration device based on FPGA, characterized in that, The device includes: The tree building module is used to obtain the cache rule set of the software switch and compile the cache rule set into a decision tree forest through a decision tree building algorithm, wherein the decision tree forest includes multiple decision trees of the same depth; An FPGA resource mapping module is used to map the decision tree forest to multiple parallel tree pipelines, wherein the tree pipelines run on the FPGA, each tree pipeline corresponds to a decision tree, and each pipeline level of the tree pipeline corresponds to a node layer of the decision tree; The data packet broadcast module is used to broadcast preset data packets to all tree pipelines for parallel processing; The data packet traversal module is used to guide the preset data packet to traverse each pipeline stage of the tree pipeline for each tree pipeline until the preset data packet reaches the target leaf node of the decision tree; The matching module is used to perform parallel rule matching on the preset data packet at the target leaf node of each decision tree to obtain the target caching rule that matches the preset data packet.

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