Semiconductor device

Abstract

The invention relates to a semiconductor device. A semiconductor device includes: a gate structure disposed on a substrate; first spacers disposed on the substrate and disposed on two opposite sides of the gate structure; a second spacer disposed on the substrate outside the first spacer; a semiconductor layer disposed on the substrate and in contact with an outer surface of the second spacer; and a third spacer covering an upper surface of the gate structure, a side surface of the second spacer, and an upper surface of the semiconductor layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0169855, filed on November 25, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure generally relate to semiconductor technology, and more specifically to a semiconductor device. Background Technology

[0004] Semiconductor memory devices have attracted much attention as important components in the electronics industry due to their miniaturization, versatility, and / or low manufacturing cost. With the development of the electronics industry, the integration level of semiconductor memory devices is also increasing. To develop semiconductor memory devices with even higher integration levels, it is necessary to further reduce the linewidth included in these devices.

[0005] Furthermore, the dimensions of various other components included in memory devices (such as transistors) are also shrinking, thus reducing the size of each part that makes up these components. However, maintaining the performance characteristics of a device while shrinking the size of its components is extremely difficult. Therefore, new and improved solutions are needed. Summary of the Invention

[0006] Embodiments of this disclosure provide a semiconductor device capable of preventing component characteristic degradation due to process defects.

[0007] Embodiments of this disclosure provide a semiconductor device, comprising: a gate structure disposed on a substrate; a first spacer disposed on the substrate and disposed on opposite sides of the gate structure; a second spacer disposed on the substrate, outside the first spacer, and comprising SiCO, SiCON, SiCOH, or a combination thereof; a semiconductor layer disposed on the substrate and in contact with the outer surface of the second spacer; and a third spacer covering the upper surface of the gate structure, the side surface of the second spacer, and the upper surface of the semiconductor layer.

[0008] Embodiments of this disclosure provide a semiconductor device comprising: a substrate including a cell region and a peripheral region surrounding the cell region; and a peripheral transistor disposed in the peripheral region of the substrate, wherein the peripheral transistor includes: a gate structure disposed on the substrate; a plurality of spacers disposed on the substrate, located on a side surface of the gate structure, and at least partially comprising SiCO, SiCON, SiCOH, or combinations thereof; and a semiconductor layer disposed on the substrate and spaced apart from the gate structure in a direction parallel to the upper surface of the substrate.

[0009] Embodiments of this disclosure provide a semiconductor device including a gate structure disposed on a substrate and spacers covering the side and top surfaces of the gate structure. The spacers include a first spacer, a second spacer, a third spacer, and a fourth spacer. The first and second spacers are disposed on the substrate and on two opposite sides of the gate structure. The third spacer is disposed on the side surface of the second spacer and also on the top surfaces of the first and second spacers and the top surface of the gate structure. The fourth spacer is disposed between the second and third spacers and does not contact the substrate.

[0010] According to embodiments of this disclosure, the degradation of the component characteristics of semiconductor devices due to process defects can be prevented. Attached Figure Description

[0011] Figure 1 This is a view illustrating transistors included in a semiconductor device according to an embodiment of the present disclosure;

[0012] Figures 2 to 4 This is a view illustrating another transistor included in a semiconductor device according to an embodiment of the present disclosure;

[0013] Figure 5 and Figure 6 This is a view illustrating a semiconductor device according to an embodiment of the present disclosure;

[0014] Figures 7 to 15 This is a view illustrating a method for manufacturing a transistor included in a semiconductor device according to an embodiment of the present disclosure; and

[0015] Figures 16 to 21 This is a view illustrating another method for manufacturing transistors included in a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0016] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0017] In the accompanying drawings, the three directions parallel to the upper surface of the substrate are defined as the first direction FD, the second direction SD, and the third direction TD, respectively, and the direction projecting perpendicularly from the upper surface of the substrate is defined as the fourth direction VD. The first direction FD and the second direction SD may be substantially perpendicular to each other. The fourth direction VD is perpendicular to the first direction FD, the second direction SD, and the third direction TD. In the following description, "perpendicular" or "perpendicular direction" will be used to have substantially the same meaning as the fourth direction VD. The directions indicated by arrows in the figures and their opposites represent the same direction.

[0018] Figure 1This is a view illustrating transistors included in a semiconductor device according to an embodiment of the present disclosure.

[0019] Reference Figure 1 The semiconductor device 100 according to an embodiment of the present disclosure includes a substrate 101, an element isolation layer 102, and a first transistor TR.

[0020] Substrate 101 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. Substrate 101 may include a III-V group semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). Substrate 101 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof. In one embodiment, substrate 101 may be silicon doped with a group III element.

[0021] A device isolation layer 102 is disposed in the substrate 101. The device isolation layer 102 can be formed using trench device isolation techniques such as shallow trench isolation (STI).

[0022] The device isolation layer 102 may comprise a single layer or multiple layers. The device isolation layer 102 may comprise at least two elements selected from the group consisting of Si, O, N, C, and H. For example, the device isolation layer 102 may comprise silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0023] The first transistor TR is disposed on the substrate 101. The first transistor TR can be an NMOS (n-channel metal-oxide-semiconductor) transistor or a PMOS (p-channel metal-oxide-semiconductor) transistor. The first transistor TR includes a gate structure 103, an impurity region 104, source / drain regions 105 and 106, a semiconductor layer 107, and a spacer 120.

[0024] The gate structure 103 is located on the substrate 101 between the source / drain regions 105 and 106. The gate structure 103 includes a gate insulating layer 108, a work function adjustment layer 109, a first gate electrode 111, a second gate electrode 112, and a gate capping layer 113.

[0025] A gate insulating layer 108 is disposed on the substrate 101. The gate insulating layer 108 may be a single layer or multiple layers. The gate insulating layer 108 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric, or a combination thereof.

[0026] A work function adjustment layer 109 is disposed on the gate insulating layer 108. The work function adjustment layer 109 can be a single layer or multiple layers. The work function adjustment layer 109 can be formed of a metal, a metal nitride, a metal carbide, a conductor including metal atoms, or a combination thereof.

[0027] The first gate electrode 111 is disposed on the work function adjustment layer 109. The first gate electrode 111 may include a conductive material, such as a metal, a metal nitride, a metal silicide, polysilicon, conductive carbon, or a combination thereof. In one embodiment, the first gate electrode 111 may be doped polysilicon.

[0028] A second gate electrode 112 is disposed on the first gate electrode 111. The second gate electrode 112 includes barrier layers 112a and 112b and an electrode layer 112c. The barrier layers 112a and 112b and the electrode layer 112c may include conductive materials, such as metals, metal nitrides, metal silicides, polycrystalline silicon, conductive carbon, or combinations thereof. In one embodiment, the barrier layers 112a and 112b may include at least one stacked structure selected from tungsten nitride (WNx), silicon tungsten nitride (WSiN), tantalum / titanium nitride (Ta / TiN), titanium / titanium nitride (Ti / TiN), magnesium / titanium nitride (Mg / TiN), and strontium / titanium nitride (Sr / TiN). In one embodiment, the electrode layer 112c may include W, Mo, Au, Cu, Al, Ni, or Co.

[0029] A gate capping layer 113 is disposed on the second gate electrode 112. In one embodiment, the gate capping layer 113 may include silicon nitride.

[0030] Source / drain regions 105 and 106 are disposed in substrate 101. In one embodiment, source / drain regions 105 and 106 may comprise single-crystal silicon having N-type impurities. N-type impurities may comprise P, As, or a combination thereof.

[0031] Impurity region 104 is located between source / drain regions 105 and 106. Impurity region 104 is a region doped with impurities and may include impurities at a higher concentration than those on substrate 101. In one embodiment, impurity region 104 may include a lightly doped drain (LDD) region and a halo-doped region. The halo-doped region involves a higher concentration of dopant.

[0032] Spacer 120 is disposed on the side surface of gate structure 103. Spacer 120 includes a first spacer 121, a second spacer 122 and a third spacer 123.

[0033] A first spacer 121 is disposed on a side surface of the gate structure 103. The first spacer 121 is in contact with the side surface of the gate structure 103. In one embodiment, the first spacer 121 may cover the entire side surface of the gate structure 103. The lower surface of the first spacer 121 is in contact with the upper surface of the substrate 101. The lower surface of the first spacer 121 may be in contact with an impurity region 104 in the substrate 101. The first spacer 121 may include silicon nitride, silicon carbide, silicon oxide, or a combination thereof. In one embodiment, the first spacer 121 may be silicon nitride. In another embodiment, the first spacer 121 may include silicon oxycarbonate (SiCO), silicon oxycarbonitrile (SiCON), silicon oxyhydrocarbon (SiCOH), or a combination thereof.

[0034] A second spacer 122 is disposed on the outer surface of the first spacer 121. In one embodiment, the second spacer 122 may cover the entire outer surface of the first spacer 121. The second spacer 122 is in contact with the upper surface of the substrate 101. The lower surface of the second spacer 122 may be in contact with the impurity region 104 in the substrate 101. In one embodiment, the lower surface of the second spacer 122 may be located at a position lower than the lower surface of the first spacer 121. The second spacer 122 may include silicon nitride, silicon carbide, silicon oxide, or a combination thereof. In one embodiment, the second spacer 122 may include silicon carbide (SiCO), silicon carbonitride (SiCON), silicon oxyhydrocarbon (SiCOH), or a combination thereof. A semiconductor layer 107 is disposed on the outer surface of the second spacer 122. The semiconductor layer 107 is disposed on the source / drain regions 105 and 106 of the substrate 101. The semiconductor layer 107 may be located at a position higher than the upper surface of the substrate 101. Semiconductor layer 107 may be an epitaxial layer formed using methods such as selective epitaxial growth (SEG). Semiconductor layer 107 may be a material layer capable of enhancing carrier mobility. In one embodiment, semiconductor layer 107 may include silicon germanium.

[0035] A third spacer 123 is disposed on the semiconductor layer 107, the second spacer 122, and the gate structure 103. The third spacer 123 may cover the upper surface of the semiconductor layer 107, the side and upper surfaces of the second spacer 122, and the upper surface of the gate structure 103. (Refer to...) Figure 1 The upper surface of the gate structure 103 may be formed by the top surface of the gate capping layer 113. The inner surface of the third spacer 123 may contact the second spacer 122. The third spacer 123 may include silicon nitride, silicon carbide, silicon oxide, or a combination thereof. In one embodiment, the third spacer 123 may be silicon nitride.

[0036] In one embodiment, the second spacer 122 may comprise a material with a dielectric constant less than that of the material forming the first spacer 121. For example, the first spacer 121 may comprise silicon nitride, while the second spacer 122 may comprise silicon oxycarbide (SiCO), silicon oxycarbonitrile (SiCON), silicon oxyhydrocarbon (SiCOH), or a combination thereof.

[0037] In another embodiment, the second spacer 122 may comprise the same material as the material forming the first spacer 121. In the above embodiments, the first spacer 121 and the second spacer 122 may comprise SiCO, SiCON, SiCOH, or combinations thereof.

[0038] In one embodiment, the third spacer 123 may comprise the same material as the material forming the first spacer 121. For example, both the first spacer 121 and the third spacer 123 may comprise silicon nitride.

[0039] In one embodiment, the first spacer 121 may include silicon nitride, the second spacer 122 may include SiCO, SiCON, SiCOH or a combination thereof, and the third spacer 123 may include silicon nitride.

[0040] In another embodiment, the first spacer 121 and the second spacer 122 may include SiCO, SiCON, SiCOH or a combination thereof, while the third spacer 123 may include silicon nitride.

[0041] Figures 2 to 4 A view of another transistor included in a semiconductor device according to an embodiment of the present disclosure is shown.

[0042] Reference Figure 2 According to one embodiment, a semiconductor device 100 includes a substrate 101, an element isolation layer 102, and a first transistor TR.

[0043] The first transistor TR may include a gate structure 103, an impurity region 104, source / drain regions 105 and 106, a semiconductor layer 107, and a spacer 220.

[0044] The spacer 220 includes a first spacer 121, a second spacer 222, a third spacer 123, and a fourth spacer 224.

[0045] A first spacer 121 is disposed on a side surface of the gate structure 103. The first spacer 121 is in contact with the side surface of the gate structure 103. In one embodiment, the first spacer 121 may cover the entire side surface of the gate structure 103. The lower surface of the first spacer 121 is in contact with the upper surface of the substrate 101. The lower surface of the first spacer 121 may be in contact with an impurity region 104 in the substrate 101. The first spacer 121 may include silicon nitride, silicon carbide, silicon oxide, or a combination thereof. In one embodiment, the first spacer 121 may be silicon nitride.

[0046] The second spacer 222 is disposed on the outer surface of the first spacer 121. In one embodiment, the upper surface of the second spacer 222 may be located at a lower height than the upper surface of the first spacer 121. The outer and upper surfaces of the second spacer 222 are in contact with the fourth spacer 224. The lower surface of the second spacer 222 may be in contact with the impurity region 104 in the substrate 101. In one embodiment, the lower surface of the second spacer 222 may be located at a lower position than the lower surface of the first spacer 121. The second spacer 222 may include silicon nitride, silicon carbide, silicon oxide, or a combination thereof. In one embodiment, the second spacer 222 may include SiCO, SiCON, SiCOH, or a combination thereof.

[0047] Semiconductor layer 107 may be disposed on the outer surface of the second spacer 222. More specifically, semiconductor layer 107 may be disposed only on the lower portion of the outer surface of the second spacer 222. The remaining portion of the outer surface of the second spacer 222 may be covered by the fourth spacer 224. Semiconductor layer 107 may also be disposed on the source / drain regions 105 and 106 of the substrate 101. More specifically, the lower surface of semiconductor layer 107 (also referred to as the bottom surface of semiconductor layer 107) may be disposed on the source / drain regions 105 and 106 of the substrate 101. Semiconductor layer 107 may be located at a position higher than the upper surface of the substrate 101. At least the uppermost portion of the inner surface of semiconductor layer 107 may contact the lowermost portion of the outer surface of the fourth spacer 224.

[0048] In one embodiment, the semiconductor layer 107 may have an outer surface consisting of a vertical lower portion and an inclined upper portion. For example... Figure 2 As shown, in the first direction FD, the top surface of the semiconductor layer 107 can be much smaller than the bottom surface of the semiconductor layer 107.

[0049] A third spacer 123 is disposed on the semiconductor layer 107, the fourth spacer 224, and the gate structure 103. The third spacer 123 may cover the upper surface of the semiconductor layer 107, the inclined portion of the side surface of the semiconductor layer 107, the upper surface of the fourth spacer 224, the outer surface of the fourth spacer 224 not covered by the semiconductor layer 107, and the upper surface of the gate structure 103. The inner surface of the third spacer 123 may contact the fourth spacer 224. The third spacer 123 may include silicon nitride, silicon carbide, silicon oxide, or a combination thereof. In one embodiment, the third spacer 123 may be silicon nitride.

[0050] A fourth spacer 224 is disposed between the second spacer 222 and the third spacer 123. In one embodiment, the fourth spacer 224 may be a layer formed by oxidizing the surface of the second spacer 222. The outer surface of the fourth spacer 224 is in contact with the third spacer 123. At least a portion of the outer surface of the fourth spacer 224 may be in contact with the semiconductor layer 107. The lower surface of the fourth spacer 224 may be spaced apart from the substrate 101 in the vertical direction. In one embodiment, the fourth spacer 224 may include silicon oxide.

[0051] In one embodiment, the second spacer 222 may comprise a material with a dielectric constant lower than that of the material forming the first spacer 121. For example, the first spacer 121 may comprise silicon nitride, while the second spacer 222 may comprise SiCO, SiCON, SiCOH, or a combination thereof.

[0052] In one embodiment, the fourth spacer 224 may comprise a material with a dielectric constant lower than that of the material forming the second spacer 222. For example, the fourth spacer 224 may comprise silicon oxide.

[0053] In one embodiment, the first spacer 121 may include silicon nitride, the second spacer 222 may include SiCO, SiCON, SiCOH or a combination thereof, the third spacer 123 may include silicon nitride, and the fourth spacer 224 may include silicon oxide.

[0054] Reference Figure 3 According to one embodiment, a semiconductor device 100 includes a substrate 101, an element isolation layer 102, and a first transistor TR.

[0055] The first transistor TR includes a gate structure 103, an impurity region 104, source / drain regions 105 and 106, a semiconductor layer 107, and a spacer 320.

[0056] The spacer 320 includes a first spacer 321, a second spacer 322, a third spacer 323, and a fourth spacer 324.

[0057] A first spacer 321 is disposed on a side surface of the gate structure 103. The first spacer 321 contacts the side surface of the gate structure 103. In one embodiment, the first spacer 321 may expose a portion of the side surface of the gate structure 103. The lower surface of the first spacer 321 may contact an impurity region 104 in the substrate 101. The upper surface of the first spacer 321 may be spaced apart from a third spacer 123. The first spacer 321 may include silicon nitride, silicon carbide, silicon oxide, or a combination thereof. In one embodiment, the first spacer 321 may include SiCO, SiCON, SiCOH, or a combination thereof.

[0058] The second spacer 322 is disposed on the outer surface of the first spacer 321. In one embodiment, the upper surface of the second spacer 322 may be located at a lower height than the upper surface of the first spacer 321. The outer and upper surfaces of the second spacer 322 may contact the fourth spacer 324. The lower surface of the second spacer 322 may contact the impurity region 104 in the substrate 101. In one embodiment, the lower surface of the second spacer 322 may be located at a lower position than the lower surface of the first spacer 321. The second spacer 322 may include silicon nitride, silicon carbide, silicon oxide, or a combination thereof. In one embodiment, the second spacer 322 may include SiCO, SiCON, SiCOH, or a combination thereof.

[0059] A fourth spacer 324 is disposed between the second spacer 322 and the third spacer 123. In one embodiment, the fourth spacer 324 may be a layer formed by oxidizing the surface of the second spacer 322. At least a portion of the outer surface of the fourth spacer 324 may contact the semiconductor layer 107. The lower surface of the fourth spacer 324 may be spaced apart from the substrate 101 in the vertical direction. The fourth spacer 324 may contact the upper surface of the first spacer 321 and the upper and side surfaces of the second spacer 322. In one embodiment, the fourth spacer 324 may comprise silicon oxide.

[0060] In one embodiment, the second spacer 322 may comprise the same material as the material forming the first spacer 321. For example, the first spacer 321 and the second spacer 322 may comprise SiCO, SiCON, SiCOH, or combinations thereof.

[0061] In one embodiment, the fourth spacer 324 may comprise a material with a dielectric constant less than that of the material forming the second spacer 322. For example, the fourth spacer 324 may comprise silicon oxide.

[0062] In one embodiment, the first spacer 321 and the second spacer 322 may include SiCO, SiCON, SiCOH or a combination thereof, the third spacer 123 may include silicon nitride, and the fourth spacer 324 may include silicon oxide.

[0063] Reference Figure 4 According to one embodiment, a semiconductor device 100 includes a substrate 101, an element isolation layer 102, and a first transistor TR.

[0064] The first transistor TR includes a gate structure 103, an impurity region 104, source / drain regions 105 and 106, and a spacer 420.

[0065] The spacer 420 includes a first spacer 421, a second spacer 422, and a third spacer 423.

[0066] A first spacer 421 is disposed on a side surface of the gate structure 103. The first spacer 421 contacts the side surface of the gate structure 103. In one embodiment, the first spacer 421 may cover the entire side surface of the gate structure 103. The lower surface of the first spacer 421 contacts the upper surface of the substrate 101. The lower surface of the first spacer 421 may contact the impurity region 104 in the substrate 101. The first spacer 421 may include silicon nitride, silicon carbide, silicon oxide, or a combination thereof. In one embodiment, the first spacer 421 may include SiCO, SiCON, SiCOH, or a combination thereof.

[0067] A second spacer 422 is disposed on the outer surface of the first spacer 421. In one embodiment, the second spacer 422 may cover the entire outer surface of the first spacer 421. The second spacer 422 contacts the upper surface of the substrate 101. The lower surface of the second spacer 422 may contact the impurity region 104 in the substrate 101. In one embodiment, the lower surface of the second spacer 422 may be located at a position lower than the lower surface of the first spacer 421. The second spacer 422 may include silicon nitride, silicon carbide, silicon oxide, or a combination thereof. In one embodiment, the second spacer 422 may include silicon oxide.

[0068] A third spacer 423 is disposed on the source / drain regions 105 and 106, the second spacer 422, and the gate structure 103. The third spacer 423 may cover the upper surfaces of the source / drain regions 105 and 106 in the substrate 101, the side and upper surfaces of the second spacer 422, and the upper surface of the gate structure 103. The inner surface of the third spacer 423 may contact the second spacer 422. The lower surface of the third spacer 423 may contact the source / drain regions 105 and 106 of the substrate 101. The third spacer 423 may comprise silicon nitride, silicon carbide, silicon oxide, or a combination thereof. In one embodiment, the third spacer 423 may be silicon nitride.

[0069] In one embodiment, the first spacer 421 may comprise a material with a dielectric constant lower than that of the material forming the third spacer 423. For example, the first spacer 421 may comprise SiCO, SiCON, SiCOH, or a combination thereof.

[0070] In one embodiment, the first spacer 421 may include SiCO, SiCON, SiCOH or a combination thereof, the second spacer 422 may include silicon oxide, and the third spacer 423 may include silicon nitride.

[0071] Figure 5 and Figure 6 This is a view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0072] Figure 5 This is a view showing the planar structure of a semiconductor device 500 according to an embodiment of the present disclosure. Figure 6 This is a view showing the cross-sectional structure of a semiconductor device 500 according to an embodiment of the present disclosure.

[0073] In one embodiment, the semiconductor device 500 may be a memory device. The semiconductor device may be, for example, dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low-power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low-power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin-transfer torque random access memory (STT-RAM). However, the semiconductor device 500 is not necessarily limited to a memory device. That is, the semiconductor device 500 may be a non-memory device.

[0074] However, for ease of description, the following describes the case where the semiconductor device 500 is a memory device (e.g., DRAM).

[0075] Reference Figure 5 The semiconductor device 500 includes a cell region CR and a peripheral region PR. The cell region CR is the region in which an array of memory cells is disposed. The peripheral region PR is the region in which peripheral circuitry for transmitting various voltages or signals to the memory cells disposed in the cell region CR is disposed around the cell region CR. In one embodiment, the peripheral region PR may surround the cell region CR.

[0076] Semiconductor device 500 includes bit line BL, word line WL and active region 510.

[0077] Active regions 510 are spaced apart from each other in the first direction FD and the second direction SD. Active regions 510 extend along the third direction TD. Bit line BL and word line WL are configured to intersect with active regions 510. Bit line BL extends in the second direction SD. Word line WL extends in the first direction FD. Bit line BL and word line WL are configured to overlap with cell region CR.

[0078] although Figure 5 The illustration shows one bit line BL and one word line WL set in a cell region CR, but the embodiment is not limited to this. For example, the number of bit lines BL and word lines WL set in cell region CR can be greater than the number shown. Furthermore, bit lines BL and word lines WL can be set in all cell regions CR.

[0079] Reference Figure 6 The semiconductor device 500 includes a substrate 601, element isolation layers 602 and 632, a cell gate insulating layer 633, a word line WL, a word line cover layer 636, an insulating layer 610, a bit line contact BLC, a conductive layer 640, a bit line BL, a bit line cover layer 645, a first transistor TR, and a buried insulating layer 650.

[0080] In the cell region CR, a device isolation layer 602 that confines the active region 510 is disposed in the substrate 601. The substrate 601 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The substrate 601 may include a group III-V semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). The substrate 601 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof. In one embodiment, the substrate 601 may be silicon doped with a group III element.

[0081] Word lines WL are buried in the active region 510 of substrate 601. Word lines WL can be referred to as buried word lines or buried gates. Word lines WL include a first word line 634 and a second word line 635. A word line capping layer 636 is disposed on word lines WL. A cell gate insulating layer 633 is disposed between word lines WL and substrate 601. Cell gate insulating layer 633 is also disposed between word line capping layer 636 and substrate 601. Cell gate insulating layer 633 surrounds the side and bottom surfaces of word lines WL. Word lines WL may include conductive materials such as metals, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. Cell gate insulating layer 633 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric, or combinations thereof. Word line capping layer 636 may include silicon nitride.

[0082] An insulating layer 610 is disposed on the substrate 601. The insulating layer 610 can be a single layer or multiple layers. The insulating layer 610 may include silicon oxide or silicon nitride.

[0083] Bit line contacts (BLCs) pass through insulating layer 610 and contact the active region 510 of substrate 601. The lower surface of the bit line contact (BLC) may be located lower than the upper surface of substrate 601. In one embodiment, two word lines (WLs) may be located between the two bit line contacts (BLCs) in a second direction (SD). In one embodiment, the bit line contacts (BLCs) may comprise the same material as the material forming the first gate electrode 611.

[0084] A conductive layer 640, a bit line BL, and a bit line cover layer 645 are sequentially disposed on the bit line contact BLC in a vertical direction. The conductive layer 640 is disposed on the bit line contact BLC. In one embodiment, the conductive layer 640 may comprise the same material as the material forming the bit line contact BLC.

[0085] Bit lines BL are disposed on conductive layer 640. Bit lines BL include a first bit line 642, a second bit line 643, and a third bit line 644. In one embodiment, the first bit line 642 and the second bit line 643 may each comprise the same material as the materials forming barrier layers 612a and 612b. In one embodiment, the third bit line 644 may comprise the same material as the material forming electrode layer 612c.

[0086] Bit line capping layer 645 is disposed on bit line BL. In one embodiment, bit line capping layer 645 may comprise the same material as forming gate capping layer 613. Buried insulating layer 650 may be disposed on bit line capping layer 645.

[0087] In the peripheral region PR, the first transistor TR includes a gate structure 603, an impurity region 604, source / drain regions 605 and 606, and a spacer 620. The first transistor TR may be a transistor included in peripheral circuitry. In one embodiment, the first transistor TR may be a transistor included in a sub-word line driver or a sense amplifier. Hereinafter, the first transistor TR may be referred to as the peripheral transistor TR.

[0088] The gate structure 603, the impurity region 604, the source / drain regions 605 and 606, and the spacer 620 can be respectively connected to the reference. Figure 1 The gate structure 103, the impurity region 104, the source / drain regions 105 and 106, and the spacer 120 of the semiconductor device 100 described are substantially the same.

[0089] Figures 7 to 15 This is a view illustrating a method for manufacturing a transistor included in a semiconductor device according to an embodiment of the present disclosure.

[0090] Reference Figure 7 At least one element isolation layer 102 is formed in the substrate 101. A gate structure 103 is formed on the substrate 101 between the element isolation layers 102. The gate structure 103 may have a structure in which a gate insulating layer 108, a work function adjustment layer 109, a first gate electrode 111, a second gate electrode 112, and a gate capping layer 113 are sequentially stacked. In one embodiment, the second gate electrode 112 may be formed in a structure in which barrier layers 112a and 112b and an electrode layer 112c are sequentially stacked. The process of forming the gate structure 103 on the substrate 101 may include an etching process. The width of the gate structure 103 in the first direction FD can be formed by the etching process.

[0091] Reference Figure 8 A first insulating layer 821 is formed on the side surface of the gate structure 103 and also on the exposed top surface of the substrate 101. In one embodiment, the first insulating layer 821 may conformally cover the top surface of the substrate 101 and the side surface of the gate structure 103. In one embodiment, the first insulating layer 821 may include silicon nitride. In another embodiment, the first insulating layer 821 may include SiCO, SiCON, SiCOH, or a combination thereof.

[0092] Reference Figure 9 A portion of the first insulating layer 821 is removed to form the first spacer 121. The process of removing the first insulating layer 821 may include an etching process. In the process of removing a portion of the first insulating layer 821, a portion of the substrate 101 may also be removed. In one embodiment, at least a portion of the upper surface of the substrate 101 adjacent to the gate structure 103 may be located at a lower position than the upper surface of the substrate 101 overlapping the gate structure 103.

[0093] Reference Figure 10 An impurity region 104 is formed on the upper portion of the substrate 101 adjacent to the gate structure 103. The impurity region 104 may be a region with an impurity concentration higher than that included in the substrate 101. The impurity region 104 may include a lightly doped drain (LDD) region and a halo-doped region. The process for forming the impurity region 104 may include a doping process, such as an ion implantation process.

[0094] Reference Figure 11A second insulating layer 1122 is formed on the substrate 101, the first spacer 121, and the gate structure 103. In one embodiment, the second insulating layer 1122 may conformally cover the upper surface of the impurity region 104 of the substrate 101, the side and upper surfaces of the first spacer 121, and the upper surface of the gate structure 103. In one embodiment, the second insulating layer 1122 may include SiCO, SiCON, SiCOH, or a combination thereof. In another embodiment, the second insulating layer 1122 may include silicon oxide.

[0095] Reference Figure 12 A portion of the second insulating layer 1122 is removed to form the second spacer 122. The process of removing the second insulating layer 1122 may include an etching process. In the process of removing a portion of the second insulating layer 1122, a portion of the substrate 101 may also be removed. In one embodiment, at least a portion of the upper surface of the substrate 101 adjacent to the second spacer 122 may be located at a lower position than the upper surface of the substrate 101 overlapping the second spacer 122.

[0096] Reference Figure 13 Source / drain regions 105 and 106 are formed on the upper portion of substrate 101 adjacent to the second spacer 122. The process for forming source / drain regions 105 and 106 may include a doping process, such as ion implantation. In one embodiment, source / drain regions 105 and 106 may be formed by doping with N-type impurities. N-type impurities may include P, As, or combinations thereof. Source / drain regions 105 and 106 may be formed adjacent to impurity region 104. Source / drain regions 105 and 106 may extend deeper in substrate 101 than impurity region 104.

[0097] Reference Figure 14 A semiconductor layer 107 is formed on the source / drain regions 105 and 106. Before forming the semiconductor layer 107, a cleaning process (e.g., wet etching process) for removing the oxide layer can be performed. The oxide layer formed on the upper surfaces of the source / drain regions 105 and 106 can be removed by the cleaning process.

[0098] Semiconductor layer 107 can be formed using methods such as selective epitaxial growth (SEG). Semiconductor layer 107 can be a material layer capable of enhancing carrier mobility. In one embodiment, semiconductor layer 107 may include silicon germanium. The upper surface of semiconductor layer 107 may be located at a higher position than the upper surface of substrate 101.

[0099] Reference Figure 15 A third spacer 123 is formed on the semiconductor layer 107, the second spacer 122, and the gate structure 103. The third spacer 123 may contact the upper surface of the gate structure 103. In one embodiment, the third spacer 123 may include silicon nitride.

[0100] Figures 16 to 21 This is a view illustrating another method for manufacturing transistors included in a semiconductor device according to embodiments of the present disclosure.

[0101] Figure 16 The semiconductor device shown can be used in conjunction with the reference. Figures 7 to 14 The methods described for manufacturing semiconductor devices are essentially the same in form.

[0102] Reference Figure 16 A fourth spacer 224 is formed on the outer surface of the second spacer 222. The fourth spacer 224 may be formed by partial oxidation. Figure 14 The second spacer 122 of the semiconductor device shown is formed on the upper and side portions of the second spacer 122. The fourth spacer 224 may include an oxide. In one embodiment, the fourth spacer 224 may be silicon oxide. At least a portion of the outer surface of the fourth spacer 224 may contact the semiconductor layer 107. The lower surface of the fourth spacer 224 may be spaced apart from the upper surface of the substrate 101 in the vertical direction. The lower surface of the fourth spacer 224 may be located at a position lower than the upper surface of the semiconductor layer 107, such that the upper portion of the inner surface of the semiconductor layer 107 may contact the lower outer surface of the fourth spacer located below the top surface of the semiconductor layer 107.

[0103] Reference Figure 2 and Figure 17 A third spacer 123 is formed on the semiconductor layer 107, the fourth spacer 224, and the gate structure 103. The third spacer 123 may be spaced apart from the second spacer 222. The inner surface of the third spacer 123 may not contact the second spacer 222. In other words, the third spacer 123 may be separated from the second spacer 222 by the fourth spacer 224. In one embodiment, the third spacer 123 may comprise silicon nitride.

[0104] Reference Figure 18 The first spacer 321 may include elements that form a reference. Figures 7 to 14 The first spacer 321 included in the described semiconductor device is made of a different material. In one embodiment, the first spacer 321 may include SiCO, SiCON, SiCOH, or a combination thereof. Figure 18 The first spacer 321 shown can be used in conjunction with the reference. Figure 8 and Figure 9 The method for forming the first spacer 121 described is formed in a substantially similar manner.

[0105] Impurity region 104, source / drain regions 105 and 106, second spacer 322, and semiconductor layer 107 can be referenced. Figures 10 to 14The methods described for manufacturing semiconductor devices are formed in essentially the same way.

[0106] A fourth spacer 324 is formed on the outer surface of the second spacer 322. The fourth spacer 324 may be a layer formed by partially oxidizing the upper portion of the first spacer 321 and the upper and side portions of the second spacer 322. The fourth spacer 324 may include an oxide. In one embodiment, the fourth spacer 324 may be silicon oxide.

[0107] The fourth spacer 324 may contact the side surface of the gate capping layer 113 included in the gate structure 103. At least a portion of the outer surface of the fourth spacer 324 may contact the semiconductor layer 107. The lower surface of the fourth spacer 324 may be spaced apart from the upper surface of the substrate 101 in the vertical direction. The lower surface of the fourth spacer 324 may be located at a position lower than the upper surface of the semiconductor layer 107.

[0108] Reference Figure 3 and Figure 19 A third spacer 123 is formed on the semiconductor layer 107, the fourth spacer 324, and the gate structure 103. The third spacer 123 may be spaced apart from the first spacer 321 and the second spacer 322. The third spacer 123 may not contact the upper surface of the first spacer 321 and the upper surface of the second spacer 322. In one embodiment, the third spacer 123 may comprise silicon nitride.

[0109] Reference Figure 20 The first spacer 421 may include elements that form a reference. Figures 7 to 14 The first spacer 421 included in the described semiconductor device is made of a different material. In one embodiment, the first spacer 421 may include SiCO, SiCON, SiCOH, or a combination thereof. Figure 20 The first spacer 421 shown can be used in conjunction with the reference. Figure 8 and Figure 9 The method for forming the first spacer 121 described is formed in a substantially similar manner.

[0110] The second spacer 422 may include elements that form a reference. Figures 7 to 14 The material of the second spacer 122 included in the described semiconductor device is different. In one embodiment, the second spacer 422 may comprise silicon oxide. The second spacer 422 may be made of a material different from that used in the reference stencil. Figure 11 and Figure 12 The method for forming the second spacer 122 is formed in a substantially the same manner as described.

[0111] Impurity region 104 and source / drain regions 105 and 106 can be compared with the reference. Figure 10 and 13The methods described for manufacturing semiconductor devices are formed in essentially the same way.

[0112] Reference Figure 4 and Figure 21 A third spacer 423 is formed on the source / drain regions 105 and 106, the second spacer 422, and the gate structure 103. The third spacer 423 may contact the side and top surfaces of the second spacer 422. The third spacer 423 may contact the source / drain regions 105 and 106 of the substrate 101. The third spacer 423 may include a material different from the material forming the first spacer 421. In one embodiment, the third spacer 423 may include silicon nitride.

[0113] Return to reference Figure 1 and Figure 14 The semiconductor device 100 according to an embodiment of the present disclosure includes a semiconductor layer 107, a first spacer 121, a second spacer 122, and a third spacer 123. The second spacer 122 may include SiCO, SiCON, SiCOH, or a combination thereof.

[0114] According to embodiments of this disclosure, after the formation of the second spacer 122 and before the formation of the semiconductor layer 107, a cleaning process such as wet etching can be performed to remove the oxide layers formed on the source / drain regions 105 and 106. Since the second spacer 122 comprises SiCO, SiCON, SiCOH, or a combination thereof, the second spacer 122 can be prevented from being etched away during the cleaning process. Furthermore, since the second spacer 122 comprises a material with a relatively low dielectric constant compared to silicon nitride, the parasitic capacitance generated around the gate electrode structure 103 can be reduced compared to using a material with a high dielectric constant, such as silicon nitride, as the second spacer 122.

[0115] Return to reference Figure 2 , Figure 3 , Figure 16 and Figure 18 The semiconductor device 100 according to an embodiment of this disclosure includes a fourth spacer 224 or 324. The fourth spacer 224 or 324 may be a layer formed by partially oxidizing the second spacer 222 or 322. The fourth spacer 224 or 324 may include silicon oxide.

[0116] According to embodiments of this disclosure, since the fourth spacer 224 or 324 comprises a material with a dielectric constant lower than that of SiCO, SiCON, SiCOH, or combinations thereof, parasitic capacitance can be further reduced compared to providing only the second spacer 222 or 322 on the side surface of the gate structure 103.

[0117] Therefore, the semiconductor device according to the embodiments of this disclosure can prevent the increase of parasitic capacitance in the element due to process defects, thereby preventing the deterioration of the element characteristics.

[0118] The above embodiments are merely examples, and those skilled in the art will recognize that various modifications can be made thereto without departing from the scope of this disclosure. Therefore, the embodiments described herein are provided for illustrative purposes only and are not intended to limit the scope of this disclosure, and it should be understood that the scope of this disclosure is not limited to these embodiments. The scope of this disclosure should be interpreted by the following claims, and all technical details within their equivalent scope should be interpreted as falling within the scope of this disclosure. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: A gate structure disposed on a substrate; A first spacer is disposed on the substrate and on both sides of the gate structure; The second spacer is disposed on the substrate, outside the first spacer, and comprises SiCO, SiCON, SiCOH or a combination thereof; A semiconductor layer disposed on the substrate and in contact with the outer surface of the second spacer; as well as A third spacer covers the upper surface of the gate structure, the side surface of the second spacer, and the upper surface of the semiconductor layer.

2. The semiconductor device according to claim 1, wherein, The first spacer comprises a material whose dielectric constant is greater than that of the material forming the second spacer.

3. The semiconductor device according to claim 2, wherein, The first spacer comprises silicon nitride.

4. The semiconductor device according to claim 1, wherein, The first spacer comprises the same material as the material forming the second spacer.

5. The semiconductor device according to claim 1, further comprising a fourth spacer disposed between the second spacer and the third spacer.

6. The semiconductor device according to claim 5, wherein, The fourth spacer contacts the side surface of the semiconductor layer and is spaced apart from the upper surface of the substrate.

7. The semiconductor device according to claim 5, wherein, The fourth spacer comprises a material whose dielectric constant is less than that of the material forming the second spacer.

8. The semiconductor device according to claim 7, wherein, The fourth spacer comprises silicon oxide.

9. The semiconductor device according to claim 1, wherein, The semiconductor layer is an epitaxial layer.

10. A semiconductor device, comprising: A substrate comprising a cell region and a peripheral region surrounding the cell region; as well as A peripheral transistor disposed in the peripheral region of the substrate, wherein the peripheral transistor comprises: A gate structure disposed on the substrate; A plurality of spacers disposed on the substrate, located on a side surface of the gate structure, and at least partially comprising SiCO, SiCON, SiCOH, or combinations thereof; and A semiconductor layer is disposed on the substrate and spaced apart from the gate structure in a direction parallel to the upper surface of the substrate.

11. The semiconductor device according to claim 10, wherein, The plurality of spacers further includes a first spacer that contacts the side surface of the gate structure and a second spacer disposed outside the first spacer, and The second spacer includes SiCO, SiCON, SiCOH, or a combination thereof.

12. The semiconductor device according to claim 11, wherein, The first spacer comprises SiCO, SiCON, SiCOH, or a combination thereof.

13. The semiconductor device according to claim 10, wherein, The plurality of spacers further includes: a first spacer that contacts a side surface of the gate structure; a second spacer disposed outside the first spacer; a third spacer disposed outside the second spacer; and a fourth spacer disposed between the second spacer and the third spacer; and The fourth spacer contacts the side surface of the semiconductor layer and is separated from the upper surface of the substrate.

14. A semiconductor device, comprising: A gate structure disposed on a substrate; and spacers covering the side and top surfaces of the gate structure; The spacer includes a first spacer, a second spacer, a third spacer, and a fourth spacer. The first spacer and the second spacer are disposed on the substrate and on two opposite sides of the gate structure. The third spacer is disposed on the side surface of the second spacer and also on the top surfaces of the first spacer, the second spacer, and the top surface of the gate structure. The fourth spacer is disposed between the second spacer and the third spacer and does not contact the substrate.

15. The semiconductor device of claim 14, further comprising a semiconductor layer disposed on the source region and drain region of the substrate.

16. The semiconductor device according to claim 15, wherein, The fourth spacer is disposed between the semiconductor layer and the second spacer.

17. The semiconductor device according to claim 16, wherein, The fourth spacer is spaced apart from the upper surface of the substrate.

18. The semiconductor device according to claim 16, wherein, The fourth spacer comprises a material whose dielectric constant is less than that of the material forming the second spacer.

19. The semiconductor device according to claim 18, wherein, The fourth spacer comprises silicon oxide.

20. The semiconductor device according to claim 14, wherein, The second spacer includes SiCO, SiCON, SiCOH, or a combination thereof.

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