Two-dimensional semiconductor p-type field effect transistor based on transition metal oxide contact and preparation method thereof

Abstract

The invention discloses a two-dimensional semiconductor p-type field effect transistor based on transition metal oxide contact and a preparation method thereof, and relates to the technical field of semiconductor micro-nano electronic devices, and the preparation method comprises the steps: forming a single-layer tungsten diselenide on a substrate as a channel layer; defining pattern windows of a source electrode and a drain electrode on the surface of the channel layer to form an electrode region and a non-electrode region; sequentially depositing molybdenum trioxide and gold on the pattern windows of the source electrode and the drain electrode by adopting a thermal evaporation process to form a molybdenum trioxide / gold composite electrode structure; and removing the photoresist and sediments above a non-electrode region through a stripping process to prepare the two-dimensional semiconductor p-type field effect transistor based on transition metal oxide contact. The preparation of the high-performance two-dimensional semiconductor p-type field effect transistor is realized by introducing the ultrahigh work function molybdenum trioxide as the buffer layer and combining a mild process.

Description

Technical Field

[0001] This application relates to the field of semiconductor micro-nano electronic device technology, and in particular to a two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts and its fabrication method. Background Technology

[0002] As silicon-based integrated circuits approach their physical limits, two-dimensional transition metal chalcogenides such as tungsten diselenide, with their atomic-level thickness and excellent electrical properties, have become ideal channel materials for continuing Moore's Law. In complementary metal-oxide-semiconductor (CMOS) logic circuits, both high-performance n-type and p-type field-effect transistors (FETs) are indispensable. Currently, research on tungsten diselenide-based n-type FETs is relatively mature, but the fabrication of high-performance p-type FETs faces more severe challenges, becoming a major bottleneck restricting their industrialization. Therefore, there is an urgent need to develop a novel tungsten diselenide-based p-type FET. Summary of the Invention

[0003] The main objective of this application is to propose a two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts and its fabrication method, aiming to solve the problems of high contact resistance, low hole injection efficiency and poor stability of existing p-type field-effect transistors based on tungsten diselenide.

[0004] To achieve the above objectives, in a first aspect, this application proposes a method for fabricating a two-dimensional semiconductor p-type field-effect transistor based on a transition metal oxide contact, comprising the following steps: Step S1: Form a monolayer of tungsten diselenide as a channel layer on the substrate; Step S2: Define patterned windows for the source and drain on the surface of the channel layer to form electrode regions and non-electrode regions; Step S3: Using a thermal evaporation process, molybdenum trioxide and gold are sequentially deposited in the patterned windows of the source and the drain to form a molybdenum trioxide / gold composite electrode structure. Step S4: Remove the photoresist and the deposits above the non-electrode region by a stripping process to obtain the two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide.

[0005] In some embodiments, the deposition of molybdenum trioxide is performed using a vacuum in-situ thermal evaporation process, with a vacuum level better than 10 during deposition. -6 Torr deposition temperature not exceeding 500 °C, deposition rate of 0.05–0.5 Å / s, and deposition thickness of 5–15 nm.

[0006] In some embodiments, the deposition rate of the deposited gold is 0.5 to 1.5 Å / s, and the deposition thickness is 30 to 60 nm.

[0007] In some embodiments, in step S1, the substrate is a composite substrate with a pre-fabricated bottom gate structure, and its fabrication process includes: Graphene was fabricated on a substrate as a bottom gate electrode; Hexagonal boron nitride is fabricated as a gate dielectric layer on the bottom gate electrode; The monolayer tungsten diselenide is transferred to the surface of the gate dielectric layer to form a van der Waals heterojunction structure of bottom gate electrode / hexagonal boron nitride / tungsten diselenide.

[0008] In some implementations, in step S2, patterned windows for the source and the drain are defined using electron beam lithography.

[0009] Secondly, this application also proposes a two-dimensional semiconductor p-type field-effect transistor based on a transition metal oxide contact, comprising: Substrate; A trench layer disposed on the substrate; The source and drain electrodes are disposed at both ends of the channel layer; The channel layer is a single-layer tungsten diselenide layer; The source and the drain are composite electrode structures, each comprising a molybdenum trioxide layer that is in direct physical contact with the surface of the channel layer, and a gold layer disposed on the molybdenum trioxide layer.

[0010] In some embodiments, the substrate includes a base, a bottom gate electrode, and a gate dielectric layer disposed sequentially from bottom to top; The bottom gate electrode is made of graphene; the gate dielectric layer is made of hexagonal boron nitride. The channel layer is disposed on the gate dielectric layer.

[0011] In some embodiments, the thickness of the molybdenum trioxide layer is 5-15 nm, and the thickness of the gold layer is 30-60 nm.

[0012] In some embodiments, the hole Schottky barrier height of the two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide is less than 60 meV; the hole mobility at room temperature is greater than 80 cm⁻¹. 2 / (V·s), on / off ratio greater than 10 8 The single-sided contact resistance is less than 1 kΩ·μm.

[0013] Thirdly, this application also proposes the application of the two-dimensional semiconductor p-type field-effect transistor based on the transition metal oxide contact fabrication method proposed in the first aspect of this application, and the two-dimensional semiconductor p-type field-effect transistor based on the transition metal oxide contact proposed in the second aspect of this application, in the fabrication of electronic devices.

[0014] The beneficial effects of this application are: (1) The fabrication method of the two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts proposed in this application utilizes molybdenum trioxide with ultra-high work function as a hole injection buffer layer, which effectively relieves the Fermi level pinning effect at the gold-tungsten diselenide interface, reduces the Schottky barrier height to 59.2 meV, and achieves a contact resistance as low as ~0.54 kΩ·μm. Compared with traditional palladium and platinum metal contacts, this significantly reduces the contact resistance and increases the driving current of the device.

[0015] (2) The formed molybdenum trioxide / gold composite electrode not only serves as a highly efficient hole injection layer, but also acts as an interface encapsulation and passivation layer, effectively isolating the adsorption and reaction of water and oxygen molecules in the air. After the device is placed in the air environment for more than 113 days, its electrical performance shows almost no degradation, overcoming the problem of poor stability of existing chemical surface doping technology, and has extremely high practical value.

[0016] (3) The mild thermal evaporation process is used to deposit molybdenum trioxide, which avoids the bombardment damage of high-energy particles to the atomic lattice of single-layer two-dimensional materials in traditional electron beam evaporation or magnetron sputtering, and preserves the intrinsic quality of tungsten diselenide channel to the maximum extent.

[0017] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0019] Figure 1 A schematic flowchart illustrating the fabrication method of a two-dimensional semiconductor p-type field-effect transistor based on a transition metal oxide contact provided in this application; Figure 2A schematic flowchart of the fabrication method of a two-dimensional semiconductor p-type field-effect transistor based on a transition metal oxide contact in Embodiment 1 provided for the embodiments of this application; Figure 3 A schematic diagram of the fabrication process of the two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts in Embodiment 1 provided for the embodiments of this application; Figure 4 The structure and some performance test diagrams of the two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts provided in this application are as follows: (a) is a schematic diagram of the three-dimensional structure of a two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts; (b) is an optical microscope image of a two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts; (c) is the Raman spectrum of a monolayer tungsten diselenide thin film; (d) is the photoluminescence spectrum of a monolayer tungsten diselenide thin film; (e) is a comparison of the X-ray photoelectron spectra of the W 4f orbitals of the initial tungsten diselenide thin film and the tungsten diselenide thin film after molybdenum trioxide deposition; (f) is a comparison of the ultraviolet photoelectron spectra of the initial tungsten diselenide thin film and the tungsten diselenide thin film after molybdenum trioxide deposition. Figure 5 Partial performance test diagrams of a two-dimensional semiconductor p-type field-effect transistor (device) based on a transition metal oxide contact provided in this application embodiment: (a) Comparison of transfer characteristic curves (logarithmic scale) of the devices prepared in Example 1, Comparative Example 1, and Comparative Example 2; (b) Comparison of output characteristic curves of the devices prepared in Example 1, Comparative Example 1, and Comparative Example 2; (c) Statistical histogram of mobility distribution of the device prepared in Example 1; (d) Current on / off ratio (logarithmic scale) of the device prepared in Example 1. 10 ( I on / I off (e) Distribution statistics histogram; (f) Box plot comparing the mobility and on / off ratio performance of the devices prepared in Example 1, Comparative Example 1, and Comparative Example 2; (c) Stability test graph of the transfer characteristic curve of the device prepared in Example 1 after being placed in an air environment for different numbers of days. Figure 6 Partial performance test diagrams of a two-dimensional semiconductor p-type field-effect transistor (device) based on a transition metal oxide contact provided in this application embodiment: (a) is a graph showing the mobility of the device prepared in Example 1 as a function of temperature; (b) is a graph showing the Schottky barrier height extracted and fitted from the device prepared in Example 1; (c) is a graph showing the Schottky barrier height extracted and fitted from the device prepared in Comparative Example 1. Figure 7Performance test diagrams for devices with different channel lengths provided in embodiments of this application: (a) is a schematic diagram of the structure of devices with different channel lengths; (b) is a graph of the transfer characteristic curves (linear coordinates) of devices with different channel lengths; (c) is a graph of the output characteristic curves of devices with different channel lengths; (d) is a graph of the linear fitting of the total resistance of a molybdenum trioxide contact device with the channel length; (e) is a graph of the linear fitting of the total resistance of a palladium contact device with the channel length; (f) is a graph of the linear fitting of the total resistance of a platinum contact device with the channel length.

[0020] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0022] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0023] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0024] As silicon-based integrated circuit technology gradually approaches its physical limits, the search for next-generation channel materials with higher carrier mobility and superior gate control capabilities has become an urgent need in the semiconductor field. Two-dimensional transition metal chalcogenides, especially tungsten diselenide, are widely recognized as ideal candidate materials for building next-generation high-performance, low-power logic circuits due to their atomically thin bulk properties, excellent electrostatic control capabilities, and band gaps similar to silicon.

[0025] In complementary metal-oxide-semiconductor (CMOS) technology, high-performance n-type and p-type field-effect transistors are indispensable. Currently, research on tungsten diselenide-based n-type transistors is relatively mature; however, the fabrication of high-performance p-type tungsten diselenide transistors faces more severe challenges. The core bottleneck lies in the difficulty of achieving efficient, stable, and high-quality p-type ohmic contacts that are compatible with current processes.

[0026] Existing technical solutions attempt to solve this problem, but all have fundamental flaws, as detailed below: (1) Traditional high work function metal deposition faces the dilemma of "Fermi level pinning". Theoretically, high work function metals such as platinum and palladium should form ohmic contacts with p-type tungsten diselenide. However, in actual preparation, such metals need to be deposited by physical vapor deposition (such as electron beam evaporation and magnetron sputtering). During the deposition process, high-energy particles and secondary electrons will bombard the surface of tungsten diselenide, breaking W-Se bonds and generating a large number of defects. These defects introduce high-density interface states, causing the Fermi level to be "pinned" within the band gap and unable to move to the vicinity of the valence band top, resulting in excessively high contact resistance (usually 60-100 kΩ·μm) and low hole mobility.

[0027] (2) Mechanical transfer and van der Waals contact technologies face bottlenecks in mass production. To avoid deposition damage, mechanical transfer of pre-fabricated electrodes or the use of metallic two-dimensional materials (such as vanadium diselenide) to form van der Waals contacts can achieve a lossless interface. However, this process is a serial operation in the laboratory stage, which is cumbersome and time-consuming, and cannot achieve micron-level high-precision array alignment. It is completely incompatible with the large-scale parallel manufacturing process of modern semiconductors. In addition, this method often results in an excessively low device on / off ratio, making it difficult to meet the basic requirements of logic circuits.

[0028] (3) Surface chemical doping technology has a shortcoming in environmental stability. Surface adsorption doping using strong oxidizing gases or organic molecules relies on weak physical interactions and is easily affected by ambient temperature, humidity and subsequent process thermal budget, resulting in unstable doping effect, device performance degradation over time, and lack of long-term environmental robustness.

[0029] (4) Conventional thin film deposition processes are caught in a conflict between large-area uniformity and low thermal budget. To achieve wafer-level integration, it is difficult to maintain a low-temperature environment while ensuring film quality when using conventional thermal evaporation or atomic layer deposition processes. Residual impurities in the conventional process chamber can easily contaminate the interface, while the high substrate temperature may cause thermal damage to the monolayer tungsten diselenide lattice, resulting in large performance dispersion of large-area devices, which is incompatible with the low-temperature, large-area, and high-consistency requirements of modern complementary metal-oxide-semiconductor production lines.

[0030] In summary, existing technologies cannot achieve a balance between efficient hole injection (high effective work function), ensuring interface non-destruction (ultra-low damage process), and meeting the requirements of large-scale manufacturing and long-term stability. Therefore, a novel p-type contact solution is urgently needed to simultaneously meet these stringent conditions.

[0031] Regarding the above issues, firstly, please refer to [the relevant information]. Figure 1 This application proposes a method for fabricating a two-dimensional semiconductor p-type field-effect transistor based on a transition metal oxide contact, comprising the following steps: S1. A single layer of tungsten diselenide is formed on the substrate as a channel layer; S2. Define source and drain pattern windows on the surface of the channel layer to form electrode and non-electrode regions; S3. Using a thermal evaporation process, molybdenum trioxide and gold are sequentially deposited in the patterned windows of the source and drain electrodes to form a molybdenum trioxide / gold composite electrode structure. S4. The photoresist and deposits above the non-electrode areas are removed by a stripping process to obtain a two-dimensional semiconductor p-type field-effect transistor based on a transition metal oxide contact.

[0032] When traditional high work function metals (such as platinum and palladium) are used as electrodes, the Fermi level is strongly pinned within the band gap due to metal-induced bandgap states and interfacial chemistry, making it difficult to align with the valence band of tungsten diselenide. This results in a high hole injection barrier, with contact resistance typically in the tens to hundreds of kΩ·μm range (e.g., the total contact resistance of platinum in the prior art is typically around 100 kΩ·μm), severely limiting the device's drive current. The fabrication method in this application utilizes a high work function transition metal oxide molybdenum trioxide layer to effectively reduce the Schottky barrier between gold and tungsten diselenide, achieving a contact resistance as low as 0.54 kΩ·μm. Test results show that the fabricated contact-based two-dimensional semiconductor p-type field-effect transistor exhibits characteristics close to ohmic contacts, with a hole mobility as high as 107.53 ± 23.39 cm⁻¹. 2 / (V·s), switching ratio exceeding 10 8 It also exhibits excellent long-term stability in air.

[0033] In some embodiments, in step S3, the deposition of molybdenum trioxide employs a vacuum in-situ thermal evaporation process, with a vacuum level better than 10⁻⁶ during deposition. -6 The deposition temperature is no more than 500 °C, the deposition rate is 0.05–0.5 Å / s, and the deposition thickness is 5–15 nm. For example, deposition rates of 0.05 Å / s, 0.1 Å / s, 0.2 Å / s, 0.3 Å / s, 0.4 Å / s, or 0.5 Å / s are used. The deposition thickness is 5 nm, 10 nm, or 15 nm, etc. Preferably, the deposition rate is 0.1 Å / s, and the deposition thickness is 10 nm.

[0034] In existing technologies, fabricating p-type contacts typically requires the deposition of high-melting-point metals. The high-energy particle bombardment accompanying the evaporation or sputtering process easily disrupts the atomically thin tungsten diselenide lattice, introducing numerous scattering centers. This interfacial damage results in hole mobility in the device being far lower than the theoretical value of the material (for example, the hole mobility of Pt contact devices on a monolayer of tungsten diselenide in existing technologies is only 1–10 cm⁻¹). 2 / (V·s)). The embodiments of this application employ a mild thermal evaporation oxide process to avoid lattice damage and to retain the intrinsic high mobility characteristics of the material to the maximum extent.

[0035] In some embodiments, in step S3, the gold deposition rate is 0.5–1.5 Å / s, and the deposition thickness is 30–60 nm. For example, the deposition rate is 0.5 Å / s, 1 Å / s, or 1.5 Å / s, etc., and the deposition thickness is 30 nm, 40 nm, 50 nm, or 60 nm, etc.

[0036] In some embodiments, in step S1, the substrate is a composite substrate with a pre-fabricated bottom gate structure, and its fabrication process includes: S11. Graphene is prepared on a substrate as a bottom gate electrode; S12. Prepare hexagonal boron nitride as a gate dielectric layer on the bottom gate electrode; S13. Transfer a single layer of tungsten diselenide to the surface of the gate dielectric layer to form a van der Waals heterojunction structure of bottom gate electrode / hexagonal boron nitride / tungsten diselenide.

[0037] Graphene, as the bottom gate electrode, can provide excellent electrostatic control capabilities. Using hexagonal boron nitride as the gate dielectric layer utilizes the atomically flat and dangling-bond-free characteristics of hexagonal boron nitride, which can effectively reduce interfacial heat dissipation. Furthermore, the substrate prepared by the above method can form a high-quality van der Waals heterojunction, reducing substrate scattering.

[0038] In some implementations, in step S2, patterned windows for the source and drain electrodes are defined using electron beam lithography. Electron beam lithography enables electrode patterning with sub-micron precision, ensuring accurate alignment of the source / drain electrodes with the channel layer.

[0039] This application also proposes a two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts, comprising: a substrate, a channel layer, a source, and a drain. The channel layer is disposed on the substrate, and the source and drain are disposed at both ends of the channel layer. The channel layer is a single-layer tungsten diselenide layer. The source and drain are composite electrode structures, each comprising a molybdenum trioxide layer in direct physical contact with the surface of the channel layer, and a gold layer disposed on the molybdenum trioxide layer.

[0040] Since this two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts adopts the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated here.

[0041] In some embodiments, the substrate includes a base, a bottom gate electrode, and a gate dielectric layer disposed sequentially from bottom to top. The bottom gate electrode is made of graphene; the gate dielectric layer is made of hexagonal boron nitride; and a channel layer is disposed on the gate dielectric layer.

[0042] In some embodiments, the thickness of the molybdenum trioxide layer is 5–15 nm. For example, the thickness of the molybdenum trioxide layer is 5 nm, 10 nm, or 15 nm. The thickness of the gold layer is 30–60 nm. For example, the thickness of the gold layer is 30 nm, 40 nm, 50 nm, or 60 nm.

[0043] In some implementations, the hole Schottky barrier height of the two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts has been tested to be less than 60 meV; the hole mobility at room temperature is greater than 80 cm⁻¹. 2 / (V·s), on / off ratio greater than 10 8 The single-sided contact resistance is less than 1 kΩ·μm.

[0044] This application also provides a two-dimensional semiconductor p-type field-effect transistor based on a transition metal oxide contact, prepared by the preparation method described above, and the application of the two-dimensional semiconductor p-type field-effect transistor based on a transition metal oxide contact as described above in the preparation of electronic devices.

[0045] The following specific examples provide further details.

[0046] Example 1 (1) Preparation of hardware equipment and materials: Substrate: Highly doped silicon / silicon dioxide substrate with a 285 nm oxide layer.

[0047] Two-dimensional materials: high-quality bulk graphene, hexagonal boron nitride, and tungsten diselenide crystals.

[0048] Micro / nano fabrication equipment: Two-dimensional material transfer platform: equipped with a high-magnification optical microscope and a precision micromanipulator for point-to-point dry transfer.

[0049] Electron beam lithography: used to define fine patterns for source and drain electrodes.

[0050] High-vacuum thermal evaporation equipment: used for depositing molybdenum trioxide and gold thin films, requiring a vacuum level better than 10. -6 Torr.

[0051] Semiconductor parameter analyzer (Keysight B1500A): used for testing the electrical performance of devices.

[0052] (2) Preparation steps (refer to) Figure 2 and Figure 3 ) Step S10: Material stripping and screening Bottom gate fabrication: A few-layer graphene was exfoliated from bulk graphene using a mechanical peeling method and transferred onto a cleaned silicon / silicon dioxide substrate. This graphene layer will serve as a local bottom gate electrode, providing excellent electrostatic control capabilities.

[0053] Dielectric layer and channel preparation: Using the same mechanical peeling method, a few-layer hexagonal boron nitride and a single-layer tungsten diselenide with a thickness of about 12~16 nm were peeled off onto the polydimethylsiloxane transparent colloidal stamp.

[0054] Characterization and confirmation: Samples with uniform contrast were screened using optical microscopy, and Raman and photoluminescence spectroscopy confirmed that tungsten diselenide was a monolayer. Figure 4 As shown in (c) and (d), monolayer tungsten diselenide at 250 cm⁻¹ -1 The presence of characteristic peaks and the strong emission peaks in the photoluminescence spectrum confirm the excellent quality of the material.

[0055] Step S20: Site-specific transfer of van der Waals heterojunctions Hexagonal boron nitride transfer: Using a transfer platform, a thin sheet of hexagonal boron nitride on polydimethylsiloxane is precisely aligned with a few-layer graphene on a substrate, and then slowly pressed down and released to form a hexagonal boron nitride / graphene stack.

[0056] Tungsten diselenide transfer: The monolayer of tungsten diselenide on polydimethylsiloxane is precisely aligned with the central region of hexagonal boron nitride and released again to complete the heterojunction stacking.

[0057] Step S30: Photolithographic definition of electrode windows Spin-coating photoresist: Electron beam photoresist is spin-coated onto the surface of the heterojunction at 4000 rpm for 1 minute, followed by curing on a hot plate at 180 °C.

[0058] Exposure and Development: The source and drain regions are exposed using an electron beam lithography machine, and then developed in a developer solution (MIBK:IPA=1:3) to precisely expose the contact areas at both ends of the tungsten diselenide channel. The channel length is 1 μm.

[0059] Step S40: Ultra-low-rate deposition of molybdenum trioxide layer Vacuum environment: Place the sample in a thermal evaporation apparatus and evacuate to a vacuum level better than 10. -6 Torr's high vacuum state.

[0060] Ultra-low deposition rate: The heating source is activated to evaporate molybdenum trioxide powder. The deposition rate is controlled at 0.1 Å / s, and the deposition thickness is 10 nm. The slow deposition rate can effectively prevent thermal damage or kinetic impact damage to the monolayer tungsten diselenide caused by high-temperature molecular clusters, while forming a high-quality hole injection buffer layer.

[0061] Step S50: Gold deposition Electrode construction: Following the previous step, a layer of metallic gold is deposited on the surface of molybdenum trioxide as a conductive layer.

[0062] Process parameters: Evaporation rate of 1 Å / s, deposition thickness of approximately 45 nm. This metal layer is used to connect external test circuitry.

[0063] Step S60: Debonding and Part Forming Peeling process: The sample prepared in the previous step is immersed in acetone solution to perform a peeling process.

[0064] Final shaping: Thoroughly remove excess metal / oxide deposits from photoresist and non-electrode areas, retaining only the patterned source and drain electrodes, to complete the fabrication of a two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts.

[0065] like Figure 4 As shown in (a) and (b), the final fabricated device structure is a vertically stacked van der Waals heterojunction field-effect transistor, which consists of the following layers from bottom to top: substrate support layer: silicon / silicon dioxide; bottom gate electrode: few-layer graphene; gate dielectric layer: hexagonal boron nitride; semiconductor channel: monolayer tungsten diselenide; source and drain electrodes: molybdenum trioxide / gold composite electrode.

[0066] Comparative Example 1 This comparative example uses the same method as Example 1 to prepare a field-effect transistor, except that the source and drain are palladium.

[0067] Comparative Example 2 This comparative example uses the same method as Example 1 to prepare a field-effect transistor, except that the source and drain are platinum.

[0068] Comparative Examples 3-6 The field-effect transistors in this comparative example were fabricated using the same method as in Example 1, except that the channel lengths were 0.6 μm, 0.8 μm, 1.5 μm, and 2 μm, respectively.

[0069] Comparative Examples 7-11 This comparative example uses the same method as Comparative Example 1 to fabricate field-effect transistors, except that the channel lengths are 0.8 μm, 2.0 μm, 2.7 μm, 4.7 μm and 5.7 μm, respectively.

[0070] Comparative Examples 12-16 This comparative example uses the same method as Comparative Example 2 to fabricate field-effect transistors, except that the channel lengths are 0.8 μm, 1.8 μm, 4.5 μm, 5.7 μm and 6.5 μm, respectively.

[0071] To evaluate the performance of the two-dimensional semiconductor p-type field-effect transistor (hereinafter referred to as the device) based on transition metal oxide contacts prepared in Example 1, a series of systematic micro-nano characterization and electrical testing methods were employed, as follows: (1) Material quality and band structure characterization: The mechanically exfoliated tungsten diselenide was non-destructively characterized using a micro-confocal Raman spectrometer and a photoluminescence spectrometer. For example... Figure 4 As shown in (c) and (d), the Raman spectrum is at ~250 cm⁻¹ -1 A clear and sharp E appears at the location 2g and A 1g Characteristic peaks with extremely narrow half-maximum widths (WHMs); photoluminescence spectrum shows a strong emission peak at ~1.66 eV. These characteristics confirm that the exfoliated tungsten diselenide is a high-quality monolayer material with a complete lattice structure and no obvious defects. X-ray photoelectron spectroscopy and ultraviolet photoelectron spectroscopy were used to analyze the chemical composition and band structure of the contact interface. Figure 4 As shown in (e), the X-ray photoelectron spectroscopy (XPS) spectrum confirms the stability of the tungsten diselenide lattice after molybdenum trioxide deposition, and the W 4f characteristic peak shifts towards lower binding energies. This indicates that the Fermi level has shifted towards the valence band, confirming that molybdenum trioxide has a significant p-type doping effect on tungsten diselenide, inducing charge transfer at the interface. Figure 4As shown in the UV photoelectron spectrum (f), after the deposition of molybdenum trioxide, the secondary electron cutoff edge of the sample shifts significantly towards the lower binding energy direction. The work function increases from 4.25 eV for the initial tungsten diselenide to 5.16 eV, and the valence band top shifts to near the Fermi level (~0 eV). This indicates that molybdenum trioxide possesses a high work function characteristic of deep energy levels, effectively aligning with the valence band of p-type tungsten diselenide, providing a physical basis for barrier-free hole injection.

[0072] (2) Perform DC electrical tests on the device using a semiconductor parameter analyzer under room temperature and air conditions: Transfer characteristic test: Scan gate voltage ( V g ) and monitor source leakage current ( I sd ).like Figure 5 As shown in (a) and (d), the device exhibits excellent p-type gate control characteristics. Statistical results show that the device's current switching ratio ( I on / I off The logarithmic values ​​are concentrated between 8.6 and 9.6, and the actual on / off ratio is close to or even exceeds 10. 9 It has a high current density in the on-state and an extremely low leakage current in the off-state.

[0073] Key parameter extraction and comparison: Based on linear curves, the maximum transconductance method is used to extract the field-effect mobility. For example... Figure 5 As shown in the statistical results in (e), the average hole mobility of the device prepared in Example 1 is approximately 107.53 cm⁻¹. 2 / (V·s), up to 156 cm 2 / (V·s), significantly better than devices with traditional palladium or platinum contacts.

[0074] Output characteristic test: scanning source-drain voltage ( V sd )test I sd .like Figure 5 As shown in (b), the output curve exhibits a perfect linear relationship under low bias and strictly passes through the origin, which intuitively proves that a good ohmic contact is formed between the molybdenum trioxide / gold electrode and the monolayer tungsten diselenide channel layer.

[0075] Environmental stability testing: such as Figure 5 As shown in Figure (f), the device underwent an air environment aging test for 113 days, and its transfer curve did not show significant drift. The on-state current remained highly stable, confirming the effective passivation protection effect of the molybdenum trioxide film on the channel.

[0076] (3) In order to investigate the contact barrier height and carrier scattering mechanism, tests were conducted in a vacuum environment (78~300 K) using a variable temperature probe station: Mobility evolution with temperature: such as Figure 6 As shown in (a), the mobility decreases with increasing temperature, and the fitting results are consistent with... μ ∝ T -0.40 The power-law relationship indicates that the device is primarily limited by phonon scattering, with extremely low scattering from interface impurities, confirming the cleanliness of the van der Waals integration process.

[0077] Schottky barrier height extraction: Based on the thermal emission theory model, the effective Schottky barrier is extracted using Arrhenius diagrams. For example... Figure 6 As shown in (b), the hole injection barrier of the device prepared in Example 1 is as low as 59.2 meV, approaching zero barrier contact. In contrast, Figure 6 Image (c) shows that the device with palladium electrodes has a barrier as high as 158.7 meV, which quantitatively confirms the core role of the molybdenum trioxide interlayer in reducing the barrier.

[0078] (4) To further quantify the improvement of contact performance by the introduction of molybdenum trioxide, this embodiment uses the transmission line method to conduct systematic tests on devices with different channel lengths: like Figure 7 As shown in Figure (a), device structures with different channel lengths were fabricated. Figure 7 Figures (b) and (c) show that devices with different channel lengths all exhibit consistent p-type characteristics and good linear output. This is achieved by extracting the total resistance for different channel lengths and performing linear fitting (e.g., ...). Figure 7 As shown in (d), the intercept of the straight line corresponds to twice the contact resistance. The fitting results show that the contact resistance of the device prepared in Example 1 is approximately 0.54 kΩ·μm. For comparison, Figure 7 Figures (e) and (f) show the fitting results for devices using palladium (Comparative Example 1) and platinum (Comparative Example 2) electrodes, respectively. The contact resistance of the device using palladium electrodes is 32.84 kΩ·μm, while the contact resistance of the device using platinum electrodes is 54.86 kΩ·μm. Although palladium and platinum are generally considered excellent p-type contact metals, their contact resistance is still significantly higher than that of the device prepared in Example 1 (approximately 60 to 100 times higher) due to the presence of Fermi level pinning at the interface. This significant difference further confirms the crucial role of molybdenum trioxide in relieving Fermi pinning and lowering the potential barrier, which is a key factor in achieving high device performance.

[0079] The above description is merely an exemplary embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the technical concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A method for fabricating a two-dimensional semiconductor p-type field-effect transistor based on a transition metal oxide contact, characterized in that, Includes the following steps: Step S1: Form a monolayer of tungsten diselenide as a channel layer on the substrate; Step S2: Define patterned windows for the source and drain on the surface of the channel layer to form electrode regions and non-electrode regions; Step S3: Using a thermal evaporation process, molybdenum trioxide and gold are sequentially deposited in the patterned windows of the source and the drain to form a molybdenum trioxide / gold composite electrode structure. Step S4: Remove the photoresist and the deposits above the non-electrode region by a stripping process to obtain the two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts.

2. The preparation method according to claim 1, characterized in that, In step S3, the deposition of molybdenum trioxide is performed using a vacuum in-situ thermal evaporation process, with a vacuum level better than 10 during deposition. -6 Torr deposition temperature not exceeding 500 °C, deposition rate of 0.05–0.5 Å / s, and deposition thickness of 5–15 nm.

3. The preparation method according to claim 1, characterized in that, In step S3, the deposition rate of the deposited gold is 0.5~1.5 Å / s, and the deposition thickness is 30~60 nm.

4. The preparation method according to claim 1, characterized in that, In step S1, the substrate is a composite substrate with a pre-prepared bottom gate structure, and its preparation process includes: Graphene was fabricated on a substrate as a bottom gate electrode; Hexagonal boron nitride is fabricated as a gate dielectric layer on the bottom gate electrode; The monolayer tungsten diselenide is transferred to the surface of the gate dielectric layer to form a van der Waals heterojunction structure of bottom gate electrode / hexagonal boron nitride / tungsten diselenide.

5. The preparation method according to claim 1, characterized in that, In step S2, the pattern windows of the source and the drain are defined by electron beam lithography.

6. A two-dimensional semiconductor p-type field-effect transistor based on a transition metal oxide contact, characterized in that, include: Substrate; A trench layer disposed on the substrate; The source and drain electrodes are disposed at both ends of the channel layer; The channel layer is a single-layer tungsten diselenide layer; The source and the drain are composite electrode structures, each comprising a molybdenum trioxide layer that is in direct physical contact with the surface of the channel layer, and a gold layer disposed on the molybdenum trioxide layer.

7. The two-dimensional semiconductor p-type field-effect transistor based on a transition metal oxide contact as described in claim 6, characterized in that, The substrate includes a base, a bottom gate electrode, and a gate dielectric layer arranged sequentially from bottom to top; The bottom gate electrode is made of graphene; the gate dielectric layer is made of hexagonal boron nitride. The channel layer is disposed on the gate dielectric layer.

8. The two-dimensional semiconductor p-type field-effect transistor based on a transition metal oxide contact as described in claim 6, characterized in that, The thickness of the molybdenum trioxide layer is 5~15 nm, and the thickness of the gold layer is 30~60 nm.

9. The two-dimensional semiconductor p-type field-effect transistor based on a transition metal oxide contact as described in claim 6, characterized in that, The hole Schottky barrier height of the two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts is less than 60 meV; the hole mobility at room temperature is greater than 80 cm⁻¹. 2 / (V·s), on / off ratio greater than 10 8 The single-sided contact resistance is less than 1 kΩ·μm.

10. The application of the two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts prepared by the preparation method according to any one of claims 1 to 5, and the two-dimensional semiconductor p-type field-effect transistor based on transition metal oxide contacts according to any one of claims 6 to 9 in the preparation of electronic devices.

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