Display panel, its manufacturing method and display device

Abstract

This application provides a display panel, a method for fabricating the same, and a display device. The display panel includes: an array substrate, the array substrate including a planarization layer; a pixel defining layer located on one side of the array substrate; and an encapsulation layer located on the side of the pixel defining layer opposite to the array substrate, the encapsulation layer including an organic encapsulation layer; wherein the moisture content of the planarization layer is lower than the moisture content of the organic encapsulation layer. Because the moisture content of the planarization layer in the array substrate is lower than that of the organic encapsulation layer, when removing moisture from the organic encapsulation layer, the low moisture content of the planarization layer means that almost no water vapor escapes from the planarization layer, thus not affecting the pixel defining layer. This prevents peeling between the pixel defining layer and the planarization layer, which is beneficial for improving the yield of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to display panels, their manufacturing methods, and display devices. Background Technology

[0002] A display panel is a device with display functionality. Current display panels, such as those using Organic Light Emitting Diode (OLED) and Light Emitting Diode (LED) technologies, offer advantages like high image quality, energy efficiency, slim design, and wide applicability. They are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers, becoming the mainstream display panel technology. However, the performance of current display panels still needs improvement. Summary of the Invention

[0003] In view of this, embodiments of this application provide a display panel, a method for manufacturing the same, and a display device.

[0004] The first aspect of this application provides a display panel, including:

[0005] An array substrate, the array substrate including a planarization layer;

[0006] Pixel defining layer, located on one side of the array substrate;

[0007] The encapsulation layer is located on the side of the pixel defining layer opposite to the array substrate, and the encapsulation layer includes an organic encapsulation layer;

[0008] The moisture content of the planarization layer is lower than that of the organic encapsulation layer.

[0009] In one embodiment, the moisture content of the planarization layer is 60-80% of the moisture content of the organic encapsulation layer;

[0010] Preferably, the moisture content of the planarization layer is 70% of the moisture content of the organic encapsulation layer.

[0011] In one embodiment, the display panel includes a bezel region in which the orthographic projection of the pixel defining layer onto the plane of the array substrate overlaps the orthographic projection of the planarization layer onto the plane of the array substrate.

[0012] Preferably, in the border area, at least a portion of the pixel-defining layer is in direct contact with the planarization layer;

[0013] Preferably, the side edge of the planarization layer is located in the border area, and the pixel defining layer covers the side edge of the planarization layer and contacts the array substrate.

[0014] In one embodiment, the planarization layer includes a first planarization layer and a second planarization layer, the first planarization layer being located on the side of the second planarization layer close to the pixel defining layer, the water content of the first planarization layer being lower than the water content of the organic encapsulation layer, and / or, the water content of the second planarization layer being lower than the water content of the organic encapsulation layer.

[0015] Preferably, the first planarization layer and the second planarization layer are made of the same material, and both include organic materials.

[0016] In one embodiment, the array substrate includes a substrate, a metal layer, and an insulating layer, wherein the substrate is located on the side of the metal layer opposite to the pixel defining layer;

[0017] The metal layer includes a first metal layer, a second metal layer and a third metal layer stacked together. The first metal layer is located on the side of the second metal layer closer to the substrate, and the insulating layer is located between two adjacent metal layers among the first metal layer, the second metal layer and the third metal layer.

[0018] Preferably, the planarization layer includes a second planarization layer located on the side of the third metal layer opposite to the substrate;

[0019] Preferably, the array substrate further includes a fourth metal layer located on the side of the second planarization layer facing away from the substrate, and the fourth metal layer is electrically connected to the third metal layer;

[0020] Preferably, the planarization layer includes a first planarization layer located on the side of the fourth metal layer facing away from the substrate;

[0021] Preferably, the display panel includes a bezel area, a third metal layer and an insulating layer extending to the bezel area, a second planarization layer covering a portion of the third metal layer, and a fourth metal layer covering the edge of the second planarization layer and contacting a portion of the third metal layer;

[0022] Preferably, the fourth metal layer extends to the border region, where the third metal layer includes the edge of the third metal layer, the fourth metal layer includes the edge of the fourth metal layer, and the first planarization layer covers the edge of the third metal layer and the edge of the fourth metal layer.

[0023] Preferably, the pixel defining layer extends to cover the edge of the first flat layer and contacts the insulating layer.

[0024] In one embodiment, it further includes: a first electrode layer located between the planarization layer and the pixel defining layer, the first electrode layer including a plurality of first electrodes;

[0025] Preferably, the display panel includes a display area, in which a pixel defining layer has a plurality of first openings, the first openings exposing a portion of a first electrode;

[0026] Preferably, it further includes: a light-emitting functional layer, a portion of which is located in the first opening and on the side of the first electrode facing away from the array substrate;

[0027] The second electrode layer is located on the side of the light-emitting functional layer that is away from the first electrode layer.

[0028] In one embodiment, it further includes: a partition structure located on the side of the pixel defining layer away from the array substrate, the partition structure having a plurality of second openings, the orthographic projection of the first opening on the array substrate being located within the orthographic projection range of the second opening on the array substrate;

[0029] The light-emitting functional layer includes multiple light-emitting units, which are located within the first and second openings that are connected together.

[0030] Preferably, the partition structure includes a first part and a second part stacked together, the first part being located on the side of the second part away from the array substrate, and the orthographic projection of the second part on the array substrate being within the orthographic projection range of the first part on the array substrate.

[0031] Preferably, the partition structure further includes a third part located on the side of the second part close to the array substrate, and the orthographic projection of the second part on the array substrate is within the orthographic projection range of the third part on the array substrate.

[0032] In one embodiment, the encapsulation layer further includes: a first encapsulation layer located on the side of the organic encapsulation layer close to the array substrate, the first encapsulation layer including a plurality of encapsulation portions, the encapsulation portions corresponding to the second opening, and the orthographic projection of the encapsulation portions on the array substrate covering the orthographic projection of the second electrode layer on the array substrate.

[0033] Preferably, the orthographic projection of the first encapsulation layer on the array substrate and the orthographic projection of the pixel defining layer on the array substrate at least partially overlap;

[0034] Preferably, the display panel includes a bezel area, and a portion of the first encapsulation layer located in the bezel area contacts the pixel defining layer.

[0035] In one embodiment, the encapsulation layer further includes: a second encapsulation layer located on the side of the organic encapsulation layer opposite to the array substrate, wherein the orthographic projection of the second encapsulation layer on the array substrate covers the orthographic projection of the organic encapsulation layer on the array substrate.

[0036] Preferably, the orthographic projection of the second encapsulation layer on the array substrate covers the orthographic projection of the pixel defining layer on the array substrate.

[0037] A second aspect of this application provides a display panel, comprising:

[0038] Substrate;

[0039] Pixel defining layer, located on one side of the substrate;

[0040] The first organic layer is located on the side of the pixel defining layer closest to the substrate;

[0041] The second organic layer is located on the side of the pixel defining layer that faces away from the substrate;

[0042] The water content of the first organic layer is lower than that of the second organic layer.

[0043] In one embodiment, the first organic layer includes a planarization layer;

[0044] Preferably, the second organic layer includes an organic encapsulation layer.

[0045] In one embodiment, the water content of the first organic layer is 60-80% of the water content of the second organic layer;

[0046] Preferably, the water content of the first organic layer is 70% of the water content of the second organic layer.

[0047] A third aspect of this application provides a method for manufacturing a display panel, comprising:

[0048] An array substrate including a planarization layer is provided, and the array substrate is dried.

[0049] A pixel defining layer is fabricated on one side of the array substrate;

[0050] An encapsulation layer, including an organic encapsulation layer, is fabricated on the side of the pixel defining layer facing away from the array substrate;

[0051] The moisture content of the planarization layer is lower than that of the organic encapsulation layer.

[0052] In one embodiment, the drying process includes a baking process;

[0053] Preferably, the baking conditions include at least one of the following: a temperature of 200–300°C; and a time of 10 min–1 h.

[0054] In one embodiment, prior to the step of fabricating the encapsulation layer including the organic encapsulation layer on the side of the pixel defining layer facing away from the array substrate, the method further includes:

[0055] A partition structure is fabricated on the side of the pixel defining layer away from the array substrate;

[0056] Preferably, the step of fabricating the partition structure on the side of the pixel defining layer facing away from the array substrate includes:

[0057] A second partition material layer and a first partition material layer are sequentially fabricated on the side of the pixel defining layer facing away from the array substrate; the first partition material layer and the second partition material layer are patterned to obtain multiple second openings and a stacked first part and a second part, wherein the first part is located on the side of the second part facing away from the array substrate, and the orthographic projection of the second part on the array substrate is located within the orthographic projection of the first part on the array substrate; or,

[0058] A third partition material layer, a second partition material layer, and a first partition material layer are sequentially prepared on the side of the pixel defining layer away from the array substrate. The first partition material layer, the second partition material layer, and the third partition material layer are patterned to obtain multiple second openings and a first part, a second part, and a third part stacked sequentially. The first part is located on the side of the second part away from the array substrate. The orthographic projection of the second part on the array substrate is within the orthographic projection range of the first part on the array substrate. The orthographic projection of the second part on the array substrate is within the orthographic projection range of the third part on the array substrate.

[0059] In one embodiment, before fabricating a pixel defining layer on one side of the array substrate, the method further includes: fabricating a first electrode layer on one side of the array substrate;

[0060] Preferably, before the step of fabricating the encapsulation layer including the organic encapsulation layer on the side of the pixel defining layer facing away from the array substrate, the method further includes:

[0061] A light-emitting functional layer and a second electrode layer are sequentially fabricated within the first and second openings of the pixel-defining layer that are connected.

[0062] Preferably, the step of sequentially fabricating a light-emitting functional layer and a second electrode layer within the first and second openings of the interconnected pixel defining layer includes:

[0063] A light-emitting functional material layer, a second electrode material layer, and a first encapsulation material layer are sequentially prepared within the first and second openings that are connected.

[0064] The light-emitting functional material layer, the second electrode material layer, and the first encapsulation material layer are patterned to obtain a light-emitting functional layer, a second electrode layer, and a first encapsulation layer with multiple light-emitting units.

[0065] A fourth aspect of this application provides a display device, including the display panel described above, or including a display panel prepared by the preparation method described above.

[0066] In one embodiment, the display device further includes a touch panel, which is stacked on top of the display panel.

[0067] According to the display panel provided in the embodiments of this application, the water content of the planarization layer in the array substrate is lower than that of the organic encapsulation layer. In the process of patterning and preparing the light-emitting unit, multiple cleaning and drying are required. Since the water content of the planarization layer is low, the water vapor in the planarization layer will hardly escape and will not affect the pixel defining layer or the first electrode layer of the light-emitting unit. This prevents peeling between the pixel defining layer and the planarization layer, which is beneficial to improving the yield of the display panel. Attached Figure Description

[0068] Figure 1This is a schematic diagram of the structure of the display panel in one embodiment of this application.

[0069] Figure 2 This is a schematic diagram of the partition structure in one embodiment of this application.

[0070] Figure 3 This is a schematic diagram of the partition structure in another embodiment of this application.

[0071] Figure 4 This is a schematic diagram of the partition structure in another embodiment of this application.

[0072] Figure 5 This is a schematic diagram of the structure of the display panel in another embodiment of this application.

[0073] Figure 6 This is a schematic diagram of the structure of the display panel in another embodiment of this application.

[0074] Figure 7 This is a schematic diagram of the structure of the display panel in another embodiment of this application.

[0075] Figure 8 This is a schematic diagram of the structure of the display panel in another embodiment of this application.

[0076] Figure 9 This is a schematic diagram of the structure of the display panel in another embodiment of this application.

[0077] Figure 10 This is a schematic diagram of the structure of the display panel in another embodiment of this application.

[0078] Figure 11 This is a schematic diagram of the structure of the display panel in another embodiment of this application.

[0079] Figure 12 This is a schematic diagram of the structure of the display panel in another embodiment of this application.

[0080] Figure 13 This is a schematic diagram of the structure of the display panel in another embodiment of this application.

[0081] Figure 14 This is a schematic diagram of the process for manufacturing a display panel in one embodiment of this application.

[0082] Figure 15 This is a schematic diagram of the process for manufacturing a display panel in another embodiment of this application.

[0083] Figure 16 This is a schematic diagram of the structure of a display device in one embodiment of this application. Detailed Implementation

[0084] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0085] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented even without certain specific details. In some instances, methods and means well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0086] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0087] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0088] The first aspect of this application provides a display panel, as shown in the reference... Figure 1 The schematic diagram of the display panel shown includes: an array substrate 100, which includes a planarization layer 110; a pixel defining layer 200 located on one side of the array substrate 100; and an encapsulation layer 300 located on the side of the pixel defining layer 200 facing away from the array substrate 100, wherein the encapsulation layer 300 includes an organic encapsulation layer 310; wherein the water content of the planarization layer 110 is lower than the water content of the organic encapsulation layer 310.

[0089] According to the display panel provided in the embodiments of this application, the moisture content of the planarization layer 110 in the array substrate 100 is lower than that of the organic encapsulation layer 310. In the process of patterning and fabricating the light-emitting unit, multiple cleaning and drying processes are required. Since the moisture content of the planarization layer 110 is low, the water vapor in the planarization layer 110 will hardly escape and will not affect the pixel defining layer 200 or the first electrode layer of the light-emitting unit. This prevents peeling between the pixel defining layer 200 and the planarization layer 110, which is beneficial to improving the yield of the display panel.

[0090] In one embodiment, refer to Figure 1 The display panel includes a display area AA, in which a pixel defining layer 200 has a plurality of first openings 210.

[0091] In one embodiment, refer to Figure 1The display panel also includes a partition structure 400 located on the side of the pixel defining layer 200 facing away from the array substrate 100, the partition structure 400 having a plurality of second openings 410. Patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 099419, and PCT / CN2024 / 099072 describe relevant content of the partition structure 400 and are provided for reference.

[0092] For example, the first opening 210 and the second opening 410 are correspondingly provided, and the orthographic projection of the first opening 210 on the array substrate 100 is located within the orthographic projection range of the second opening 410 on the array substrate 100.

[0093] In one embodiment, refer to Figure 2 and Figure 3 The schematic diagram of the partition structure shown illustrates that the partition structure 400 includes a first part 401 and a second part 402 stacked together. The first part 401 is located on the side of the second part 402 facing away from the array substrate 100, and the orthographic projection of the second part 402 on the array substrate 100 lies within the orthographic projection of the first part 401 on the array substrate 100. For example, the second part 402 can be designed as an independent film layer, meaning there is no physical interface within the second part 402, and all parts are made of the same material, such as aluminum. Alternatively, the second part 402 can be designed as being composed of at least two stacked film layers. For example, the second part 402 can be formed by stacking two conductive film layers, the materials of which can be molybdenum and aluminum, respectively, with the molybdenum conductive film layer located between the array substrate 100 and the aluminum conductive film layer. For example, the second part 402 may include a conductive sub-part, or the second part 402 itself may be a conductive structure. The second part 402 can overlap with the first electrode layer of the light-emitting device to electrically connect the first electrode layers of adjacent light-emitting devices, thereby realizing a full-surface cathode. The material of the first part 401 can be an organic material, an inorganic material, or a metallic material. If the first part 401 is a metallic material, it can be titanium. In this case, the cross-section of the partition structure 400 is T-shaped or inverted trapezoidal.

[0094] In one embodiment, refer to Figure 4The schematic diagram of the partition structure shown illustrates that the partition structure 400 further includes a third part 403 located on the side of the second part 402 near the array substrate 100. The orthographic projection of the second part 402 onto the array substrate 100 lies within the orthographic projection range of the third part 403 onto the array substrate 100. For example, the second part 402 is a conductive film layer made of aluminum, and the third part 403 is a conductive film layer made of molybdenum. In this case, the cross-section of the partition structure 400 is I-shaped.

[0095] In one embodiment, refer to Figure 1 The display panel further includes: a first electrode layer 510 located between the planarization layer 110 and the pixel defining layer 200; a light-emitting functional layer 520, a portion of which is located in the first opening 210 and on the side of the first electrode 511 facing away from the array substrate 100; and a second electrode layer 530 located on the side of the light-emitting functional layer 520 facing away from the first electrode layer 510. The first electrode layer 510, the light-emitting functional layer 520, and the second electrode layer 530 constitute a light-emitting device. During the fabrication of the light-emitting device, the partition structure 400 facilitates the separation of the light-emitting functional layer 520 and the second electrode layer 530, eliminating the need for a mask, and resulting in higher precision of the fabricated light-emitting functional layer 520 and the second electrode layer 530, thus improving the display quality of the display panel.

[0096] For example, the first electrode layer 510 includes a plurality of first electrodes 511, and the first opening 210 exposes a portion of the first electrodes 511.

[0097] In one embodiment, the light-emitting functional layer 520 includes a plurality of light-emitting units 521, which are located within a first opening 210 and a second opening 410 that are connected. It is understood that a portion of the light-emitting functional layer 520 is located in the first opening 210, and the remaining portion extends outward from the first opening 210 to the side of the pixel defining layer 200 opposite to the first electrode layer 510; correspondingly, a portion of the second electrode layer 530 is located in the first opening 210, and the remaining portion extends outward from the first opening 210 to the side of the pixel defining layer 200 opposite to the first electrode layer 510. Optionally, a portion of the light-emitting functional layer 520 is located in the first opening 210, and the remaining portion of the light-emitting functional layer 520 extends into the second opening 410 and is located on the side of the pixel defining layer 200 opposite to the first electrode layer 510; correspondingly, a portion of the second electrode layer 530 is located in the first opening 210, and the remaining portion of the second electrode layer 530 extends into the second opening 410 and is located on the side of the pixel defining layer 200 opposite to the first electrode layer 510.

[0098] It is understood that one of the first electrode layer 510 and the second electrode layer 530 is an anode, and the other of the first electrode layer 510 and the second electrode layer 530 is a cathode. For example, the first electrode layer 510 is an anode, and the second electrode layer 530 is a cathode.

[0099] For example, the second electrode layer 530 extending into the second opening 410 overlaps with the partition structure 400, for example, it can overlap with the third part 403 and / or the second part 402 of the partition structure, which is beneficial to realize a full-surface cathode.

[0100] For example, the light-emitting functional layer includes an emitting layer (EML), and may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), and an electron-blocking layer (EBL) located between the anode and the emitting layer (EML), and at least one of an electron injection layer (EIL), an electron transport layer (ETL), and a hole-blocking layer (HBL) located between the cathode and the emitting layer (EML).

[0101] In one embodiment, refer to Figure 5 The schematic diagram of the display panel shown indicates that the encapsulation layer 300 further includes a first encapsulation layer 320 located on the side of the organic encapsulation layer 310 near the array substrate 100. The first encapsulation layer 320 includes a plurality of encapsulation portions 321, which correspond to the second opening 410. The orthographic projection of the encapsulation portion 321 on the array substrate 100 covers the orthographic projection of the second electrode layer 530 on the array substrate 100. Therefore, the correspondence between the encapsulation portion 321 and the second opening 410 facilitates pixel-level encapsulation and improves the encapsulation effect of the display panel.

[0102] In one embodiment, the orthographic projection of the first encapsulation layer 320 on the array substrate 100 at least partially overlaps with the orthographic projection of the pixel defining layer 200 on the array substrate 100. Therefore, the encapsulation effect of the first encapsulation layer 320 is superior.

[0103] In one embodiment, refer to Figure 10 The schematic diagram of the display panel shown includes a bezel area NA, where a portion of the first encapsulation layer 320 in the bezel area NA contacts the pixel defining layer 200. This results in a better encapsulation effect for the first encapsulation layer 320.

[0104] For example, the light-emitting devices include light-emitting devices of different colors, such as red light-emitting device R, green light-emitting device G, and blue light-emitting device B. For ease of fabrication, one color of light-emitting device can be fabricated first, and a corresponding encapsulation portion 321 can be fabricated on the side of the light-emitting device facing away from the array substrate 100. Then, another color of light-emitting device and its corresponding encapsulation portion 321 can be fabricated, until all colors of light-emitting devices are fabricated. For example, they can be fabricated in the order of red light-emitting device R, green light-emitting device G, and blue light-emitting device B, or they can be fabricated in the order of other colors of light-emitting devices.

[0105] For example, when fabricating a light-emitting device of a certain color, the organic light-emitting functional layer 520, the second electrode layer 530, and the encapsulation part 321 can be deposited in a whole layer by vapor deposition. Then, the organic light-emitting functional layer 520, the second electrode layer 530, and the encapsulation part 321 at the first opening corresponding to the light-emitting devices of other colors can be etched away. The encapsulation part 321 can protect the organic light-emitting functional layer 520 and the second electrode layer 530, and prevent the etching process used when fabricating the light-emitting device of the next color from etching away the organic light-emitting functional layer 520 and the second electrode layer 530 of the light-emitting device of the previous color.

[0106] In one embodiment, refer to Figure 6 The schematic diagram of the display panel shown shows that the encapsulation layer 300 further includes: a second encapsulation layer 330, located on the side of the organic encapsulation layer 310 away from the array substrate 100, and the orthographic projection of the second encapsulation layer 330 on the array substrate 100 covers the orthographic projection of the organic encapsulation layer 310 on the array substrate 100.

[0107] In one embodiment, refer to Figure 6 The orthographic projection of the second encapsulation layer 330 on the array substrate 100 covers the orthographic projection of the pixel defining layer 200 on the array substrate 100.

[0108] In one embodiment, the first encapsulation layer 320 and the second encapsulation layer 330 comprise inorganic materials. Exemplarily, the first encapsulation layer 320 includes, but is not limited to, inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride, with a refractive index typically between 1.75 and 1.95. The second encapsulation layer 330 is also made of inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride, with a refractive index typically between 1.75 and 1.95. The organic encapsulation layer 310 is made of organic materials such as polyimide (PI) and epoxy resin, with a refractive index typically between 1.5 and 1.6. Thus, the organic encapsulation layer 310, the first encapsulation layer 320, and the second encapsulation layer 330 form a composite encapsulation layer, which provides multiple layers of protection for the functional structure of the display panel, resulting in better encapsulation performance. Exemplarily, the first encapsulation layer 320 and the second encapsulation layer 330 are formed using methods such as chemical vapor deposition (CVD). The organic encapsulation layer 310 is formed using inkjet printing (IJP).

[0109] It is understandable that, due to the arrangement of the partition structure 400, the first encapsulation layer 320 is correspondingly positioned with the second opening 410 of the partition structure 400, as shown in the reference. Figure 6 The schematic diagram of the display panel shown includes a bezel area NA and a display area AA. The bezel area NA contains only a portion of the first encapsulation layer 320, leaving the planarization layer 110 surface unprotected. In one embodiment, to protect the planarization layer 110, the orthographic projection of the pixel defining layer 200 onto the plane of the array substrate 100 covers the orthographic projection of the planarization layer 110 onto the plane of the array substrate 100 in the bezel area NA. Thus, the pixel defining layer 200 protects the planarization layer 110, preventing moisture intrusion into the planarization layer 110.

[0110] For example, in the border region NA, at least a portion of the pixel defining layer 200 is in direct contact with the planarization layer 110. Thus, the pixel defining layer 200 protects the planarization layer 110 from moisture intrusion.

[0111] It is understood that the side edge of the planarization layer 110 is located in the border region NA, and the pixel defining layer 200 covers the side edge of the planarization layer 110 and contacts the array substrate 100. This is more conducive to protecting the planarization layer 110 and preventing moisture from entering the planarization layer 110; at the same time, it can also effectively prevent moisture from escaping from the planarization layer 110 to the side of the pixel defining layer 200 away from the array substrate 100.

[0112] It is understandable that the moisture content of the planarization layer 110 in the array substrate 100 is lower than that of the organic encapsulation layer 310. When the organic encapsulation layer 310 is prepared, it is baked to reduce its moisture content. Since the planarization layer 110 has a low moisture content, the water vapor in the planarization layer 110 will hardly escape and will not affect the pixel defining layer 200. This prevents peeling between the pixel defining layer 200 and the planarization layer 110, which is beneficial to improving the yield of the display panel.

[0113] In one embodiment, the water content of the planarization layer 110 is 60-80% of the water content of the organic encapsulation layer 310, for example, it can be 60%, 65%, 70%, 75%, or 80%, preferably 70%. Therefore, the water content of the planarization layer 110 is suitable. When the organic encapsulation layer 310 is baked to reduce its water content during preparation, the water in the planarization layer 110 will hardly escape and will not affect the pixel defining layer 200, thus preventing peeling between the pixel defining layer 200 and the planarization layer 110.

[0114] In one embodiment, refer to Figure 7 The schematic diagram of the display panel shown illustrates that the planarization layer 110 includes a first planarization layer 111 and a second planarization layer 112. The first planarization layer 111 is located on the side of the second planarization layer 112 closer to the pixel defining layer 200. The water content of the first planarization layer 111 is lower than that of the organic encapsulation layer 310, and / or, the water content of the second planarization layer 112 is lower than that of the organic encapsulation layer 310. Therefore, the water content of the first planarization layer 111 and the second planarization layer 112 is relatively low. When the organic encapsulation layer 310 is prepared and baked to reduce its water content, the water in the first planarization layer 111 and the second planarization layer 112 will hardly escape and will not affect the pixel defining layer 200. This prevents peeling between the pixel defining layer 200 and the first planarization layer 111, and also prevents peeling between the first planarization layer 111 and the second planarization layer 112.

[0115] For example, both the border area NA and the display area AA have a first flat layer 111 located on a second flat layer 112.

[0116] For example, the material of the first planarization layer 111 is a conventional planarization layer material, such as including but not limited to epoxy resin, photoresist, etc., which will not be described in detail here.

[0117] For example, the material of the second planarization layer 112 is the material of a conventional planarization layer, such as including but not limited to epoxy resin, photoresist, etc., which will not be described in detail here.

[0118] In one embodiment, the first planarization layer 111 and the second planarization layer 112 are made of the same material and both include organic materials.

[0119] In one embodiment, refer to Figure 8 The schematic diagram of the display panel shown shows that the array substrate 100 includes a substrate 120, a metal layer 130, and an insulating layer 140. The substrate 120 is located on the side of the metal layer 130 away from the pixel defining layer 200. The metal layer 130 includes a first metal layer 131, a second metal layer 132, and a third metal layer 133 stacked together. The first metal layer 131 is located on the side of the second metal layer 132 close to the substrate 120. The insulating layer 140 is located between two adjacent metal layers among the first metal layer 131, the second metal layer 132, and the third metal layer 133.

[0120] For example, the display panel includes a pixel driving circuit, which includes transistors and a storage capacitor. The transistor includes a semiconductor, a gate, a source, and a drain. The storage capacitor includes a first plate and a second plate. As an example, the gate and the first plate may be located on a first metal layer 131, the second plate may be located on a second metal layer 132, and the source and drain may be located on a third metal layer 133.

[0121] In one embodiment, the planarization layer 110 includes a second planarization layer 112, which is located on the side of the third metal layer 133 facing away from the substrate 120. Thus, the second planarization layer 112 can effectively planarize the film structure located on the side of the second planarization layer 112 facing away from the substrate 120, ensuring the yield of the display panel.

[0122] In one embodiment, refer to Figure 9 The schematic diagram of the display panel shown illustrates that the array substrate 100 further includes a fourth metal layer 150 located on the side of the second planarization layer 112 facing away from the substrate 120. The fourth metal layer 150 is electrically connected to the third metal layer 133. Exemplarily, the fourth metal layer 150 is electrically connected to the first electrode layer 510. The fourth metal layer 150 serves as a connection electrode between the first electrode layer 510 and the third metal layer 133, transmitting signals from the source and drain electrodes to the first electrode layer 510 for driving the light-emitting devices.

[0123] In one embodiment, refer to Figure 9 The schematic diagram of the display panel shown shows that the planarization layer 110 includes a first planarization layer 111, which is located on the side of the fourth metal layer 150 away from the substrate 120.

[0124] In one embodiment, refer to Figure 10The schematic diagram of the display panel shown includes a bezel area NA, a third metal layer 133 and an insulating layer 140 extending to the bezel area NA, a second planarization layer 112 covering a portion of the third metal layer 133, and a fourth metal layer 150 covering the edge of the second planarization layer 112 and contacting a portion of the third metal layer 133.

[0125] In one embodiment, the fourth metal layer 150 extends to the border region NA, where the third metal layer 133 includes a third metal layer edge, the fourth metal layer 150 includes a fourth metal layer edge, and the first planarization layer 111 covers the edges of the third metal layer 133 and the fourth metal layer 150.

[0126] In one embodiment, the pixel defining layer 200 extends to cover the edge of the first planarization layer 111 and contacts the insulating layer 140. Thus, the pixel defining layer 200 can effectively prevent moisture from entering the side of the pixel defining layer 200 facing the array substrate, and can also effectively prevent moisture from the planarization layer 110 from escaping to the side of the pixel defining layer 200 away from the array substrate 100.

[0127] In one specific embodiment, refer to Figure 11The schematic diagram of the display panel shown includes: a substrate 120; a metal active layer 160 located on one side of the substrate 120; a first gate insulating layer 141 located on the side of the metal active layer 160 facing away from the substrate 120; a first metal layer 131 located on the side of the first gate insulating layer 141 facing away from the substrate 120; a capacitor insulating layer 142 located on the side of the first metal layer 131 facing away from the substrate 120; a second metal layer 132 located on the side of the capacitor insulating layer 142 facing away from the substrate 120; a buffer layer 143 located on the side of the second metal layer 132 facing away from the substrate 120; an oxide active layer 170 located on the side of the buffer layer 143 facing away from the substrate 120; and a second gate insulating layer 144 located on the side of the oxide active layer 170. Layer 170 is located on the side opposite to substrate 120; oxide gate layer 180 is located on the side opposite to substrate 120 of second gate insulating layer 144; interlayer dielectric layer 145 is located on the side opposite to substrate 120 of oxide gate layer 180; third metal layer 133 is located on the side opposite to substrate 120 of interlayer dielectric layer 145; second planarization layer 112 is located on the side opposite to substrate 120 of third metal layer 133; fourth metal layer 150 is located on the side opposite to substrate 120 of second planarization layer 112; first planarization layer 111 is located on the side opposite to substrate 120 of fourth metal layer 150; first electrode layer 510 is located on the side opposite to substrate 120 of first planarization layer 111; pixel defining layer 200 is located on the side opposite to substrate 120 of first electrode layer 510. On the side of the pixel defining layer 200 away from the substrate 120, in the display area AA, the pixel defining layer 200 has multiple first openings 210, and a portion of the first electrode layer 510 is exposed through the first openings 210. In the border area NA, the orthographic projection of the pixel defining layer 200 onto the substrate 120 overlaps the orthographic projection of the first planarization layer 111 onto the substrate 120. A partition structure 400, located on the side of the pixel defining layer 200 away from the substrate 120, in the display area AA, has multiple second openings 410, which are correspondingly arranged with the first openings 210, and the orthographic projection of the second openings 410 onto the substrate 120 overlaps the orthographic projection of the first openings 210 onto the substrate 120. A light-emitting functional layer 520, a portion of which is located... In the first opening 210, the remaining portion of the light-emitting functional layer 520 extends outward from the first opening 210 into the second opening 410, extending to the side of the pixel defining layer 200 opposite to the first electrode layer 510; the second electrode layer 530 is located on the side of the light-emitting functional layer 520 opposite to the substrate 120, with a portion of the second electrode layer 530 located in the first opening 210, and the remaining portion of the second electrode layer 530 extending outward from the first opening 210 into the second opening 410, and overlapping with the partition structure 400; the first encapsulation layer 320 includes a plurality of encapsulation portions 321, the encapsulation portions 321 corresponding to the second opening 410, and the orthographic projection of the encapsulation portions 321 on the array substrate 100 covers the orthographic projection of the second electrode layer 530 on the array substrate 100.An organic encapsulation layer 310 is located on the side of the first encapsulation layer 320 facing away from the substrate 120, and is present in both the display area AA and the bezel area NA. A second encapsulation layer 330 is located on the side of the organic encapsulation layer 310 facing away from the substrate 120. The orthographic projection of the second encapsulation layer 330 on the substrate 120 overlaps the orthographic projection of the organic encapsulation layer 310 on the substrate 120, and also overlaps the orthographic projection of the pixel defining layer 200 on the substrate 120. This display panel has two gates, resulting in higher efficiency.

[0128] Optionally, the first gate insulating layer 141, the capacitor insulating layer 142, the buffer layer 143, the second gate insulating layer 144, and the interlayer dielectric layer 145 are all insulating layers 140.

[0129] For example, the material of the oxide active layer 170 includes, but is not limited to, indium gallium zinc oxide (IGZO), and the material of the oxide gate layer 180 includes, but is not limited to, nano-cesium tungsten oxide (GATO).

[0130] In some embodiments, the array substrate may be a glass substrate. In one embodiment, the array substrate may include an organic resin material such as epoxy resin, triazine, silicone resin, or polyimide. For example, the array substrate may be an FR4 type printed circuit board (PCB), or it may be a flexible PCB that is easily deformable. In one embodiment, the array substrate may include a ceramic material such as silicon nitride, aluminum nitride, or aluminum oxide, or it may include a metal or metal compound. For example, the array substrate may be a metal core PCB (MCPCB) or a metal copper clad laminate (MCCL).

[0131] A second aspect of this application provides a display panel, as shown in [reference]. Figure 12 The schematic diagram of the display panel shown includes: a substrate 120; a pixel defining layer 200 located on one side of the substrate 120; a first organic layer 301 located on the side of the pixel defining layer 200 close to the substrate 120; and a second organic layer 302 located on the side of the pixel defining layer 200 away from the substrate 120. The water content of the first organic layer 301 is lower than that of the second organic layer 302.

[0132] In one embodiment, refer to Figure 13 The schematic diagram of the display panel shown shows that the first organic layer 301 includes a planarization layer 110; and the second organic layer 302 includes an organic encapsulation layer 310.

[0133] It should be noted that the planarization layer and organic encapsulation layer are the same as described above, and will not be elaborated further here.

[0134] In one embodiment, the water content of the first organic layer 301 is 60-80% of the water content of the second organic layer 302, for example, it can be 60%, 65%, 70%, 75%, or 80%, preferably 70%. Therefore, the water content of the first organic layer 301 is suitable. When the second organic layer 302 is baked to reduce its water content during preparation, the water in the first organic layer 301 will hardly escape and will not affect the pixel defining layer 200, thus preventing peeling between the pixel defining layer 200 and the first organic layer 301.

[0135] In one embodiment, the planarization layer 110 includes a first planarization layer 111 and a second planarization layer 112. The first planarization layer 111 is located on the side of the second planarization layer 112 closer to the pixel defining layer 200. The water content of the first planarization layer 111 is lower than that of the organic encapsulation layer 310, and / or the water content of the second planarization layer 112 is lower than that of the organic encapsulation layer 310. Therefore, the water content of the first planarization layer 111 and the second planarization layer 112 is relatively low. When the organic encapsulation layer 310 is baked to reduce its water content during fabrication, the water in the first planarization layer 111 and the second planarization layer 112 will hardly escape and will not affect the pixel defining layer 200. This prevents peeling between the pixel defining layer 200 and the first planarization layer 111, and also prevents peeling between the first planarization layer 111 and the second planarization layer 112.

[0136] For example, both the border area NA and the display area AA have a first flat layer 111 located on a second flat layer 112.

[0137] For example, the material of the first planarization layer 111 is a conventional planarization layer material, such as including but not limited to epoxy resin, photoresist, etc., which will not be described in detail here.

[0138] For example, the material of the second planarization layer 112 is the material of a conventional planarization layer, such as including but not limited to epoxy resin, photoresist, etc., which will not be described in detail here.

[0139] In one embodiment, refer to Figure 8The schematic diagram of the display panel shown shows that the array substrate 100 includes a substrate 120, a metal layer 130, and an insulating layer 140. The substrate 120 is located on the side of the metal layer 130 away from the pixel defining layer 200. The metal layer 130 includes a first metal layer 131, a second metal layer 132, and a third metal layer 133 stacked together. The first metal layer 131 is located on the side of the second metal layer 132 close to the substrate 120. The insulating layer 140 is located between two adjacent metal layers among the first metal layer 131, the second metal layer 132, and the third metal layer 133.

[0140] For example, the display panel includes a pixel driving circuit, which includes transistors and a storage capacitor. The transistor includes a semiconductor, a gate, a source, and a drain. The storage capacitor includes a first plate and a second plate. As an example, the gate and the first plate may be located on a first metal layer 131, the second plate may be located on a second metal layer 132, and the source and drain may be located on a third metal layer 133.

[0141] In one embodiment, the planarization layer 110 includes a second planarization layer 112, which is located on the side of the third metal layer 133 facing away from the substrate 120. Thus, the second planarization layer 112 can effectively planarize the film structure located on the side of the second planarization layer 112 facing away from the substrate 120, ensuring the yield of the display panel.

[0142] In one embodiment, refer to Figure 9 The schematic diagram of the display panel shown illustrates that the array substrate 100 further includes a fourth metal layer 150 located on the side of the second planarization layer 112 facing away from the substrate 120. The fourth metal layer 150 is electrically connected to the third metal layer 133. Exemplarily, the fourth metal layer 150 is electrically connected to the first electrode layer 510. The fourth metal layer 150 serves as a connection electrode between the first electrode layer 510 and the third metal layer 133, transmitting signals from the source and drain electrodes to the first electrode layer 510 for driving the light-emitting devices.

[0143] In one embodiment, refer to Figure 9 The schematic diagram of the display panel shown shows that the planarization layer 110 includes a first planarization layer 111, which is located on the side of the fourth metal layer 150 away from the substrate 120.

[0144] In one embodiment, refer to Figure 1 The display panel also includes a partition structure 400 located on the side of the pixel defining layer 200 opposite to the array substrate 100, the partition structure 400 having a plurality of second openings 410. It should be noted that the partition structure 400 is consistent with the previous description, and will not be described in detail here.

[0145] In some embodiments, the film layer structure between the substrate 120 and the first planarization layer 111 collectively constitutes the array substrate, which may be a glass substrate. In one embodiment, the array substrate may include an organic resin material such as epoxy resin, triazine, silicone resin, or polyimide. For example, the array substrate may be an FR4 type printed circuit board (PCB), or it may be a flexible PCB that is easily deformable. In one embodiment, the array substrate may include a ceramic material such as silicon nitride, aluminum nitride, or aluminum oxide, or it may include a metal or metal compound. For example, the array substrate may be a metal core PCB (MCPCB) or a metal copper clad laminate (MCCL).

[0146] It should be noted that the display panel in this embodiment can be integrated with the structure of the display panel described above, either as a whole or in part, which will not be elaborated further here.

[0147] The third aspect of this application provides a method for manufacturing a display panel, referring to... Figure 14 The diagram shows a process flow chart for manufacturing a display panel, which includes the following steps.

[0148] S100: Provides an array substrate including a planarization layer, and performs a drying process on the array substrate.

[0149] It should be noted that the array substrate is the same as described above, and will not be repeated here.

[0150] It is understandable that drying the array substrate can remove water from the planarization layer, thus preventing the planar area from peeling off from subsequent film layers, such as during heating processes. For example, it can prevent peeling between the planarization layer and the pixel defining layer.

[0151] In one embodiment, the drying process includes a baking process. Therefore, the operation is simple, convenient, and easy to implement, and can effectively remove water from the planarization layer.

[0152] In one embodiment, the baking conditions include at least one of the following: a temperature of

[0153] The baking temperature is 200–300℃, for example, 200℃, 220℃, 240℃, 260℃, 280℃, or 300℃; and the baking time is 10 min–1 h, for example, 10 min, 20 min, 30 min, 40 min, 50 min, or 1 h. Therefore, the baking effect is excellent, effectively removing water from the planarization layer. For example, the water content of the planarization layer can be 60–80% of the water content of the organic encapsulation layer. Thus, the water content of the planarization layer is suitable, and when baking the organic encapsulation layer to reduce its water content during the preparation of the organic encapsulation layer, the water in the planarization layer will hardly escape and will not affect the pixel boundary layer, preventing peeling between the pixel boundary layer and the planarization layer.

[0154] In one embodiment, the display panel includes a light-emitting device, which includes a first electrode layer, a light-emitting functional layer, and a second electrode layer, as shown in the figure. Figure 15 The schematic diagram of the display panel fabrication method shown includes the following steps before fabricating the pixel defining layer on one side of the array substrate.

[0155] S110: A first electrode layer is prepared on one side of the array substrate, and the first electrode layer is partially exposed in the first opening.

[0156] It should be noted that the preparation method of the first electrode layer is a conventional method and is not considered an improvement in this application, so it will not be described in detail here.

[0157] S200: A pixel defining layer is prepared on one side of the array substrate.

[0158] It should be noted that the pixel delimitation layer is the same as described above, and will not be elaborated on further here.

[0159] For example, the display panel includes a border area and a display area, wherein a plurality of first openings are formed in the pixel-defining layer in the display area.

[0160] It should be noted that the method for preparing the pixel delimiting layer is a conventional method and is not considered an improvement in this application, so it will not be described in detail here.

[0161] In one embodiment, refer to Figure 15 Before fabricating the organic encapsulation layer on the side of the pixel defining layer away from the array substrate, the process further includes the following steps.

[0162] S210: A partition structure is fabricated on the side of the pixel defining layer away from the array substrate.

[0163] In one embodiment, the step of fabricating a partition structure on the side of the pixel defining layer away from the array substrate includes: sequentially fabricating a second partition material layer and a first partition material layer on the side of the pixel defining layer away from the array substrate; patterning the first partition material layer and the second partition material layer to obtain a plurality of second openings and a first part and a second part stacked thereon, wherein the first part is located on the side of the second part away from the array substrate, and the orthographic projection of the second part on the array substrate is located within the orthographic projection of the first part on the array substrate. For example, the partition structure can be made of stacked materials with different etching rates, that is, the etching rates of the first partition material layer and the second partition material layer are different. For example, the material of the first partition material layer is titanium, and the material of the second partition material layer is aluminum. The etching rate of the second partition material layer is greater than that of the first partition material layer. The method for preparing the partition structure includes the following steps: a second partition material layer and a first partition material layer are sequentially prepared on the side of the first electrode layer away from the substrate. In the same etching environment, more material is etched away from the second partition material layer to form the second part of the partition structure, while less material is etched away from the first partition material layer to form the first part of the partition structure.

[0164] In another embodiment, a third partition material layer, a second partition material layer, and a first partition material layer are sequentially prepared on the side of the pixel defining layer away from the array substrate. The first partition material layer, the second partition material layer, and the third partition material layer are patterned to obtain a plurality of second openings and a first part, a second part, and a third part stacked sequentially. The first part is located on the side of the second part away from the array substrate, the orthographic projection of the second part on the array substrate is within the orthographic projection range of the first part on the array substrate, and the orthographic projection of the second part on the array substrate is within the orthographic projection range of the third part on the array substrate.

[0165] For example, the partition structure can be made of stacked materials with different etching rates, that is, the etching rates of the third partition material layer, the second partition material layer and the first partition material layer are different. For example, the materials of the first partition material layer and the third partition material layer are titanium, and the material of the second partition material layer is aluminum. The etching rate of the second partition material layer is greater than that of the first partition material layer and the third partition material layer. The method for fabricating the partition structure includes the following steps: the third partition material layer, the second partition material layer and the first partition material layer are sequentially fabricated on the side of the first electrode layer away from the substrate. In the same etching environment, more material is etched away from the second partition material layer to form the second part of the partition structure, while less material is etched away from the first partition material layer and the third partition material layer to form the first part and the third part of the partition structure.

[0166] In one embodiment, after the partition structure is fabricated, before the step of fabricating an encapsulation layer including an organic encapsulation layer on the side of the pixel defining layer facing away from the array substrate, the method further includes: sequentially fabricating a light-emitting functional layer and a second electrode layer within a first opening and a second opening of the interconnected pixel defining layer.

[0167] In one embodiment, the step of sequentially fabricating a light-emitting functional layer and a second electrode layer within a first opening and a second opening of a pixel-defining layer that are connected includes: sequentially fabricating a light-emitting functional material layer, a second electrode material layer, and a first encapsulation material layer within a first opening and a second opening that are connected; and patterning the light-emitting functional material layer, the second electrode material layer, and the first encapsulation material layer to obtain the light-emitting functional layer, the second electrode layer, and the first encapsulation layer.

[0168] S300: An encapsulation layer including an organic encapsulation layer is prepared on the side of the pixel defining layer away from the array substrate.

[0169] The moisture content of the planarization layer is lower than that of the organic encapsulation layer.

[0170] It should be noted that the organic encapsulation layer is consistent with the previous description, and will not be elaborated on further here.

[0171] It should be noted that the method for preparing the organic encapsulation layer is a conventional method and is not considered an improvement in this application, so it will not be described in detail here.

[0172] In one embodiment, the light-emitting device includes a light-emitting functional layer and a second electrode layer, and the encapsulation layer further includes a first encapsulation layer, which includes an encapsulation portion. The light-emitting device includes a red light-emitting device R, a green light-emitting device G, and a blue light-emitting device B. Exemplarily, taking the fabrication sequence of the light-emitting device as red light-emitting device R, green light-emitting device G, and blue light-emitting device B as an example, the fabrication method of the light-emitting functional layer, the second electrode layer, and the first encapsulation layer includes the following steps: fabricating the entire light-emitting functional layer corresponding to the red light-emitting device R using methods such as vapor deposition, inkjet printing, or printing; fabricating the entire second electrode layer corresponding to the red light-emitting device R using vapor deposition; fabricating the entire encapsulation portion corresponding to the red light-emitting device R using vapor deposition; etching away the light-emitting functional layer, the second electrode layer, and the encapsulation portion corresponding to the red light-emitting device R at the corresponding positions of the green light-emitting device G and the blue light-emitting device B using wet etching; and fabricating the light-emitting functional layer, the second electrode layer, and the encapsulation portion corresponding to the green light-emitting device G and the blue light-emitting device B using a fabrication method similar to that of the red light-emitting device R. In this process, the partition structure acts as a mask, resulting in higher precision of the light-emitting device and improving the manufacturing yield of the display panel.

[0173] It should be noted that in this embodiment, patterning is involved in the fabrication of the isolation structure, pixel defining layer and light-emitting device. Each patterning process requires washing and drying. Unless otherwise specified, the washing and drying processes after patterning are routine operations and are not considered improvements in this application. They will not be elaborated further here.

[0174] It should be noted that the display panel prepared by the method of this embodiment can be combined with the display panel described above in whole or in part, which will not be elaborated further here.

[0175] A fourth aspect of this application provides a display device, which includes the display panel described above, or a display panel prepared by the fabrication method described above. In this embodiment, the planarization layer and the pixel defining layer hardly peel off, resulting in a high yield rate for the display device.

[0176] In one embodiment, refer to Figure 16 The schematic diagram of the display device shown includes a touch panel 20, which is stacked with the display panel 10.

[0177] It is understood that the touch panel can be a self-capacitive touch panel or a mutual-capacitive touch panel. The structure of the touch panel is the same as that of a conventional touch panel and is not considered an improvement in this application, so it will not be described in detail here. Taking a mutual-capacitive touch panel as an example, a mutual-capacitive touch panel includes a stacked emitter electrode layer, an insulating layer, and a receiver electrode layer. The structure of the emitter electrode layer, the insulating layer, and the receiver electrode layer is a conventional structure and is not considered an improvement in this application, so it will not be described in detail here.

[0178] It should be noted that, in addition to the display panel and touch panel described above, the display device may also include the structures that a conventional display device should have, such as the casing, power supply, and driver chip, which will not be elaborated on further here.

[0179] For example, the display device can be used for color display or for black and white display; the display device can be used for dynamic display or for static display.

[0180] Exemplarily, the display device can include any device or product with display functionality. For example, the display device can be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc. Because this display device includes the display panel described in this application, it offers excellent packaging, superior display performance, and lower cost.

[0181] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0182] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A display panel, characterized in that, include: An array substrate, the array substrate including a planarization layer; A pixel defining layer is located on one side of the array substrate; An encapsulation layer is located on the side of the pixel defining layer opposite to the array substrate, and the encapsulation layer includes an organic encapsulation layer; The water content of the planarization layer is lower than that of the organic encapsulation layer.

2. The display panel according to claim 1, characterized in that, The moisture content of the planarization layer is 60-80% of the moisture content of the organic encapsulation layer; Preferably, the water content of the planarization layer is 70% of the water content of the organic encapsulation layer.

3. The display panel according to claim 1, characterized in that, The display panel includes a border area, in which the orthographic projection of the pixel defining layer on the plane of the array substrate overlaps the orthographic projection of the planarization layer on the plane of the array substrate. Preferably, in the border region, at least a portion of the pixel defining layer is in direct contact with the planarization layer; Preferably, the side edge of the planarization layer is located in the border area, and the pixel defining layer covers the side edge of the planarization layer and contacts the array substrate.

4. The display panel according to claim 1, characterized in that, The planarization layer includes a first planarization layer and a second planarization layer. The first planarization layer is located on the side of the second planarization layer that is close to the pixel defining layer. The water content of the first planarization layer is lower than the water content of the organic encapsulation layer, and / or the water content of the second planarization layer is lower than the water content of the organic encapsulation layer. Preferably, the first planarization layer and the second planarization layer are made of the same material, and both include organic materials.

5. The display panel according to claim 1, characterized in that, The array substrate includes a substrate, a metal layer, and an insulating layer, wherein the substrate is located on the side of the metal layer opposite to the pixel defining layer; The metal layer includes a first metal layer, a second metal layer and a third metal layer stacked together, wherein the first metal layer is located on the side of the second metal layer closer to the substrate, and the insulating layer is located between two adjacent metal layers among the first metal layer, the second metal layer and the third metal layer; Preferably, the planarization layer includes a second planarization layer located on the side of the third metal layer opposite to the substrate; Preferably, the array substrate further includes a fourth metal layer located on the side of the second planarization layer opposite to the substrate, and the fourth metal layer is electrically connected to the third metal layer; Preferably, the planarization layer includes a first planarization layer located on the side of the fourth metal layer opposite to the substrate; Preferably, the display panel includes a bezel area, the third metal layer and the insulating layer extend to the bezel area, the second planarization layer covers a portion of the third metal layer, and the fourth metal layer covers the edge of the second planarization layer and contacts a portion of the third metal layer; Preferably, the fourth metal layer extends to the border region, where the third metal layer includes a third metal layer edge, the fourth metal layer includes a fourth metal layer edge, and the first planarization layer covers the edge of the third metal layer and the edge of the fourth metal layer; Preferably, the pixel defining layer extends to cover the edge of the first flat layer and contacts the insulating layer.

6. The display panel according to claim 1, characterized in that, Also includes: A first electrode layer is located between the planarization layer and the pixel defining layer, and the first electrode layer includes a plurality of first electrodes; Preferably, the display panel includes a display area, in which the pixel defining layer has a plurality of first openings, the first openings exposing a portion of the first electrode; Preferably, it further includes: a light-emitting functional layer, a portion of which is located in the first opening and on the side of the first electrode facing away from the array substrate; The second electrode layer is located on the side of the light-emitting functional layer opposite to the first electrode layer.

7. The display panel according to claim 6, characterized in that, Also includes: A partition structure is located on the side of the pixel defining layer opposite to the array substrate. The partition structure has a plurality of second openings, and the orthographic projection of the first opening on the array substrate is located within the orthographic projection range of the second opening on the array substrate. The light-emitting functional layer includes multiple light-emitting units, which are located within the first opening and the second opening that are connected together. Preferably, the partition structure includes a first part and a second part stacked together, the first part being located on the side of the second part away from the array substrate, and the orthographic projection of the second part on the array substrate being within the orthographic projection range of the first part on the array substrate; Preferably, the partition structure further includes a third part located on the side of the second part close to the array substrate, wherein the orthographic projection of the second part on the array substrate is within the orthographic projection range of the third part on the array substrate.

8. The display panel according to claim 7, characterized in that, The encapsulation layer further includes: a first encapsulation layer located on the side of the organic encapsulation layer close to the array substrate, the first encapsulation layer including a plurality of encapsulation portions, the encapsulation portions corresponding to the second opening, and the orthographic projection of the encapsulation portions on the array substrate covering the orthographic projection of the second electrode layer on the array substrate; Preferably, the orthographic projection of the first encapsulation layer on the array substrate at least partially overlaps with the orthographic projection of the pixel defining layer on the array substrate; Preferably, the display panel includes a border area, and a portion of the first encapsulation layer located in the border area contacts the pixel defining layer.

9. The display panel according to claim 8, characterized in that, The encapsulation layer further includes: a second encapsulation layer located on the side of the organic encapsulation layer opposite to the array substrate, wherein the orthographic projection of the second encapsulation layer on the array substrate covers the orthographic projection of the organic encapsulation layer on the array substrate; Preferably, the orthographic projection of the second encapsulation layer on the array substrate covers the orthographic projection of the pixel defining layer on the array substrate.

10. A display panel, characterized in that, include: Substrate; A pixel defining layer is located on one side of the substrate; The first organic layer is located on the side of the pixel defining layer closest to the substrate; The second organic layer is located on the side of the pixel defining layer opposite to the substrate; The water content of the first organic layer is lower than that of the second organic layer.

11. The display panel according to claim 10, characterized in that, The first organic layer includes a planarization layer; Preferably, the second organic layer includes an organic encapsulation layer.

12. The display panel according to claim 10 or 11, characterized in that, The water content of the first organic layer is 60-80% of the water content of the second organic layer; Preferably, the water content of the first organic layer is 70% of the water content of the second organic layer.

13. A method for manufacturing a display panel, characterized in that, include: An array substrate including a planarization layer is provided, and the array substrate is subjected to a drying process; A pixel defining layer is prepared on one side of the array substrate; An encapsulation layer including an organic encapsulation layer is prepared on the side of the pixel defining layer opposite to the array substrate; The water content of the planarization layer is lower than that of the organic encapsulation layer.

14. The preparation method according to claim 13, characterized in that, The drying process includes baking. Preferably, the baking conditions include at least one of the following: a temperature of 200–300°C; and a time of 10 min–1 h.

15. The preparation method according to claim 13, characterized in that, Before the step of fabricating the encapsulation layer including the organic encapsulation layer on the side of the pixel defining layer opposite to the array substrate, the method further includes: A partition structure is prepared on the side of the pixel defining layer opposite to the array substrate; Preferably, the step of fabricating the partition structure on the side of the pixel defining layer opposite to the array substrate includes: A second barrier material layer and a first barrier material layer are sequentially fabricated on the side of the pixel defining layer opposite to the array substrate; the first barrier material layer and the second barrier material layer are patterned to obtain a plurality of second openings and a stacked first part and a second part, wherein the first part is located on the side of the second part opposite to the array substrate, and the orthographic projection of the second part on the array substrate is located within the orthographic projection of the first part on the array substrate; or... A third isolation material layer, a second isolation material layer, and a first isolation material layer are sequentially prepared on the side of the pixel defining layer opposite to the array substrate. The first isolation material layer, the second isolation material layer, and the third isolation material layer are patterned to obtain a plurality of second openings and a first part, a second part, and a third part stacked sequentially. The first part is located on the side of the second part opposite to the array substrate. The orthographic projection of the second part on the array substrate is within the orthographic projection range of the first part on the array substrate. The orthographic projection of the second part on the array substrate is within the orthographic projection range of the third part on the array substrate.

16. The preparation method according to claim 15, characterized in that, Before fabricating the pixel defining layer on one side of the array substrate, the method further includes: fabricating a first electrode layer on one side of the array substrate; Preferably, before the step of fabricating the encapsulation layer including the organic encapsulation layer on the side of the pixel defining layer opposite to the array substrate, the method further includes: A light-emitting functional layer and a second electrode layer are sequentially fabricated within the first opening and the second opening of the pixel defining layer that are connected together. Preferably, the step of sequentially fabricating a light-emitting functional layer and a second electrode layer within the first opening and the second opening of the interconnected pixel defining layer includes: A light-emitting functional material layer, a second electrode material layer, and a first encapsulation material layer are sequentially prepared within the first and second openings that are connected. The light-emitting functional material layer, the second electrode material layer, and the first encapsulation material layer are patterned to obtain the light-emitting functional layer, the second electrode layer, and the first encapsulation layer having multiple light-emitting units.

17. A display device, characterized in that, It includes the display panel according to any one of claims 1 to 12, or the display panel prepared by the preparation method according to claims 13 to 16.

18. The display device according to claim 17, characterized in that, The display device further includes a touch panel, which is stacked on top of the display panel.

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