A surface repair method, a semiconductor substrate, and a semiconductor device

Abstract

This invention discloses a surface repair method, a semiconductor substrate, and a semiconductor device, belonging to the field of semiconductor manufacturing technology. The surface repair method includes: providing a substrate to be etched; etching the substrate using inductively coupled plasma (ICP) to obtain an etched substrate, the etched substrate comprising an unetched area and an etched area with a surface roughness Ra of 0.5 nm to 10 nm; immersing the etched substrate in a phosphoric acid solution with a mass percentage concentration of 15% to 85% at a processing temperature of 50°C to 110°C to perform surface repair treatment on the etched area, obtaining a semiconductor substrate with a surface roughness Ra of less than 0.3 nm in the etched area. This invention achieves atomic-level smooth repair of the surface after ICP etching, exhibits good process compatibility, and provides an ideal interface foundation for subsequent key device processes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically to a surface repair method, a semiconductor substrate, and a semiconductor device. Background Technology

[0002] Wide bandgap substrates, such as gallium nitride (GaN), gallium oxide (Ga2O3), and aluminum nitride (AlN), have become core materials for manufacturing high-performance devices due to their excellent physical properties. The ultimate performance of such devices depends on the atomic-level quality of their key interfaces.

[0003] In the fabrication of wide-bandgap semiconductor devices, inductively coupled plasma (ICP) etching is an indispensable key process for defining device patterns. However, the high-energy ion bombardment during this process inevitably introduces severe lattice damage, forms a non-stoichiometric defect layer, and introduces contaminants to the material surface, causing the surface roughness Ra of the etched region to deteriorate significantly to the nanometer scale (e.g., Ra > 0.5 nm). This etching-induced damage layer severely degrades the interfacial electrical properties, directly affecting the quality of subsequent processes such as gate dielectric deposition, ohmic contact formation, or selective epitaxial regeneration, becoming a key bottleneck restricting the final performance and reliability of the device.

[0004] However, existing technologies do not provide a phosphoric acid treatment solution specifically for repairing surface damage to wide bandgap semiconductors after ICP etching and for efficiently restoring atomically smooth surfaces. This fails to meet the stringent requirements of high-performance devices for atomically smoothness (Ra < 0.3 nm) and pattern fidelity.

[0005] It should be noted that the above description of the background technology is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of the present invention. Summary of the Invention

[0006] The present invention aims to overcome the shortcomings of the prior art and provide a surface repair method that can effectively and controllably remove the surface damage layer introduced by ICP etching, thereby restoring the surface roughness of the etched area to atomic level flatness (Ra < 0.3 nm), providing an ideal interface basis for subsequent device processes.

[0007] To achieve the above objectives, the present invention provides a surface repair method, comprising the following steps: Provide the substrate to be etched; The substrate to be etched is etched using inductively coupled plasma to obtain an etched substrate; wherein the etched substrate includes an unetched area and an etched area with a surface roughness of 0.5 nm to 10 nm, and the surface roughness of the etched area is greater than that of the unetched area. Under a processing temperature of 50℃~110℃, the etched substrate is immersed in a phosphoric acid solution with a mass percentage concentration of 15%~85% to perform surface repair treatment on the etched area, thereby obtaining a semiconductor substrate; wherein the surface roughness of the etched area in the semiconductor substrate is less than 0.3nm.

[0008] As a further improvement of the present invention, the etched substrate is immersed in a phosphoric acid solution to perform surface repair treatment on the etched area, thereby obtaining a semiconductor substrate, comprising: At a first set temperature, the etched substrate is immersed in a phosphoric acid solution with a mass percentage concentration of the first set mass percentage for a first set time to perform a first surface repair treatment, thereby obtaining a repaired substrate; At a second set temperature, the repair substrate is immersed in a phosphoric acid solution with a mass percentage concentration of the second set mass percentage for a second set time for a second surface repair treatment to obtain the semiconductor substrate; Wherein, the first set mass percentage concentration is higher than the second set mass percentage concentration; and / or, the first set temperature is greater than or equal to the second set temperature; and / or, the first set time is less than the second set time.

[0009] As a further improvement of the present invention, the material of the substrate to be etched includes gallium nitride, gallium oxide, or aluminum nitride; When the material of the substrate to be etched is gallium nitride, the mass percentage concentration of the phosphoric acid solution is 30% to 85%, the processing temperature of the surface repair treatment is 60°C to 100°C, and the processing time of the surface repair treatment is 1 minute to 10 minutes; When the material of the substrate to be etched is gallium oxide, the mass percentage concentration of the phosphoric acid solution is 15% to 50%, the processing temperature of the surface repair treatment is 50°C to 80°C, and the processing time of the surface repair treatment is 30 seconds to 5 minutes. When the material of the substrate to be etched is aluminum nitride, the mass percentage concentration of the phosphoric acid solution is 70%~85%, the processing temperature of the surface repair treatment is 90℃~110℃, and the processing time of the surface repair treatment is 10 minutes~30 minutes.

[0010] As a further improvement of the present invention, the material of the substrate to be etched is gallium nitride, and the surface repair treatment includes: The mass percentage concentration of the phosphoric acid solution, the processing temperature of the surface repair treatment, and the processing time of the surface repair treatment are determined based on the surface roughness of the etched area of ​​the etched substrate. Wherein, the surface roughness of the etched substrate is Ra; When 0.5nm≤Ra<2 nm, the mass percentage concentration is 50%~70%, the surface repair treatment temperature is 70℃~85℃, and the surface repair treatment time is 2 minutes~4 minutes; When 2nm≤Ra≤5nm, the mass percentage concentration is 60%~80%, the surface repair treatment temperature is 75℃~90℃, and the surface repair treatment time is 3 minutes~6 minutes; When 5nm < Ra ≤ 10nm, the mass percentage concentration is 70% to 85%, the surface repair treatment temperature is 80℃ to 100℃, and the surface repair treatment time is 4 minutes to 10 minutes.

[0011] As a further improvement of the present invention, the method further includes: Under an inert gas or nitrogen atmosphere, the semiconductor substrate is subjected to a thermal annealing treatment for 30 to 120 seconds at a controlled temperature of 800°C to 950°C. And / or, in an inert gas atmosphere, the surface of the semiconductor substrate is subjected to low-energy plasma treatment for 30 to 120 seconds, wherein the processing power of the low-energy plasma treatment is 50W to 150W.

[0012] As a further improvement of the present invention, after the surface repair treatment step, the method further includes: The semiconductor substrate is removed and rinsed with deionized water. The rinsed semiconductor substrate is then subjected to ultrasonic cleaning. Dry the semiconductor substrate after ultrasonic cleaning; And / or, the etched substrate further includes an unetched area, and prior to the surface repair treatment step, the method further includes: forming a temporary protective layer on the surface of the unetched area of ​​the etched substrate, wherein the temporary protective layer is used to protect the unetched area from corrosion by the phosphoric acid solution; after the surface repair treatment, the method further includes: removing the temporary protective layer.

[0013] As a further improvement of the present invention, the material of the substrate to be etched is gallium nitride, the mass percentage concentration of the phosphoric acid solution is 50% to 80%, the processing temperature of the surface repair treatment is 70°C to 90°C, and the processing time of the surface repair treatment is 2 minutes to 6 minutes.

[0014] As a further improvement of the present invention, the material of the substrate to be etched is gallium nitride, and the surface of the substrate to be etched is an N-polar surface; And / or, the etching of the substrate to be etched using inductively coupled plasma etching includes: forming a mask layer on the substrate to be etched; wherein the mask layer partially covers the substrate to be etched; and etching the portion of the substrate not covered by the mask layer using an etching gas under conditions of 200W to 400W power and 50V to 150V RF bias, to form an etched region; wherein the etching gas includes Cl2 and Ar, and the etching depth is 80 nm to 120 nm.

[0015] The present invention also provides a semiconductor substrate, which is prepared by the above-described surface repair method.

[0016] The present invention also provides a semiconductor device, comprising: a semiconductor substrate and a device structure stacked together, wherein the semiconductor substrate is a semiconductor substrate obtained by the above-described surface repair method.

[0017] Compared with the prior art, the beneficial effects of the present invention are: This invention constructs a general and efficient surface repair process framework: a structure with a specific roughness is formed through ICP etching, and then treated with a phosphoric acid solution within a specific process window to reduce the surface roughness of the etched area from the nanometer scale (Ra 0.5 nm–10 nm) to the atomic scale (Ra < 0.3 nm), thus providing an ideal interface foundation for subsequent key device processes. This surface repair method has advantages such as simple process, low cost, and easy integration into existing production lines. Furthermore, its mild and isotropic reaction characteristics effectively repair the etched area while maximally protecting the original morphology and the formed precision pattern structure of the unetched area, thereby meeting the stringent requirements for high pattern fidelity in the manufacture of high-performance semiconductor devices. Attached Figure Description

[0018] Figure 1 This is a flowchart of the surface repair method provided in the embodiments of the present invention.

[0019] Figure 2 This is a cross-sectional schematic diagram of the process of performing ICP etching and wet etching repair on a substrate to be etched according to an embodiment of the present invention. (a) is a cross-sectional schematic diagram of the substrate to be etched before etching, (b) is a cross-sectional schematic diagram of the etched substrate formed after ICP etching, and (c) is a cross-sectional schematic diagram of the semiconductor substrate formed after wet repair.

[0020] Figure 3Figure 1 is a schematic diagram of the selective protection process provided in the embodiments of the present invention, wherein (a) is a schematic diagram of the cross-sectional structure of a temporary protective layer coated on the surface of an etched substrate, (b) is a schematic diagram of the cross-sectional structure after the temporary protective layer above the etched area is removed, and (c) is a schematic diagram of the cross-sectional structure of selective phosphoric acid repair process.

[0021] Figure 4 This is an atomic force microscope image of the three-dimensional topography of the etched area on the GaN substrate surface after ICP etching, provided in Embodiment 1 of the present invention.

[0022] Figure 5 This is provided in Embodiment 1 of the present invention, and... Figure 4 A three-dimensional morphological image of the same area after being repaired by the method of this invention using an atomic force microscope.

[0023] Figure 6 This is a schematic diagram of the structure of the semiconductor substrate provided in an embodiment of the present invention.

[0024] Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0025] The present invention will now be described in detail with reference to the embodiments shown in the accompanying drawings. However, it should be noted that these embodiments are not intended to limit the present invention. Equivalent changes or substitutions in function, method, or structure made by those skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0026] Combination Figure 1 and Figure 2 As shown, the surface repair method provided in this embodiment of the invention includes core steps S1 to S3.

[0027] Step S1: Provide the substrate to be etched.

[0028] In one embodiment, the reference Figure 2 As shown in (a), a substrate 1a to be etched is provided, which has a flat upper surface 11. The material of the substrate 1a to be etched is one of GaN, Ga2O3 or AlN.

[0029] Step S2: The substrate to be etched is etched using inductively coupled plasma to obtain the etched substrate.

[0030] Figure 2(b) shows the etched substrate 1b formed after ICP etching, on which a recessed etched region A1 and an unetched region B1 that remains essentially atomically flat are formed on the surface 11. Due to the high-energy ion bombardment effect of ICP etching, the surface roughness Ra of the etched region A1 is significantly higher than that of the unetched region B1. Typically, the surface roughness Ra of the etched region A1 is 0.5 nm to 10 nm, for example: the surface roughness Ra of the etched region A1 is 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm; while the surface roughness Ra of the unetched region B1 is < 0.3 nm, for example: the surface roughness Ra of the unetched region B1 is 0.1 nm, 0.15 nm, 0.17 nm, 0.19 nm, 0.21 nm, 0.23 nm, 0.25 nm, 0.27 nm or 0.29 nm. The etched region A1 can be formed using a conventional ICP etching process. In one exemplary process, a patterned mask layer can be formed on the substrate 1a to be etched. Etching is performed using a chlorine-containing gas (such as a Cl2 / Ar mixture) under conditions of approximately 200W to 400W ICP power and approximately 50V to 150V RF bias to form a patterned structure 21 with a depth of approximately 80nm to 120nm. For example, the ICP power can be 200W, 225W, 250W, 275W, 300W, 325W, 350W, 375W, or 400W, the RF bias can be 50V, 70V, 90V, 110V, 130V, or 150V, and the depth of the patterned structure 21 can be 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, or 120nm.

[0031] Through the above process control, high-energy ion bombardment introduces lattice damage and an amorphous layer into the etched region A1, causing its surface roughness Ra to deteriorate from the sub-nanometer level (e.g., <0.3 nm) before repair to the range targeted and intended for repair by this invention (0.5 nm to 10 nm). The above process aims to effectively remove the physical damage layer and chemical contaminants introduced by ICP etching on the surface without causing new damage to the bulk material.

[0032] Step S3: Under the condition of processing temperature of 50℃~110℃, the etched substrate is immersed in a phosphoric acid solution with a mass percentage concentration of 15%~85% to perform surface repair treatment on the etched area and obtain a semiconductor substrate.

[0033] The etched substrate 1b provided in step S2 is immersed in a phosphoric acid solution to perform surface repair treatment on the etched area A1. In a basic implementation, the mass percentage concentration of the phosphoric acid solution is 15% to 85%, and the treatment temperature is 50℃ to 110℃, thereby achieving efficient and controllable surface repair treatment.

[0034] To achieve superior repair results, this surface repair treatment can precisely match the activity of the phosphoric acid solution (controlled by concentration, temperature, and time) based on the material characteristics of the substrate 1a to be etched. This design principle aims to overcome the dilemma of "insufficient general wet cleaning reaction" and "severe chemical corrosion damaging the pattern" in existing technologies, ultimately achieving the goal of "selectively removing the damaged layer and maximizing the protection of the crystal body and pattern structure." Based on a deep understanding of the chemical properties of material surfaces, this invention reveals the differentiated repair mechanism and parameter design principles for different materials: (1) For GaN: ICP etching mainly introduces an amorphous Ga2O3 damage layer and underlying lattice damage on the surface of the etched region A1. Phosphoric acid (H3PO4), as a moderately strong acid, has good selective dissolution ability for Ga2O3, while the etching rate for the underlying intact GaN crystal and the unetched region B1 is extremely low and controllable at a specific temperature. Therefore, a process window with medium temperature (60℃~100℃), medium concentration (30%~85%), and matching time (1 minute~10 minutes) can be matched for GaN. Within this window, phosphoric acid can preferentially and rapidly remove the damaged Ga2O3 layer and amorphous materials. Once it touches the intact GaN crystal, the reaction rate drops significantly, thereby achieving selective removal and self-stopping of the Ga2O3 damage layer, effectively avoiding over-etching of the etched region A1 and erosion of the unetched region B1.

[0035] For example, the surface repair treatment temperature can be 60℃, 65℃, 70℃, 75℃, 80℃, 85℃, 90℃, 95℃, or 100℃; the surface repair treatment concentration can be 30%, 40%, 50%, 60%, 70%, 80%, or 85%; and the surface repair treatment duration can be 1 minute, 2 minutes, 3 minutes, 4 minutes, 5 minutes, 6 minutes, 7 minutes, 8 minutes, 9 minutes, or 10 minutes.

[0036] (2) For Ga2O3: its repair mechanism is different from that of GaN. Phosphoric acid reacts directly with the Ga2O3 bulk, and its process objective is more focused on "atomic-level smoothing and thinning of the etched region A1". Since this chemical reaction is isotropic, theoretically it has the same etching rate for both the etched region A1 and the unetched region B1. Therefore, an extremely mild process parameter window is matched for it: low temperature (50℃~80℃), low concentration (15%~50%) and short time (30 seconds~5 minutes) to control the overall etching rate at an extremely low level (e.g., sub-nanometer per minute).

[0037] Under these conditions, although the two regions are thinned at the same rate, the results are quite different: for the rough etched region A1, it is necessary to remove protrusions of several nanometers to tens of nanometers to achieve smoothness, and this mild window is sufficient to achieve this goal; for the originally flat unetched region B1, the same low etching rate only results in a uniform thinning at the "sub-nanometer" level. This uniform removal at the atomic scale does not introduce new roughness, and its morphological changes have a negligible impact on the performance of subsequent devices.

[0038] (3) For AlN: its surface (including etched region A1 and unetched region B1) already has a dense primary alumina (Al2O3) layer with extremely stable chemical properties before ICP etching. The ICP etching process will partially destroy the Al2O3 layer in etched region A1 and damage the underlying AlN crystal, but the newly exposed surface will be rapidly re-oxidized. Therefore, the surface of the etched region A1 to be repaired is actually covered with a mixed oxide layer composed of dense primary Al2O3 and ICP-induced amorphous / damaged Al2O3. At the same time, the reaction kinetics between phosphoric acid and the AlN bulk are extremely slow.

[0039] Therefore, to initiate and complete effective surface repair, a high reaction driving force is required. To this end, a high-temperature (90℃~110℃), high-concentration (70%~85%), and long-term (10 minutes~30 minutes) activation process window can be matched. High-concentration, high-temperature phosphoric acid can first effectively destroy and remove the dense surface Al2O3 layer, followed by extremely slow and controllable shallow etching of the exposed underlying AlN layer, thereby removing the very shallow (atomic to nanoscale) damage introduced by ICP etching.

[0040] Similar to the Ga2O3 case, this chemical process is synchronous and isotropic for both the etched region A1 and the unetched region B1. The key difference lies in the fact that the intrinsically slow reaction rate of AlN is an inherent characteristic of this process. The "long-term" treatment designed for this invention is precisely to accumulate sufficient repair effects at this low rate, rather than to achieve rapid bulk material thinning. Therefore, this approach can effectively repair the etched region A1 while, thanks to its extremely low etching rate, ensuring that the morphological changes in the unetched region B1 are strictly limited to the atomic level. This achieves both effective repair of the patterned surface A1 and complete protection of the unetched region B1.

[0041] It should be noted that, under the process constraints of matching the properties of each material, phosphoric acid is the key and suitable choice for achieving the aforementioned repair effect. Compared with other common inorganic acids, such as hydrochloric acid (HCl), sulfuric acid (H2SO4), and nitric acid (HNO3), which typically have excessively fast and isotropic etching rates under similar conditions, easily leading to surface roughening and making atomic-level smoothness impossible, phosphoric acid's moderate acidity and unique reaction selectivity allow it to achieve a balance between "efficient removal of the damaged layer" and "gentle etching of intact crystals (and unetched areas)" within an optimized process window. This is the key chemical basis for obtaining the atomic-level repair effect of Ra < 0.3 nm.

[0042] The aforementioned "kinetic selective removal" for GaN, "low-rate controllable thinning" for Ga2O3, and "high activation energy surface reconstruction" for AlN have fundamentally different mechanisms of action. This reflects the core inventive concept of this invention: it does not provide a universal pickling formula, but rather establishes a set of rational design and application principles based on "intrinsic surface chemical properties of materials → specific damage mechanisms induced by ICP etching → customized differentiated phosphoric acid process windows".

[0043] To clearly demonstrate the repair solutions tailored for different materials, the aforementioned differentiated process parameters are summarized as follows: Table 1. Window of Differentiated Phosphoric Acid Remediation Process Parameters Based on Material Properties

[0044] Guided by the aforementioned principles and differentiated parameter design, this invention innovatively combines wet phosphoric acid etching with ICP dry etching, forming a complete "precision patterning (ICP etching) → atomic-level interface repair (phosphoric acid treatment)" process module. This module not only efficiently and selectively removes physical damage and chemical contamination introduced by the ICP process, but also provides an ideal interface with atomically smoothness and chemical cleanliness for subsequent key processes such as gate dielectric deposition and ohmic contact formation, while maintaining the original pattern structure. The phosphoric acid treatment process proposed in this invention has a wide process window (15%–85%, 50℃–110℃), is easy to implement on standard process lines, has strong compatibility with existing semiconductor manufacturing processes, good repeatability, and is suitable for large-scale production. By improving the surface quality after etching, the defect density of subsequent metal deposition or epitaxial growth is reduced, improving the performance and reliability of wide-bandgap semiconductor devices and increasing production yield.

[0045] For GaN, an important material, based on the aforementioned mechanism and extensive experimental verification, within the established process window (concentration 30%–85%, temperature 60℃–100℃, processing time 1 minute–10 minutes), the core parameter range that demonstrates good repair effects and process robustness for various typical types of damage can be further optimized. Specifically, when using a phosphoric acid solution with a mass percentage concentration of 50%–80% and processing at a temperature of 70℃–90℃ for 2 to 6 minutes, it is possible to effectively remove damage of various degrees while achieving a good balance between repair efficiency, surface quality, and process safety, making it particularly suitable for a wide range of scenarios for surface repair of gallium nitride substrates.

[0046] Furthermore, to achieve optimal repair efficiency and surface quality, the process parameters of the aforementioned phosphoric acid solution can be more precisely matched and selected based on the initial surface roughness Ra of the etched region A1: For slightly damaged surfaces (0.5nm≤Ra <2nm): it is preferable to use a combination of parameters with lower activity, namely, a phosphoric acid mass percentage concentration of 50% to 70%, a treatment temperature of 70℃ to 85℃, and a treatment time of 2 minutes to 4 minutes.

[0047] For moderately damaged surfaces (2nm≤Ra≤5nm): a moderately active parameter combination is preferred, namely, a phosphoric acid mass percentage concentration of 60% to 80%, a treatment temperature of 75℃ to 90℃, and a treatment time of 3 to 6 minutes.

[0048] For severely damaged surfaces (5nm < Ra ≤ 10nm): a combination of parameters with higher activity is preferred, namely, a phosphoric acid mass percentage concentration of 70% to 85%, a treatment temperature of 80℃ to 100℃, and a treatment time of 4 to 10 minutes.

[0049] Table 2. Recommended phosphoric acid repair process parameters for GaN surfaces with different initial roughness.

[0050] The aforementioned refined matching relationship was derived through extensive systematic experiments. It enables those skilled in the art to quickly determine targeted, near-optimal repair process conditions based on the initial surface roughness Ra, thereby greatly improving the reliability, repeatability, and consistency of the process.

[0051] As an optimization of the basic single-immersion repair method described above, the surface repair treatment can also employ a gradient concentration repair method. Specifically, this may include at least two sequential immersion treatments: S31: First immersion treatment: At a first set temperature, the etched substrate is immersed in a phosphoric acid solution with a mass percentage concentration of a first set mass percentage for a first set time for a first surface repair treatment to obtain a repaired substrate.

[0052] S32: Second immersion treatment: At a second set temperature, the repair substrate is immersed in a phosphoric acid solution with a mass percentage concentration of a second set mass percentage concentration for a second set time to perform a second surface repair treatment, thereby obtaining a semiconductor substrate.

[0053] The first set mass percentage concentration is higher than the second set mass percentage concentration; and / or, the first set temperature is greater than or equal to the second set temperature; and / or, the first set time is less than the second set time.

[0054] This gradient method separates the two stages of "rapid removal of the main damaged layer" and "fine smoothing" by varying the concentration from high to low. This ensures repair efficiency while further reducing the risk of excessive corrosion and improving the uniformity of the repaired surface morphology. This invention reveals that the gradient concentration repair method has particular advantages for GaN materials. This is mainly due to GaN's repair mechanism—"kinetic selective removal." When repairing severe damage, using an initially highly reactive single parameter, while rapidly removing the main damaged layer, may also slightly erode the underlying intact GaN crystals due to uneven reaction control, affecting the final surface uniformity and electrical properties. However, the gradient method, with its high-to-low concentration approach, optimizes the process, thereby achieving better overall surface quality while maintaining repair efficiency.

[0055] In a typical implementation, the GaN substrate is repaired using a two-stage immersion process: the first immersion uses a first phosphoric acid solution with a higher mass percentage concentration than the second phosphoric acid solution used in the second immersion, to achieve rapid removal of most of the damaged layer (coarse repair); the processing temperature of the first immersion is typically no lower than that of the second immersion. Subsequently, the second immersion is performed at a lower concentration (and optionally a lower temperature) to finely smooth the surface (fine repair), thereby obtaining a more atomically smooth surface.

[0056] After the surface repair treatment is completed with phosphoric acid solution, a series of optional post-treatment steps can be flexibly introduced according to actual process requirements to further improve the repair effect or meet the requirements of specific device processes.

[0057] In one embodiment, basic post-processing can also be performed: cleaning and drying. First, the substrate to be etched after phosphoric acid repair treatment needs to be thoroughly cleaned and dried to terminate the chemical reaction and remove residues. A typical cleaning and drying process includes: thorough rinsing with deionized water, followed by ultrasonic-assisted cleaning (optionally using organic solvents such as acetone or ethanol), and finally drying by introducing a drying gas (such as nitrogen) or heating.

[0058] In one embodiment, thermal annealing can be performed after the cleaning and drying steps to further optimize surface quality. This step is typically carried out in an inert gas (such as argon) or nitrogen atmosphere, with typical rapid thermal annealing conditions being a temperature of 800°C to 950°C and a time of 30 to 120 seconds. Thermal annealing helps to further remove surface adsorbates, eliminate processing stress, reconstruct the surface atomic arrangement, and optimize the surface electronic states, thereby obtaining a more stable interface with superior electrical properties.

[0059] In another embodiment, to further improve surface cleanliness and atomic regularity, dry surface optimization methods such as low-energy plasma treatment can be performed after cleaning and drying. For example, the sample can be placed in a reactive ion etching (RIE) device, argon gas can be introduced, and the sample can be processed for a short time (e.g., 30 seconds to 120 seconds) under low power (e.g., 50W to 150W) and low pressure (e.g., 10mTorr to 50mTorr).

[0060] Low-energy ion bombardment can physically strip away trace amounts of adsorbed pollutants and activate surface atoms, creating a synergistic effect with thermal annealing to achieve deeper surface reconstruction.

[0061] In another embodiment, after cleaning and drying, a low-energy plasma treatment is performed, followed by thermal annealing, to further improve the quality of the semiconductor substrate. Specific process parameters are as described above and will not be repeated here.

[0062] In one embodiment, a selective protection process can also be performed before step S3. For specific cases where the pattern structure is complex or where absolute protection of unetched areas is required (e.g., in the fabrication of GaN-based high electron mobility transistors, where only the bottom of the gate trench needs to be repaired while strictly protecting the sidewalls and mesa), a selective protection step can be added before the phosphoric acid surface repair process to ensure that the acid only acts on the target area.

[0063] Specifically, combined Figure 3 As shown, a temporary protective layer 31 (such as photoresist) can be formed on the entire surface 11 of the etched substrate 1b. The portion above the etched area A1 is selectively removed using photolithography and development processes, ensuring that the subsequent phosphoric acid solution only contacts the etched area A1 that needs repair, while the unetched area B1 is tightly covered by the temporary protective layer 31. After the repair and subsequent cleaning steps are completed, this temporary protective layer 31 is removed. The specific process steps are as follows: Step 1) Prepare a temporary protective layer 31.

[0064] In obtaining such Figure 3 After etching the substrate 1b shown in (a), a temporary protective material with high resistance to phosphoric acid solution is spin-coated onto its entire surface to form a temporary protective layer 31. The material of the temporary protective layer 31 can be selected from photoresist (such as AZ series positive photoresist) or polyimide (PI). For photoresist, pre-baking and post-baking are usually required after spin-coating to enhance its acid resistance (i.e., to achieve high corrosion resistance).

[0065] Step 2) Graphicalize the temporary protective layer 31 to selectively expose the etched area A1.

[0066] like Figure 3 As shown in (b), the temporary protective layer 31 is patterned by standard photolithography process (including exposure and development), and the temporary protective layer 31 located above the etched area A1 is selectively removed, thereby precisely exposing the surface of the etched area A1 to be repaired, while the unetched area B1 is tightly covered by the retained temporary protective layer 31.

[0067] Step 3) Perform phosphoric acid repair treatment.

[0068] like Figure 3 As shown in (c), the etched substrate 1b with a temporary protective layer 31 is immersed in a phosphoric acid solution. At this time, the phosphoric acid solution only contacts and reacts with the exposed etched area A1, achieving area-selective surface repair, while the unetched area B1 is unaffected due to the protection of the mask.

[0069] Step 4) Remove the temporary protective layer 31.

[0070] After completing the phosphoric acid repair treatment and subsequent initial water rinsing to terminate the reaction, the temporary protective layer 31 is peeled off using a removal process compatible with the temporary protective material. For example, for photoresist, acetone immersion combined with ultrasonic-assisted peeling can be used; for polyimide, a specialized stripping solution or an oxygen plasma ashing process can be used.

[0071] Step 5) Perform the final cleaning.

[0072] After the temporary protective layer 31 is removed, the etched substrate 1b is thoroughly cleaned and dried according to the basic post-processing steps (i.e., cleaning and drying) to obtain a clean repaired surface.

[0073] This masked process provides a high degree of selectivity and controllability for the repair process, and is especially suitable for device manufacturing processes that have stringent requirements for the surface condition of unetched areas.

[0074] It should be noted that the aforementioned principle of selective protection also applies to more complex three-dimensional structures. For cases requiring simultaneous protection of the substrate sidewalls, bottom, and other non-target repair areas (e.g., protecting the sidewalls of grooves when repairing etched areas), a well-covered temporary protective layer can be formed using appropriate coating processes (such as spin coating combined with reflow, chemical vapor deposition, etc.), and selective exposure of areas can be achieved in conjunction with corresponding patterning processes. Such extended applications demonstrate the flexibility and versatility of the present invention's method in dealing with complex patterned structures.

[0075] After the aforementioned core phosphoric acid repair treatment and any optional post-processing steps, the surface-repaired semiconductor substrate can be obtained. For example... Figure 2 As shown in (c), the etched area A1 is repaired and becomes A2, and its surface roughness Ra value has been reduced to below 0.3 nm, reaching atomic-level flatness; while the morphology of the unetched area B1 is basically unaffected.

[0076] The preferred embodiments and extended applications of the method of the present invention will be described in detail below with reference to specific examples. Example 1

[0077] S1: Using a Cl2 / Ar mixed gas, under the conditions of ICP power of 300W and RF bias of 100V, the GaN substrate is etched to form an etched region with a depth of 80nm.

[0078] The parameters were obtained by atomic force microscopy (AFM). Figure 4 The test results show that the surface roughness Ra of the etched area of ​​the GaN substrate is 1.5 nm.

[0079] S2: Preheat a phosphoric acid solution with a concentration of 10.3 mol / L (corresponding to a mass percentage concentration of approximately 70%) to 85°C, and immerse the etched GaN substrate in the phosphoric acid solution for 3 minutes to obtain the repaired GaN substrate.

[0080] This parameter combination falls within the lower activity parameters set by this invention for GaN within the process window (see Table 2 for the recommended preferred parameter range for the "0.5nm≤Ra<2nm" range), which can effectively remove the damaged layer while avoiding excessive etching of the underlying intact crystal.

[0081] The repaired GaN substrate was removed, cleaned, and dried. AFM was then used to characterize the treated GaN substrate. Figure 5 The results show that the surface roughness Ra of the etched area decreased to 0.164 nm. X-ray photoelectron spectroscopy (XPS) analysis of the treated GaN substrate revealed a significant reduction in the oxide layer signal on the GaN substrate surface. Example 2

[0082] S1: Using a Cl2 / Ar mixed gas, the GaN substrate is etched to form an etched region with a depth of 100nm.

[0083] According to AFM measurements, the surface roughness Ra of the etched region of the GaN substrate is 4.8 nm.

[0084] S2: Preheat a phosphoric acid solution with a mass percentage concentration of approximately 75% to 90°C, immerse the etched GaN substrate in the phosphoric acid solution, and process for 5 minutes to obtain the repaired GaN substrate.

[0085] This parameter combination falls within the process window set for GaN in this invention, and is the preferred parameter range for moderate damage (see the "2nm≤Ra≤5nm" range in Table 2), which is a medium to high activity parameter.

[0086] The repaired GaN substrate was removed, cleaned and dried, and then subjected to AFM characterization. The measurement results showed that the surface roughness Ra of the etched area decreased to 0.27 nm.

[0087] These results demonstrate that for moderately damaged surfaces, effective atomic-level repair can be achieved within a reasonable timeframe by employing matched, moderately to highly active phosphoric acid process parameters. Example 3

[0088] S1: ICP etching of GaN substrate is performed using Cl2 / Ar mixed gas to form an etched region with a depth of 120nm.

[0089] According to AFM measurements, the surface roughness Ra of the etched area of ​​the GaN substrate is approximately 7.5 nm.

[0090] S2: Preheat a phosphoric acid solution with a mass percentage concentration of approximately 80% to 95°C, and immerse the etched GaN substrate in the phosphoric acid solution for 8 minutes to obtain the repaired GaN substrate.

[0091] This parameter combination falls within the high-activity parameters set for GaN in this invention (see Table 2 for the recommended preferred parameter range for the "5nm < Ra ≤ 10nm" range), and is designed to provide sufficient reaction driving force to remove thicker damage layers.

[0092] After the repaired GaN substrate was removed, cleaned and dried, it was characterized by AFM. The measurement results showed that the surface roughness Ra value of the etched area was reduced to 0.29 nm.

[0093] This embodiment demonstrates that for damaged surfaces with high initial surface roughness (Ra > 5 nm), atomic-level repair (Ra < 0.3 nm) can be effectively achieved by using a high-concentration, high-temperature, and matched-long-term phosphoric acid solution. Example 4

[0094] Compared with Example 1, the difference lies in the inclusion of the following steps: S3: Remove the repaired GaN substrate and rinse it with flowing ultrapure deionized water for 60 seconds to completely terminate the reaction.

[0095] S4: Place the GaN substrate obtained after step S3 into an ultrasonic cleaner and clean it in acetone and ethanol for 5 minutes each, and finally dry it with high-purity nitrogen.

[0096] S5: The GaN substrate obtained after step S4 is subjected to low-energy argon plasma treatment (power of 100W, treatment time of 60 seconds) to further optimize the surface cleanliness.

[0097] S6: Under an annealing temperature of 900°C, the GaN substrate obtained after step S5 is subjected to rapid thermal annealing in a nitrogen atmosphere for 60 seconds.

[0098] Tests revealed that the GaN substrate obtained in Example 4 had a lower roughness of 0.14 nm compared to Example 1. This demonstrates that post-processing steps can further reduce surface roughness and improve quality.

[0099] Comparative Example 1 Compared with Example 4, the difference lies in step S1: a GaN sample that has undergone abnormally severe ICP etching (or already has serious defects) is prepared, with a surface roughness Ra of 15 nm. The other steps are the same and will not be described again here.

[0100] AFM characterization of the repaired GaN substrate revealed limited improvement in surface roughness Ra, which decreased to only about 12 nm, and a large number of macroscopic defects such as deep pits and microcracks still existed.

[0101] The comparison between Comparative Example 1 and Example 4 demonstrates that the optimized process window of the present invention is developed for surface damage of a specific degree (Ra = 0.5 nm to 10 nm). For surfaces with excessive initial damage (Ra > 10 nm), the damage layer may have penetrated deep into the bulk, resulting in severe structural damage. The mild surface treatment of the present invention cannot effectively repair these surfaces, requiring other processes. This proves that the technical solution of the present invention has a clear applicable target and precise design purpose, and its effectiveness is based on a specific damage mechanism, rather than being an indiscriminate and universal roughness reduction method. Example 5

[0102] This embodiment is similar to Embodiment 2, except that: S2: Immerse the etched GaN substrate in a phosphoric acid solution preheated to 90°C and with a mass percentage concentration of 73% for 2 minutes.

[0103] S3: Quickly transfer the GaN substrate obtained in step two to another phosphoric acid solution preheated to 85°C and with a mass percentage concentration of 50%, and treat for 3 minutes.

[0104] The repaired GaN substrate was characterized by AFM, and the measurement results showed that the surface roughness Ra value of the etched area decreased to 0.25 nm.

[0105] The results of this embodiment demonstrate that the stepwise gradient treatment scheme is effective. This method, through "continuous processing without intermediate water rinsing," immediately transitions to a gentle finishing stage after rapidly removing the main damage. This not only successfully achieves atomic-level smoothness but also offers advantages over schemes using a single medium-concentration phosphoric acid solution for the same total treatment time in terms of surface chemical cleanliness, uniformity, and reduced risk of over-etching. This further verifies the feasibility of using a gradient concentration repair method with flexible parameter combinations within the process window to adapt to different initial damage states and optimize the overall repair effect. Example 6

[0106] S1: ICP etching of Ga2O3 substrate is performed using a Cl2 / Ar mixed gas.

[0107] According to AFM measurements, the initial surface roughness Ra of the etched region of the Ga2O3 substrate is approximately 3.2 nm.

[0108] S2: Immerse the etched Ga2O3 substrate in a phosphoric acid solution preheated to 65°C with a mass percentage concentration of 35% for 2 minutes.

[0109] The repaired Ga2O3 substrate was characterized by AFM, and the measurement results showed that the surface roughness Ra of the etched area decreased to 0.24 nm. Example 7

[0110] S1: ICP etching of AlN substrate is performed using a Cl2 / Ar mixed gas.

[0111] According to AFM measurements, the initial surface roughness Ra of the etched region of the AlN substrate is approximately 4.2 nm.

[0112] S2: Immerse the etched AlN substrate in a phosphoric acid solution preheated to 105°C and with a mass percentage concentration of 80% for 20 minutes.

[0113] The repaired AlN substrate was characterized by AFM, and the measurement results showed that the surface roughness Ra value of the etched area decreased to 0.26 nm.

[0114] As can be seen from Examples 1-7 above, for etched surfaces with an initial surface roughness Ra in the range of 0.5 nm to 10 nm, whether GaN, Ga2O3, or AlN, after treatment with the phosphoric acid process provided by this invention that matches their material properties, the surface roughness Ra value can be reduced to below 0.3 nm, achieving atomic-level smoothness. The significant effect of this method in efficiently removing the ICP damage layer and improving the surface chemical state was jointly verified by analytical methods such as AFM and XPS.

[0115] Combination Figure 6 As shown, the present invention also provides a surface-repaired semiconductor substrate 100, which is a direct product obtained by the aforementioned method. The semiconductor substrate 100 includes a substrate 110 having an etched region 120.

[0116] The material of the substrate 110 is selected from GaN, Ga2O3 or AlN, and its morphology can be a single crystal or polycrystalline substrate, self-supporting or non-self-supporting, or an epitaxial layer composite structure grown on a heterogeneous substrate.

[0117] The etched region 120 is formed by inductively coupled plasma etching and repaired by the method of this invention. The surface roughness Ra of the etched region 120 is <0.3 nm, achieving atomic-level flatness. This remarkable surface condition clearly distinguishes it from substrates that have undergone conventional etching without treatment or other processes.

[0118] Combination Figure 7 As shown, the present invention also provides a semiconductor device 200, which includes the above-mentioned surface-repaired semiconductor substrate 100 and a device functional structure 210 formed on the semiconductor substrate 100.

[0119] Specifically, the device functional structure 210 is directly constructed on the atomically smooth etched region 120 surface. The device functional structure 210 can be one or more combinations of key components such as a gate dielectric layer, ohmic contact electrode, Schottky contact, selective epitaxial regeneration layer, or passivation layer. Because the interface between the device functional structure 210 and the semiconductor substrate 100 is established on an ultra-smooth surface with a surface roughness of less than 0.3 nm, the interface state density is significantly reduced, and the interface electric field distribution is more uniform, thereby fundamentally improving the device's carrier transport efficiency, breakdown voltage, long-term reliability, and manufacturing yield. For example, in GaN high electron mobility transistors, depositing the gate dielectric in the repaired gate trench region (corresponding to the etched region 120) can significantly reduce gate leakage current and improve threshold voltage stability; forming ohmic contacts on the repaired mesa sidewalls can achieve lower and more uniform contact resistance. Therefore, the semiconductor device 200 containing the aforementioned semiconductor substrate 100 possesses excellent interface characteristics, exhibiting superior overall electrical performance and reliability.

[0120] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

[0121] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0122] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A surface repair method characterized by, The method comprises the following steps: providing a substrate to be etched; etching the substrate to be etched by using an inductively coupled plasma to obtain an etched substrate; wherein the etched substrate comprises an unetched region and an etched region with a surface roughness of 0.5 nm to 10 nm, and the surface roughness of the etched region is greater than that of the unetched region; immersing the etched substrate in a phosphoric acid solution with a mass percentage concentration of 15% to 85% at a treatment temperature of 50°C to 110°C to perform surface repair treatment on the etched region, thereby obtaining a semiconductor substrate; wherein the surface roughness of the etched region in the semiconductor substrate is less than 0.3 nm.

2. The method of claim 1, wherein, immersing the etched substrate in a phosphoric acid solution to perform surface repair treatment on the etched region, thereby obtaining a semiconductor substrate, comprising: immersing the etched substrate in a phosphoric acid solution with a first set mass percentage concentration at a first set temperature for a first set time to perform first surface repair treatment, thereby obtaining a repaired substrate; immersing the repaired substrate in a phosphoric acid solution with a second set mass percentage concentration at a second set temperature for a second set time to perform second surface repair treatment, thereby obtaining the semiconductor substrate; wherein the first set mass percentage concentration is higher than the second set mass percentage concentration; and / or the first set temperature is greater than or equal to the second set temperature; and / or the first set time is less than the second set time.

3. The method of claim 1, wherein, The material of the substrate to be etched comprises gallium nitride, gallium oxide or aluminum nitride; when the material of the substrate to be etched is gallium nitride, the mass percentage concentration of the phosphoric acid solution is 30% to 85%, the treatment temperature of the surface repair treatment is 60°C to 100°C, and the treatment time of the surface repair treatment is 1 minute to 10 minutes; when the material of the substrate to be etched is gallium oxide, the mass percentage concentration of the phosphoric acid solution is 15% to 50%, the treatment temperature of the surface repair treatment is 50°C to 80°C, and the treatment time of the surface repair treatment is 30 seconds to 5 minutes; when the material of the substrate to be etched is aluminum nitride, the mass percentage concentration of the phosphoric acid solution is 70% to 85%, the treatment temperature of the surface repair treatment is 90°C to 110°C, and the treatment time of the surface repair treatment is 10 minutes to 30 minutes.

4. The method of claim 1, wherein, The material of the substrate to be etched is gallium nitride, and before the surface repair treatment, comprising: determining the mass percentage concentration of the phosphoric acid solution, the treatment temperature of the surface repair treatment and the treatment time of the surface repair treatment according to the surface roughness of the etched region of the etched substrate; wherein the surface roughness of the etched substrate is Ra; when 0.5 nm≤Ra<2 nm, the mass percentage concentration is 50% to 70%, the treatment temperature of the surface repair treatment is 70°C to 85°C, and the treatment time of the surface repair treatment is 2 minutes to 4 minutes; When 2nm≤Ra≤5nm, the mass percentage concentration is 60%~80%, the surface repair treatment temperature is 75℃~90℃, and the surface repair treatment time is 3 minutes~6 minutes; When 5nm < Ra ≤ 10 nm, the mass percentage concentration is 70% to 85%, the surface repair treatment temperature is 80℃ to 100℃, and the surface repair treatment time is 4 minutes to 10 minutes.

5. The method of claim 1, wherein, The method further includes: Under an inert gas or nitrogen atmosphere, the semiconductor substrate is subjected to a thermal annealing treatment for 30 to 120 seconds at a controlled temperature of 800°C to 950°C. And / or, in an inert gas atmosphere, the surface of the semiconductor substrate is subjected to low-energy plasma treatment for 30 to 120 seconds, wherein the processing power of the low-energy plasma treatment is 50W to 150W.

6. The method of claim 1, wherein, Following the surface repair treatment step, the procedure further includes: The semiconductor substrate is removed and rinsed with deionized water. The rinsed semiconductor substrate is then subjected to ultrasonic cleaning. Dry the semiconductor substrate after ultrasonic cleaning; And / or, the etched substrate further includes an unetched area, and prior to the surface repair treatment step, the method further includes: forming a temporary protective layer on the surface of the unetched area of ​​the etched substrate, wherein the temporary protective layer is used to protect the unetched area from corrosion by the phosphoric acid solution; after the surface repair treatment, the method further includes: removing the temporary protective layer.

7. The method of claim 1, wherein, The substrate to be etched is made of gallium nitride, the phosphoric acid solution has a mass percentage concentration of 50% to 80%, the surface repair treatment temperature is 70°C to 90°C, and the surface repair treatment time is 2 minutes to 6 minutes.

8. The method of claim 1, wherein, The material of the substrate to be etched is gallium nitride, and the surface of the substrate to be etched is an N-polar surface; And / or, the etching of the substrate to be etched using inductively coupled plasma etching includes: forming a mask layer on the substrate to be etched; wherein the mask layer partially covers the substrate to be etched; and etching the portion of the substrate not covered by the mask layer using an etching gas under conditions of 200W to 400W power and 50V to 150V RF bias, to form an etched region; wherein the etching gas includes Cl2 and Ar, and the etching depth is 80 nm to 120 nm.

9. A semiconductor substrate, characterized by, The semiconductor substrate is prepared by the method described in any one of claims 1 to 8.

10. A semiconductor device, characterized by comprising: include: A semiconductor substrate and device structure stacked together, wherein the semiconductor substrate is the semiconductor substrate as described in claim 9.

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