3D lamination alignment detection method, device and equipment based on TSV (Through Silicon Via), and storage medium

Abstract

The invention provides a TSV through hole-based 3D lamination alignment detection method, device and equipment and a storage medium, and the method comprises the steps: carrying out the high-resolution imaging of the side wall of a TSV through hole through a section sample obtained by carrying out the layer-by-layer etching of each TSV through hole in a first lamination layer in a direction perpendicular to the surface of a wafer, and obtaining a side wall image; measuring the longitudinal continuous distribution of the conductive filling material in the TSV through hole based on the side wall image to obtain a current response map; determining an effective conductive axis based on position information of a depth interval in which the current intensity is higher than a preset intensity threshold value in the current response map, and constructing a reference axis based on the effective conductive axis in combination with geometric center coordinates of a top opening of the TSV; and calculating a space offset vector of the reference axis of the corresponding TSV between the two laminations based on the reference axis of the TSV at the corresponding position on the second lamination to obtain an alignment deviation value. According to the invention, the robustness of alignment detection of the 3D lamination under a complex process condition is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, and storage medium for 3D stack alignment and detection based on TSV vias. Background Technology

[0002] In 3D integrated circuit (3DIC) manufacturing, wafer stacking processes based on through-silicon vias (TSVs) rely on high-precision alignment and inspection to ensure reliable electrical connections between upper and lower stacks. A typical existing method involves acquiring images of the TSV edge contours using an optical microscopy imaging system and identifying the center position of the via by utilizing image contrast differences, thereby determining the relative displacement between upper and lower stacks.

[0003] However, this method has significant drawbacks in practical applications. When the TSV via surface has an oxide layer, residues, or local irregularities, its edge reflection characteristics change non-uniformly, leading to image contrast distortion and making it impossible to accurately extract the geometric center of the via. This results in increased alignment errors, severely affecting subsequent bonding quality and electrical performance. This problem stems from relying solely on a single optical imaging mode to obtain surface morphology information, lacking effective perception of the internal structural features of the TSV via, thus making it difficult to achieve robust alignment detection under complex process conditions. Summary of the Invention

[0004] This invention provides a 3D stack alignment detection method, apparatus, device, and storage medium based on TSV vias, which can fundamentally avoid alignment errors caused by surface reflection distortion and improve the robustness of 3D stack alignment detection under complex process conditions.

[0005] In a first aspect, the present invention provides a 3D wafer alignment detection method based on TSV vias, wherein the 3D wafer to be detected includes a first layer and a second layer, each layer containing a plurality of regularly arranged TSV vias; the 3D wafer alignment detection method includes: Each TSV via on the first stack is etched layer by layer using a focused ion beam along a direction perpendicular to the wafer surface to obtain a cross-sectional sample. Based on the cross-sectional sample, a scanning electron microscope is used to perform high-resolution imaging of the TSV via sidewalls to obtain a sidewall image. Based on the sidewall image, the longitudinal continuity distribution of the conductive filling material in the TSV via is measured by electron beam induced current effect to obtain the current response spectrum; Based on the location information of the depth range where the current intensity is higher than the preset intensity threshold in the current response spectrum, the effective conductive axis of the TSV via in the depth direction is determined, and a reference axis is constructed based on the effective conductive axis and the geometric center coordinates of the top opening of the TSV via. Based on the reference axis of the corresponding TSV via on the second stack, the spatial offset vector of the reference axis of the corresponding TSV via between the two stacks is calculated to obtain the alignment deviation of the 3D stack.

[0006] Secondly, the present invention also provides a 3D laminate alignment and detection device based on TSV vias, applied to the 3D laminate alignment and detection method based on TSV vias as described in the first aspect; the 3D laminate to be detected includes a first layer and a second layer, each layer containing a plurality of regularly arranged TSV vias; the 3D laminate alignment and detection device includes: The via processing module is used to use a focused ion beam to etch each TSV via on the first stack layer by layer in a direction perpendicular to the wafer surface to obtain a cross-sectional sample, and to use a scanning electron microscope to perform high-resolution imaging of the TSV via sidewalls based on the cross-sectional sample to obtain a sidewall image. The response spectrum construction module is used to measure the longitudinal continuity distribution of the conductive filling material in the TSV via through the electron beam induced current effect based on the sidewall image, and obtain the current response spectrum. The axis construction module is used to determine the effective conductive axis of the TSV via in the depth direction based on the position information of the depth range where the current intensity is higher than the preset intensity threshold in the current response spectrum, and to construct a reference axis based on the effective conductive axis and the geometric center coordinates of the top opening of the TSV via. The alignment detection module is used to calculate the spatial offset vector of the corresponding TSV via reference axis between the two stacks based on the reference axis of the corresponding TSV via on the second stack, so as to obtain the alignment deviation of the 3D stack.

[0007] Thirdly, the present invention also provides an electronic device, comprising: a memory for storing computer software programs; and a processor for reading and executing the computer software programs, thereby realizing the 3D stack alignment and detection method based on TSV vias as described above.

[0008] Fourthly, the present invention also provides a non-transitory computer-readable storage medium storing a computer software program, which, when executed by a processor, implements the 3D stack alignment detection method based on TSV vias as described above.

[0009] Fifthly, the present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the 3D stack alignment detection method based on TSV vias as described above.

[0010] The 3D stack alignment and detection method based on TSV vias provided in this invention utilizes a focused ion beam to vertically etch each TSV via on the first stack layer by layer to obtain a cross-sectional sample. High-resolution imaging of the TSV via sidewalls is then performed using a scanning electron microscope to obtain sidewall images. Therefore, by exposing the internal structure of the via through layer-by-layer etching, combined with the high-resolution imaging capability of the scanning electron microscope, interference from oxide layers, residues, and irregular local morphology on the TSV via surface can be directly avoided. Information is no longer dependent on surface reflection characteristics, thus obtaining the true structural information of the internal sidewalls of the vias instead of relying solely on surface morphology. This results in a high-resolution, true structural image of the internal sidewalls of the TSV vias, solving the problem of surface contrast distortion. Based on the sidewall images, the longitudinal continuity distribution of the conductive filling material within the TSV vias is measured using the electron beam-induced current effect. Therefore, by utilizing the difference in current response between conductive and non-conductive materials, the distribution of the effective conductive region inside the via is accurately captured. Based on the current response spectrum, depth ranges with current intensities exceeding a preset threshold are selected. The effective conductive axis of the TSV via in the depth direction is determined according to the location information of these depth ranges. This eliminates interference from non-conductive defects inside the via (such as incomplete filling areas), locking onto the core axis that truly enables electrical connection and avoiding alignment deviations caused by misjudging conductive areas. A reference axis is constructed based on the effective conductive axis and the geometric center coordinates of the TSV via's top opening. This balances the effective conductive structure inside the via with the position of the top opening, ensuring the alignment reference matches the actual electrical connection requirements while avoiding the drawbacks of relying solely on the geometric center of the surface opening (susceptible to surface defects) and eliminating dependence on single-surface optical imaging. The spatial offset vector between the reference axis of the corresponding TSV via on the second stack and the corresponding reference axis of the first stack is calculated based on the reference axis, yielding the alignment deviation of the 3D stack. Therefore, using the internal effective conductive axis as the reference, rather than the surface contour, ensures the accuracy of the offset measurement. Based on the alignment deviation, the relative displacement between two stacks can be accurately determined, which fundamentally avoids the alignment error caused by the distortion of surface reflection characteristics in the existing technology. It effectively solves the problems that a single optical imaging mode cannot perceive the internal structure and the lack of robustness under complex process conditions, and improves the robustness of 3D stacking alignment detection under complex process conditions. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating the 3D stack alignment and detection method based on TSV vias provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of the 3D stack alignment and detection device based on TSV through-hole provided in an embodiment of the present invention; Figure 3 An embodiment diagram of the electronic device provided in this invention; Figure 4An embodiment diagram of a computer-readable storage medium provided in accordance with the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] See Figure 1 , Figure 1 This is a flowchart illustrating the 3D die stack alignment and detection method based on TSV vias provided by the present invention. In this embodiment, the execution entity of the 3D die stack alignment and detection method based on TSV vias is a chip inspection device. Therefore, the 3D die stack alignment and detection method based on TSV vias includes: Step 10: Use a focused ion beam to etch each TSV via on the first stack layer by layer along a direction perpendicular to the wafer surface to obtain a cross-sectional sample. Based on the cross-sectional sample, use a scanning electron microscope to perform high-resolution imaging of the TSV via sidewalls to obtain sidewall images.

[0014] Optionally, the chip inspection device acquires the 3D wafer to be inspected. The 3D wafer includes at least a first layer and a second layer. A plurality of through-silicon vias (TSVs) are pre-prepared on the first layer. The TSVs are through-hole structures that penetrate the thickness direction of the first layer and are used to realize electrical connections between the layers of the 3D wafer. Each TSV is filled with a conductive filler material.

[0015] Furthermore, the chip detection device activates the focused ion beam generation module to generate a focused ion beam. The focused ion beam is an ion beam that has undergone focusing treatment and has high energy and high collimation. The ion type can be gallium ions, and the beam spot diameter of the focused ion beam is controlled in the range of 1 nanometer to 10 nanometers.

[0016] Furthermore, the chip inspection device adjusts the emission direction of the focused ion beam through the displacement adjustment module, so that the emission direction of the focused ion beam is perpendicular to the wafer surface of the first stack. The wafer surface is the side surface of the first stack away from the second stack, ensuring that the etching direction is consistent with the depth direction of the TSV via, and avoiding etching deviation that would cause the cross-sectional sample to fail to accurately reflect the internal structure of the TSV via sidewall.

[0017] Furthermore, the chip inspection device controls the focused ion beam to align with each TSV via on the first stack, and etches each TSV via layer by layer according to preset etching parameters. Layer-by-layer etching is performed along the depth direction of the TSV via, from the wafer surface towards the interface between the first and second stacks, etching a preset thickness of material each time, with the etching thickness controlled within the range of 5 nanometers to 20 nanometers. After each etching operation, etching is paused and the generated debris is removed. Debris removal is performed using an inert gas purging method, with argon as the inert gas, and the purging pressure controlled between 0.1 and 0.3 MPa. This layer-by-layer etching and debris removal operation continues until the etching depth penetrates the entire thickness of the first stack, completely exposing the internal structure of the TSV via sidewalls, obtaining a cross-sectional sample corresponding to each TSV via. The cross-sectional sample is a longitudinal section along the diameter direction of the TSV via, with its flatness controlled within 2 nanometers, including the roughness of the sidewalls and the bonding state between the conductive filling material and the sidewalls.

[0018] Furthermore, the chip inspection device transfers the sample stage carrying the cross-sectional sample into the inspection chamber of the scanning electron microscope (SEM). The inspection chamber is sealed and evacuated, with the vacuum level controlled within the range of 1*10^-5 Pa to 1*10^-7 Pa to prevent airborne impurities from affecting image quality. The chip inspection device then starts the SEM and adjusts its imaging parameters. The accelerating voltage is controlled between 5 kV and 20 kV, and the magnification is controlled between 1000x and 100000x, flexibly adjusted according to the size of the TSV via and the required inspection accuracy, ensuring clear capture of the details of the TSV via's inner wall contour and the interface with the filling material.

[0019] Furthermore, the chip detection device controls the electron beam of the scanning electron microscope to scan the sidewall region of the TSV via in the cross-sectional sample. The electron beam interacts with the cross-sectional sample to generate secondary electrons and backscattered electrons. The scanning electron microscope collects these electron signals through a detector and converts them into electrical signals. After signal amplification, filtering and other processing, a sidewall image containing the inner wall contour of the TSV via and the interface of the filling material is generated. The sidewall image is a two-dimensional grayscale image with an image resolution controlled within the range of 1 nanometer to 5 nanometers to ensure that the boundary between the inner wall contour of the TSV via and the conductive filling material can be clearly distinguished in the image.

[0020] In one embodiment, the first layer of the 3D wafer to be inspected is a silicon wafer with a thickness of 100 micrometers. 100 TSV vias are fabricated on the first layer, each with a diameter of 5 micrometers and a depth of 100 micrometers, filled with copper as a conductive filler. The chip inspection device activates the focused ion beam generation module to generate a gallium ion focused ion beam, adjusting the beam spot diameter to 5 nanometers. A displacement adjustment module ensures the focused ion beam is perpendicular to the wafer surface of the first layer.

[0021] The chip inspection device controls the focused ion beam to align with the first TSV via, etching layer by layer at a thickness of 10 nanometers each time. After each etching, the etched surface is purged with 0.2 MPa argon gas to remove debris. Etching continues until the etching depth reaches 100 micrometers, penetrating the entire first stack, obtaining a longitudinal cross-sectional sample of the TSV via with a flatness of 1.5 nanometers. Following the same etching parameters and operating procedures, the remaining 99 TSV vias are etched layer by layer, obtaining 100 corresponding cross-sectional samples. The sample stage containing 100 cross-sectional samples was transferred to the scanning electron microscope (SEM) chamber, and the vacuum was evacuated to 5*10^-6 Pa. The accelerating voltage of the SEM was adjusted to 10 kV, and the magnification was set to 50,000. The electron beam was controlled to scan the TSV via sidewall region of each cross-sectional sample. The electron signals were collected and processed to obtain sidewall images corresponding to 100 TSV vias. The resolution of each sidewall image was 3 nanometers. The images clearly showed the inner wall contour of the TSV vias and the interface boundary between the copper filling material and the inner wall.

[0022] Step 20: Based on the sidewall image, the longitudinal continuity distribution of the conductive filling material in the TSV via is measured by electron beam induced current effect to obtain the current response spectrum.

[0023] Optionally, the chip detection device preprocesses the sidewall image. The preprocessing operations include image denoising, image enhancement, and image calibration. Image denoising uses a Gaussian filtering algorithm to remove random noise in the image and ensure image clarity. Image enhancement is used to improve the contrast between the inner wall contour of the TSV via and the interface of the filling material, which facilitates the subsequent positioning of the detection area. Image calibration is used to correct the geometric distortion of the image to ensure that the image can truly reflect the actual structure of the TSV via.

[0024] After preprocessing, the chip detection device uses the electron beam induced current effect to measure the longitudinal continuity distribution of the conductive filling material in the TSV via based on the preprocessed sidewall image, and obtains the current response spectrum characterizing the electrical continuity state of the TSV via, as described in steps 201 to 204.

[0025] Step 30: Based on the location information of the depth range where the current intensity is higher than the preset intensity threshold in the current response spectrum, determine the effective conductive axis of the TSV via in the depth direction, and construct a reference axis based on the effective conductive axis and the geometric center coordinates of the top opening of the TSV via.

[0026] Optionally, the preset intensity threshold is the minimum induced current intensity that can characterize the effective electrical conduction of the conductive filler material in the TSV via. It is determined according to the type of conductive filler material, the size of the TSV via, and the preset electrical performance requirements. The preset intensity threshold is determined by: retrieving the current response data of a standard TSV via with the same conductive filler material and the same size. The standard TSV via is a verified TSV via with good electrical continuity and continuous, defect-free conductive filler material. The minimum value of the induced current intensity in the current response spectrum of the standard TSV via is extracted, and this minimum value is used as the preset intensity threshold to ensure that the preset intensity threshold can accurately distinguish between the effective conduction area and the ineffective conduction area of ​​the conductive filler material.

[0027] Optionally, the chip detection device analyzes the current response spectrum of each TSV via and identifies the depth range in the spectrum where the current intensity is higher than a preset intensity threshold. This depth range is the area in which the conductive filling material in the TSV via can achieve effective electrical conduction, and is called the effective conduction range.

[0028] Furthermore, the chip detection device extracts the position information of the effective conductive region, wherein the position information includes the start depth and end depth of the effective conductive region, the start depth is the depth value of the effective conductive region near the wafer surface, and the end depth is the depth value of the effective conductive region near the interface between the first stack and the second stack.

[0029] Further, based on the location information of the effective conductive region, the chip detection device determines the effective conductive axis of the TSV via in the depth direction. The effective conductive axis is the center line running through the entire effective conductive region in the depth direction of the TSV via. Optionally, the determination method in this embodiment of the invention is as follows: calculate the intermediate depth of the effective conductive region, which is the arithmetic mean of the starting depth and the ending depth, i.e., intermediate depth = (starting depth + ending depth) / 2; then, within the effective conductive region, along the depth direction of the TSV via, a cross section is extracted at preset intervals, with the preset interval controlled within the range of 1 micrometer to 5 micrometers. The geometric center coordinates of the conductive filling material at each cross section are measured. The geometric center coordinates are established in a two-dimensional coordinate system with the wafer surface as the reference plane, where the horizontal axis is the horizontal distance and the vertical axis is the vertical distance (i.e., depth). The geometric centers of the conductive filling materials at all cross sections are fitted to obtain a straight line running through the entire effective conductive region. This straight line is the effective conductive axis of the TSV via in the depth direction.

[0030] Further, the chip inspection device measures the geometric center coordinates of the top opening of the TSV via. The top opening of the TSV via is the opening of the TSV via located on one side of the wafer surface. Optionally, in this embodiment of the invention, the geometric center coordinates are measured as follows: based on the sidewall image obtained in step 10, the edge contour of the top opening of the TSV via is located. The edge contour is the outer boundary of the top opening. The feature points of the edge contour are extracted using an edge detection algorithm. The number of feature points is not less than 10. Then, the average abscissa and the average ordinate of all feature points are calculated. The coordinates formed by the average abscissa and the average ordinate are the geometric center coordinates of the top opening of the TSV via.

[0031] In one embodiment, for example, the current response spectra of 100 TSV vias obtained in step 20 are used to retrieve the current response data of a standard TSV via that is the same as the TSV via to be detected (copper filling material, diameter 5 micrometers, depth 100 micrometers). In the current response spectra of the standard TSV via, the minimum value of the induced current intensity is 3*10^-10 Amperes. Therefore, the preset intensity threshold is set to 3*10^-10 Amperes.

[0032] The current response spectrum of one TSV via was analyzed to identify the depth range where the current intensity exceeds 3*10^-10 amperes, with an initial depth of 15 micrometers and an ending depth of 90 micrometers, meaning the effective conductive range is from 15 micrometers to 90 micrometers. The intermediate depth of this effective conductive range was calculated as (15 micrometers + 90 micrometers) / 2 = 52.5 micrometers. Subsequently, along the depth direction of the TSV via, a cross-section was extracted every 3 micrometers, for a total of 26 cross-sections (15 micrometers, 18 micrometers, 21 micrometers...90 micrometers). The geometric center coordinates of the copper filler material at each cross-section were measured. A two-dimensional coordinate system was established with the wafer surface as the reference plane, with the horizontal axis as the horizontal direction (x-axis) and the vertical axis as the depth direction (y-axis). The measured geometric center coordinates of each cross-section were (0 micrometers, 15 micrometers), (0.01 micrometers, 18 micrometers), (0.01 micrometers, 21 micrometers)...(0.02 micrometers, 90 micrometers). These geometric center coordinates were linearly fitted to obtain a straight line, which is the effective conductive axis of the TSV via in the depth direction.

[0033] Based on the TSV via sidewall image obtained in step 10, the Canny edge detection algorithm was used to extract the edge contour of the top opening of the TSV via, extracting 12 feature points with coordinates of (2.5 μm, 0 μm), (-2.5 μm, 0 μm), (0 μm, 2.5 μm), (0 μm, -2.5 μm), (1.77 μm, 1.77 μm), (1.77 μm, -1.77 μm), (-1.77 μm, 1.77 μm), (-1.77 μm, 1.77 μm), (-1.77 μm, 1.77 μm), (-1.77 μm, The x-coordinates of these feature points are (-1.77 μm), (2.2 μm, 1.1 μm), (2.2 μm, -1.1 μm), (-2.2 μm, 1.1 μm), and (-2.2 μm, -1.1 μm). The average x-coordinate of these feature points is (2.5 - 2.5 + 0 + 0 + 1.77 + 1.77 - 1.77 - 1.77 + 2.2 + 2.2 - 2.2 - 2.2) / 12 = 0. The average y-coordinate of these feature points is 0. Therefore, the geometric center coordinates of the top opening of the TSV via are (0, 0).

[0034] Furthermore, based on the effective conductive axis combined with the geometric center coordinates of the top opening of the TSV via, a reference axis is constructed that penetrates the three-dimensional space of the TSV via, as described in steps 301 to 304.

[0035] Step 40: Calculate the spatial offset vector of the corresponding TSV via reference axis between the two stacks based on the reference axis of the corresponding TSV via on the second stack, and obtain the alignment deviation of the 3D stack.

[0036] Optionally, the chip detection device acquires the reference axis of each TSV via on the first stack and simultaneously acquires the reference axis of the corresponding TSV via on the second stack. The corresponding TSV via is a TSV via on the second stack that is designed to achieve interlayer electrical connection and whose position corresponds one-to-one with a certain TSV via on the first stack. The acquisition method of the reference axis of the corresponding TSV via on the second stack is completely consistent with the acquisition method of the reference axis of the TSV via in the first stack in steps 10 to 30.

[0037] Furthermore, the chip inspection device establishes a three-dimensional coordinate system to calculate the spatial offset vector of the corresponding TSV via reference axis between the two stacks. The three-dimensional coordinate system is established as follows: the wafer surface of the first stack is the xy plane, the geometric center of the wafer surface is the origin (0, 0, 0), the x-axis and y-axis are two mutually perpendicular directions in the xy plane, corresponding to the transverse and longitudinal directions of the wafer, respectively, the z-axis is the direction perpendicular to the xy plane, that is, the depth direction of the TSV via, and the positive direction of the z-axis is the direction from the first stack to the second stack, ensuring that the coordinate system can accurately represent the three-dimensional spatial position of the TSV via reference axis on the two stacks.

[0038] It should be noted that in the established three-dimensional coordinate system, the chip detection device extracts the axis parameters of the reference axis of a certain TSV via in the first stack and the axis parameters of the reference axis of the corresponding TSV via in the second stack. The axis parameters include the direction vector of the reference axis and the three-dimensional coordinates of any feature point on the reference axis. The feature point is selected as the midpoint of the reference axis. The midpoint is the point corresponding to the middle position of the reference axis through the depth direction of the TSV via. Optionally, the three-dimensional coordinates of this embodiment are obtained by measuring the three-dimensional coordinates of the starting point and the ending point of the reference axis. The starting point is the endpoint of the reference axis on one side of the stack surface, and the ending point is the endpoint of the reference axis on the side of the interface between the stack and another stack. The three-dimensional coordinates of the midpoint are the arithmetic mean of the three-dimensional coordinates of the starting point and the ending point, that is, the midpoint x-coordinate = (starting point x-coordinate + ending point x-coordinate) / 2, the midpoint y-coordinate = (starting point y-coordinate + ending point y-coordinate) / 2, and the midpoint z-coordinate = (starting point z-coordinate + ending point z-coordinate) / 2.

[0039] Further, based on the axial parameters of the two reference axes, the chip detection device calculates the spatial offset vector of the corresponding TSV via reference axis between the two stacks. The spatial offset vector is a vector used to characterize the relative offset degree and offset direction of the two reference axes in three-dimensional space. Optionally, the calculation algorithm of this embodiment of the invention is as follows: First, select corresponding feature points on the two reference axes, usually the midpoint of the two reference axes is selected as the corresponding feature point, and denoted as the first midpoint (midpoint of the first stack reference axis) and the second midpoint (midpoint of the corresponding reference axis of the second stack); Second, calculate the three-dimensional coordinate difference between the second midpoint and the first midpoint, that is, the x-component of the spatial offset vector = x-coordinate of the second midpoint - x-coordinate of the first midpoint, the y-component of the spatial offset vector = y-coordinate of the second midpoint - y-coordinate of the first midpoint, and the z-component of the spatial offset vector = z-coordinate of the second midpoint - z-coordinate of the first midpoint; Finally, combine the x-component, y-component and z-component to obtain the spatial offset vector of the corresponding TSV via reference axis between the two stacks. The magnitude of this vector is the spatial offset distance between the two reference axes, and the direction of the vector is the offset direction.

[0040] Therefore, the chip testing device calculates the spatial offset vector between each TSV via on the first stack and the reference axis of the corresponding TSV via on the second stack according to the above calculation method. All spatial offset vectors together constitute the alignment deviation of the 3D stack. The alignment deviation is used to characterize the alignment accuracy of the TSV vias between the first and second stacks of the 3D stack. If the magnitude of a certain spatial offset vector exceeds the preset alignment threshold, it indicates that the alignment deviation of the TSV via at the corresponding position is too large, which may affect the interlayer electrical connection performance of the 3D stack, and subsequent correction processing is required.

[0041] If the magnitude of all spatial offset vectors is less than or equal to the preset alignment threshold, it indicates that the alignment accuracy of the 3D stack meets the requirements. The preset alignment threshold is determined based on the design requirements and electrical performance requirements of the 3D stack, and is typically controlled within the range of 0.1 micrometers to 1 micrometer.

[0042] In one embodiment, the chip inspection device acquires reference axes for 100 TSV vias in the first stack, and simultaneously acquires reference axes for 100 corresponding TSV vias in the second stack using the same method as steps 10 to 30. The second stack has the same structure as the first stack, both being silicon wafers with a thickness of 100 micrometers. The diameter, depth, and filling material of the corresponding TSV vias are consistent with those in the first stack. A three-dimensional coordinate system is established: the wafer surface of the first stack is the xy plane, the geometric center of the wafer surface is the origin (0, 0, 0), the x-axis is the wafer's horizontal axis, the y-axis is the wafer's vertical axis, and the z-axis is perpendicular to the xy plane and points positively towards the second stack. The unit of the coordinate system is micrometers. A TSV via (TSV1) in the first stack and its corresponding TSV via (TSV1') in the second stack are selected for calculation. The axis parameters of the TSV1 reference axis are extracted: the starting point coordinates of the TSV1 reference axis are (0 μm, 0 μm, 0 μm), and the ending point coordinates are (0.02 μm, 0.01 μm, 100 μm). Therefore, the three-dimensional coordinates of the midpoint (first midpoint) of the TSV1 reference axis are ((0+0.02) / 2, (0+0.01) / 2, (0+100) / 2) = (0.01 μm, 0.005 μm, 50 μm), and the direction vector of the TSV1 reference axis is (0.02, 0.01, 100).

[0043] Extract the axis parameters of the TSV1' reference axis: The starting point coordinates of the TSV1' reference axis are (0.03 μm, 0.02 μm, 100 μm), and the ending point coordinates are (0.05 μm, 0.03 μm, 200 μm). Therefore, the three-dimensional coordinates of the midpoint (second midpoint) of the TSV1' reference axis are ((0.03+0.05) / 2, (0.02+0.03) / 2, (100+200) / 2) = (0.04 μm, 0.025 μm, 150 μm). The direction vector of the TSV1' reference axis is (0.02, 0.01, 100). Calculate the spatial offset vector between the reference axes of TSV1 and TSV1': x component = 0.04 μm - 0.01 μm = 0.03 μm, y component = 0.025 μm - 0.005 μm = 0.02 μm, z component = 150 μm - 50 μm = 100 μm. Therefore, the spatial offset vector is (0.03 μm, 0.02 μm, 100 μm). The magnitude of this vector is approximately 100.0000065 μm. The offset distance in the x and y directions is approximately 0.036 μm, which is the horizontal alignment deviation between TSV1 and TSV1' between the two stacks.

[0044] Following the same calculation method described above, the spatial offset vectors of the remaining 99 TSV vias in the first stack and the corresponding TSV via reference axes in the second stack were calculated sequentially. Assuming a preset alignment threshold of 0.1 micrometers, the horizontal offset distances (combined displacements in the x and y directions) of all spatial offset vectors were calculated to be between 0.02 and 0.05 micrometers, all less than 0.1 micrometers. The z-direction offsets were all 100 micrometers (consistent with the thickness of the two stacks, which is a normal offset). Therefore, the alignment deviations of all corresponding TSV vias met the requirements. All spatial offset vectors together constituted the alignment deviation of the 3D stack, indicating that the alignment accuracy between the first and second stacks of the 3D stack was good.

[0045] The embodiments of the present invention fundamentally avoid alignment errors caused by distortion of surface reflection characteristics, and improve the robustness of alignment detection of 3D stacking under complex process conditions.

[0046] Optionally, the processes of steps 201 to 204 include: Step 201: Based on the geometric boundary information of the TSV via along the depth direction in the sidewall image, determine the start and end positions of the electron beam scanning path in the direction perpendicular to the wafer surface.

[0047] Optionally, the chip inspection device performs boundary extraction processing on the sidewall image. The boundary extraction processing in this embodiment of the invention adopts an edge detection algorithm to accurately identify the geometric boundary information of the TSV via along the depth direction in the sidewall image. The geometric boundary information is the inner wall contour boundary of the TSV via in the depth direction, including the top boundary of the TSV via near the wafer surface and the bottom boundary near the interface between the first and second stacks. It also includes the sidewall boundaries on both sides of the TSV via in the depth direction. The geometric boundary information is presented in the form of pixel coordinates, and each boundary point corresponds to a unique depth coordinate and horizontal coordinate.

[0048] Furthermore, the chip inspection device filters and calibrates the geometric boundary information. The filtering operation is used to remove false boundary points generated during edge detection. False boundary points are boundary points that do not belong to the true inner wall contour of the TSV via, caused by interference factors such as image noise and etching marks. The filtering criteria are: retain boundary points with a deviation from the TSV via design size within 0.1 micrometers, and remove boundary points with a deviation exceeding 0.1 micrometers. The calibration operation is used to correct the coordinate deviation of the boundary points. The coordinate deviation is the systematic error generated during edge detection. The calibration method is to linearly correct the coordinates of the filtered boundary points based on the design depth and design diameter of the TSV via, ensuring that the geometric boundary information truly reflects the structure of the TSV via.

[0049] Furthermore, the chip inspection device determines the start and end positions of the electron beam scanning path in the direction perpendicular to the wafer surface, which is the depth direction of the TSV via. The start position is the depth coordinate corresponding to the top boundary of the TSV via, which is the inner wall contour boundary of the TSV via near the wafer surface, and its depth coordinate value is 0 micrometers (with the wafer surface as the reference plane). The end position is the depth coordinate corresponding to the bottom boundary of the TSV via, which is the inner wall contour boundary of the TSV via near the interface between the first and second stacks, and its depth coordinate value is equal to the actual depth of the TSV via, which is the thickness of the TSV via penetrating the first stack measured during the etching process in step 10. By accurately determining the start and end positions, it is ensured that the electron beam scanning path can completely cover the entire depth range of the TSV via.

[0050] Step 202: Based on the start and end positions, determine the electron beam point-by-point scanning sequence covering the entire TSV via depth range.

[0051] Optionally, the chip inspection device determines the coverage range of the electron beam scanning path in the depth direction based on the start and end positions of the electron beam scanning path. Therefore, the coverage range is the complete depth interval from the start position (0 micrometers) to the end position (actual depth of the TSV via). Further, based on this coverage range, the chip inspection device determines an electron beam point-by-point scanning sequence covering the entire depth range of the TSV via. The electron beam point-by-point scanning sequence is the arrangement order of the scanning points in the depth direction and the specific position parameters of each scanning point, including the depth coordinates and horizontal coordinates of each scanning point.

[0052] Furthermore, the chip detection device determines the depth interval of the scanning points. The depth interval is the distance between two adjacent scanning points in the depth direction. The depth interval is determined based on the actual depth of the TSV via and the measurement accuracy requirements. The measurement accuracy requirements are the minimum amount of variation in the longitudinal continuity of the conductive filling material that can be accurately captured, which is usually controlled within the range of 1 nanometer to 10 nanometers. The depth interval is calculated as follows: Depth interval = (Depth coordinate of the end position - Depth coordinate of the start position) / Total number of preset scanning points. The total number of preset scanning points is determined according to the measurement accuracy requirements to ensure that the depth interval between two adjacent scanning points is not greater than the maximum value of the measurement accuracy requirements. For example, if the actual depth of the TSV via is 100 micrometers and the measurement accuracy requirement is 5 nanometers, then the total number of preset scanning points is not less than 20,000, and the depth interval is 5 nanometers.

[0053] Furthermore, the chip detection device determines the horizontal coordinates of each scanning point. The horizontal coordinates are the positions of the scanning points perpendicular to the depth direction, i.e., the horizontal coordinates of the sidewall image. The determination of the horizontal coordinates is based on the geometric center of the inner wall contour of the TSV via. The geometric center is the center position of the inner wall contour at a certain depth section of the TSV via. Its horizontal coordinates are obtained by calculating the average horizontal coordinates of the boundary points of the inner wall contour at that depth section. This ensures that each scanning point is located on the geometric center line of the inner wall contour of the TSV via, so that the electron beam can accurately irradiate the central area of ​​the conductive filling material, avoiding current signal acquisition failure or signal distortion caused by the scanning point deviating from the conductive filling material.

[0054] Furthermore, the chip inspection device combines all scanning points in the order of depth coordinates from the start position to the end position to form an electron beam point-by-point scanning sequence. Each scanning point corresponds to a unique depth coordinate and horizontal coordinate. The arrangement order of the scanning points in the scanning sequence is consistent with the depth direction of the TSV via, ensuring that the electron beam can scan point by point in an orderly manner along the depth direction.

[0055] Step 203: Based on the electron beam point-by-point scanning sequence, a focused electron beam is applied to the TSV through-hole cross-section sample in a scanning electron microscope to collect the current signal induced by the electron beam and obtain the original electron beam induced current value corresponding to each scanning point.

[0056] Optionally, the chip detection device fixes the sample stage carrying the TSV through-hole cross-section sample in the detection chamber of the scanning electron microscope to ensure the stability of the cross-section sample position and avoid scanning deviation caused by sample displacement during scanning. The vacuum degree of the detection chamber is maintained in the range of 1*10^-5 Pa to 1*10^-7 Pa to avoid impurities in the air from affecting the propagation of the electron beam and the acquisition of the current signal.

[0057] Furthermore, the chip inspection device activates the scanning electron microscope and adjusts the electron beam parameters of the scanning electron microscope. The electron beam parameters include accelerating voltage, beam spot diameter, and beam current intensity. The accelerating voltage is controlled between 5 kV and 20 kV, the beam spot diameter is controlled between 1 nm and 5 nm, and the beam current intensity is controlled between 1*10^-12 Apertures and 1*10^-10 Apertures. The adjustment of the above parameters is based on the type of conductive filling material and the size of the TSV via, to ensure that the electron beam can be focused to form a high-energy, high-collimation focused electron beam, and that the interaction between the electron beam and the conductive filling material can generate a stable electron beam induced current signal.

[0058] Furthermore, the chip detection device, based on the electron beam point-by-point scanning sequence, controls the electron beam deflection module of the scanning electron microscope to drive the focused electron beam to irradiate the conductive filling material area of ​​the TSV via cross-section sample point by point according to the arrangement order in the scanning sequence. The irradiation time of each scanning point is controlled within the range of 1 microsecond to 10 microseconds. The determination of the irradiation time is based on the acquisition stability of the current signal to ensure that a sufficiently strong current signal can be acquired, avoiding weak signals that cannot be identified due to too short an irradiation time, or damage to the conductive filling material due to too long an irradiation time.

[0059] It should be noted that during the point-by-point irradiation process of the focused electron beam, the electron beam interacts with the conductive filling material in the TSV via, generating electron-hole pairs. These electron-hole pairs are formed when electrons in the conductive filling material absorb energy and transition from the valence band to the conduction band after the electron beam irradiates the conductive filling material, while simultaneously forming a pair of charge carriers, namely holes, in the valence band.

[0060] Furthermore, the chip detection device applies a preset bias voltage through electrodes pre-connected to both ends of the TSV via. The preset bias voltage is a DC voltage that enables electron-hole pairs to separate and form an induced current. The voltage value is controlled within the range of 0.5 volts to 5 volts, specifically determined based on the resistivity of the conductive filling material.

[0061] Under a preset bias voltage, electron-hole pairs separate, with electrons moving towards the positive electrode and holes towards the negative electrode, forming an induced current, which is the electron beam induced current. Therefore, the chip detection device uses a current detection module to acquire the electron beam induced current signal corresponding to each scanning point in real time. The detection accuracy of the current detection module is controlled within the range of 1*10^-13 amperes to 1*10^-11 amperes, ensuring accurate capture of minute changes in the current signal. After signal amplification, filtering, and analog-to-digital conversion, the acquired current signal yields the original electron beam induced current value corresponding to each scanning point.

[0062] Step 204: Based on the original electron beam induced current value and its corresponding depth coordinate position, combined with the longitudinal continuity distribution of the conductive filling material in the TSV via, the current response spectrum is obtained.

[0063] Optionally, the chip detection device obtains a current response spectrum based on the original electron beam induced current value and its corresponding depth coordinate position, combined with the longitudinal continuity distribution of the conductive filling material in the TSV via, as described in steps 2041 to 2044.

[0064] This invention enables accurate and comprehensive measurement of the longitudinal continuity distribution of conductive filling material within TSV vias. It can effectively distinguish between continuous and discontinuous areas of conductive filling material, accurately capture the distribution of the effective conductive area inside the via, avoid continuity judgment errors caused by unreasonable scanning paths, ensure the accuracy of 3D stack alignment deviation measurement, effectively solve the problem of inaccurate conductivity continuity measurement caused by surface interference, and improve the robustness of TSV via electrical performance testing.

[0065] Optionally, the process of steps 2041 to 2044 includes: Step 2041: Based on the original electron beam induced current value and its corresponding depth coordinate position, the current signal is arranged in depth order to obtain a one-dimensional current intensity sequence distributed along the TSV through hole axis.

[0066] Optionally, the depth coordinate position is the specific location of each scanning point in the direction perpendicular to the wafer surface (i.e., the depth direction of the TSV via). The depth coordinate position is based on the wafer surface, and the coordinate values ​​increase sequentially from 0 (starting position) to the actual depth of the TSV via (ending position). Therefore, the original electron beam induced current value and its corresponding depth coordinate position are correlated and matched. Correlation and matching is to bind each original electron beam induced current value with its corresponding depth coordinate position to form a one-to-one key-value pair.

[0067] Furthermore, after the association matching is completed, the chip detection device sorts all the bound key-value pairs in ascending order of depth coordinate position values. The sorting order is consistent with the axis (depth direction) of the TSV via, that is, it is sorted sequentially from the starting position (0 micrometers) of the TSV via near the wafer surface to the ending position (actual depth of the TSV via) near the interface between the first and second stacks.

[0068] Furthermore, after sorting, the chip detection device extracts the original electron beam induced current value from each key-value pair after sorting, and arranges these current values ​​sequentially according to the sorting order to form a one-dimensional current intensity sequence distributed along the TSV via axis. The one-dimensional current intensity sequence is a single-dimensional set of current intensity data arranged in depth order. Each current intensity data in the sequence corresponds to a unique depth coordinate position, and the arrangement order of the sequence is completely consistent with the scanning order along the depth direction of the TSV via, which can intuitively reflect the current intensity distribution at different positions along the depth direction of the TSV via. Step 2042: Based on the current change trend between adjacent depth points in the one-dimensional current intensity sequence, identify the depth range where the jump amplitude of the current intensity is greater than a preset amplitude threshold, and obtain the set of critical depth positions that characterize the existence of electrical connections or disconnections inside the conductive filling material.

[0069] Optionally, the preset amplitude threshold is a critical current difference used to determine whether the current intensity has changed significantly and to identify abrupt changes in the electrical connection state of the conductive filler material. The preset amplitude threshold is determined based on the inherent conductivity characteristics of the conductive filler material, the design electrical parameters of the TSV via, and the measurement accuracy requirements. In this embodiment of the invention, the specific method for determining the preset amplitude threshold is as follows: the chip detection device retrieves the current intensity change data of standard TSV vias with the same conductive filler material and the same size. The standard TSV via is a verified TSV via with continuous and defect-free conductive filler material and good electrical connection state. The maximum current change amplitude between adjacent depth points in the one-dimensional current intensity sequence of the standard TSV via is extracted, and 1.5 to 2 times the maximum current change amplitude is set as the preset amplitude threshold. This ensures that the preset amplitude threshold can accurately distinguish between normal small fluctuations and abnormal abrupt changes in the electrical connection state of the conductive filler material, avoiding the omission of critical depth positions due to an excessively high threshold or the misjudgment of critical depth positions due to an excessively low threshold.

[0070] Furthermore, the chip detection device performs point-by-point analysis on the one-dimensional current intensity sequence, and calculates the current intensity difference between two adjacent depth points in the sequence in turn. Optionally, the calculation algorithm for the current intensity difference in this embodiment of the invention is as follows: starting from the first current value in the one-dimensional current intensity sequence, two adjacent current intensity data are selected in turn, and the previous current intensity data is subtracted from the next current intensity data to obtain the current intensity difference between two adjacent depth points. The current intensity difference can be positive (the current intensity of the next depth point is greater than that of the previous one), negative (the current intensity of the next depth point is less than that of the previous one), or zero (the current intensities of the two depth points are the same). The absolute value of the current intensity difference is used to characterize the jump amplitude of the current intensity between adjacent depth points. After calculating the current intensity difference between all adjacent depth points, the chip detection device compares the absolute value of each current intensity difference with a preset amplitude threshold, and selects adjacent depth point pairs whose absolute value of the current intensity difference is greater than the preset amplitude threshold. The depth interval corresponding to this adjacent depth point pair is the depth interval where the current intensity jump amplitude is greater than the preset amplitude threshold. This type of depth interval indicates that the electrical connection state of the conductive filling material in the TSV via has changed significantly, and the conductive filling material may switch between conduction and disconnection.

[0071] Furthermore, the chip detection device extracts the boundary depth coordinates of all selected depth intervals, which are the critical locations where electrical connections or disconnections exist within the conductive filler material. All critical locations are then aggregated to form a critical depth location set. This set of critical depth locations represents the collection of depth coordinates that characterize abrupt changes in the electrical connection state of the conductive filler material. Each critical depth location corresponds to a turning point where the conductive filler material changes from a conductive state to a disconnected state or vice versa.

[0072] Step 2043: Based on the current intensity values ​​at each location in the critical depth location set, determine whether the conductive filling material has an effective current carrying capacity at the corresponding depth, and obtain the continuity state of the conductive path inside the TSV via in the depth direction.

[0073] Optionally, the chip detection device compares the current intensity value corresponding to each critical depth position in the set of critical depth positions with a preset intensity threshold to determine whether the conductive filling material at each critical depth position has effective current carrying capacity. Effective current carrying capacity is the ability of the conductive filling material to stably conduct current and realize electrical connection function. The judgment criteria of this embodiment are as follows: if the current intensity value corresponding to a certain critical depth position is higher than the preset intensity threshold, it indicates that the conductive filling material at the critical depth position can realize effective electrical conduction and has effective current carrying capacity; if the current intensity value corresponding to a certain critical depth position is lower than or equal to the preset intensity threshold, it indicates that the conductive filling material at the critical depth position cannot realize effective electrical conduction and does not have effective current carrying capacity.

[0074] Furthermore, the chip detection device, based on the distribution order of each critical position in the critical depth position set, divides different regions along the depth direction of the TSV via. Each region corresponds to a continuous depth range. Subsequently, it determines whether the effective current-carrying capacity of the conductive filler material in each region is continuous, thus obtaining the continuity status of the conductive path inside the TSV via in the depth direction. The continuity status characterizes whether the conductive path inside the TSV via is continuous in the depth direction and whether there are any disconnection defects. Specifically, it includes a continuous conducting region (where the current intensity at all depth points in this region is higher than a preset intensity threshold, and the conductive filler material has effective current-carrying capacity and is continuous), a disconnected region (where the current intensity at all depth points in this region is lower than or equal to the preset intensity threshold, and the conductive filler material does not have effective current-carrying capacity), and a conducting-disconnected alternating region (where there are multiple critical depth positions in this region, and the effective current-carrying capacity of the conductive filler material changes alternately), reflecting the true situation of the longitudinal continuity of the conductive filler material inside the TSV via.

[0075] Step 2044: Construct a current response spectrum based on the continuous state.

[0076] Optionally, the chip detection device constructs a current response spectrum based on the continuous state, as described in steps 20441 to 20444.

[0077] The embodiments of the present invention realize the orderly transformation from discrete raw current signals to accurate and visualized current response spectra, ensuring that the generated current response spectra can accurately reflect the longitudinal continuity distribution of conductive filling material in TSV vias, solving the problem of spectrum distortion caused by chaotic current signals and inaccurate determination of conductivity status, improving the reliability of current response spectra, and thus improving the robustness of 3D stack alignment detection.

[0078] Optionally, the process of steps 20441 to 20444 includes: Step 20441: Obtain the conductive path connectivity interval of the continuity status indication.

[0079] Optionally, the chip inspection device performs analytical processing on the continuous state. This analytical processing involves identifying each region type indicated in the continuous state and filtering out continuously conducting regions. A continuously conducting region is a depth region where the current intensity at all depth points is higher than a preset intensity threshold, the conductive filling material has effective current-carrying capacity, and the region is continuous; this is the conductive path connection interval. The conductive path connection interval is the depth range within the TSV via that enables stable current conduction and maintains the continuity of the conductive path. Each conductive path connection interval corresponds to a continuous depth range, and there are no conductive break defects within the interval.

[0080] Furthermore, the chip inspection device extracts the depth start position and depth end position of each conductive path connection interval. The depth start position is the starting depth coordinate of the conductive path connection interval near the top of the TSV via (on the wafer surface side), and the depth end position is the ending depth coordinate of the conductive path connection interval near the bottom of the TSV via (on the side of the interface between the first and second stacks).

[0081] Step 20442: Extract all continuous depth segments in the connected region of the conductive path where the current intensity is higher than the preset intensity threshold, to obtain a set of longitudinal conductive regions with effective current conduction capability within the TSV via.

[0082] Optionally, the chip detection device verifies each conductive path connection interval one by one. The verification process is as follows: retrieve the one-dimensional current intensity sequence, extract the current intensity values ​​corresponding to all depth points in each conductive path connection interval, and determine whether the current intensity value of each depth point is higher than the preset intensity threshold. This ensures that all depth points in the conductive path connection interval meet the requirements for effective electrical conduction and avoids some non-compliant depth segments from being mixed into the conductive path connection interval due to continuity state analysis errors.

[0083] Furthermore, after verification, the chip testing device filters out all continuous depth segments within each conductive path connection interval where the current intensity is higher than a preset intensity threshold. These continuous depth segments are those where the conductive filling material within the TSV via can stably achieve effective current conduction without any disconnection defects; that is, they are the longitudinal conductive regions with effective current conduction capability. Effective current conduction capability is the conduction capability of the conductive filling material to stably conduct current and meet the functional requirements of interlayer electrical connection in the TSV via. The core criterion for its judgment is that the current intensity is continuously higher than the preset intensity threshold and the depth segment is continuous and uninterrupted.

[0084] Furthermore, all longitudinally conductive regions with effective current conduction capability are aggregated to form a set of longitudinally conductive regions with effective current conduction capability within the TSV via. The set of longitudinally conductive regions is a collection of all continuous depth segments that meet the requirements for effective current conduction. Each element of the set includes the corresponding depth start position, depth end position, and current intensity range within the interval. The longitudinally conductive regions within the set are arranged in ascending order of depth coordinate position, consistent with the depth direction of the TSV via.

[0085] Step 20443: Calculate the center depth position of the conductive region based on the depth start position and depth end position of each conductive region in the set of longitudinal conductive regions, and obtain multiple center depth positions arranged in depth order.

[0086] Optionally, the chip detection device calculates the center depth position of each longitudinal conductive region based on the depth start position and depth end position of each longitudinal conductive region. The center depth position is the depth coordinate corresponding to the geometric center of each longitudinal conductive region in the depth direction, which is used to characterize the core position of the longitudinal conductive region. The specific calculation process of this embodiment is as follows: the center depth position of each longitudinal conductive region is equal to the arithmetic mean of the depth start position and depth end position of the region, that is, center depth position = (depth start position + depth end position) / 2.

[0087] Furthermore, the chip detection device sorts all calculated center depth positions in ascending order of depth coordinates. This sorting order is consistent with the depth direction of the TSV via and the arrangement order of the longitudinal conductive region set, ultimately resulting in multiple center depth positions arranged in depth order. Each center depth position uniquely corresponds to a longitudinal conductive region, and the sorted data can intuitively reflect the distribution pattern of the effective conductive region along the depth direction of the TSV via.

[0088] Step 20444: Based on whether the current intensity of multiple center depth locations and their corresponding conductive regions is higher than a preset intensity threshold, each center depth location is mapped to an effective conductive feature point in the current response spectrum. The depth coordinate is used as the horizontal axis and the current intensity is used as the vertical axis to connect all effective conductive feature points to form a continuous or segmented current response curve, thus obtaining the current response spectrum.

[0089] Optionally, the chip detection device maps each center depth position to a valid conductive feature point in the current response spectrum based on whether the current intensity of multiple center depth positions and their corresponding conductive regions is higher than a preset intensity threshold. The specific mapping process in this embodiment is as follows: Each center depth position is individually confirmed to correspond to a longitudinal conductive region, and it is determined whether the current intensity of that longitudinal conductive region is higher than a preset intensity threshold (since the longitudinal conductive region has already been screened in step 20442, and the current intensity of all its depth points is higher than the preset intensity threshold, it is directly mapped after confirmation here); each center depth position is used as the abscissa (depth coordinate) of the valid conductive feature point, and the average current intensity of the longitudinal conductive region corresponding to that center depth position is used as the ordinate (current intensity) of the valid conductive feature point. The average current intensity is the arithmetic mean of the current intensity values ​​of all depth points within the longitudinal conductive region, ensuring that the feature point can accurately characterize the current conduction state of the corresponding longitudinal conductive region.

[0090] Furthermore, the chip detection device establishes a coordinate system for the current response spectrum, with the depth coordinate of the TSV via as the horizontal axis, the horizontal axis coordinate range from the start position (0 micrometers) of the TSV via to the end position (actual depth of the TSV via), and the coordinate interval is consistent with the depth interval of the scanning points in sub-step 2042; with the current intensity as the vertical axis, the vertical axis coordinate range from 0 amperes to the maximum current intensity value in the one-dimensional current intensity sequence, ensuring that the differences in current intensity changes can be clearly presented.

[0091] Furthermore, the chip detection device marks all effective conductive feature points in the established coordinate system, and then connects all effective conductive feature points in sequence according to the depth coordinates from smallest to largest to form a continuous or segmented current response curve.

[0092] If the longitudinal conductive regions corresponding to two adjacent effective conductive feature points are continuous and uninterrupted in the depth direction, then the connection forms a continuous curve.

[0093] If there is a break in the longitudinal conductive region corresponding to two adjacent effective conductive feature points in the depth direction, then the connection forms a piecewise curve. The position of the break at the segment corresponds to the position of the break, and a current response spectrum is obtained that can intuitively characterize the electrical continuity of the TSV through hole and reflect the longitudinal continuity distribution of the conductive filling material.

[0094] The embodiments of the present invention achieve accurate conversion from continuous state to visualized current response spectrum, ensuring that the generated current response spectrum can clearly reflect the distribution of effective conductive area and current conduction state within the TSV via, effectively avoiding problems such as feature point deviation and curve distortion, improving the accuracy and reliability of the current response spectrum, thereby improving the robustness of 3D stack alignment detection.

[0095] Optionally, the processes of steps 301 to 304 include: Step 301: Based on the spatial coordinate point with the smallest depth value in the set of spatial coordinate points continuously distributed in the depth direction of the effective conductive axis, determine the three-dimensional coordinates of the top functional endpoint of the effective conductive axis.

[0096] Optionally, the chip inspection device extracts a set of spatial coordinate points continuously distributed along the depth direction of the effective conductive axis. The set of spatial coordinate points is a summary of all spatial coordinate points on the effective conductive axis. Each spatial coordinate point contains three-dimensional coordinate information. The three-dimensional coordinates are determined based on the three-dimensional coordinate system established in step 40. That is, the wafer surface of the first stack is the xy plane, the geometric center of the wafer surface is the origin (0, 0, 0), the x-axis and y-axis are two mutually perpendicular directions in the xy plane, corresponding to the transverse and longitudinal directions of the wafer, respectively, the z-axis is the direction perpendicular to the xy plane (i.e., the depth direction of the TSV via), and the positive direction of the z-axis is the direction from the first stack to the second stack. The unit of the coordinate system is micrometers.

[0097] Furthermore, the chip inspection device analyzes all spatial coordinate points in the set of spatial coordinate points and extracts the depth value of each spatial coordinate point. The depth value is the z-axis coordinate value of the spatial coordinate point, which is used to characterize the specific position of the coordinate point in the depth direction of the TSV via. The smaller the depth value, the closer the coordinate point is to the top of the TSV via (one side of the wafer surface), and the larger the depth value, the closer the coordinate point is to the bottom of the TSV via (one side of the interface between the first stack and the second stack).

[0098] The chip inspection device compares the depth values ​​of all spatial coordinate points and selects the spatial coordinate point with the smallest depth value. This spatial coordinate point is the coordinate point closest to the top of the TSV via on the effective conductive axis, which is the top functional endpoint of the effective conductive axis. The top functional endpoint is the connection point between the effective conductive axis and the top region of the TSV via, and can characterize the specific position of the effective conductive axis at the top of the TSV via. The three-dimensional coordinate information of this spatial coordinate point with the smallest depth value is extracted, which is the three-dimensional coordinate of the top functional endpoint of the effective conductive axis. This three-dimensional coordinate includes x-axis coordinates, y-axis coordinates, and z-axis coordinates (depth value), accurately reflecting the specific position of the top functional endpoint of the effective conductive axis in three-dimensional space.

[0099] Step 302: Based on the geometric center coordinates of the top opening of the TSV through hole, obtain its coordinate representation in the preset three-dimensional space to obtain the reference three-dimensional coordinates of the top structure of the TSV through hole.

[0100] Optionally, the top opening of the TSV via is the opening of the TSV via located on one side of the wafer surface. Its geometric center coordinates are the coordinates composed of the average of the abscissa and ordinate of all feature points of the edge contour of the opening. The coordinates are initially two-dimensional coordinates, containing only the x-axis coordinate and the y-axis coordinate (coordinates in the horizontal plane), and are used to characterize the geometric center position of the top opening of the TSV via on the wafer surface.

[0101] Optionally, the chip inspection device converts the geometric center coordinates of the top opening of the TSV via into coordinates in the preset three-dimensional space. The conversion process is as follows: retain the original x-axis and y-axis coordinates of the geometric center coordinates of the top opening of the TSV via, and supplement the z-axis coordinate value of the geometric center coordinates. Since the top opening of the TSV via is located on the wafer surface of the first stack, and the wafer surface is the xy plane of the three-dimensional coordinate system (the z-axis coordinate value is 0 micrometers), the z-axis coordinate value of the geometric center coordinates is set to 0 micrometers.

[0102] Furthermore, the chip inspection device obtains coordinate points containing three-dimensional coordinate information (x-axis coordinate, y-axis coordinate, z-axis coordinate), which are the reference three-dimensional coordinates of the top structure of the TSV via. The reference three-dimensional coordinates of the top structure are used to characterize the geometric center position of the top opening of the TSV via in three-dimensional space.

[0103] Step 303: Based on the three-dimensional coordinates of the top functional endpoint and the three-dimensional coordinates of the top structural reference, determine whether the distance between the two on the horizontal plane is less than the preset process tolerance threshold, and obtain the process tolerance result.

[0104] Optionally, the lateral plane is a plane parallel to the surface of the first stacked wafer, i.e., the xy plane in the three-dimensional coordinate system. The distance on the lateral plane is the horizontal distance between two coordinate points in the xy plane, excluding the distance in the depth direction (z-axis direction). This distance is used to characterize the degree of offset between the two reference coordinates on the lateral plane. The chip inspection device calculates the distance between the three-dimensional coordinates of the top functional endpoint and the three-dimensional coordinates of the top structural reference on the lateral plane. The calculation algorithm of this embodiment is as follows: First, extract the x-axis coordinates and y-axis coordinates of the two three-dimensional coordinates, and denot them as the x1 coordinate and y1 coordinate of the top functional endpoint, and the x2 coordinate and y2 coordinate of the top structural reference, respectively.

[0105] Secondly, calculate the difference between the two coordinate points along the x-axis, i.e., x-axis difference = |x2 coordinate - x1 coordinate|. Calculate the difference between the two coordinate points along the y-axis, i.e., y-axis difference = |y2 coordinate - y1 coordinate|. Finally, calculate the horizontal distance on the horizontal plane using the Pythagorean theorem.

[0106] The preset process tolerance threshold is a critical distance value used to determine whether the offset of two reference coordinates in the transverse plane is within a reasonable process range. This threshold is determined based on the design process requirements of 3D stacking, the size of TSV vias, and the requirements for interlayer alignment accuracy. It is usually controlled within the range of 0.01 micrometers to 0.1 micrometers. The preset process tolerance threshold is a reasonable deviation range set in the industry based on process feasibility and electrical performance requirements to ensure that the construction of the reference axis not only conforms to the actual process but also meets the electrical connection requirements.

[0107] The chip testing device compares the calculated distance on the horizontal plane with the preset process tolerance threshold, determines the relationship between the two, and obtains the process tolerance result.

[0108] The process tolerance results are divided into two cases: the first case is that the distance on the horizontal plane is less than the preset process tolerance threshold, indicating that the offset of the two reference coordinates on the horizontal plane is within the reasonable process range and meets the design requirements; the second case is that the distance on the horizontal plane is greater than or equal to the preset process tolerance threshold, indicating that the offset of the two reference coordinates on the horizontal plane exceeds the reasonable process range and does not meet the design requirements.

[0109] Step 304: Construct a reference axis based on the process tolerance results.

[0110] Optionally, the chip inspection device constructs a reference axis based on the process tolerance results, as described in steps 3041 to 3043.

[0111] The embodiments of the present invention achieve precise construction of a reference axis that takes into account both the effective conductive structure inside the TSV via and the position of the top opening, thus locking in the actual electrical connection function, improving the reliability and accuracy of the reference axis, and thereby improving the robustness of 3D stack alignment detection.

[0112] Optionally, the processes of steps 3041 to 3043 include: Step 3041: If the process tolerance result is less than the preset process tolerance threshold, then the top functional endpoint is determined as the top fusion reference point.

[0113] Optionally, if the process tolerance result clearly indicates that the distance on the aforementioned transverse plane is less than the preset process tolerance threshold, it means that the offset of the top functional endpoint of the effective conductive axis and the geometric center of the top opening of the TSV via on the transverse plane is within a reasonable process range. The positional deviation between the two will not affect the reference accuracy of the reference axis, nor will it have an adverse effect on the calculation of the subsequent 3D stacking alignment deviation.

[0114] In this case, the chip testing device directly determines the top functional endpoint of the effective conductive axis as the top fusion reference point. The top fusion reference point is the core starting reference point for the construction of the reference axis, used to fuse the functional characteristics of the effective conductive axis (fitting the actual electrical connection requirements) with the structural characteristics of the top opening of the TSV via (fitting the top structural position). Since the offset between the two reference points is reasonable at this time, no additional fusion correction is required. The top functional endpoint is directly used as the top fusion reference point, which ensures the consistency between the reference point and the actual electrical connection function, while also taking into account the rationality of the process.

[0115] Step 3042: If the process tolerance result indicates that it is greater than or equal to the preset process tolerance threshold, then based on the actual positional relationship between the three-dimensional coordinates of the top functional endpoint and the three-dimensional coordinates of the top structural reference on the horizontal plane, a top associated line segment is constructed with the top structural reference point as the starting point and the top functional endpoint as the ending point. A top fusion reference point is generated based on the midpoint coordinates of the top associated line segment and its corresponding depth value.

[0116] Optionally, if the process tolerance result clearly indicates that the distance between the three-dimensional coordinates of the top functional endpoint and the three-dimensional coordinates of the top structural reference in the horizontal plane is greater than or equal to the preset process tolerance threshold, it indicates that the offset of the two reference coordinates in the horizontal plane exceeds the reasonable process range. If a single reference point is used directly to construct the reference axis, it will result in an excessive reference axis deviation, affecting the accuracy of subsequent alignment deviation calculation. Therefore, it is necessary to fuse the two reference points to generate a reasonable top fused reference point.

[0117] Furthermore, the chip inspection device analyzes the actual positional relationship of the two reference coordinates on the horizontal plane. The actual positional relationship is the relative offset direction and offset distance of the two coordinate points in the xy plane. The offset direction is determined by the difference between the x-axis and y-axis coordinates of the two coordinate points, and the offset distance is the horizontal distance on the horizontal plane calculated in step 303. Further, based on the above actual positional relationship, the chip inspection device constructs a top-connecting line segment, starting from the top structural reference point (i.e., the coordinate point corresponding to the three-dimensional coordinates of the top structural reference) and ending at the top functional endpoint (i.e., the coordinate point corresponding to the three-dimensional coordinates of the top functional endpoint). The top-connecting line segment is a line segment connecting the two reference points and located above the top plane of the TSV via. The top plane of the TSV via is the plane where the top opening of the TSV via is located, i.e., the xy plane in the three-dimensional coordinate system (z-axis coordinate value is 0 micrometers). The top-connecting line segment lies entirely on this plane, ensuring that the line segment can truly reflect the relative positional relationship of the two reference points on the top plane. The length of the line segment is the offset distance of the two reference points on the horizontal plane, and the direction of the line segment is the offset direction.

[0118] Furthermore, after the top associated line segment is constructed, the chip detection device calculates the midpoint coordinates of the line segment. The midpoint coordinates are the coordinates corresponding to the geometric center of the top associated line segment. The calculation algorithm is as follows: extract the x-axis and y-axis coordinates of the starting point (top structural reference point) and the ending point (top functional endpoint) of the top associated line segment; calculate the arithmetic mean of the x-axis coordinates and the arithmetic mean of the y-axis coordinates respectively, that is, the midpoint x-axis coordinate = (starting point x-axis coordinate + ending point x-axis coordinate) / 2, the midpoint y-axis coordinate = (starting point y-axis coordinate + ending point y-axis coordinate) / 2; since the top associated line segment is located on the top plane of the TSV via, the z-axis coordinate value of the midpoint is consistent with the z-axis coordinate values ​​of the starting point and the ending point, which are both 0 micrometers. Thus, the midpoint coordinates (three-dimensional coordinates) of the top associated line segment are obtained.

[0119] Furthermore, the chip inspection device extracts the depth value corresponding to the midpoint coordinates. The depth value is the z-axis coordinate value (0 micrometers) of the midpoint coordinates. Then, based on the midpoint coordinates and the corresponding depth value, a top fusion reference point is generated. The top fusion reference point is the starting reference point after fusion correction. Its position is between the top structural reference point and the top functional endpoint, which can simultaneously take into account the structural position of the TSV via top opening and the functional position of the effective conductive axis, correcting the problem of excessive offset between the two reference points.

[0120] Step 3043: Construct a reference axis based on the top fusion reference point.

[0121] Optionally, the chip detection device constructs a reference axis based on the top fusion reference point, as described in steps 30431 to 30433.

[0122] The embodiments of the present invention avoid the drawbacks of relying solely on the geometric center of the surface opening (which is susceptible to surface defects) or relying solely on the top endpoint of the internal effective conductive axis (which is susceptible to reference deviation due to process offset). Furthermore, through process tolerance adaptation processing, it ensures that the construction of the reference axis meets the design process requirements of 3D stacking, thereby improving the reliability of the reference axis and thus enhancing the robustness of 3D stacking alignment and detection.

[0123] Optionally, the processes of steps 30431 to 30433 include: Step 30431: Based on the spatial coordinate points of the effective conductive axis excluding the top functional endpoint, construct a spatial point sequence with the top fusion reference point to obtain the axis point set extending downward along the effective conductive axis with the top fusion reference point as the starting point.

[0124] Optionally, the chip inspection device filters the set of spatial coordinate points of the effective conductive axis, filtering out all spatial coordinate points except for the top functional endpoint. The top functional endpoint is the spatial coordinate point with the smallest depth value on the effective conductive axis, that is, the coordinate point on the effective conductive axis closest to the top of the TSV via, which has been determined in step 301. The purpose of this filtering is to remove the top functional endpoint to avoid it from repeating with the top fusion reference point or interfering with the construction of subsequent axis point sets, ensuring that the axis point set takes the top fusion reference point as the unique starting point.

[0125] Furthermore, after screening, the chip detection device integrates the top fusion reference point with the spatial coordinates of the effective conductive axis obtained after screening to construct a spatial point sequence.

[0126] Optionally, the integration process in this embodiment of the invention is as follows: The top fusion reference point is used as the first point in the spatial point sequence. Subsequently, the spatial coordinate points of the selected effective conductive axes are arranged sequentially after the top fusion reference point according to their depth values ​​in ascending order (i.e., from the top to the bottom of the TSV via), forming a complete spatial point sequence. This spatial point sequence is the set of axis points extending downwards along the effective conductive axes, starting from the top fusion reference point. The axis point set is the basic set of points constructed from the reference axes. Its starting point is the top fusion reference point, and all subsequent points come from the effective conductive axes. This ensures that the axis point set not only takes into account the structural position of the TSV via's top opening and its internal effective conductive function, but also accurately reflects the spatial distribution of the effective conductive area along the extension direction of the effective conductive axes in the depth direction of the TSV via.

[0127] Step 30432: Based on the points in the axis point set, adjacent points are connected sequentially in ascending depth order to obtain a continuous polygonal path extending from the top to the bottom of the TSV via. The continuous polygonal path reflects the spatial trajectory of the coordinated characteristics of the structural opening center and the internal electrical conduction area.

[0128] Optionally, the chip testing device sorts and verifies the spatial coordinate points in the axis point set to ensure that all points are arranged strictly in ascending order of depth value. As the depth value increases, the z-axis coordinate value gradually increases from the minimum. This prevents the subsequently constructed path from deviating from the extension direction of the effective conductive axis due to incorrect point arrangement, thus affecting the accuracy of the reference axis. After sorting and verification, if any missorted points are found, the chip testing device adjusts them to the correct position to ensure the accuracy of the axis point set's sorting.

[0129] Furthermore, after verification, the chip detection device connects adjacent points in the axis point set sequentially according to the increasing depth value. That is, the first point (top fusion reference point) connects to the second point, the second point to the third point, and so on, until it connects to the last point in the axis point set, forming a continuous polygonal path extending from the top to the bottom of the TSV via. This continuous polygonal path is formed by connecting multiple line segments sequentially. Each line segment connects two adjacent spatial coordinate points in the axis point set. The extension direction of the polygonal path is consistent with the extension direction of the effective conductive axis, accurately conforming to the spatial trajectory of the effective conductive axis. The continuous polygonal path reflects the spatial trajectory of the coordinated characteristics of the structural opening center and the internal electrical conduction area. The characteristics of the structural opening center are reflected by the top fusion reference point (which fuses the structural reference of the TSV via top opening), while the characteristics of the internal electrical conduction area are reflected by subsequent points in the axis point set (all subsequent points are from the effective conductive axis, representing the internal effective conductive area). The coordinated characteristics of these two aspects represent the dual characteristics of the reference axis, which must consider both structural position and electrical function.

[0130] Step 30433: Based on the spatial trajectory and depth value range corresponding to the continuous polyline path, limit it to the actual physical depth range of the TSV through hole to obtain the reference axis.

[0131] Optionally, the chip inspection device extracts the spatial trajectory and depth range corresponding to the continuous polyline path. The spatial trajectory is the extension trajectory of the continuous polyline path in three-dimensional space, and the depth range is the range of z-axis coordinate values ​​of all points on the continuous polyline path, that is, from the z-axis coordinate value (0 micrometers) of the top fusion reference point to the z-axis coordinate value of the last point in the axis point set. The chip inspection device compares the depth range of the continuous polyline path with the actual physical depth range of the TSV via to determine whether the depth range of the continuous polyline path is completely within the actual physical depth range of the TSV via.

[0132] If the depth value range of a continuous polyline path exceeds the actual physical depth range, the chip detection device performs a trimming process on the continuous polyline path, cutting off the part that exceeds the actual physical depth range and retaining the polyline part that is within the actual physical depth range; if the depth value range of a continuous polyline path is completely within the actual physical depth range, no trimming process is required, and the continuous polyline path is directly retained.

[0133] Therefore, after the range is defined (trimmed or directly retained), the resulting continuous broken-line path is the reference axis. Thus, the reference axis of this embodiment is completely located within the actual physical depth range of the TSV via, inheriting the synergistic characteristics of the structural opening center and the internal electrical conduction area reflected by the continuous broken-line path, and conforming to the actual physical structure of the TSV via.

[0134] The embodiments of the present invention improve the accuracy and reliability of the reference axis by constructing point sets, connecting paths, and defining ranges, ensuring that the reference axis can truly reflect the structural and electrical synergistic characteristics of the TSV via, thereby improving the robustness of 3D stack alignment detection.

[0135] Furthermore, the 3D stack alignment and detection device based on TSV vias provided by the present invention will be described below. The 3D stack alignment and detection device based on TSV vias described below can be referred to in correspondence with the 3D stack alignment and detection method based on TSV vias described above.

[0136] Optional, refer to Figure 2 , Figure 2 This is a schematic diagram of the 3D stack alignment and inspection device based on TSV vias provided by the present invention. The 3D stack alignment and inspection device based on TSV vias includes: The via processing module 210 is used to use a focused ion beam to etch each TSV via on the first stack layer by layer in a direction perpendicular to the wafer surface to obtain a cross-sectional sample, and to use a scanning electron microscope to perform high-resolution imaging of the TSV via sidewalls based on the cross-sectional sample to obtain a sidewall image. The response spectrum construction module 220 is used to measure the longitudinal continuity distribution of the conductive filling material in the TSV via through the electron beam induced current effect based on the sidewall image, and obtain the current response spectrum. The axis construction module 230 is used to determine the effective conductive axis of the TSV via in the depth direction based on the position information of the depth range where the current intensity is higher than the preset intensity threshold in the current response spectrum, and to construct a reference axis based on the effective conductive axis and the geometric center coordinates of the top opening of the TSV via. The alignment detection module 240 is used to calculate the spatial offset vector of the corresponding TSV via reference axis between the two stacks based on the reference axis of the corresponding TSV via on the second stack, so as to obtain the alignment deviation of the 3D stack.

[0137] The embodiments of the present invention fundamentally avoid alignment errors caused by distortion of surface reflection characteristics, and improve the robustness of alignment detection of 3D stacking under complex process conditions.

[0138] Please see Figure 3 , Figure 3 An embodiment diagram of an electronic device provided in accordance with the present invention. For example... Figure 3 As shown, an embodiment of the present invention provides an electronic device 300, including a memory 310, a processor 320, and a computer program 311 stored in the memory 310 and executable on the processor 320. When the processor 320 executes the computer program 311, it implements the processes of steps 10 to 40.

[0139] Please see Figure 4 , Figure 4 An embodiment diagram of a computer-readable storage medium provided in accordance with an embodiment of the present invention is shown. Figure 4 As shown, this embodiment provides a computer-readable storage medium 400 on which a computer program 311 is stored. When the computer program 311 is executed by a processor, it implements the processes of steps 10 to 40.

[0140] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer is able to execute the 3D stack alignment detection method based on TSV vias provided by the above methods, which includes steps 10 to 40.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A 3D stack alignment detection method based on TSV vias, characterized in that, The 3D laminate to be inspected includes a first layer and a second layer, each layer containing multiple TSV vias arranged in a regular pattern; the 3D laminate alignment inspection method includes: Each TSV via on the first stack is etched layer by layer using a focused ion beam along a direction perpendicular to the wafer surface to obtain a cross-sectional sample. Based on the cross-sectional sample, a scanning electron microscope is used to perform high-resolution imaging of the TSV via sidewalls to obtain a sidewall image. Based on the sidewall image, the longitudinal continuity distribution of the conductive filling material in the TSV via is measured by electron beam induced current effect to obtain the current response spectrum; Based on the location information of the depth range where the current intensity is higher than the preset intensity threshold in the current response spectrum, the effective conductive axis of the TSV via in the depth direction is determined, and a reference axis is constructed based on the effective conductive axis and the geometric center coordinates of the top opening of the TSV via. Based on the reference axis of the corresponding TSV via on the second stack, the spatial offset vector of the reference axis of the corresponding TSV via between the two stacks is calculated to obtain the alignment deviation of the 3D stack.

2. The 3D stack alignment detection method based on TSV vias according to claim 1, characterized in that, The steps for determining the current response spectrum include: Based on the geometric boundary information of the TSV via along the depth direction in the sidewall image, the start and end positions of the electron beam scanning path in the direction perpendicular to the wafer surface are determined. Based on the start position and the end position, an electron beam point-by-point scanning sequence covering the entire TSV via depth range is determined; Based on the electron beam point-by-point scanning sequence, a focused electron beam is applied to the TSV through-hole cross-section sample in a scanning electron microscope to collect the current signal induced by the electron beam and obtain the original electron beam induced current value corresponding to each scanning point. The current response spectrum is obtained based on the original electron beam induced current value and its corresponding depth coordinate position, combined with the longitudinal continuity distribution of the conductive filling material in the TSV via.

3. The 3D stack alignment and detection method based on TSV vias according to claim 2, characterized in that, The current response spectrum is obtained by combining the original electron beam induced current value and its corresponding depth coordinate position with the longitudinal continuity distribution of the conductive filling material in the TSV via, including: Based on the original electron beam induced current value and its corresponding depth coordinate position, the current signal is arranged in depth order to obtain a one-dimensional current intensity sequence distributed along the TSV through-hole axis. Based on the current change trend between adjacent depth points in the one-dimensional current intensity sequence, the depth range where the current intensity jump amplitude is greater than a preset amplitude threshold is identified, and a set of critical depth positions characterizing the existence of electrical connections or disconnections inside the conductive filling material is obtained. Based on the current intensity values ​​at each location in the set of critical depth locations, it is determined whether the conductive filling material has an effective current-carrying capacity at the corresponding depth, and the continuity state of the conductive path inside the TSV via in the depth direction is obtained. The current response spectrum is constructed based on the continuous state.

4. The 3D stack alignment and detection method based on TSV vias according to claim 3, characterized in that, The construction of the current response spectrum based on the continuous state includes: Obtain the conductive path connectivity interval of the continuity state indication; Extract all continuous depth segments in the connected region of the conductive path where the current intensity is higher than a preset intensity threshold to obtain a set of longitudinal conductive regions with effective current conduction capability within the TSV via. The center depth position of the conductive region is calculated based on the depth start position and depth end position of each conductive region in the set of longitudinal conductive regions, resulting in multiple center depth positions arranged in depth order; Based on whether the current intensity of multiple center depth locations and their corresponding conductive regions is higher than a preset intensity threshold, each center depth location is mapped to an effective conductive feature point in the current response spectrum. With depth coordinates as the horizontal axis and current intensity as the vertical axis, all effective conductive feature points are connected to form a continuous or segmented current response curve, thus obtaining the current response spectrum.

5. The 3D stack alignment detection method based on TSV vias according to claim 1, characterized in that, The construction of a reference axis based on the effective conductive axis and the geometric center coordinates of the top opening of the TSV via includes: Based on the spatial coordinate point with the smallest depth value in the set of spatial coordinate points continuously distributed along the depth direction of the effective conductive axis, the three-dimensional coordinates of the top functional endpoint of the effective conductive axis are determined. Based on the geometric center coordinates of the top opening of the TSV through hole, its coordinate representation in the preset three-dimensional space is obtained, and the reference three-dimensional coordinates of the top structure of the TSV through hole are obtained. Based on the three-dimensional coordinates of the top functional endpoint and the three-dimensional coordinates of the top structural reference, determine whether the distance between the two on the horizontal plane is less than a preset process tolerance threshold, and obtain the process tolerance result. The reference axis is constructed based on the process tolerance results.

6. The 3D stack alignment detection method based on TSV vias according to claim 5, characterized in that, The construction of the reference axis based on the process tolerance results includes: If the process tolerance result is less than the preset process tolerance threshold, then the top functional endpoint is determined as the top fusion reference point; If the process tolerance result indicates that it is greater than or equal to the preset process tolerance threshold, then based on the actual positional relationship between the three-dimensional coordinates of the top functional endpoint and the three-dimensional coordinates of the top structural reference on the horizontal plane, a top associated line segment is constructed with the top structural reference point as the starting point and the top functional endpoint as the ending point; a top fusion reference point is generated based on the midpoint coordinates of the top associated line segment and its corresponding depth value. The reference axis is constructed based on the top fusion reference point.

7. The 3D stack alignment detection method based on TSV vias according to claim 6, characterized in that, The construction of the reference axis based on the top fusion reference point includes: Based on the spatial coordinates of the effective conductive axis except for the top functional endpoint, a spatial point sequence is constructed with the top fusion reference point to obtain a set of axis points extending downward along the effective conductive axis with the top fusion reference point as the starting point; Based on the points in the set of axis points, adjacent points are connected in ascending order of depth to obtain a continuous broken line path extending from the top to the bottom of the TSV through hole; the continuous broken line path reflects the spatial trajectory of the coordinated characteristics of the structural opening center and the internal electrical conduction area. Based on the spatial trajectory and depth range corresponding to the continuous polygonal path, it is limited to the actual physical depth range of the TSV through hole to obtain the reference axis.

8. A 3D stack alignment and inspection device based on TSV through-holes, characterized in that, The method is applied to the 3D stack alignment and detection method based on TSV vias as described in any one of claims 1 to 7; the 3D stack to be detected includes a first stack and a second stack, each of which contains a plurality of TSV vias arranged in a regular manner. The 3D stack alignment and detection device includes: The via processing module is used to use a focused ion beam to etch each TSV via on the first stack layer by layer in a direction perpendicular to the wafer surface to obtain a cross-sectional sample, and to use a scanning electron microscope to perform high-resolution imaging of the TSV via sidewalls based on the cross-sectional sample to obtain a sidewall image. The response spectrum construction module is used to measure the longitudinal continuity distribution of the conductive filling material in the TSV via through the electron beam induced current effect based on the sidewall image, and obtain the current response spectrum. The axis construction module is used to determine the effective conductive axis of the TSV via in the depth direction based on the position information of the depth range where the current intensity is higher than the preset intensity threshold in the current response spectrum, and to construct a reference axis based on the effective conductive axis and the geometric center coordinates of the top opening of the TSV via. The alignment detection module is used to calculate the spatial offset vector of the corresponding TSV via reference axis between the two stacks based on the reference axis of the corresponding TSV via on the second stack, so as to obtain the alignment deviation of the 3D stack.

9. An electronic device, comprising: Memory, used to store computer software programs; A processor for reading and executing the computer software program, characterized in that, when the processor executes the computer software program, it implements the 3D stack alignment detection method based on TSV vias as described in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium, wherein a computer software program is stored therein, characterized in that, When the computer software program is executed by the processor, it implements the 3D stack alignment and detection method based on TSV vias as described in any one of claims 1 to 7.

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