Semiconductor devices and semiconductor packages including the semiconductor devices

Abstract

A semiconductor device and a semiconductor package are disclosed. Some example embodiments of the semiconductor device include: a first substrate having a first surface and a second surface facing each other; a logic block on the first surface; a power transmission network on the second surface, the power transmission network including a plurality of back lines connected to the logic block; a second substrate on the logic block and opposite to the first surface of the first substrate; a first through-structure penetrating the first substrate; and a second through-structure penetrating the second substrate and electrically connected to the first through-structure. The first through-structure includes: a through conductive pattern horizontally spaced from the logic block and penetrating the first substrate; a plurality of upper conductive patterns stacked on the top surface of the through conductive pattern; and a plurality of lower conductive patterns stacked on the bottom surface of the through conductive pattern.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0164433, filed on November 18, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present invention relate to a semiconductor device and a semiconductor package including the semiconductor device. Background Technology

[0004] Semiconductor devices can include integrated circuits composed of metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices continue to shrink, the size of MOSFETs can also shrink. However, shrinking MOSFETs can degrade the operating characteristics of semiconductor devices. Therefore, research is ongoing to fabricate semiconductor devices with superior performance while overcoming the limitations that may arise from the higher integration density of semiconductor devices.

[0005] Furthermore, with the active development of three-dimensional semiconductor packages that include multiple semiconductor chips mounted in a single semiconductor package, it may be necessary to ensure the electrical and / or mechanical stability of the vertically penetrating substrate or die to form electrically coupled connection structures. Summary of the Invention

[0006] Some exemplary embodiments of the present invention provide a semiconductor device including an electrical path structure electrically connecting the top and bottom ends of the semiconductor device. This semiconductor device can be included in a semiconductor package and can achieve improved space optimization and / or improved thermal radiation performance.

[0007] The exemplary embodiments of the present invention are not limited to the above disclosure, and those skilled in the art will clearly understand from the following description other objectives not mentioned above.

[0008] According to some exemplary embodiments of the present invention, a semiconductor device may include: a first substrate having a first surface and a second surface facing each other; a logic block on the first surface of the first substrate; a power transmission network on the second surface of the first substrate, and the power transmission network including a plurality of back lines connected to the logic block; a second substrate on the logic block and opposite to the first surface of the first substrate; a first through structure penetrating the first substrate; and a second through structure penetrating the second substrate, and the second through structure being electrically connected to the first through structure. The first through structure includes: a through conductive pattern horizontally spaced from the logic block and penetrating the first substrate; a plurality of upper conductive patterns stacked on the top surface of the through conductive pattern; and a plurality of lower conductive patterns stacked on the bottom surface of the through conductive pattern.

[0009] According to some exemplary embodiments of the present invention, a semiconductor device may include: a first substrate having a first surface and a second surface facing each other; a logic block on the first surface of the first substrate; a plurality of top lines on the first surface of the first substrate and connected to the logic block; a power transmission network on the second surface of the first substrate, and the power transmission network including a plurality of back lines connected to the logic block; a second substrate on the logic block and opposite to the first surface of the first substrate; and a connection structure penetrating the first substrate and the second substrate. The connection structure includes: a through-conductive pattern penetrating the first substrate and horizontally spaced from the logic block; and an upper through-structure penetrating the second substrate and electrically connected to the through-conductive pattern. The bottom surface of the upper through-structure is located at a level lower than the level of the top surface of the uppermost of the plurality of top lines.

[0010] According to some exemplary embodiments of the present invention, a semiconductor package may include: a redistribution substrate; a first semiconductor chip on the redistribution substrate; and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes: a logic block on a first surface of the first substrate; an upper line on the first surface of the first substrate and connected to the logic block; a power transmission network on a second surface of the first substrate, and the power transmission network includes a plurality of power lines connected to the logic block; a second substrate on the logic block and opposite to the first surface of the first substrate; and a connection structure penetrating the first and second substrates. The connection structure includes: a first through-structure penetrating the first substrate; and a second through-structure penetrating the second substrate, and the second through-structure being electrically connected to the first through-structure. The first through-structure includes: a through conductive pattern penetrating the first substrate and horizontally spaced from the logic block; a plurality of upper conductive patterns on the first surface of the first substrate, and the plurality of upper conductive patterns stacked on the top surface of the through conductive pattern; and a plurality of lower conductive patterns on the second surface of the first substrate, and the plurality of lower conductive patterns stacked on the bottom surface of the through conductive pattern.

[0011] According to some exemplary embodiments of the present invention, a method of manufacturing a semiconductor device may include: forming a first active pattern on a first surface of a first substrate; forming a second active pattern on the first surface of the first substrate; forming a device isolation layer between the first active pattern and the second active pattern; forming a gate electrode and an active contact on the first active pattern and the second active pattern; forming a first interlayer dielectric layer surrounding the first active pattern and the second active pattern; forming a second interlayer dielectric layer on the first interlayer dielectric layer; forming an upper line in a third interlayer dielectric layer on the second interlayer dielectric layer; and forming a device isolation layer between the first and second active patterns. The process involves: forming an upper conductive pattern and an upper conductive via; forming a trench on a second substrate, the trench including a sacrificial pattern filling the trench; attaching the second substrate to a third interlayer dielectric layer of a first substrate; performing a thinning process on a second surface of the first substrate; forming a replacement dielectric substrate on the second surface of the first substrate; forming a via exposing one or more active contacts in the replacement dielectric substrate; forming a back contact in the via; forming a through conductive pattern penetrating the replacement dielectric substrate; forming a power transmission network on the replacement dielectric substrate that contacts the back contact; and forming a lower conductive pattern and a lower conductive via on the through conductive pattern.

[0012] According to some exemplary embodiments of the present invention, the thermal conductivity of the second substrate is greater than that of the third interlayer dielectric layer. Attached Figure Description

[0013] Figure 1 A cross-sectional view of a semiconductor package including a semiconductor device is shown, illustrating some example embodiments of the concept according to the present invention.

[0014] Figure 2 A simplified plan view of a semiconductor device illustrating some example embodiments of the concept according to the present invention is shown.

[0015] Figure 3 It shows Figure 2 A cross-sectional view of part P1 in the diagram.

[0016] Figure 4 It shows along Figure 3 The cross-sectional view taken by line A-A' in the figure partially illustrates a semiconductor device according to some exemplary embodiments of the concept of the present invention.

[0017] Figures 5A to 5D It shows the relationship with Figure 4 Correspondingly, and in part, cross-sectional views of semiconductor devices according to some exemplary embodiments of the present invention are shown.

[0018] Figure 6 A simplified plan view of a logic block disposed on a semiconductor device, illustrating some example embodiments of the concept according to the present invention, is shown.

[0019] Figure 7 A plan view of a semiconductor device, partially illustrating some example embodiments of the concept according to the present invention, is shown.

[0020] Figure 8 It shows along Figure 7 The cross-sectional view taken by line I-I' in the figure illustrates a semiconductor device according to some exemplary embodiments of the concept of the present invention.

[0021] Figure 9 A cross-sectional view of a semiconductor package including a semiconductor device is shown, illustrating some example embodiments of the concept according to the present invention.

[0022] Figures 10 to 12E A cross-sectional view is shown illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the concept of the present invention.

[0023] Figures 13A to 13D A cross-sectional view is shown illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the concept of the present invention. Detailed Implementation

[0024] In the following discussion, semiconductor devices and semiconductor packages including the semiconductor devices according to some exemplary embodiments of the present invention will be discussed in conjunction with the accompanying drawings.

[0025] Figure 1 A cross-sectional view of a semiconductor package including a semiconductor device is shown, illustrating some example embodiments of the concept according to the present invention.

[0026] Reference Figure 1 The semiconductor package may include a first redistribution substrate 1000, a first semiconductor device 1100, and a second semiconductor device 1200.

[0027] The first redistribution substrate 1000 may include a lower bonding pad 1001 disposed on its bottom surface and an upper bonding pad 1003 disposed on its top surface. The first redistribution substrate 1000 may include a plurality of base dielectric layers and a plurality of redistribution patterns. The redistribution patterns may include conductive line patterns located on the base dielectric layers and conductive vias that vertically penetrate the base dielectric layers.

[0028] The first connection terminal 1050 may be attached to the lower bonding pad 1001 of the first redistribution substrate 1000. The first connection terminal 1050 may be at least one selected from solder balls, conductive bumps, and conductive pillars. The first connection terminal 1050 may include at least one selected from copper, tin, and lead. However, the exemplary embodiments are not limited thereto.

[0029] The semiconductor package can use the first connection terminal 1050 to send and receive signals with other external packages or other semiconductor devices. For example, power signals (or ground signals) for driving the first semiconductor device 1100 and the second semiconductor device 1200 can be received through at least one of the first connection terminals 1050 of the first redistribution substrate 1000.

[0030] The first semiconductor device 1100 may be mounted on the first redistribution substrate 1000. The first semiconductor device 1100 may be a logic chip including a processor (e.g., a microelectromechanical system (MEMS) device, an optoelectronic device, a central processing unit (CPU), a graphics processing unit (GPU), a mobile application, or a digital signal processor (DSP)). However, the example embodiments are not limited thereto.

[0031] The first semiconductor device 1100 may include a connection structure ICS connecting its top and bottom surfaces. Electrical signals can be supplied from the first redistribution substrate 1000 to the second semiconductor device 1200 via at least one connection structure ICS. The first semiconductor device 1100 may include a lower chip pad 1101 disposed on its bottom surface.

[0032] The second connection terminal 1150 may be disposed between the upper bonding pad 1003 of the first redistribution substrate 1000 and the lower chip pad 1101 of the first semiconductor device 1100. The second connection terminal 1150 may be a solder ball or bump formed of tin, lead or copper. For example, the second connection terminal 1150 may be smaller than the first connection terminal 1050.

[0033] The second semiconductor device 1200 may be mounted on the first semiconductor device 1100. The second semiconductor device 1200 may receive power and signals from the first redistribution substrate 1000 through the first semiconductor device 1100.

[0034] The second semiconductor device 1200 can be supplied with electrical voltage from the first redistribution substrate 1000 through one or more interconnect ICS in the first semiconductor device 1100, and can be supplied with ground voltage from the first redistribution substrate 1000 through another one or more interconnect ICS. In addition, the second semiconductor device 1200 can transmit and receive signals with the first semiconductor device 1100 through yet another one or more interconnect ICS in the first semiconductor device 1100.

[0035] The second semiconductor device 1200 may be a single chip or a stack of chips. The second semiconductor device 1200 may include a memory cell array, a column decoder, a row decoder, a sense amplifier, a write driver, and an input / output buffer. However, the example embodiments are not limited thereto.

[0036] The first semiconductor device 1100 and the second semiconductor device 1200 can be connected to each other via a third connection terminal 1250. The third connection terminal 1250 can electrically connect the connection structure ICS of the first semiconductor device 1100 to the lower chip pad 1201 of the second semiconductor device 1200. The third connection terminal 1250 can be a solder ball or bump formed of tin, lead, or copper. For example, the third connection terminal 1250 can be smaller than the second connection terminal 1150.

[0037] Figure 2 A simplified plan view of a semiconductor device illustrating some example embodiments of the concept according to the present invention is shown. Figure 3 It shows Figure 2 A cross-sectional view of part P1 in the diagram. Figure 4 It shows along Figure 3 The cross-sectional view taken by line A-A' in the figure partially illustrates a semiconductor device according to some exemplary embodiments of the concept of the present invention.

[0038] Reference Figure 2 and Figure 3 The first semiconductor device 1100 may include a central region R1 and an edge region R2 surrounding the central region R1. A logic block IP may be disposed on the central region R1 of the first semiconductor device 1100. An interconnect structure ICS may be disposed on the edge region R2 of the first semiconductor device 1100.

[0039] Logic block IPs can be arranged in a matrix. Logic block IPs can be referred to as function blocks, hard macros, or intellectual property (IP). Logic block IPs can refer to reusable blocks implemented with specific interconnections and fixed layouts to perform desired electrical functions. For example, logic block IPs may include macroblocks for data processing and / or computation, and storage blocks for data storage. Logic block IPs may include multiple standard cells or logic units. Standard cells can refer to logic devices that perform specific functions, such as AND, OR, XOR, XNOR, and inverters. However, the example embodiments are not limited to this. For example, a standard cell may include transistors constituting a logic device and wiring for connecting transistors to each other.

[0040] Reference Figure 3 and Figure 4 The first semiconductor device 1100 may include a first substrate 105, a logic block IP, a power transmission network (or power distribution network) PDN, a second substrate 200, and a connection structure ICS that vertically penetrates the first semiconductor device 1100.

[0041] The first substrate 105 may have a first surface 105a and a second surface 105b facing each other. The first substrate 105 may include a silicon-based dielectric layer. The first substrate 105 may be a semiconductor substrate or a dielectric substrate. For example, the first substrate 105 may include a silicon substrate, and as another example, the first substrate 105 may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. However, the exemplary embodiments are not limited thereto.

[0042] The first substrate 105 may have a device isolation layer STI defining an active region therein. The device isolation layer STI may be formed of a dielectric material (e.g., silicon oxide).

[0043] The logic block IP can be integrated on the first surface 105a of the first substrate 105. The logic block IP can be an AND, OR, NOR, inverter, or latch. In addition, the logic block IP can include field-effect transistors and resistors.

[0044] According to some example embodiments, the logic block IP may include a gate electrode GE disposed on a first surface 105a of a first substrate 105, and a source / drain pattern SD on the opposite side of each gate electrode GE and in the first substrate 105. An active contact AC may be electrically connected to the source / drain pattern SD.

[0045] On the first surface 105a of the first substrate 105, the upper line FM1 can be connected to the logic block IP. The upper line FM1 can be electrically connected to the gate electrode GE and the active contact AC via contact plugs. The upper line FM1 may include multiple metal lines stacked across the front interlayer dielectric layers FILD, and upper lines FM1 of different layers can be electrically connected via upper vias FV1. The upper line FM1 may include clock lines for transmitting clock signals and signal lines for transmitting general signals.

[0046] The interlayer dielectric layer (FILD) can be disposed on a first surface 105a of the first substrate 105. On the first surface 105a, the interlayer dielectric layer (FILD) can cover the logic block IP, the top line FM1, and the top via FV1. The interlayer dielectric layer (FILD) can include multiple dielectric layers, including at least one selected from silicon oxide, silicon nitride, and silicon oxynitride. However, the example embodiment is not limited thereto.

[0047] The second substrate 200 may be disposed on the first surface 105a of the first substrate 105. The second substrate 200 may be disposed on the logic block IP and the front interlayer dielectric layer FILD, and the bottom surface of the second substrate 200 may face the first surface 105a of the first substrate 105. For example, an adhesive layer (not shown) may be additionally disposed between the second substrate 200 and the front interlayer dielectric layer FILD. The second substrate 200 may be a semiconductor substrate (e.g., a silicon substrate) and may also include silicon carbide. However, the example embodiment is not limited thereto. The second substrate 200 may exhibit relatively superior thermal conductivity compared to the front interlayer dielectric layer FILD.

[0048] A power transmission network (PDN) may be disposed on a second surface 105b of a first substrate 105. The PDN may include multiple back lines BM1 spanning an inter-backside dielectric layer (BILD), with the BILD located between the multiple back lines BM1. Some of the back lines BM1 may be power lines transmitting power voltage or ground voltage. The BILD may include multiple dielectric layers, including at least one selected from, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0049] The power lines of the back line BM1 can be electrically connected to the source / drain pattern SD through the back contact BC penetrating the first substrate 105. The diameter of the back contact BC can be, for example, from about a few nanometers to a few micrometers. The vertical length of the back contact BC can be, for example, from about tens of nanometers to a few micrometers. Although not shown, a dielectric layer (not shown) can be disposed between the first substrate 105 and the sidewall of the back contact BC. The back line BM1 and the back contact BC can include metallic materials such as W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB. However, the exemplary embodiment is not limited thereto.

[0050] According to some example embodiments, the interconnect structure ICS can vertically penetrate the first substrate 105 and the second substrate 200. Each interconnect structure ICS may include a first through structure TS vertically penetrating the first substrate 105 and a second through structure 210 vertically penetrating the second substrate 200. The interconnect structure ICS may be configured to be horizontally spaced from the logic block IP. The interconnect structure ICS may include a first redistribution substrate (see...) Figure 1 1000 in the middle) is connected to the second semiconductor device (see Figure 1 (1200 in the first redistribution substrate). The interconnect structure ICS can transmit power voltage or ground voltage from the first redistribution substrate 1000 to the second semiconductor device 1200.

[0051] The first through-structure TS can extend vertically and penetrate the first substrate 105. The first through-structure TS may include a through conductive pattern BP, an upper conductive pattern FM2, and a lower conductive pattern BM2 penetrating the first substrate 105. The through conductive pattern BP, the upper conductive pattern FM2, and the lower conductive pattern BM2 can vertically overlap each other. The lowermost lower conductive pattern BM2 can be referred to as the lower chip pad 1101. The second connection terminal 1150 can be attached to the bottom surface of the lower chip pad 1101.

[0052] The upper conductive pattern FM2 can be vertically stacked on the top surface of the through conductive pattern BP. For example, the upper conductive pattern FM2 can vertically overlap with the through conductive pattern BP. The upper conductive pattern FM2 can be disposed on the first surface 105a of the first substrate 105. When viewed in a plan view, the upper conductive pattern FM2 can have a square shape, a rectangular shape, or a polygonal shape. The shape of the upper conductive pattern FM2 is not limited to these and can be varied to take into account the resistance of each pattern. For example, the bottommost upper conductive pattern FM2 can cover the top surface of the through conductive pattern BP. The number and stacking level of the upper conductive patterns FM2 can be varied.

[0053] Some upper conductive patterns FM2 may be located at substantially the same level as the upper line FM1 connected to the logic block IP. For example, the top surface of the lowermost upper conductive pattern FM2 may be substantially coplanar with the top surface of at least one upper line FM1. Some lower conductive patterns BM2 may be located at substantially the same level as the back line BM1 connected to the logic block IP. For example, the bottom surface of the uppermost lower conductive pattern BM2 may be substantially coplanar with the bottom surface of at least one back line BM1.

[0054] The lower conductive pattern BM2 can be vertically stacked on the bottom surface of the through conductive pattern BP. For example, the lower conductive pattern BM2 can vertically overlap with the through conductive pattern BP. The lower conductive pattern BM2 can be disposed on the second surface 105b of the first substrate 105. When viewed in a plan view, the lower conductive pattern BM2 can have a square shape, a rectangular shape, or a polygonal shape. The shape of the lower conductive pattern BM2 is not limited to these and can be varied to take into account the resistance of each pattern. For example, the uppermost lower conductive pattern BM2 can cover the bottom surface of the through conductive pattern BP. The number and stacking level of the lower conductive patterns BM2 can be varied.

[0055] The first through structure TS may further include an upper conductive via FV2 disposed between upper conductive patterns FM2 and a lower conductive via BV2 disposed between lower conductive patterns BM2. The upper conductive via FV2 may be disposed between vertically adjacent upper conductive patterns FM2, and may electrically connect adjacent upper conductive patterns FM2 to each other. The lower conductive via BV2 may be disposed between vertically adjacent lower conductive patterns BM2, and may electrically connect adjacent lower conductive patterns BM2 to each other.

[0056] The vertical length and diameter of the through-conductive pattern BP can be smaller than the vertical length and diameter of the second through-structure 210, which will be discussed below. The diameter (or horizontal width) of the through-conductive pattern BP can be, for example, from about tens of nanometers to tens of micrometers. The top surface of the through-conductive pattern BP can be higher than the first surface 105a of the first substrate 105. The through-conductive pattern BP can include a metallic material, such as W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB. However, the example embodiments are not limited thereto.

[0057] The second through-structure 210 can penetrate the second substrate 200. The second through-structure 210 can be disposed on the first through-structure TS and can be referred to as the upper through-structure. The second through-structure 210 can vertically overlap with the first through-structure TS. A third connection terminal 1250 can be attached to the second through-structure 210. The maximum width of each third connection terminal 1250 can be less than the maximum width of each second connection terminal 1150. The maximum widths of the second connection terminal 1150 and the third connection terminal 1250 can each represent widths in the horizontal direction. Although not shown, chip pads can be additionally disposed between the second through-structure 210 and the third connection terminal 1250.

[0058] A second through-structure 210 may be electrically connected to the first through-structure TS. The second through-structure 210 may vertically penetrate the second substrate 200. The diameter (or horizontal width) of the second through-structure 210 may be, for example, from about tens of nanometers to about several hundred micrometers. For example, when viewed in a planar view, the second through-structure 210 may have one of a circular shape and an elliptical shape, but the inventive concept is not limited thereto. When viewed in a plane, the second through-structure 210 may have a strip shape extending in one direction. The second through-structure 210 may include a metallic material, such as at least one selected from W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB. However, the exemplary embodiments are not limited thereto.

[0059] The second through-structure 210 can contact the first through-structure TS. For example, the second through-structure 210 can contact the uppermost upper conductive pattern FM2 in the upper conductive pattern FM2 of the first through-structure TS. The second through-structure 210 can be connected to the upper conductive pattern FM2 and the upper conductive via FV2 to achieve electrical connection with the through conductive pattern BP. Furthermore, the second through-structure 210 can be electrically connected to the lower conductive pattern BM2 on the bottom surface of the through conductive pattern BP. The second through-structure 210 and the first through-structure TS can be used to mount a first semiconductor chip (see...) Figure 1 The top and bottom ends of the first redistribution substrate 1000 are electrically connected, and the first redistribution substrate 1000 is connected to (reference 1100). Figure 1 The electrical path of the second semiconductor device 1200 (discussed) is electrically connected.

[0060] For example, when the through-structure is configured to penetrate the first substrate 105 and the second substrate 200, the front interlayer dielectric layer FILD, and the back interlayer dielectric layer BILD, the fabrication complexity may increase because a deeper recess may be required to form the through-structure. Furthermore, because the recess is formed with an aspect ratio equal to (or substantially equal to) or greater than a certain level due to the characteristics of recess formation, the through-structure can be formed with a large horizontal width. Therefore, a minimum gap may need to be provided between the through-structure and the logic block IP to reduce (and / or minimize) electrical interference between the through-structure and the logic block IP, potentially reducing the space utilization (or integration density) of the semiconductor chip.

[0061] In contrast, according to some exemplary embodiments of the present invention, since the first through-structure TS and the second through-structure 210 are formed and disposed separately, the difficulty of the etching process for forming the first through-structure TS and the second through-structure 210 can be reduced. Furthermore, since the horizontal width of the first through-structure TS is relatively smaller than the horizontal width of the through-structure explained in the above examples, the space utilization (integration density) of the semiconductor chip can be improved.

[0062] Furthermore, according to some exemplary embodiments of the present invention, heat generated during the operation of the semiconductor chip can be transferred to a second substrate 200, which may have a higher thermal conductivity than the semiconductor chip, and the heat can be dissipated outward through the sidewalls of the second substrate 200. In this sense, the semiconductor chip can improve its thermal radiation performance and can at least partially reduce and / or prevent performance degradation.

[0063] Figures 5A to 5D It shows the relationship with Figure 4Cross-sectional views of semiconductor devices according to some exemplary embodiments of the present invention are shown in correspondence and in part. For the sake of brevity, detailed descriptions of the same technical features as those of the semiconductor devices described above may be omitted, and only the differences will be described.

[0064] Reference Figure 5A The second through-structure 210 can extend vertically to partially penetrate the front interlayer dielectric layer (FILD). For example, the second through-structure 210 can penetrate the second substrate 200 and further penetrate a portion of the front interlayer dielectric layer (FILD). The vertical length of the second through-structure 210 can be greater than the vertical length of the second substrate 200. The second through-structure 210 can penetrate a portion of the front interlayer dielectric layer (FILD) and is electrically connected to the first through-structure TS.

[0065] The uppermost conductive pattern FM2 in the upper conductive pattern FM2 of the first through-structure TS can be located at a level lower than the top surface of the previous interlayer dielectric layer FILD. The uppermost conductive pattern FM2 in the upper conductive pattern FM2 can be directly connected to the second through-structure 210.

[0066] Reference Figure 5B The through-conductive pattern BP' can be configured to be directly connected to the second through structure 210. The through-conductive pattern BP' can extend vertically while penetrating the first substrate 105 and be directly connected to the second through structure 210. The bottom surface of the through-conductive pattern BP' can be located at a level substantially lower than the level of at least one of the back lines BM1.

[0067] The vertical length and diameter of the through-conductive pattern BP' can be greater than the vertical length and diameter of the back contact portion BC. Furthermore, the vertical length and diameter of the through-conductive pattern BP' can be smaller than the vertical length and diameter of the second through-structure 210. The diameter (or horizontal width) of the through-conductive pattern BP' can be, for example, from about tens of nanometers to tens of micrometers. The bottom surface of the through-conductive pattern BP' can be lower than the bottom surface of the back contact portion BC, and the top surface of the through-conductive pattern BP can be higher than the first surface 105a of the first substrate 105.

[0068] The lower chip pad 1101 can be disposed on the bottom end of the through conductive pattern BP'. The through conductive pattern BP' can be electrically connected to the lower chip pad 1101.

[0069] The second through-structure 210 can penetrate a portion of the front interlayer dielectric layer FILD and the second substrate 200. The bottom surface of the second through-structure 210 can be located at a level lower than the level of the top surface of the front interlayer dielectric layer FILD. Furthermore, the bottom surface of the second through-structure 210 can be located at a level lower than the level of the top surface of some of the upper lines FM1. For example, the bottom surface of the second through-structure 210 can be located at a level lower than the level of the top surface of the uppermost upper line FM1.

[0070] The bottom surface of the second through structure 210 may be located at a level higher than the level of the first surface 105a of the first substrate 105. For example, the second through structure 210 may be vertically spaced from the first substrate 105.

[0071] The second through structure 210, the through conductive pattern BP' and the lower chip pad 1101 can be electrically connected to each other and can be used as an electrical path to connect the top and bottom of the semiconductor chip.

[0072] Reference Figure 5C The second through structures 210L, 210Va, and 210Vb can be configured to be electrically connected to the first through structure TS. The second through structures 210L, 210Va, and 210Vb may include a first conductive via 210Va connected to the first through structure TS, and may also include a conductor 210L connected to the first conductive via 210Va and extending in a direction parallel to the bottom surface of the second substrate 200. The first conductive via 210Va may vertically overlap with the first through structure TS. For example, when viewed in a plan view, the first conductive via 210Va may have a circular or elliptical shape. For example, when viewed in a plan view, the conductor 210L may have a strip shape extending in one direction. The top surface of the conductor 210L may be coplanar (and / or substantially coplanar) with the top surface of the second substrate 200.

[0073] The second through-structures 210L, 210Va, and 210Vb may further include a second conductive via 210Vb connected to the wire 210L. The second conductive via 210Vb may be horizontally spaced from the first conductive via 210Va. For example, the second conductive via 210Vb may be electrically connected to the upper line FM1 connected to the logic block IP. The logic block IP may be electrically connected to a second semiconductor chip (see above) via the upper line FM1, the second conductive via 210Vb, and the wire 210L. Figure 1 (1200 in the middle).

[0074] Reference Figure 5DThe second redistribution substrate 300 may be disposed on the second through structure 210. The second redistribution substrate 300 may include multiple base dielectric layers 310 and multiple redistribution patterns 315 and 320. The redistribution patterns 315 and 320 may include redistribution pads 320 in the bottommost base dielectric layer 310. Although not shown, a third connection terminal (see...) Figure 4 The 1250 in the middle can be set on the second redistribution substrate 300.

[0075] The second through structure 210 can be electrically connected to the redistribution patterns 315 and 320 of the second redistribution substrate 300. The connection structure ICS can be connected from... Figure 1 The first redistribution substrate 1000 discussed herein receives power and signals, and can transmit power and signals to the second redistribution substrate 300 and the second semiconductor device 1200.

[0076] Figure 6 A simplified plan view is shown of a logic block disposed on a portion of a semiconductor device illustrating some example embodiments of the concept according to the present invention.

[0077] Reference Figure 6 The first substrate 105 may have a first lower electric field line VPR1, a second lower electric field line VPR2, and a third lower electric field line VPR3 disposed thereon. The second lower electric field line VPR2 may be disposed between the first lower electric field line VPR1 and the third lower electric field line VPR3.

[0078] The first substrate 105 of the logic block IP may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2.

[0079] The first NMOSFET region NR1 can be adjacent to the first lower electric field line VPR1. The second NMOSFET region NR2 can be adjacent to the third lower electric field line VPR3. The first PMOSFET region PR1 and the second PMOSFET region PR2 can be adjacent to the second lower electric field line VPR2. When viewed in a plan view, the second lower electric field line VPR2 can be positioned between the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0080] The first height HE can be defined as the length of the logic block IP in the first direction D1. The first height HE can be approximately twice the distance (e.g., pitch) between the first lower power line VPR1 and the second lower power line VPR2. The first PMOSFET region PR1 and the second PMOSFET region PR2 of the logic block IP can operate together as a single PMOSFET region.

[0081] Figure 7 A plan view of a semiconductor device, partially illustrating some example embodiments of the concept according to the present invention, is shown. Figure 8 It shows along Figure 7 The cross-sectional view taken by line I-I' in the figure illustrates a semiconductor device according to some exemplary embodiments of the concept of the present invention.

[0082] Reference Figures 6 to 8 The first substrate 105 may have logic transistors included in the logic block IP disposed thereon. The first substrate 105 may include a silicon-based dielectric layer. For example, the first substrate 105 may be a dielectric substrate. For example, the first substrate 105 may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. However, the example embodiments are not limited thereto.

[0083] The first substrate 105 may have a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. Each of the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 may extend along a second direction D2.

[0084] The first substrate 105 may have a first dielectric pattern and a second dielectric pattern (or active pattern) extending along the second direction D2 on its upper portion. The first dielectric pattern and the second dielectric pattern may be vertical protrusions of the first substrate 105. The first dielectric pattern may be disposed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The second dielectric pattern may be disposed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0085] The first channel pattern CH1 can be correspondingly disposed on the first PMOSFET region PR1 and the second PMOSFET region PR2, and the second channel pattern can be correspondingly disposed on the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0086] Each of the first channel pattern CH1 and the second channel pattern may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked in sequence. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in the vertical direction (or the third direction D3).

[0087] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). However, the exemplary embodiments are not limited thereto. For example, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include crystalline silicon. Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be a nanosheet.

[0088] The first source / drain pattern SD1 can be disposed on the opposite side of the first channel pattern CH1. The first source / drain pattern SD1 can be an impurity region having a first conductivity type (e.g., p-type). The first channel pattern CH1 can be located between a pair of first source / drain patterns SD1. For example, the pair of first source / drain patterns SD1 can be connected by stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3.

[0089] A second source / drain pattern (not shown) may be disposed on opposite sides of each second channel pattern disposed on the first NMOSFET region NR1 and the second NMOSFET region NR2. The second source / drain pattern may be an impurity region having a second conductivity type (e.g., n-type). A second channel pattern (not shown) may be situated between a pair of second source / drain patterns. For example, the pair of second source / drain patterns may be connected by stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3.

[0090] The first source / drain pattern SD1 can be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the top surface of each first source / drain pattern SD1 can be located at a level substantially the same as the top surface of the third semiconductor pattern SP3. Alternatively, the top surface of each first source / drain pattern SD1 can be higher than the top surface of the third semiconductor pattern SP3. Similarly, the second source / drain pattern can be an epitaxial pattern.

[0091] The first source / drain pattern SD1 may also include an n-type dopant (e.g., phosphorus, arsenic, or antimony). The first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) with a lattice constant greater than that of the semiconductor element in the first channel pattern CH1. Therefore, a pair of first source / drain patterns SD1 can provide compressive stress to the first channel pattern CH1 between them. The second source / drain patterns disposed on the first NMOSFET region NR1 and the second NMOSFET region NR2 may include the same semiconductor element as the second channel pattern (e.g., Si).

[0092] Each second source / drain pattern may include silicon (Si). The second source / drain pattern may also include an n-type dopant (e.g., phosphorus, arsenic, or antimony).

[0093] The gate electrode GE can be configured to extend along a first direction D1 while extending across the first channel pattern CH1 and the second channel pattern CH2. The gate electrode GE can be arranged at a first pitch in the second direction D2.

[0094] The gate electrode GE may include a first internal electrode PO1 between the first substrate 105 and the first semiconductor pattern SP1, a second internal electrode PO2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third internal electrode PO3 between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and an external electrode PO4 on the third semiconductor pattern SP3.

[0095] The gate electrode GE can be disposed on the top surface, bottom surface, and opposite sidewall of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. For example, the transistor according to some example embodiments can be a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET), wherein the gate electrode GE surrounds the channel in three dimensions.

[0096] The gate cleavage pattern CT can be configured to overlap with the gate electrode GE. The gate cleavage pattern CT may include a dielectric material, such as a silicon oxide layer, a silicon nitride layer, or a combination thereof.

[0097] The gate electrode GE can be divided in the first direction D1 by a gate dicing pattern CT. For example, the gate dicing pattern CT can divide a gate electrode GE extending in the first direction D1 into multiple gate electrodes GE.

[0098] A pair of gate spacers GS may be disposed on opposite sidewalls of the outer electrode PO4 of the gate electrode GE. The gate spacers GS may extend along the gate electrode GE in a first direction D1. The top surface of the gate spacers GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS may be coplanar (and / or substantially coplanar) with the top surface of the first interlayer dielectric layer 110, which will be discussed below. The gate spacers GS may comprise at least one selected from SiCN, SiCON, and SiN. Alternatively, each gate spacer GS may comprise a multilayer formed of at least two selected from SiCN, SiCON, and SiN. However, the exemplary embodiments are not limited thereto.

[0099] A gate cap pattern GP may be disposed on the gate electrode GE. The gate cap pattern GP may extend along the gate electrode GE in a first direction D1. The gate cap pattern GP may include a material having etch selectivity relative to the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, which will be discussed below. For example, the gate cap pattern GP may include at least one selected from SiON, SiCN, SiCON, and SiN. However, the exemplary embodiments are not limited thereto.

[0100] The gate dielectric layer GI may be located between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern (not shown). The gate dielectric layer GI may cover the top surface, bottom surface, and opposite sidewalls of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0101] The gate dielectric layer GI may include one or more of a silicon oxide layer, a silicon oxynitride layer, and a high-k dielectric layer. The high-k dielectric layer may include a high-k dielectric material with a dielectric constant greater than that of the silicon oxide layer. For example, the high-k dielectric material may include at least one selected from hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. However, the exemplary embodiments are not limited thereto.

[0102] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate dielectric layer GI and may be adjacent to the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. The thickness and composition of the first metal pattern can be adjusted to achieve the desired threshold voltage of the transistor. For example, the first internal electrode PO1, the second internal electrode PO2, and the third internal electrode PO3 of the gate electrode GE may be formed from the first metal pattern or the work function metal.

[0103] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). Furthermore, the first metal pattern may also include carbon (C). However, the example embodiments are not limited thereto. The first metal pattern may include multiple stacked work function metal layers.

[0104] The second metal pattern may include a metal with a resistance less than that of the first metal pattern. For example, the second metal pattern may include at least one metal selected from tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). However, the example embodiments are not limited thereto. For example, the external electrode PO4 of the gate electrode GE may include the first metal pattern and the second metal pattern on the first metal pattern.

[0105] A first interlayer dielectric layer 110 may be disposed on a first substrate 105. The first interlayer dielectric layer 110 may cover a gate spacer GS, a first source / drain pattern SD1, and a second source / drain pattern. The top surface of the first interlayer dielectric layer 110 may be substantially coplanar with the top surface of the gate cap pattern GP and the top surface of the gate spacer GS. A second interlayer dielectric layer 120 covering the gate cap pattern GP may be disposed on the first interlayer dielectric layer 110. A third interlayer dielectric layer 130, a fourth interlayer dielectric layer 140, a fifth interlayer dielectric layer 150, a sixth interlayer dielectric layer 160, and a seventh interlayer dielectric layer 170 may be disposed on the second interlayer dielectric layer 120. Upper lines FM1 connected to the logic block IP and upper vias FV0 and FV1 may be disposed therein in the first to seventh interlayer dielectric layers 110 to 170. The number of stacked interlayer dielectric layers and the number of stacked upper lines FM1 connected to the logic block IP can be varied. For example, the first interlayer dielectric layer 110 to the seventh interlayer dielectric layer 170 may include a silicon oxide layer. The first interlayer dielectric layer 110 to the seventh interlayer dielectric layer 170 may be referred to as... Figure 4 The interlayer dielectric layer FILD discussed in the article.

[0106] A pair of separate structures DB can be opposite each other in the second direction D2 and extend parallel to the gate electrode GE in the first direction D1. The spacing between the separate structure DB and its adjacent gate electrode GE can be the same as the first spacing.

[0107] The discrete structure DB can penetrate the gate cap pattern GP and the gate electrode GE, thereby extending into the first substrate 105. The discrete structure DB can penetrate the upper part of the first substrate 105.

[0108] The active contact AC can be configured to penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, thereby correspondingly electrically connecting to the first source / drain pattern SD1 and the second source / drain pattern. Each active contact AC can be configured to be adjacent to one side of the gate electrode GE. When viewed in a plan view, the active contact AC can have a strip extending in the first direction D1.

[0109] The active contact AC can be a self-aligned contact. For example, a gate cap pattern GP and a gate spacer GS can be used to form the active contact AC in a self-aligned manner. The active contact AC can cover at least a portion of, for example, the sidewall of the gate spacer GS. Although not shown, the active contact AC can cover a portion of the top surface of the gate cap pattern GP.

[0110] A metal-semiconductor compound layer SC or a silicide layer may be located between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern. The active contact AC can be electrically connected to one of the first source / drain pattern SD1 and the second source / drain pattern via the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include at least one selected from titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide. However, the example embodiments are not limited thereto.

[0111] The gate contact GC can be configured to penetrate the second interlayer dielectric layer 120 and the gate cap pattern GP, ​​thereby electrically connecting to the gate electrode GE. When viewed in a plan view, the two gate contacts GC can be configured to overlap with the first PMOSFET region PR1. The gate contacts GC can be freely disposed on the gate electrode GE without being restricted in position.

[0112] The upper dielectric pattern UIP can fill the upper portion of the active contact AC, which is adjacent to the gate contact GC. The bottom surface of the upper dielectric pattern UIP can be lower than the bottom surface of the gate contact GC. For example, the upper dielectric pattern UIP can make the active contact AC adjacent to the gate contact GC have a top surface that is lower than the bottom surface of the gate contact GC. Therefore, short circuits caused by contact between the gate contact GC and its adjacent active contact AC can be reduced and / or prevented. For example, the upper dielectric pattern UIP can include a silicon-based dielectric material (e.g., a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer).

[0113] The active contact AC may include a conductive pattern FM and a barrier metal pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. However, the example embodiment is not limited thereto. The barrier metal pattern BM may cover the sidewalls and bottom surface of the conductive pattern FM. The barrier metal pattern BM may include a metal layer and a metal nitride layer. The metal layer may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. However, the example embodiment is not limited thereto. The metal nitride layer may include at least one selected from titanium nitride (TiN) layer, tantalum nitride (TaN) layer, tungsten nitride (WN) layer, nickel nitride (NiN) layer, cobalt nitride (CoN) layer, and platinum nitride (PtN) layer. However, the example embodiment is not limited thereto. Similarly, the gate contact GC may include a conductive pattern and a barrier metal pattern surrounding the conductive pattern. The conductive pattern and the barrier metal pattern may include substantially the same materials as the conductive pattern FM and the barrier metal pattern BM included in the active contact AC.

[0114] A power transmission network (PDN) can be disposed on the second surface 105b of the first substrate 105. The PDN may include a first lower power line VPR1, a second lower power line VPR2, and a third lower power line VPR3, as well as multiple back lines BM1 electrically connected to the first lower power line VPR1, the second lower power line VPR2, and the third lower power line VPR3.

[0115] The first lower electric field line VPR1, the second lower electric field line VPR2, and the third lower electric field line VPR3 can extend parallel to each other in the second direction D2. The first lower electric field line VPR1 can vertically overlap with the first NMOSFET region NR1. The second lower electric field line VPR2 can vertically overlap with the first PMOSFET region PR1 and the second PMOSFET region PR2. The third lower electric field line VPR3 can vertically overlap with the second NMOSFET region NR2.

[0116] The first lower electric field line VPR1, the second lower electric field line VPR2, and the third lower electric field line VPR3 may include at least one selected from copper, molybdenum, tungsten, and ruthenium. Each of the first lower electric field line VPR1, the second lower electric field line VPR2, and the third lower electric field line VPR3 may be in contact with the second surface 105b of the first substrate 105.

[0117] The first lower power line VPR1 and the third lower power line VPR3 can be paths used to provide source voltage (e.g., ground voltage VSS). The second lower power line VPR2 can be a path used to provide drain voltage (e.g., power voltage VDD).

[0118] The back contact BC can be configured to penetrate the first substrate 105 and extend vertically from the second lower power line VPR2 to the first source / drain pattern SD1.

[0119] The back contact BC may have a conductive post shape, which vertically connects the second lower power line VPR2 to the first source / drain pattern SD1. A power voltage VDD can be applied to the first source / drain pattern SD1 through the back contact BC. The back contact BC may include at least one metal selected from, for example, tungsten, molybdenum, ruthenium, cobalt, aluminum, or copper. However, the example embodiment is not limited thereto.

[0120] The first back dielectric layer 180, the second back dielectric layer 190, and the third back dielectric layer 195 can be sequentially stacked on the second surface 105b of the first substrate 105, and a back line BM1 can be disposed in the first back dielectric layer 180, the second back dielectric layer 190, and the third back dielectric layer 195. The first back dielectric layer 180, the second back dielectric layer 190, and the third back dielectric layer 195 can include, for example, silicon oxide, and can be referred to as an interlayer dielectric layer BILD.

[0121] According to some example embodiments, the through-conductive pattern BP can be horizontally spaced from the logic block IP to pass through the first substrate 105 in the third direction D3. The vertical length of the through-conductive pattern BP can be greater than the vertical length of the back contact BC. For example, the through-conductive pattern BP can penetrate the first interlayer dielectric layer 110, the second interlayer dielectric layer 120, and the first back dielectric layer 180.

[0122] The through-conductive pattern BP can have a cylindrical, quadrilateral, or polygonal prism shape. When viewed along one direction (e.g., the second direction D2), the width of the through-conductive pattern BP can be greater than the width of the back contact portion BC. The through-conductive pattern BP can include at least one metal selected from, for example, copper, aluminum, tungsten, molybdenum, and cobalt. However, the example embodiments are not limited thereto. Furthermore, the through-conductive pattern BP may also include a metal nitride layer (not shown) covering its sidewalls. The metal nitride layer can include at least one selected from, for example, titanium nitride (TiN) layer, tantalum nitride (TaN) layer, tungsten nitride (WN) layer, nickel nitride (NiN) layer, cobalt nitride (CoN) layer, and platinum nitride (PtN) layer. However, the example embodiments are not limited thereto.

[0123] The upper conductive pattern FM2 and the upper conductive via FV2 can be alternately stacked on the top surface of the through conductive pattern BP. The lower conductive pattern BM2 and the lower conductive via BV2 can be sequentially stacked on the bottom surface of the through conductive pattern BP.

[0124] Figure 9 A cross-sectional view of a semiconductor package including a semiconductor device is shown, illustrating some example embodiments of the concept according to the present invention.

[0125] Reference Figure 9 The semiconductor package may include a first redistribution substrate 1000, a first semiconductor device 1100, a second semiconductor device 1200, and a third semiconductor device 1300. The first semiconductor device 1100 and the third semiconductor device 1300 may be mounted on the first redistribution substrate 1000, and the second semiconductor device 1200 may be mounted on the first semiconductor device 1100.

[0126] In some example embodiments, the first redistribution substrate 1000, the first semiconductor device 1100, and the second semiconductor device 1200 may include components similar to those described above. Figure 1 The components in the example embodiments discussed are substantially the same. For example, the first semiconductor device 1100 may include the aforementioned interconnect structure ICS, and the second semiconductor device 1200 may be electrically connected to the first redistribution substrate 1000 via the interconnect structure ICS.

[0127] A first connection terminal 1050 may be attached to the lower portion of the first redistribution substrate 1000, and a second connection terminal 1150 may be attached to the upper portion of the first redistribution substrate 1000. Furthermore, a third connection terminal 1250 may be connected between the first semiconductor device 1100 and the second semiconductor device 1200. The first connection terminal 1050, the second connection terminal 1150, and the third connection terminal 1250 may be at least one selected from solder balls, conductive bumps, and conductive pillars. The first connection terminal 1050, the second connection terminal 1150, and the third connection terminal 1250 may include, for example, at least one selected from copper, tin, and lead. However, the exemplary embodiment is not limited thereto.

[0128] The semiconductor package can use the first connection terminal 1050 to transmit and receive signals with other external packages or other semiconductor devices. For example, power signals (or ground signals) for driving the first semiconductor device 1100 and the second semiconductor device 1200 can be received through at least one of the first connection terminals 1050 of the first redistribution substrate 1000.

[0129] The first redistribution substrate 1000 can connect the first semiconductor device 1100 and the third semiconductor device 1300 to each other. The first redistribution substrate 1000 can connect the first semiconductor device 1100 and the third semiconductor device 1300 to each other and can provide a physical path formed by a conductive material. Therefore, the first semiconductor device 1100 and the third semiconductor device 1300 can be mounted on the first redistribution substrate 1000 and can transmit and receive signals from each other.

[0130] Semiconductor device 1200 can use first semiconductor device 1100 to execute applications supported by a semiconductor package. For example, second semiconductor device 1200 may include at least one processor selected from central processing unit (CPU), application processor (AP), graphics processing unit (GPU), neural processing unit (NPU), tensor processing unit (TPU), vision processing unit (VPU), image signal processor (ISP), and digital signal processor (DSP) to perform specialized calculations.

[0131] On the first redistribution substrate 1000, the third semiconductor device 1300 may be configured to be horizontally spaced from the first semiconductor device 1100. The third semiconductor device 1300 may include a memory chip. For example, the memory chip may include one or more of DRAM, SRAM, MRAM, and NAND flash memory. However, the example embodiment is not limited thereto.

[0132] A fourth connection terminal 1550 may be disposed between the third semiconductor device 1300 and the first redistribution substrate 1000. The third semiconductor device 1300 can be electrically connected to the first redistribution substrate 1000 via the fourth connection terminal 1550. The fourth connection terminal 1550 can connect the chip pads of the third semiconductor device 1300 to the upper bonding pads of the first redistribution substrate 1000. Furthermore, the third semiconductor device 1300 can be electrically connected to the first semiconductor device 1100 and the second semiconductor device 1200 via redistribution lines in the first redistribution substrate 1000.

[0133] The semiconductor package may further include a molding layer 1500 covering the side surfaces of the first semiconductor device 1100, the second semiconductor device 1200, and the third semiconductor device 1300, as well as the top surface of the first redistribution substrate 1000. The side surfaces of the molding layer 1500 may be substantially coplanar with the side surfaces of the first redistribution substrate 1000. The molding layer 1500 may include, for example, an epoxy molding compound (EMC). However, the exemplary embodiments are not limited thereto.

[0134] Figures 10 to 12E A cross-sectional view is shown illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the concept of the present invention.

[0135] Reference Figure 10 A first semiconductor substrate 100 may be provided. The first semiconductor substrate 100 may be, for example, a silicon substrate. The first semiconductor substrate 100 may have a first surface 100a and a second surface 100b opposite to the first surface 100a.

[0136] A first active pattern AP1 and a second active pattern AP2 can be formed on a first surface 100a of a first semiconductor substrate 100. The first active pattern AP1 and the second active pattern AP2 can have a line shape extending in a first direction D1. The first active pattern AP1 and the second active pattern AP2 can be formed by patterning the first semiconductor substrate 100 to form trenches. The first active pattern AP1 and the second active pattern AP2 can be part of the first semiconductor substrate 100 and can be defined by trenches formed in the first semiconductor substrate 100.

[0137] A device isolation layer STI can be formed between the first active pattern AP1 and the second active pattern AP2. The top surface of the device isolation layer STI can be lower than the top surfaces of the first active pattern AP1 and the second active pattern AP2 to expose the upper parts of the first active pattern AP1 and the second active pattern AP2.

[0138] A gate electrode can be formed (see Figure 8 The active contact AC can contact the first active pattern AP1 and the second active pattern AP2. Each active contact AC may include a barrier metal layer and a metal layer.

[0139] A first interlayer dielectric layer ILD1 can be formed on the first semiconductor substrate 100. The first interlayer dielectric layer ILD1 can cover the gate spacer (see...). Figure 9 GS in the middle), first source / drain pattern (see ... Figure 9 The first inter-layer dielectric layer (ID1) and the second source / drain pattern are shown. The second inter-layer dielectric layer (ID2) can be stacked on the first inter-layer dielectric layer (ID1).

[0140] Reference Figure 11 A top line FM1 can be stacked on the second inter-layer dielectric layer ILD2. The top line FM1 can be formed in a third inter-layer dielectric layer ILD3, which includes multiple dielectric layers. The vertically stacked top lines FM1 can be electrically connected via contact plugs and can be coupled to a logic block (or gate electrode and active contact). An upper conductive pattern FM2 and an upper conductive via FV2 can be formed simultaneously with the top line FM1 connected to the logic block. The uppermost upper conductive pattern FM2 can be coplanar (and / or substantially coplanar) with the third inter-layer dielectric layer ILD3. The first inter-layer dielectric layer ILD1, the second inter-layer dielectric layer ILD2, and the third inter-layer dielectric layer ILD3 can include, for example, silicon oxide and can be referred to as... Figure 4 The front interlayer dielectric layer FILD in the middle.

[0141] Reference Figure 12AA second substrate 200 can be fabricated. The second substrate 200 can be patterned on one surface to form trenches TR. A sacrificial pattern PH can fill the trenches TR of the second substrate 200. The second substrate 200 can be disposed on a third interlayer dielectric layer ILD3. The second substrate 200 and the third interlayer dielectric layer ILD3 can be adhered such that the sacrificial pattern PH filling the trenches TR contacts the uppermost upper conductive pattern FM2 in the upper conductive pattern FM2. An adhesive layer (not shown) can also be provided between the second substrate 200 and the third interlayer dielectric layer ILD3. The second substrate 200 can be, for example, a silicon substrate, and may also include silicon carbide. However, the exemplary embodiments are not limited thereto.

[0142] Reference Figure 12A and Figure 12B A thinning process can be performed to reduce the thickness of the first semiconductor substrate 100. The thinning process may include grinding or polishing the second surface 100b of the first semiconductor substrate 100 and / or anisotropically or isotropically etching the second surface 100b of the first semiconductor substrate 100.

[0143] The first semiconductor substrate 100 can be flipped, a grinding or polishing process can remove a portion of the first semiconductor substrate 100, and then an anisotropic or isotropic etching process can be performed on the residual surface defects on the first semiconductor substrate 100.

[0144] A process can be performed to replace the first semiconductor substrate 100 with a first substrate 105 formed of a dielectric material. Similar to the first semiconductor substrate 100, the first substrate 105 may include a first source pattern AP1 and a second active pattern AP2. Furthermore, the first substrate 105 may have a first surface 105a in contact with the device isolation layer STI and a second surface 105b opposite to the first surface 105a.

[0145] The second surface 105b of the first substrate 105 can be patterned to form a via, which exposes one or more active contacts AC and source / drain patterns. The vertical length of the via can be equal to or substantially equal to or less than about 1 μm. The via can be filled with a metallic material and then planarized such that the second surface 105b of the first substrate 105 can be exposed to form a back contact BC.

[0146] After forming the back contact portion BC, a through conductive pattern BP can be formed to penetrate the first substrate 105. The through conductive pattern BP can be formed by the following operations: partially patterning the second surface 105b of the first substrate 105 and the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 to form a via exposing the conductive pattern FM2; filling the via with a metal material; and then planarizing the metal material to expose the second surface 105b of the first substrate 105.

[0147] Reference Figure 12C After forming the through conductive pattern BP, a power transmission network (PDN) can be formed on the second surface 105b of the first substrate 105. Forming the PDN may include forming multiple power lines or back lines BM1 across the interlayer dielectric layer BILD. Furthermore, during the formation of the back lines BM1, a lower conductive pattern BM2 and a lower conductive via BV2 can be simultaneously formed on the through conductive pattern BP. The uppermost lower conductive pattern BM2 can be referred to as the lower chip pad 1101.

[0148] The lower chip pad 1101 can be electrically connected to the through conductive pattern BP through the lower conductive pattern BM2 and the lower conductive via BV2. When the lower chip pad 1101 is formed, a first through structure TS can be formed, which includes the through conductive pattern BP, the upper conductive pattern FM2 and the lower conductive pattern BM2.

[0149] The second connection terminal 1150 may be attached to the lower chip pad 1101. The lower chip pad 1101 may include at least one selected from copper, nickel, zinc, gold, silver, platinum, palladium, chromium, titanium, and alloys thereof. The second connection terminal 1150 may include at least one selected from tin, silver, lead, nickel, copper, and alloys thereof. However, the exemplary embodiments are not limited thereto.

[0150] Reference Figure 12D A sub-substrate WF can be configured to connect to the second connection terminal 1150. The sub-substrate WF can be the one described above. Figure 1 The first redistribution substrate 1000 is discussed in the text, but the inventive concept is not limited thereto. The sub-substrate WF can be attached to the second connection terminal 1150, and the second substrate 200 can then be flipped.

[0151] Reference Figure 12E The sacrificial pattern PH in the trench TR can be selectively removed. A second through-structure 210 can be formed in the trench TR after the sacrificial pattern PH has been removed. The second through-structure 210 can be formed by filling the trench TR with a metallic material and then planarizing the metallic material to expose the top surface of the second substrate 200. A second through-structure 210 penetrating the second substrate 200 can be formed to achieve the interconnect structure ICS.

[0152] Figures 13A to 13D Cross-sectional views are shown illustrating methods for manufacturing semiconductor devices according to some exemplary embodiments of the present invention, and descriptions are provided. Figures 12A to 12D Different manufacturing methods. Figures 13A to 13D The method for manufacturing semiconductor devices shown can be referred to next. Figure 10 and Figure 11 The method for manufacturing semiconductor devices is discussed. For the sake of brevity, detailed descriptions of technical features identical to those of the semiconductor devices described above may be omitted, and only the differences will be described.

[0153] Reference Figure 13A A second substrate 200 may be disposed on the third interlayer dielectric layer ILD3. An adhesive layer (not shown) may also be disposed between the second substrate 200 and the third interlayer dielectric layer ILD3.

[0154] Reference Figure 13B A thinning process can be performed to reduce the thickness of the first semiconductor substrate 100.

[0155] The first semiconductor substrate 100 can be flipped, and a grinding or polishing process can remove a portion of the first semiconductor substrate 100. A process can be performed to replace the first semiconductor substrate 100 with a first substrate 105 formed of a dielectric material.

[0156] The second surface 105b of the first substrate 105 can be patterned to form a via, which exposes one or more active contacts AC and source / drain patterns. The via can be filled with a metallic material and then planarized such that the second surface 105b of the first substrate 105 can be exposed to form a back contact BC. After forming the back contact BC, a through-conductive pattern BP can be formed to penetrate the first substrate 105.

[0157] Reference Figure 13C After forming the through conductive pattern BP, a power transmission network (PDN) can be formed on the second surface 105b of the first substrate 105. The PDN can include multiple power lines or back lines BM1 spanning the interlayer dielectric layers BILD. Furthermore, during the formation of the back lines BM1, a lower conductive pattern BM2 and a lower conductive via BV2 can be simultaneously formed on the through conductive pattern BP. The uppermost lower conductive pattern BM2 can be referred to as the lower chip pad 1101. A second connection terminal 1150 can be attached to the lower chip pad 1101.

[0158] Reference Figure 13D and Figure 12EA sub-substrate WF can be configured to connect to the second connection terminal 1150. The sub-substrate WF can be the one described above. Figure 1 The first redistribution substrate 1000 is discussed in the text, but the inventive concept is not limited thereto. The sub-substrate WF can be attached to the second connection terminal 1150, and the second substrate 200 can then be flipped.

[0159] The second substrate 200 can be patterned to form trenches TR that penetrate the second substrate 200. The second through structure 210 can be formed by filling the trenches TR with a metallic material and then planarizing the metallic material to expose the top surface of the second substrate 200.

[0160] According to some exemplary embodiments of the present invention, a connection structure can be provided to electrically connect the top and bottom ends of a semiconductor chip. This connection structure may include a first through-structure penetrating a first substrate on which logic blocks are formed and a second through-structure penetrating a second substrate on the first substrate. This connection structure can serve as an electrical path between vertically stacked semiconductor chips. Furthermore, the first through-structure may include upper and lower lines and through conductive vias penetrating the first substrate, and the upper and lower lines may be suitably configured to bypass the logic blocks. Therefore, a larger area can be formed for logic blocks disposed in the semiconductor device, and the design freedom and / or integration density of the semiconductor device can be improved.

[0161] Furthermore, the heat generated by the operation of the semiconductor chip can be transferred to a second substrate with excellent thermal conductivity and dissipated outward through the sidewalls of the second substrate. Therefore, the semiconductor chip's thermal radiation performance can be improved, and / or its degradation can be at least partially reduced and / or prevented.

[0162] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, the numerical values ​​to be associated are intended to include manufacturing or operational tolerances (e.g., ±10%) near said numerical values. Furthermore, when the terms “generally” and “substantially” are used in conjunction with geometry, it is intended not to require precision in the geometry, but rather a tolerance for the shape within the scope of this disclosure. Moreover, regardless of whether numerical values ​​or shapes are modified to “about” or “substantially”, it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) near said numerical values ​​or shapes. When a range is specified, the range includes all values ​​within that range, such as increments of 0.1%.

[0163] Although the invention has been described with reference to some exemplary embodiments of the inventive concept illustrated in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and essential characteristics of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made without departing from the scope and spirit of the inventive concept.

Claims

1. A semiconductor device, comprising: A first substrate has a first surface and a second surface facing each other; A logic block on the first surface of the first substrate; A power transmission network is located on the second surface of the first substrate, and the power transmission network includes multiple back lines connected to the logic block; A second substrate is located on the logic block and opposite the first surface of the first substrate; The first through-structure penetrates the first substrate; as well as A second through-structure penetrates the second substrate, and the second through-structure is electrically connected to the first through-structure. The first through structure includes: A through-conductive pattern is horizontally spaced from the logic block and penetrates the first substrate; Multiple conductive patterns are stacked on the top surface of the through-conductive pattern; and Multiple lower conductive patterns are stacked on the bottom surface of the through conductive pattern.

2. The semiconductor device according to claim 1, wherein, The plurality of upper conductive patterns and the plurality of lower conductive patterns vertically overlap with the through conductive pattern.

3. The semiconductor device according to claim 1, wherein, The first through structure includes: Multiple upper conductive vias, between the multiple upper conductive patterns, and Multiple lower conductive vias are located between the multiple lower conductive patterns.

4. The semiconductor device according to claim 1, further comprising: An interlayer dielectric layer, on the first surface of the first substrate, covers the plurality of upper conductive patterns. The second through structure penetrates at least a portion of the front interlayer dielectric layer.

5. The semiconductor device according to claim 1, wherein, The second through structure includes: The first conductive via is vertically connected to the first through structure, and A wire is connected to the first conductive via, and the wire extends in a direction parallel to the bottom surface of the second substrate.

6. The semiconductor device according to claim 5, further comprising: Multiple lines are connected to the logic block on the first surface of the first substrate. The second through structure also includes: A second conductive via is connected to the wire, and the second conductive via is horizontally spaced from the first conductive via. The second conductive via is electrically connected to the plurality of upper lines.

7. The semiconductor device according to claim 1, further comprising: Redistribution substrate, on the second substrate, The second through structure is electrically connected to the redistribution pattern of the redistribution substrate.

8. The semiconductor device according to claim 1, wherein, The logic block includes: Multiple source / drain patterns, A channel pattern, between the plurality of source / drain patterns, comprising a plurality of semiconductor patterns stacked on top of each other and spaced apart. Gate electrode, on the channel pattern, An active contact portion is provided on the plurality of source / drain patterns, and the active contact portion is connected to one of the plurality of source / drain patterns. Multiple lines are connected to the active contact portion, and A back contact portion, located below the plurality of source / drain patterns, connects another of the plurality of source / drain patterns to one of the plurality of back lines.

9. The semiconductor device according to claim 1, wherein, The second through structure is in contact with the uppermost upper conductive pattern in the upper conductive pattern.

10. The semiconductor device according to claim 1, further comprising: Multiple overhead lines are connected to the logic block on the first surface of the first substrate. Among them, the top surface of the lowest upper conductive pattern among the plurality of upper conductive patterns is coplanar with the top surface of at least a portion of the upper lines among the plurality of upper lines.

11. The semiconductor device according to claim 1, wherein, The bottom surface of the lowest lower conductive pattern among the plurality of lower conductive patterns is coplanar with the bottom surface of at least a portion of the back lines among the plurality of back lines.

12. A semiconductor device, comprising: A first substrate has a first surface and a second surface facing each other; A logic block on the first surface of the first substrate; Multiple lines are connected to the logic block on the first surface of the first substrate; A power transmission network is located on the second surface of the first substrate, and the power transmission network includes multiple back lines connected to the logic block; A second substrate is located on the logic block and opposite the first surface of the first substrate; as well as The connection structure penetrates both the first substrate and the second substrate. The connection structure includes: A through-conductive pattern penetrates the first substrate, and the through-conductive pattern is horizontally spaced from the logic block; and The upper through-structure penetrates the second substrate, and the upper through-structure is electrically connected to the through conductive pattern. The bottom surface of the upper through structure is located at a level lower than the top surface of the uppermost of the multiple upper lines.

13. The semiconductor device according to claim 12, wherein, The horizontal width of the through conductive pattern is smaller than the horizontal width of the upper through structure.

14. The semiconductor device according to claim 12, wherein, The vertical length of the through conductive pattern is less than the vertical length of the upper through structure.

15. The semiconductor device according to claim 12, wherein, The upper through-structure is vertically spaced from the first substrate.

16. The semiconductor device according to claim 12, wherein, The logic block includes: Multiple source / drain patterns, A channel pattern, between the plurality of source / drain patterns, comprising a plurality of semiconductor patterns stacked on top of each other and spaced apart. Gate electrode, on the channel pattern, An active contact portion is provided on the plurality of source / drain patterns, and the active contact portion is connected to one of the plurality of source / drain patterns; the plurality of upper lines are connected to the active contact portion; and A back contact portion is located below the plurality of source / drain patterns, and the back contact portion connects another of the plurality of source / drain patterns to one of the plurality of back lines.

17. The semiconductor device according to claim 16, wherein, The horizontal width of the through conductive pattern is greater than the horizontal width of the back contact portion.

18. A semiconductor package, comprising: Redistribution substrate; A first semiconductor chip is disposed on the redistribution substrate; as well as The second semiconductor chip is located on the first semiconductor chip. The first semiconductor chip includes: Logic blocks, on the first surface of the first substrate. An upper line is located on the first surface of the first substrate, and the upper line is connected to the logic block. A power transmission network is located on the second surface of the first substrate, and the power transmission network includes multiple power lines connected to the logic block. A second substrate, on the logic block and opposite to the first surface of the first substrate, and The connection structure penetrates both the first substrate and the second substrate. The connection structure includes: The first through-structure penetrates the first substrate, and A second through-structure penetrates the second substrate, and the second through-structure is electrically connected to the first through-structure. The first through structure includes: A through-conductive pattern penetrates the first substrate, and the through-conductive pattern is horizontally spaced from the logic block. Multiple upper conductive patterns are disposed on the first surface of the first substrate, and the multiple upper conductive patterns are stacked on the top surface of the through conductive pattern. Multiple lower conductive patterns are disposed on the second surface of the first substrate, and the multiple lower conductive patterns are stacked on the bottom surface of the through conductive pattern.

19. The semiconductor package of claim 18, wherein, The second through structure overlaps vertically with the first through structure.

20. The semiconductor package of claim 18, wherein, The logic block includes: Multiple source / drain patterns; A channel pattern, between the plurality of source / drain patterns, the channel pattern comprising a plurality of semiconductor patterns stacked on top of each other and spaced apart; Gate electrode, on the channel pattern; An active contact portion is provided on the plurality of source / drain patterns, and the active contact portion is connected to one of the plurality of source / drain patterns; the upper line is connected to the active contact portion; and A back contact portion is located below the source / drain pattern, and the back contact portion connects another of the source / drain patterns to the back line.

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