A display panel and display device

Abstract

This disclosure provides a display panel and display device, including a data line, a test switch circuit, and an output pad located on one side of a substrate. The test switch circuit and the output pad are located in a chip bonding area, and the output pad is located on the side of the test switch circuit closer to the display area. The output pad includes a first conductive portion extending along the data line extension direction and a second conductive portion and a third conductive portion located between the first conductive portion and the substrate. The orthographic projections of the second conductive portion and the third conductive portion on the substrate are arranged and spaced apart along the data line extension direction. The second conductive portion is closer to the test switch circuit, and the third conductive portion is closer to the display area. The orthographic projection of the first conductive portion on the substrate overlaps with the orthographic projections of the second and third conductive portions on the substrate. The first conductive portion is electrically connected to the second and third conductive portions respectively. The second conductive portion is directly electrically connected to the test switch circuit through a first trace, and the third conductive portion is electrically connected to the display area through a second trace.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display panel and a display device. BACKGROUND

[0002] In a display panel, the frame is the key to limit the size of the entire display product, and the product with narrow frame is currently required by customers and manufacturers. Firstly, the narrow frame is more beautiful, which makes the product more competitive, and in addition, the narrower frame means that a large motherboard can arrange more screens under the premise of the same display area, and the BOM cost is lower.

[0003] SUMMARY

[0004] The display panel and the display device are provided by the embodiments of the present disclosure, and the specific solutions are as follows:

[0005] The display panel provided by the embodiments of the present disclosure comprises a display area and a non-display area surrounding the display area, and the non-display area comprises a chip bonding area located at one side of the display area.

[0006] The display panel comprises:

[0007] a substrate;

[0008] a plurality of data lines located at one side of the substrate and in the display area;

[0009] a test switch circuit located at one side of the substrate and in the chip bonding area;

[0010] a plurality of output pads located at one side of the substrate and in the chip bonding area, and located at one side of the test switch circuit close to the display area; wherein the output pad comprises a first conductive part extending along the extension direction of the data line, and a second conductive part and a third conductive part located between the first conductive part and the substrate, the orthographic projection of the second conductive part and the third conductive part on the substrate is arranged and spaced along the extension direction of the data line, the second conductive part is close to the test switch circuit, the third conductive part is close to the display area, and the orthographic projection of the first conductive part on the substrate overlaps the orthographic projection of the second conductive part and the third conductive part on the substrate.

[0011] The first conductive part is electrically connected with the second conductive part and the third conductive part respectively, the second conductive part is directly electrically connected with the test switch circuit through a first trace, and the third conductive part is electrically connected with the display area through a second trace.

[0012] In a possible implementation, in the display panel provided by the embodiment of the present disclosure, the length of the third conductive part along the extension direction of the data line is greater than or equal to the length of the second conductive part along the extension direction of the data line.

[0013] In a possible implementation, in the display panel provided by the embodiment of the present disclosure, the display area further includes a plurality of gate lines arranged in a layer different from the data line, the gate line is located between the substrate and the data line, and the first conductive part is located on the side of the data line away from the substrate.

[0014] The first trace is arranged in the same layer as the data line, and the second conductive part is arranged in the same layer as the data line.

[0015] In a possible implementation, in the display panel provided by the embodiment of the present disclosure, further comprising: a gate insulating layer located between the gate line and the data line, and a passivation layer located between the data line and the first conductive part.

[0016] The first conductive part is electrically connected to the second conductive part through a first via hole penetrating the passivation layer.

[0017] In a possible implementation, in the display panel provided by the embodiment of the present disclosure, the third conductive part of at least part of the output pads and the electrically connected second trace are arranged in the same layer as the gate line, and the first conductive part is electrically connected to the third conductive part through a second via hole penetrating the passivation layer and the gate insulating layer.

[0018] In a possible implementation, in the display panel provided by the embodiment of the present disclosure, the number of the second via holes is greater than or equal to the number of the first via holes.

[0019] In a possible implementation, in the display panel provided by the embodiment of the present disclosure, the third conductive part of at least part of the output pads and the electrically connected second trace are arranged in the same layer as the data line, and the first conductive part is electrically connected to the third conductive part through a third via hole penetrating the passivation layer.

[0020] In a possible implementation, in the display panel provided by the embodiment of the present disclosure, the number of the third via holes is greater than or equal to the number of the first via holes.

[0021] In a possible implementation, in the display panel provided by the embodiments of the present disclosure, the chip bonding area is divided into a first region, a middle region and a second region along the extension direction of the gate lines, and the output pads include a plurality of data signal output pads located in the middle region; the test switch circuit includes a plurality of first test transistors located in the middle region and corresponding to the data lines one by one, a plurality of first control signal test lines located in the middle region and extending along the extension direction of the gate lines, and a plurality of data signal test lines.

[0022] The first pole of each first test transistor is electrically connected with the corresponding first control signal test line, the second pole of each first test transistor is electrically connected with the corresponding data signal test line, and the third pole of each first test transistor is electrically connected with the second conductive part of the corresponding data signal output pad through the corresponding first trace.

[0023] In a possible implementation, in the display panel provided by the embodiments of the present disclosure, the first control signal test lines and at least part of the data signal test lines are arranged in the same layer as the gate lines; the test switch circuit further includes a first connecting part and a third trace arranged in the same layer as the data lines, and a second connecting part arranged in the same layer as the first conductive part, the second pole of the first test transistor is electrically connected with the first connecting part through the third trace, and the second connecting part is electrically connected with the corresponding first connecting part and data signal test line respectively.

[0024] At least part of the first connecting part and the data signal test line overlap on the substrate in the orthographic projection.

[0025] In a possible implementation, in the display panel provided by the embodiments of the present disclosure, the second connecting part is electrically connected with the first connecting part through a fourth via penetrating the passivation layer, the second connecting part is electrically connected with the data signal test line through a fifth via penetrating the passivation layer and the gate insulating layer, and the fourth via and the fifth via are arranged along the extension direction of the gate lines.

[0026] In a possible implementation, in the display panel provided by the embodiments of the present disclosure, the width of the data signal test line covered by the second connecting part is greater than the width of the data signal test line between adjacent second connecting parts.

[0027] In a possible implementation, in the display panel provided by the embodiments of the present disclosure, the third conductive part of each data signal output pad and the electrically connected second trace are arranged in the same layer as the gate lines.

[0028] In a possible implementation, in the display panel provided by the embodiments of the present disclosure, the output pads further include a plurality of first gate signal output pads located in the first area, and a plurality of second gate signal output pads located in the second area.

[0029] The test switch circuit further includes a plurality of second test transistors located in the first area, a plurality of third test transistors located in the second area, a plurality of second control signal test lines and a first gate signal test line extending along the extending direction of the gate lines in the first area, and a plurality of third control signal test lines and a second gate signal test line extending along the extending direction of the gate lines in the second area.

[0030] The first electrode of each of the second test transistors is electrically connected to the corresponding second control signal test line, the second electrode of each of the second test transistors is electrically connected to the first gate signal test line, and the third electrode of each of the second test transistors is electrically connected to the second conductive part of the first gate signal output pad through the corresponding first trace.

[0031] The first electrode of each of the third test transistors is electrically connected to the corresponding third control signal test line, the second electrode of each of the third test transistors is electrically connected to the second gate signal test line, and the third electrode of each of the third test transistors is electrically connected to the second conductive part of the second gate signal output pad through the corresponding first trace.

[0032] In a possible implementation, in the display panel provided by the embodiments of the present disclosure, the second control signal test lines and the third control signal test lines are arranged in the same layer as the gate lines, and the first gate signal test line and the second gate signal test line are arranged in the same layer as the data lines.

[0033] In a possible implementation, in the display panel provided by the embodiments of the present disclosure, the third conductive part of the first gate signal output pad and the third conductive part of the second gate signal output pad are electrically connected to the gate lines through the corresponding second traces.

[0034] In a possible implementation, in the display panel provided by the embodiments of the present disclosure, the non-display area further includes a gate drive circuit electrically connected to the gate lines, the gate drive circuit and the chip bonding area are located on different sides of the display area, and the third conductive part of the first gate signal output pad and the third conductive part of the second gate signal output pad are electrically connected to the gate drive circuit through the corresponding second traces.

[0035] In a possible implementation, in the display panel provided by the embodiment of the present disclosure, the third conductive part of part of the first gate signal output pad and the second trace electrically connected are arranged in the same layer as the gate line, the third conductive part of part of the first gate signal output pad and the second trace electrically connected are arranged in the same layer as the data line, the third conductive part of part of the second gate signal output pad and the second trace electrically connected are arranged in the same layer as the gate line, the third conductive part of part of the second gate signal output pad and the second trace electrically connected are arranged in the same layer as the data line, and the second trace arranged in the same layer as the gate line and the second trace arranged in the same layer as the data line are arranged alternately along the extension direction of the gate line.

[0036] In a possible implementation, in the display panel provided by the embodiment of the present disclosure, the plurality of first test transistors are located in different rows, and each row is electrically connected with a first control signal test line; the plurality of second test transistors are located in different rows, and each row is electrically connected with a second control signal test line; and the plurality of third test transistors are located in different rows, and each row is electrically connected with a third control signal test line.

[0037] Each of the second control signal test lines and each of the first control signal test lines are electrically connected through a third connecting part in adjacent regions of the first region and the intermediate region, and the third connecting part is arranged in the same layer as the first conductive part;

[0038] Each of the first control signal test lines and each of the third control signal test lines are electrically connected through a fourth connecting part in adjacent regions of the second region and the intermediate region, and the fourth connecting part is arranged in the same layer as the first conductive part.

[0039] In a possible implementation, in the display panel provided by the embodiment of the present disclosure, the data signal test line includes at least one first data signal test line and at least one second data signal test line arranged along the extension direction of the data line, the first data signal test line is configured to transmit a first data signal to an odd column of the data line, and the second data signal test line is configured to transmit a second data signal to an even column of the data line.

[0040] In a possible implementation, in the display panel provided by the embodiment of the present disclosure, further comprising: a first gate signal test pad, a first data signal test pad and a first common signal test pad located on one side of the chip binding area along the extension direction of the gate line, and a control signal test pad, a second gate signal test pad, a second data signal test pad and a second common signal test pad located on the other side of the chip binding area along the extension direction of the gate line.

[0041] It also includes: a plurality of input pads located in the chip bonding area and on the side of the test switch circuit away from the display area, and a common signal line arranged around the display area and on the same layer as the gate line; the common signal line includes a common trace that enters the chip bonding area from both sides along the extension direction of the gate line and is located between the test switch circuit and the input pads;

[0042] The control signal test pad is electrically connected to each of the third control signal test lines via a fourth trace. The first gate signal test pad is electrically connected to the first gate signal test line via a fifth trace. The second gate signal test pad is electrically connected to the second gate signal test line via a sixth trace. The first data signal test pad is electrically connected to each of the first data signal test lines via a seventh trace. The second data signal test pad is electrically connected to the second data signal test line via an eighth trace. Both the first common signal test pad and the second common signal test pad are electrically connected to the common trace.

[0043] The fourth and seventh traces are both arranged on the same layer as the gate line, and the fifth and sixth traces are both arranged on the same layer as the data line;

[0044] The fourth, sixth, eighth, and common traces are arranged sequentially along the extension direction of the data line in the edge region of the second region. The eighth trace and the common trace are designed with jumpers in the edge region of the second region. The eighth trace in the jumper region is disposed on the same layer as the first conductive part, and the eighth trace in the non-jumper region is disposed on the same layer as the data line.

[0045] Accordingly, this disclosure also provides a display device, including the display panel provided in the embodiments of this disclosure. Attached Figure Description

[0046] Figure 1 is a plan view of a display panel provided in an embodiment of this disclosure;

[0047] Figure 2 is an enlarged schematic diagram of the chip bonding area in Figure 1;

[0048] Figure 3 is another enlarged schematic diagram of the chip bonding area in Figure 1;

[0049] Figure 4 is an enlarged view of the area within the dashed box E1 in Figure 3;

[0050] Figure 5 is an enlarged view of the area within the dashed box E2 in Figure 3;

[0051] Figure 6 is an enlarged view of the area within the dashed box E3 in Figure 5;

[0052] Fig. 7 is a schematic cross-sectional view of Fig. 6 along the direction of CC';

[0053] Fig. 8 is a schematic enlarged view of a structure transformation within the dashed box E3 in Fig. 5;

[0054] Fig. 9 is a schematic enlarged view within the dashed box E4 in Fig. 5;

[0055] Fig. 10 is a schematic enlarged view of another structure transformation in Fig. 5;

[0056] Fig. 11 is a schematic enlarged view within the dashed box E5 in Fig. 4;

[0057] Fig. 12 is a schematic enlarged view within the dashed box E6 in Fig. 3;

[0058] Fig. 13 is a schematic enlarged view of the area corresponding to the dashed box E2 in Fig. 3 when the display panel is an LCD;

[0059] Fig. 14 is a schematic plan view of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict, if necessary. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0061] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the common meanings thereof by those skilled in the art to which the present disclosure belongs. The similar words such as "comprise" or "contain" and the like used in the present disclosure mean that the elements or objects before the words cover the elements or objects listed after the words and their equivalents, and do not exclude other elements or objects. The similar words such as "connect" or "connected" do not mean the physical or mechanical connection, but can include the electrical connection, whether direct or indirect. The words "in", "out", "upper", "lower", and the like only represent the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0062] It should be noted that the size and shape of each figure in the drawings do not reflect the true proportions, but only serve to illustrate the present disclosure. And the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout the drawings.

[0063] In a conventional display panel, the display panel is composed of a display area and a surrounding frame, wherein the surrounding frame (generally a lower frame) includes a binding area, the binding area mainly including input and output pads of an IC, FPC pads and an ET system, the ET system including ET pads on both sides of the IC and a SW (switch) in the IC. The main function of the ET system is to perform yield detection before the display panel is bound with the IC, and it is a key to product control when the product is shipped.

[0064] At present, the market demand for narrow frame of display panel is increasingly strong, and the binding area is the area with the highest proportion of the frame of the entire display panel, so reducing the size of the binding area is the key to realize the narrow frame. In actual production, the SW in the IC needs to occupy a large part of the space, and discarding this part will cause a significant loss of product yield, therefore, in order to realize the narrow frame, a super-narrow size IC is used, which requires further optimization of the design of the SW in the IC, so as to successfully place the SW in the IC and narrow the frame.

[0065] Embodiments of the present disclosure provide a display panel, as shown in FIGS. 1-7, FIG. 1 is a plan view of the display panel, FIG. 2 is an enlarged view of a chip binding area in FIG. 1, FIG. 3 is another enlarged view of the chip binding area in FIG. 1, FIG. 4 is an enlarged view of a dashed box E1 in FIG. 3, FIG. 5 is an enlarged view of a dashed box E2 in FIG. 3, FIG. 6 is an enlarged view of a dashed box E3 in FIG. 5, and FIG. 7 is a cross-sectional view along a CC' direction in FIG. 6. The display panel includes a display area AA and a non-display area BB surrounding the display area AA, the non-display area BB including a chip binding area (IC) located on one side of the display area AA;

[0066] The display panel includes:

[0067] a substrate 1;

[0068] a plurality of data lines 2 located on one side of the substrate 1 and in the display area AA;

[0069] a test switch circuit 3 located on one side of the substrate 1 and in the chip binding area IC;

[0070] The plurality of output pads 4 are located on one side of the substrate 1, in the chip bonding area BD, and on the side of the test switch circuit 3 close to the display area AA; wherein the output pad 4 includes a first conductive part 41 extending along the extension direction Y of the data line 2, and a second conductive part 42 and a third conductive part 43 located between the first conductive part 41 and the substrate 1, the orthogonal projection of the second conductive part 42 and the third conductive part 43 on the substrate 1 is arranged and spaced along the extension direction of the data line 2, the second conductive part 42 is close to the test switch circuit 3, the third conductive part 43 is close to the display area AA, and the orthogonal projection of the first conductive part 41 on the substrate 1 overlaps the orthogonal projection of the second conductive part 42 and the third conductive part 43 on the substrate 1; specifically, the output pad 4 is generally arranged in two rows;

[0071] The first conductive part 41 is electrically connected with the second conductive part 42 and the third conductive part 43 respectively, the second conductive part 42 is directly electrically connected with the test switch circuit 3 through the first wire 5, and the third conductive part 43 is electrically connected with the display area AA through the second wire 6.

[0072] The display panel provided by the embodiments of the present disclosure adopts the mode that the output pad and the test switch circuit are directly electrically connected through the first wire, compared with the mode that the output pad and the test switch circuit are connected through the jumper hole in the related art, the present disclosure can narrow the distance between the output pad and the input pad (to be introduced later) in the chip bonding area, so that the super-narrow-size IC can be used to narrow the frame of the display panel, and therefore the present disclosure solves the problem that the test switch circuit cannot be placed due to the too small distance between the output pad and the input pad in the IC, and further solves the problem that the product yield cannot be detected, in the case of using the super-narrow-size IC. In addition, the second conductive part and the third conductive part of the output pad are arranged in a spaced manner, which is equivalent to a partition design of the second conductive part and the third conductive part, and the gap between the second conductive part and the third conductive part acts as the jumper hole in the related art, thereby reducing the ESD risk.

[0073] Specifically, the material of the first conductive part 41 can be a transparent conductive material, such as ITO and the like.

[0074] Optionally, the material of the data line 2 can include molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), and the like, and the data line 2 can be a single-layer structure or a laminated structure, for example, the data line 2 is a laminated structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer.

[0075] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 4-7, the length of the third conductive part 43 along the extension direction Y of the data line 2 is greater than or equal to the length of the second conductive part 42 along the extension direction Y of the data line 2. Preferably, the length of the third conductive part 43 along the extension direction Y of the data line 2 is greater than the length of the second conductive part 42 along the extension direction Y of the data line 2, because the signal on the first trace 5 needs to be transmitted to the second trace 6 and then to the display area AA through the second conductive part 42, the first conductive part 41 and the third conductive part 43 in turn, and the third conductive part 43 designed to be longer does not affect the signal transmission.

[0076] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 1, 3-7, the display area AA further comprises a plurality of gate lines 7 arranged in a layer different from the data line 2, for example, the data line 2 and the gate line 7 are arranged vertically, and the extension direction of the gate line 7 is X; the gate line 7 is located between the substrate 1 and the data line 2, and the first conductive part 41 is located on the side of the data line 2 away from the substrate 1.

[0077] For example, the output pads 4 are divided into two rows in total, the first row of output pads 4 is away from the display area AA, and the second row of output pads 4 is close to the display area AA. The first traces 5 electrically connected to the two rows of output pads 4 can be arranged in the same layer as the data line 2, and the second conductive parts 42 of the two rows of output pads 4 can be arranged in the same layer as the data line 2, that is, the first trace 5, the second conductive part 42 and the data line 2 are all located in the source-drain metal layer (SD). In this way, only the original patterning pattern needs to be changed when forming the data line 2, that is, the patterns of the first trace 5, the second conductive part 42 and the data line 2 can be formed by one-time patterning process, without increasing the process of separately preparing the first trace 5 and the second conductive part 42, so that the preparation process flow can be simplified, the production cost can be saved, and the production efficiency can be improved.

[0078] Optionally, the material of the gate line 7 can include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc. The gate line 7 can be a single-layer structure or a laminated structure, for example, the gate line 7 is a single-layer structure composed of a molybdenum metal layer.

[0079] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 4-7, further comprising: a gate insulating layer 8 located between the gate line 7 and the data line 2, and a passivation layer 9 located between the data line 2 and the first conductive part 41.

[0080] The first conductive part 41 is electrically connected to the second conductive part 42 through the first via V1 penetrating the passivation layer 9.

[0081] Optionally, the material of the gate insulating layer 8 can be at least one of inorganic insulating materials such as silicon oxide, silicon nitride and silicon oxynitride.

[0082] Optionally, the material of the passivation layer 9 can be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0083] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 4 and 5, the third conductive part 43 of at least part of the output pad 4 and the second wire 6 electrically connected are arranged in the same layer as the gate line 7, for example, the third conductive part 43 of the first row of output pads 4 and the second wire 6 electrically connected are arranged in the same layer as the gate line 7 in FIGS. 4 and 5, so that only the original patterning pattern needs to be changed when the gate line 7 is formed, that is, the pattern of the third conductive part 43, the second wire 6 and the gate line 7 of the first row of output pads 4 can be formed by one-time patterning process, without increasing the process of separately preparing the third conductive part 43 and the second wire 6, which can simplify the preparation process flow, save production cost and improve production efficiency; the first conductive part 41 is electrically connected with the third conductive part 43 through the second via V2 penetrating the passivation layer 9 and the gate insulating layer 8. The present disclosure reduces the jumper design between the output pad 4 and the test switch circuit 3 compared with the related art, for example, the number of jumpers can be reduced by 30% per unit area, the probability of water vapor entering the inside of the display panel is reduced, and the corrosion risk is reduced.

[0084] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 4-6, the number of the second via V2 is greater than or equal to the number of the first via V1. This is because the third conductive part 43 mainly acts as a circuit for conducting the IC and the display area AA, and the signal needs to be normally transmitted through the third conductive part 43, so the length of the third conductive part 43 along the extension direction Y of the data line 2 is greater than the length of the second conductive part 42 along the extension direction Y of the data line 2, and the number of the second via V2 is set to be greater than or equal to the number of the first via V1 in the present embodiment, which can reduce the contact resistance and further improve the signal transmission performance. Optionally, the number of the first via V1 is 1, and the number of the second via V2 is 5, of course, not limited thereto; for example, the number of the first via V1 is 2-3, to ensure the normal transmission of the signal to the display area AA.

[0085] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 4 and 5, the third conductive part 43 of at least part of the output pads 4 and the second wiring 6 electrically connected thereto can be arranged in the same layer as the data line 2, for example, the third conductive part 43 of the output pads 4 in the second row and the second wiring 6 electrically connected thereto are arranged in the same layer as the data line 2 in FIG. 4, and the third conductive part 43 of the output pads 4 in the second row and the second wiring 6 electrically connected thereto are arranged in the same layer as the gate line 7 in FIG. 5. In this way, the third conductive part 43 of the output pads 4 in the second row and the second wiring 6 electrically connected thereto in FIG. 4 only need to change the original patterning pattern when the data line 2 is formed, that is, the pattern of the third conductive part 43, the second wiring 6 and the data line 2 in the second row of output pads 4 can be formed by one-time patterning process, without increasing the process of separately preparing the third conductive part 43 and the second wiring 6, so that the preparation process flow can be simplified, the production cost can be saved, and the production efficiency can be improved. The first conductive part 41 is electrically connected to the third conductive part 43 through the third via hole V3 penetrating the passivation layer 9.

[0086] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 4, the number of third via holes V3 is greater than or equal to the number of first via holes V1. Optionally, the number of first via holes V1 is 1, and the number of third via holes V3 is 5, of course, not limited to this; for example, the number of first via holes V1 is 2-3, so as to ensure the normal transmission of signals to the display area AA.

[0087] It should be noted that the third conductive part 43 of the output pads 4 in the first row and the second wiring 6 electrically connected thereto in FIGS. 4 and 5 are taken as an example of being arranged in the same layer as the gate line 7, of course, the third conductive part 43 of the output pads 4 in the first row and the second wiring 6 electrically connected thereto can also be arranged in the same layer as the data line 2, as shown in FIG. 8, so that the first conductive part 41 of the output pads 4 in the first row is electrically connected to the third conductive part 43 through the sixth via hole V6 penetrating the passivation layer.

[0088] It should be noted that the third conductive part 43 of the output pads 4 in the second row and the second wiring 6 electrically connected thereto in FIG. 4 are taken as an example of being arranged in the same layer as the data line 2, of course, the third conductive part 43 of the output pads 4 in the second row and the second wiring 6 electrically connected thereto can also be arranged in the same layer as the gate line 7, referring to the third conductive part 43 of the output pads 4 in the second row and the second wiring 6 electrically connected thereto in FIG. 5.

[0089] It should be noted that the third conductive part 43 of the output pads 4 in the second row and the second wiring 6 electrically connected thereto in FIG. 5 are taken as an example of being arranged in the same layer as the gate line 7, of course, the third conductive part 43 of the output pads 4 in the second row and the second wiring 6 electrically connected thereto can also be arranged in the same layer as the data line 2.

[0090] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 3, FIG. 5 and FIG. 9, FIG. 9 is an enlarged schematic view of the dashed box E4 in FIG. 5, the chip bonding area IC is divided into a first region D1, a middle region D2 and a second region D3 along the extension direction X of the gate line 7, and the output pad 4 includes a plurality of data signal output pads 4' located in the middle region D2; the test switch circuit 3 includes a plurality of first test transistors T1 located in the middle region D2 and corresponding to the data line 2, a plurality of first control signal test lines 10 located in the middle region D2 and extending along the extension direction X of the gate line 7, and a plurality of data signal test lines 20.

[0091] The first electrode of each first test transistor T1 is electrically connected to the corresponding first control signal test line 10, the second electrode of each first test transistor T1 is electrically connected to the corresponding data signal test line 20, and the third electrode of each first test transistor is electrically connected to the second conductive part 42 of the corresponding data signal output pad 4' through the corresponding first trace 5. In this way, when performing the ET test, the first control signal test line 10 controls the first test transistor T1 to be turned on, and the data signal on the data signal test line 20 is transmitted to the first trace 5 through the first test transistor T1, and then transmitted to the data line 2 of the display area AA through the data signal output pad 4'.

[0092] Specifically, as shown in FIG. 5 and FIG. 9, the first electrode of the first test transistor T1 is the gate electrode (G), the second electrode of the first test transistor T1 is the source electrode (S), and the third electrode of the first test transistor T1 is the drain electrode (D); or, the first electrode of the first test transistor T1 is the gate electrode (G), the second electrode of the first test transistor T1 is the drain electrode (D), and the third electrode of the first test transistor T1 is the source electrode (S).

[0093] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 3, FIG. 5 and FIG. 9, the first control signal test line 10 and at least part of the data signal test line 20 are arranged in the same layer as the gate line 7, so that the original patterning pattern needs to be changed only when the gate line 7 is formed, that is, the patterns of the first control signal test line 10, the data signal test line 20 and the gate line 7 can be formed by one-time patterning process, without the need to increase the process of separately preparing the first control signal test line 10 and the data signal test line 20, so that the preparation process flow can be simplified, the production cost can be saved, and the production efficiency can be improved; the test switch circuit 3 further includes a first connecting part 30 and a third trace 40 arranged in the same layer as the data line 2, and a second connecting part 50 arranged in the same layer as the first conductive part 41, the second electrode of the first test transistor T1 is electrically connected to the first connecting part 30 through the third trace 40, and the second connecting part 50 is respectively electrically connected to the corresponding first connecting part 30 and the data signal test line 20;

[0094] At least part of the first connection part 30 (for example, the first connection part 30 of the bottom row away from the display area AA) on the substrate 1 has an orthogonal projection overlapping the orthogonal projection of the data signal test line 20 on the substrate 1, and at least part of the second connection part 50 (for example, the second connection part 50 of the bottom row away from the display area AA) extends along the extension direction X of the gate line 7. In this way, the second connection part 50 is designed in a flat-lying manner (that is, extending along the X direction), which can reduce the Y direction height of the position of the second connection part 50, further narrow the Y direction size of the size of the IC, and realize the narrow frame design of the display panel.

[0095] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 5 and 9, the second connection part 50 is electrically connected to the first connection part 30 through the fourth via V4 penetrating the passivation layer 9, and the second connection part 50 is electrically connected to the data signal test line 20 through the fifth via V5 penetrating the passivation layer 9 and the gate insulating layer 8. For example, the fourth via V4 and the fifth via V5 corresponding to the second connection part 50 of the bottom row away from the display area AA are arranged along the extension direction X of the gate line 7. The second connection part 50 of the bottom row in the present disclosure is designed in a flat-lying manner. Compared with the second connection part 50 in the related art which is designed to extend along the Y direction, the height of the IC along the Y direction can be saved by about 30 μm.

[0096] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 5 and 9, in order to facilitate wiring, only the second connection part 50 of the bottom row is flat-lying in FIG. 5. If the Pitch between the output pads 4 in the IC allows, the second connection part 50 of the top row close to the display area AA can also be designed in a flat-lying manner, as shown in FIG. 10. In this way, the height of the IC along the Y direction can save space of about 60 μm, further narrowing the size of the IC.

[0097] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 5, 9 and 10, the width W1 of the data signal test line 20 covered by the second connection part 50 can be greater than the width W2 of the data signal test line 20 between adjacent second connection parts 50. In this way, by increasing the width W1 of the data signal test line 20 covered by the second connection part 50, for example, from 16.5 μm in the related art to 18 μm, the present disclosure can increase the wrapping of the fourth via V4 and the fifth via V5 by the data signal test line 20, reduce the risk of leakage and corrosion of the fourth via V4 and the fifth via V5, and ensure the normal transmission of signals.

[0098] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 5, the third conductive part 43 of each data signal output pad 4' and the electrically connected second wiring 6 can be arranged in the same layer as the gate line 7.

[0099] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 3, FIG. 4 and FIG. 11, the output pad 4 further comprises: a plurality of first gate signal output pads 4" located in the first area D1, and a plurality of second gate signal output pads (not shown) located in the second area D3.

[0100] The test switch circuit 3 further comprises: a plurality of second test transistors T2 located in the first area D1, a plurality of third test transistors (not shown) located in the second area D3, a plurality of second control signal test lines 60 and a first gate signal test line 70 extending along the extension direction X of the gate line 7 in the first area D1, and a plurality of third control signal test lines 80 and a second gate signal test line 90 extending along the extension direction X of the gate line 7 in the second area D3;

[0101] The first pole of each second test transistor T2 is electrically connected with the corresponding second control signal test line 60, the second pole of each second test transistor T2 is electrically connected with the first gate signal test line 70, and the third pole of each second test transistor T2 is electrically connected with the second conductive part 42 of the first gate signal output pad 4" through the corresponding first wire 5.

[0102] The first pole of each third test transistor is electrically connected with the corresponding third control signal test line 80, the second pole of each third test transistor is electrically connected with the second gate signal test line 90, and the third pole of each third test transistor is electrically connected with the second conductive part 42 of the second gate signal output pad through the corresponding first wire 5. In the embodiments of the present disclosure, the second pole of the corresponding test transistor is directly electrically connected with the corresponding gate signal test line in the first area D1 and the second area D3, which can further narrow the size of the IC, compared with the related art in which the second pole of the corresponding test transistor is electrically connected with the corresponding gate signal test line through a jumper hole.

[0103] Specifically, as shown in FIG. 4 and FIG. 11, the first pole of the second test transistor T2 is the gate (G), the second pole of the second test transistor T2 is the source (S), and the third pole of the second test transistor T2 is the drain (D); or, the first pole of the second test transistor T2 is the gate (G), the second pole of the second test transistor T2 is the drain (D), and the third pole of the second test transistor T2 is the source (S).

[0104] Specifically, the first pole of the third test transistor is the gate (G), the second pole of the third test transistor is the source (S), and the third pole of the third test transistor is the drain (D); or, the first pole of the third test transistor is the gate (G), the second pole of the third test transistor is the drain (D), and the third pole of the third test transistor is the source (S).

[0105] Specifically, the structures of the first region D1 and the second region D3 are generally symmetrically arranged, and the test switch circuit 3 corresponding to the second region D3 is shown in FIG. 4.

[0106] The second control signal test line 60 and the third control signal test line 80 are arranged in the same layer as the gate line, so that the patterns of the second control signal test line 60, the third control signal test line 80 and the gate line 7 can be formed by one patterning process by changing the original patterning pattern when the gate line 7 is formed, without increasing the process of separately preparing the second control signal test line 60 and the third control signal test line 80, which can simplify the preparation process flow, save production cost and improve production efficiency; the first gate signal test line 70 and the second gate signal test line 90 are arranged in the same layer as the data line 2, so that the patterns of the first gate signal test line 70, the second gate signal test line 90 and the data line 2 can be formed by one patterning process by changing the original patterning pattern when the data line 2 is formed, without increasing the process of separately preparing the first gate signal test line 70 and the second gate signal test line 90, which can simplify the preparation process flow, save production cost and improve production efficiency.

[0107] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 1, 3, 4 and 11, the first gate signal output pad 4' and the third conductive part 43 of the second gate signal output pad are both electrically connected to the gate line 7 through the corresponding second trace 6.

[0108] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 1, 3, 4 and 11, the non-display area BB further includes a gate drive circuit (not shown) electrically connected to the gate line 7, the gate drive circuit and the chip bonding area IC are located at different sides of the display area AA, for example, the chip bonding area IC is located in the lower frame area of the display panel, and the gate drive circuit is located in the left and right frame areas of the display panel; the first gate signal output pad 4' and the third conductive part 43 of the second gate signal output pad are both electrically connected to the gate drive circuit through the corresponding second trace 6.

[0109] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 4, the third conductive part 43 of the partial first gate signal output pad 4" (for example, the first row of output pads 4 away from the display area AA) and the second wire 6 electrically connected thereto are arranged in the same layer as the gate line 7, the third conductive part 43 of the partial first gate signal output pad 4" (for example, the second row of output pads 4 close to the display area AA) and the second wire 6 electrically connected thereto are arranged in the same layer as the data line 2, the third conductive part 43 of the partial second gate signal output pad and the second wire 6 electrically connected thereto are arranged in the same layer as the gate line 7, and the third conductive part 43 of the partial second gate signal output pad and the second wire 6 electrically connected thereto are arranged in the same layer as the data line 2. The second wire 6 arranged in the same layer as the gate line 7 and the second wire 6 arranged in the same layer as the data line 2 are arranged alternately along the extension direction X of the gate line 7.

[0110] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 5, the plurality of first test transistors T1 are arranged in different rows, and each row is electrically connected to a first control signal test line 10; as shown in FIG. 4, the plurality of second test transistors T2 are arranged in different rows, and each row is electrically connected to a second control signal test line 60; and the plurality of third test transistors are arranged in different rows, and each row is electrically connected to a third control signal test line, as shown in FIG. 4.

[0111] Each second control signal test line 60 and each first control signal test line 10 are electrically connected by a third connecting part 100 in the adjacent regions of the first region D1 and the middle region D2, and the third connecting part 100 is arranged in the same layer as the first conductive part 41.

[0112] Each first control signal test line 10 and each third control signal test line 80 are electrically connected by a fourth connecting part 200 in the adjacent regions of the second region D3 and the middle region D2, and the fourth connecting part 200 is arranged in the same layer as the first conductive part 41. In this way, the gates of all the first test transistors T1, all the second test transistors T2 and all the third test transistors are controlled by the same control signal, that is, during the ET test, all the first test transistors T1, all the second test transistors T2 and all the third test transistors are turned on at the same time, and the corresponding data signals are loaded to the data line 2 of the display area AA by controlling the data signal test lines, so as to realize the gray scale display.

[0113] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 5, the data signal test line 20 includes at least one first data signal test line (for example, two DO signal lines) and at least one second data signal test line (for example, one DE signal line) arranged along the extension direction Y of the data line 2, the first data signal test line DO is configured to transmit a first data signal to the odd column data line 2, and the second data signal test line DE is configured to transmit a second data signal to the even column data line 2. Specifically, the display panel corresponding to FIG. 5 can be an electronic paper, and the two first data signal test lines DO are electrically connected with the gate line 7 in the same layer, and the second data signal test line DE is arranged in the same layer with the data line 2.

[0114] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 1, FIG. 3 and FIG. 12, FIG. 12 is an enlarged schematic view of the dashed line frame E6 in FIG. 3, further comprising: a first gate signal test pad Pad1, a first data signal test pad Pad2 and a first common signal test pad Pad3 located on one side (for example, the left side of the IC) of the chip binding area IC along the extension direction of the gate line 7, and a control signal test pad Pad4, a second gate signal test pad Pad5, a second data signal test pad Pad6 and a second common signal test pad Pad7 located on the other side (for example, the right side of the IC) of the chip binding area along the extension direction of the IC gate line;

[0115] Further comprising: a plurality of input pads 11 located in the chip binding area IC and located away from the display area AA side of the test switch circuit 3, and a common signal line 12 arranged around the display area AA and arranged in the same layer with the gate line 7; the common signal line 12 includes a common wire 121 entering the chip binding area IC from both sides of the chip binding area IC along the extension direction X of the gate line 7 and located between the test switch circuit 3 and the input pad 11;

[0116] The control signal test pad Pad4 is electrically connected with each third control signal test line 80 through a fourth wire 13, the first gate signal test pad Pad1 is electrically connected with the first gate signal test line 70 through a fifth wire 14, the second gate signal test pad Pad5 is electrically connected with the second gate signal test line 90 through a sixth wire 15, the first data signal test pad Pad2 is electrically connected with each first data signal test line DO through a seventh wire 16, the second data signal test pad Pad6 is electrically connected with the second data signal test line DE through an eighth wire 17, and the first common signal test pad Pad3 and the second common signal test pad Pad7 are both electrically connected with the common wire 121; wherein,

[0117] The fourth wire 13 and the seventh wire 16 are arranged in the same layer with the gate line 7, and the fifth wire 14 and the sixth wire 15 are arranged in the same layer with the data line 2;

[0118] The fourth trace 13, the sixth trace 15, the eighth trace 17 and the common trace 121 are arranged in sequence along the extension direction Y of the data line 2 at the edge region of the second region D3, the eighth trace 17 and the common trace 121 are designed to be jumpered at the edge region of the second region D3, the eighth trace 17 of the jumpered region F is arranged in the same layer as the first conductive part 41, and the eighth trace 17 of the non-jumpered region is arranged in the same layer as the data line 2. That is, a section of the eighth trace 17 entering the IC from the right side of the IC is arranged in the same layer as the data line 2, then jumps to the film layer where the gate line 7 is located, then crosses the common trace 121 in the Y direction, and then jumps to the film layer where the data line 2 is located. In this way, large current can be prevented, and signal transmission performance can be improved.

[0119] It should be noted that the display panel in the embodiments of the present disclosure is taken as an example of electronic paper, and the display panel is not limited to this, for example, the display panel can also be any display panel such as an LCD (Liquid Crystal Display), an OLED (Organic Light-Emitting Diode), etc.

[0120] Specifically, as shown in FIG. 13, which is an enlarged schematic view of the region E2 in dashed line box in FIG. 3 when the display panel is an LCD, the difference between FIG. 13 and FIG. 5 is that the gate line 7 and the data line 2 in the display area AA of the LCD display panel define a plurality of sub-pixels arranged in an array, the sub-pixels in the same column are of the same color, and the sub-pixels in the same row include a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B.

[0121] The data signal test line 20 includes a red picture test line L1, a green picture test line L2 and a blue picture test line L3 arranged along the extension direction Y of the data line 2, the red picture test line L1 is configured to transmit a red picture data signal to the data line 2 corresponding to the red sub-pixel R in the display area AA, the green picture test line L2 is configured to transmit a green picture data signal to the data line 2 corresponding to the green sub-pixel G in the display area AA, and the blue picture test line L3 is configured to transmit a blue picture data signal to the data line 2 corresponding to the blue sub-pixel B in the display area AA.

[0122] Specifically, as shown in FIG. 13, the red picture test line L1, the green picture test line L2 and the blue picture test line L3 are arranged in the same layer as the gate line 7. In this way, only the original patterning pattern needs to be changed when the gate line 7 is formed, that is, the patterns of the red picture test line L1, the green picture test line L2, the blue picture test line L3 and the gate line 7 can be formed by one patterning process, without increasing the process of separately preparing the red picture test line L1, the green picture test line L2 and the blue picture test line L3. Therefore, the preparation process flow can be simplified, the production cost can be saved, and the production efficiency can be improved.

[0123] Specifically, as shown in FIG. 13, the second connecting portion 50 corresponding to the red picture test line L1 and the green picture test line L2 is only laid flat in FIG. 13, if the pitch between the output pads 4 in the IC allows, the second connecting portion 50 corresponding to the red picture test line L1, the green picture test line L2 and the blue picture test line L3 can all be designed to be laid flat, so that the height of the IC along the Y direction can save about 90 μm of space, further narrowing the size of the IC.

[0124] Specifically, as shown in FIG. 13, the third conductive portion 43 of the two rows of data signal output pads 4' and the second traces 6 electrically connected are all disposed in the same layer as the gate line 7; of course, one of the corresponding third conductive portion 43 and the second traces 6 electrically connected can be disposed in the same layer as the gate line 7, and the other corresponding third conductive portion 43 and the second traces 6 electrically connected can be disposed in the same layer as the data line 2; or the third conductive portion 43 of the two rows of data signal output pads 4' and the second traces 6 electrically connected can all be disposed in the same layer as the data line 2; the specific selection and design can be made according to the size of the trace space of each film layer.

[0125] Specifically, as shown in FIG. 13, the IC corresponding to the LCD display panel is generally large in size, the distance between the output pad 4' and the input pad 11 in the large-size IC is large, and the transverse pitch between the adjacent pads is large, the first test transistor T1 can be designed to be reduced from four rows to two rows or three rows, the space in the IC is further compressed, compared with the SW design of the small-size IC, the space in the large-size IC can be further compressed by 30%.

[0126] In summary, compared with the SW design of the IC in the related art, the display panel provided by the embodiments of the present disclosure removes the jump hole between each test transistor and the output pad, and designs the output pad to be partitioned, which not only saves space, but also reduces the risk of corrosion and ESD; for the jump hole connection region between each test transistor and the data signal test line, the second connecting portion is designed to be laid flat, and the width of the data signal test line below the second connecting portion is widened, the wrapping of the corresponding via is increased, and the risk of corrosion and the like is avoided. The above optimization design of the present disclosure maximizes the saving of the space in the IC, realizes the narrow frame of the display product, ensures the yield, and is also applied to the small-size IC of the LCD, and has universality in the display product. The optimization scheme of the partitioning processing of the output pad and the laying flat design of the second connecting portion in the IC of the display panel provided by the present disclosure successfully places the SW in the ultra-narrow size IC, and in actual use, the function is normal, and does not have any adverse effect on the display function.

[0127] It should be noted that other essential components in the array substrate are understood by those skilled in the art, which are not described herein and should not be regarded as a limitation on the present disclosure.

[0128] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure also includes the display panel provided by the embodiments of the present disclosure. Since the display device solves problems in a similar principle to the display panel, the implementation of the display device provided by the embodiments of the present disclosure can be referred to the implementation of the display panel, and the repeated parts will not be described here.

[0129] In the implementation, the display device provided by the embodiments of the present disclosure can be an electronic paper, an LCD display device, an OLED display device, etc.

[0130] In the implementation, the display device provided by the embodiments of the present disclosure can be a full-screen display device, or can also be a flexible display device, etc., which is not limited here.

[0131] In the implementation, the display device provided by the embodiments of the present disclosure can be a full-screen mobile phone as shown in FIG. 14.

[0132] Of course, the display device provided by the embodiments of the present disclosure can also be any product or component with display function, such as a mobile phone, a projector, a 3D printer, a virtual reality device, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0133] Specifically, other essential components of the display device should be understood by those skilled in the art, which will not be described here, and should not be regarded as a limitation of the present disclosure.

[0134] The display device includes but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply, etc.

[0135] In addition, those skilled in the art can understand that the above structure does not constitute a limitation of the display device provided by the embodiments of the present disclosure, in other words, the display device provided by the embodiments of the present disclosure can include more or less components, or combine certain components, or different component arrangements.

[0136] The display panel and the display device provided by the embodiments of the present disclosure adopt a mode in which output pads and test switch circuits are directly electrically connected through first traces, compared with a mode in which output pads and test switch circuits are connected through jumpers in the related art, the present disclosure can narrow the distance between output pads and input pads in the chip bonding area, so that an ultra-narrow size IC can be used to narrow the frame of the display panel, therefore, the present disclosure solves the problem that the test switch circuit cannot be placed due to the too small distance between the output pads and the input pads in the IC, and further solves the problem that the product yield cannot be detected, in the case of using the ultra-narrow size IC. In addition, the second conductive part and the third conductive part of the output pad are arranged at intervals, which is equivalent to a design in which the second conductive part and the third conductive part are separated, and the gap between the second conductive part and the third conductive part acts as a jumper in the related art, thereby reducing the ESD risk.

[0137] Although the preferred embodiments of the present disclosure have been described, those skilled in the art who are aware of the basic inventive concept can make further changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0138] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A display panel, wherein, The display panel comprises: a substrate substrate; a plurality of data lines located on one side of the substrate substrate and in the display area; a test switch circuit located on one side of the substrate substrate and in the chip binding area; a plurality of output pads located on one side of the substrate substrate and in the chip binding area, and located on one side of the test switch circuit close to the display area; wherein the output pad comprises a first conductive part extending along the extension direction of the data line, and a second conductive part and a third conductive part located between the first conductive part and the substrate substrate, the second conductive part and the third conductive part are arranged and spaced along the extension direction of the data line, the second conductive part is close to the test switch circuit, the third conductive part is close to the display area, and the first conductive part is overlapped with the second conductive part and the third conductive part on the substrate substrate; wherein the first conductive part is electrically connected with the second conductive part and the third conductive part respectively, the second conductive part is directly electrically connected with the test switch circuit through the first trace, and the third conductive part is electrically connected with the display area through the second trace. The length of the third conductive part along the extension direction of the data line is greater than or equal to the length of the second conductive part along the extension direction of the data line.

2. The display panel of claim 1, wherein, The display area further comprises a plurality of gate lines arranged in different layers and crossed with the data lines, the gate lines are located between the substrate substrate and the data lines, and the first conductive part is located on the side of the data line away from the substrate substrate; 3. The display panel of claim 2, wherein, wherein the first trace is arranged in the same layer as the data line, and the second conductive part is arranged in the same layer as the data line. Further comprising: a gate insulating layer located between the gate line and the data line, and a passivation layer located between the data line and the first conductive part; 4. The display panel of claim 3, wherein, wherein the first conductive part is electrically connected with the second conductive part through the first via penetrating the passivation layer. The third conductive part of at least part of the output pad and the electrically connected second trace are arranged in the same layer as the gate line, and the first conductive part is electrically connected with the third conductive part through the second via penetrating the passivation layer and the gate insulating layer.

5. The display panel of claim 4, wherein, The number of the second via is greater than or equal to the number of the first via.

6. The display panel of claim 5, wherein, The third conductive part of at least part of the output pad and the electrically connected second trace are arranged in the same layer as the data line, and the first conductive part is electrically connected with the third conductive part through the third via penetrating the passivation layer.

7. The display panel of any of claims 4-6, wherein, The number of the third via is greater than or equal to the number of the first via.

8. The display panel of claim 7, wherein, The chip binding area is divided into a first region, a middle region and a second region along the extension direction of the gate line, and the output pad comprises a plurality of data signal output pads located in the middle region; 9. The display panel of any of claims 4-8, wherein, ​ The test switch circuit comprises a plurality of first test transistors located in the middle region and corresponding to the data lines, a plurality of first control signal test lines located in the middle region and extending along the extending direction of the gate lines, and a plurality of data signal test lines; The first pole of each of the first test transistors is electrically connected to the corresponding first control signal test line, the second pole of each of the first test transistors is electrically connected to the corresponding data signal test line, and the third pole of each of the first test transistors is electrically connected to the second conductive part of the corresponding data signal output pad through the corresponding first wire.

10. The display panel of claim 9, wherein, The first control signal test lines and at least part of the data signal test lines are arranged in the same layer as the gate lines; the test switch circuit further comprises a first connecting part and a third wire arranged in the same layer as the data lines, and a second connecting part arranged in the same layer as the first conductive part, the second pole of the first test transistor is electrically connected to the first connecting part through the third wire, and the second connecting part is electrically connected to the corresponding first connecting part and data signal test line, respectively; At least part of the first connecting part and the data signal test line overlap on the substrate in the orthographic projection.

11. The display panel of claim 10, wherein, The second connecting part is electrically connected to the first connecting part through a fourth via hole penetrating the passivation layer, and is electrically connected to the data signal test line through a fifth via hole penetrating the passivation layer and the gate insulating layer, and the fourth via hole and the fifth via hole are arranged along the extending direction of the gate lines.

12. The display panel of claim 11, wherein, The width of the data signal test line covered by the second connecting part is greater than the width of the data signal test line between adjacent second connecting parts.

13. The display panel of any of claims 9-12, wherein, The third conductive part of each data signal output pad and the electrically connected second wire are arranged in the same layer as the gate lines.

14. The display panel of any of claims 9-13, wherein, The output pad further comprises a plurality of first gate signal output pads located in the first region, and a plurality of second gate signal output pads located in the second region; The test switch circuit further comprises a plurality of second test transistors located in the first region, a plurality of third test transistors located in the second region, a plurality of second control signal test lines and first gate signal test lines located in the first region and extending along the extending direction of the gate lines, and a plurality of third control signal test lines and second gate signal test lines located in the second region and extending along the extending direction of the gate lines; The first pole of each of the second test transistors is electrically connected to the corresponding second control signal test line, the second pole of each of the second test transistors is electrically connected to the first gate signal test line, and the third pole of each of the second test transistors is electrically connected to the second conductive part of the first gate signal output pad through the corresponding first wire. The first electrode of each of the third test transistors is electrically connected with a corresponding third control signal test line, the second electrode of each of the third test transistors is electrically connected with the second gate signal test line, and the third electrode of each of the third test transistors is electrically connected with the second conductive part of the second gate signal output pad through a corresponding first trace.

15. The display panel of claim 14, wherein, The second control signal test line and the third control signal test line are arranged in the same layer as the gate line, and the first gate signal test line and the second gate signal test line are arranged in the same layer as the data line.

16. The display panel of claim 15, wherein, The third conductive part of the first gate signal output pad and the third conductive part of the second gate signal output pad are electrically connected with the gate line through a corresponding second trace.

17. The display panel of claim 15, wherein, The non-display area further comprises a gate drive circuit electrically connected with the gate line, the gate drive circuit and the chip bonding area are located on different sides of the display area, and the third conductive part of the first gate signal output pad and the third conductive part of the second gate signal output pad are electrically connected with the gate drive circuit through a corresponding second trace.

18. The display panel of claim 16 or 17, wherein, The third conductive part of part of the first gate signal output pad and the second trace electrically connected therewith are arranged in the same layer as the gate line, the third conductive part of part of the first gate signal output pad and the second trace electrically connected therewith are arranged in the same layer as the data line, the third conductive part of part of the second gate signal output pad and the second trace electrically connected therewith are arranged in the same layer as the gate line, and the third conductive part of part of the second gate signal output pad and the second trace electrically connected therewith are arranged in the same layer as the data line. The second trace arranged in the same layer as the gate line and the second trace arranged in the same layer as the data line are arranged alternately along the extension direction of the gate line.

19. The display panel of any of claims 14-18, wherein, The plurality of first test transistors are arranged in different rows, each row being electrically connected with a corresponding first control signal test line; the plurality of second test transistors are arranged in different rows, each row being electrically connected with a corresponding second control signal test line; and the plurality of third test transistors are arranged in different rows, each row being electrically connected with a corresponding third control signal test line. Each of the second control signal test lines and each of the first control signal test lines are electrically connected through a third connecting part in adjacent areas of the first area and the intermediate area, and the third connecting part is arranged in the same layer as the first conductive part. Each of the first control signal test lines and each of the third control signal test lines are electrically connected through a fourth connecting part in adjacent areas of the second area and the intermediate area, and the fourth connecting part is arranged in the same layer as the first conductive part.

20. The display panel of claim 19, wherein, The data signal test line comprises at least one first data signal test line and at least one second data signal test line arranged along the extension direction of the data line, the first data signal test line is configured to transmit a first data signal to odd-numbered columns of the data line, and the second data signal test line is configured to transmit a second data signal to even-numbered columns of the data line.

21. The display panel of claim 20, wherein, The display panel further comprises a first gate signal test pad, a first data signal test pad and a first common signal test pad located on one side of the chip bonding area along the extending direction of the gate lines, and a control signal test pad, a second gate signal test pad, a second data signal test pad and a second common signal test pad located on the other side of the chip bonding area along the extending direction of the gate lines; The display panel further comprises a plurality of input pads located in the chip bonding area and away from the display area, and a common signal line arranged around the display area and in the same layer as the gate lines; the common signal line comprises a common wire entering the chip bonding area from both sides of the chip bonding area along the extending direction of the gate lines and located between the test switch circuit and the input pads; The control signal test pad is electrically connected to each of the third control signal test lines through a fourth wire, the first gate signal test pad is electrically connected to the first gate signal test lines through a fifth wire, the second gate signal test pad is electrically connected to the second gate signal test lines through a sixth wire, the first data signal test pad is electrically connected to each of the first data signal test lines through a seventh wire, the second data signal test pad is electrically connected to the second data signal test lines through an eighth wire, and the first common signal test pad and the second common signal test pad are both electrically connected to the common wire; The fourth wire and the seventh wire are arranged in the same layer as the gate lines, and the fifth wire and the sixth wire are arranged in the same layer as the data lines; The fourth wire, the sixth wire, the eighth wire and the common wire are arranged in the extending direction of the data lines in the edge region of the second area in sequence, the eighth wire and the common wire are jumper designed in the edge region of the second area, the eighth wire in the jumper region is arranged in the same layer as the first conductive part, and the eighth wire in the non-jumper region is arranged in the same layer as the data lines. The display panel comprises any one of the display panels according to claims 1-21.

22. A display device comprising: ​

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