Beam-controlled laser device and its manufacturing method

Abstract

A vertical-cavity surface-emitting laser (VCSEL) includes a substrate, a first reflector structure formed above a first surface of the substrate, and a second reflector structure formed above the first surface of the substrate. Furthermore, a multi-junction active region is formed above the first surface of the substrate between the first reflector structure and the second reflector structure. The multi-junction active region includes multiple quantum well (MQW) regions and multiple oxide layers, each of which includes a peripheral region and an aperture region. The peripheral region surrounds the aperture region. A stress field of at least 2 gigapascals is achieved at the edge between the peripheral region and the aperture region.

Description

Technical Field

[0001] This disclosure relates primarily to semiconductor-based lasers and methods for manufacturing the same. Background Technology

[0002] Figure 1 A schematic diagram of a typical vertical-cavity surface-emitting laser (VCSEL) 100 is shown. The VCSEL 100 includes a p-type distributed Bragg reflector (DBR) 105 at the top and an n-type DBR 110 similarly at the bottom.

[0003] The reflector structure (e.g., DBR or DBR mirrors 105 and 110) is based on an AlGaAs / GaAs material system. That is, each of the DBR mirrors 105 and 10 includes alternating layers. The first layer 112 may be an aluminum gallium arsenide (AlGaAs) layer, and the second layer 114 may be a gallium arsenide (GaAs) layer.

[0004] VCSEL 100 may include an active region consisting primarily of pin junctions, which may include multiple quantum wells (MQWs) that generate photons. Figure 1 An MQW or MQW layer 120 is shown. Electrical and optical confinement in the VCSEL 100 is achieved using an oxide layer 130, which may be positioned or placed above (and sometimes below) the active region. The oxide layer 130 is typically an aluminum oxide layer (Al2O3). The oxide layer 130 may include an opening region 150. The opening region 150 may be formed of a semiconductor layer or material.

[0005] These layers are typically grown on GaAs substrate 140 using metal-organic chemical vapor deposition (MOCVD) technology.

[0006] like Figure 1 As shown, an ohmic contact at the top (also known as anode 165) and an ohmic contact at the bottom (also known as cathode 160) are positioned to inject current into the device.

[0007] VCSEL 100 can be configured to emit beam 170.

[0008] Figure 1 The axes depicted in the figure show the typical directions in which the epitaxial layer is grown and on which it is based. In other words, the

[001] direction (e.g., the Z-axis) represents the growth direction, while the

[110] direction (e.g., the X-axis) and [1-10] (e.g., the Y-axis) are the directions typically used to manufacture VCSEL 100.

[0009] One challenge with VCSELs (such as VCSEL 100) is the difficulty in controlling the beam divergence. For example, for most automotive laser imaging, detection, and ranging (LIDAR) applications, a small divergence angle is desirable so that most of the output power is imaged over a small occupied area. However, for large-aperture VCSELs, the divergence angle is often quite large, mainly due to the excitation of higher-order lateral modes.

[0010] Similarly, a similar phenomenon was observed as the bias current injected into the VCSEL increased, mainly due to enhanced current crowding around the oxide layer edges. Attached Figure Description

[0011] In the accompanying drawings, the same reference numerals generally refer to the same parts in different views. These drawings are not necessarily drawn to scale, but rather generally emphasize the principles of this disclosure. In the following description, various aspects of this disclosure are described with reference to the following drawings, in which: Figure 1 A schematic diagram of a typical vertical-cavity surface-emitting laser is shown. Figure 2 A schematic diagram depicting the formation of an oxide layer using an oxidation process is shown. Figure 3 and Figure 4 Each shows a partial view of the alumina layer; Figure 5 and Figure 6 Each shows a partial view of another alumina layer; Figure 7A and Figure 7B This is an example of a single-node VCSEL; Figure 8 An example of a multi-junction VCSEL is shown; Figures 9A to 9C Each example of a multi-junction VCSEL is shown; Figures 10A to 10C Each example of a multi-junction VCSEL is shown; Figure 11 A flowchart of a method according to at least one aspect of this disclosure is shown. Detailed Implementation

[0012] The following detailed description refers to the accompanying drawings, which illustrate by way of illustration specific details and aspects in which the present disclosure may be practiced. One or more aspects are described in sufficient detail to enable those skilled in the art to practice the present disclosure. Other aspects may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The aspects described herein are not necessarily mutually exclusive, as some aspects may be combined with one or more other aspects to form new aspects. Multiple aspects are described in conjunction with methods, and multiple aspects are described in conjunction with apparatus. However, it is understood that the aspects described in conjunction with methods can be similarly applied to apparatus, and vice versa. Throughout the drawings, it should be noted that the same reference numerals are used to depict the same or similar elements, features, and structures. Throughout the drawings, it should be noted that these scales are not necessarily proportional, and the dimensions of features are emphasized for ease of illustration.

[0013] Figure 2 A schematic diagram is shown, for example, of creating or forming an alumina (Al2O3) layer for VCSELs by wet thermal oxidation.

[0014] Prior to the oxidation process, layer 210 may be used or provided, for example, a native semiconductor material or layer 210. This layer 210 may be provided with one or more spacer layers 205. Layer 210 may have a high aluminum content, for example, it may be at least 98% aluminum. In one case, layer 210 may be or include aluminum gallium arsenide, for example, in Al form. x Ga 1-x The form is As, where 0.98 ≤ x < 1. In another case, layer 210 may be or include aluminum arsenide (AlAs).

[0015] The spacer layers 205 located on top of and at the bottom of layer 210 are based on AlGaAs but have a lower Al content (such as 0.9 or lower).

[0016] As shown in the figure, for both scenarios, at least an oxidation process is applied to the semiconductor layer or material 210 to form an oxide layer.

[0017] For the oxidation process, high-temperature steam (e.g., greater than 340°C) is injected from the sidewalls of the mesa, thereby forming alumina (Al2O3) along the

[110] and [1-10] directions. However, it has been recognized (e.g., see Advances in Selective Wet Oxidation of AlGaAs Alloys, IEEE Quantum Electronics Proceedings, 3(3), 600-608) that when alumina is formed, its thickness and volume are reduced to some extent compared to the natural material before oxidation.

[0018] Layers or materials 220a and 230a are produced by an oxidation process applied to layer 210 (i.e., the aluminum gallium arsenide (AlGaAs) layer). In other words, layer 220a is an aluminum oxide layer produced by the oxidation of aluminum gallium arsenide, while layer 230a represents the residual aluminum gallium arsenide remaining after the oxidation process has occurred.

[0019] Similarly, when layer 210 is an aluminum arsenide (AlAs) layer, layers or materials 220b and 230b are produced by an oxidation process applied to layer 210. More specifically, layer 220b is an alumina layer produced by the oxidation of the aluminum arsenide material, while layer 230b represents the residual aluminum arsenide remaining after the oxidation process is completed.

[0020] It has been recognized that alumina formed from AlGaAs shrinks by approximately 3% to 6%, while alumina formed from AlAs shrinks by approximately 13%. For example, Figure 3 and Figure 4 Enlarged cross-sectional views and enlarged top views of the aluminum oxide layer 220a formed by the oxidation of aluminum gallium arsenide are shown respectively.

[0021] Figure 5 and Figure 6 Enlarged cross-sectional views and enlarged top views of the alumina layer 220b formed from aluminum arsenide are shown respectively.

[0022] refer to Figure 3 and Figure 4 The shrinkage caused by the oxidation process creates a stress field 270a at the periphery or edge of the oxide layer 220a.

[0023] Similarly, refer to Figure 5 and Figure 6 The shrinkage caused by the oxidation process generates a stress field 270b at the periphery or edge of the oxide layer 220b.

[0024] In both cases, stress fields 270a and 270b are located at the interface between the oxide layer edges (220a, 220b) and the corresponding aperture regions (230a, 230b). In both cases, residual unoxidized native semiconductor material forms the aperture regions, which are surrounded by the formed oxide layer.

[0025] Although the formation of oxide layer 220a and oxide layer 230 each generates a corresponding stress field, the magnitudes of these stress fields are different. (Visual comparison is possible.) Figure 3 and Figure 4 The stress field 270a and Figure 5 and Figure 6As can be seen from the stress field 270b, the amplitude of the stress field 270b formed at the (inner) edge of the aluminum oxide layer 220b (formed of aluminum arsenide) is significantly greater than that of the stress field 270a formed at the (inner) edge of the aluminum oxide layer 220a (formed of aluminum gallium arsenide). This difference in stress field intensity occurs because the oxide layer 220b formed of aluminum arsenide (AlAs) rather than aluminum gallium arsenide undergoes a larger or more significant contraction.

[0026] The influence and interaction of this stress field can significantly affect the electro-optic properties of VCSELs. For example, see... Figure 1 With VCSEL 100, the stress field may affect the divergence angle of the beam emitted from the VCSEL in the far field at 170°.

[0027] Figure 7A An example of a single-junction VCSEL 700a is shown. Figure 7B An example of a single-junction VCSEL 700b is shown. Single-junction VCSELs 700a and 700b can be used with... Figure 1 The VCSEL 100 is formed or implemented in a similar manner, except for the oxide layer. In particular, the VCSEL 700a includes an oxide layer 130a formed on aluminum gallium arsenide (AlGaAs), and... Figure 3 and Figure 4 The oxide layer 220a is similar to or the same as the oxide layer 220a.

[0028] VCSEL 700b includes an oxide layer 130b formed of aluminum arsenide (AlAs), similar to... Figure 5 and Figure 6 The oxide layer 220b. Therefore, the VCSEL 700a includes a stress field 135a similar to the stress field 170a presented by the oxide layer 220a, and is therefore located at at least the (inner) edge of the oxide layer 130a.

[0029] VCSEL 700b includes a stress field 135b, similar to the stress field 170a presented by the oxide layer 220b. The stress field 170a can therefore also be located at least at the edge of the oxide layer 130b, which can be the inner periphery or inner periphery region of the oxide layer 130b. This inner periphery region can be formed around the opening region 150. In this case, the opening region 150 can be made substantially of aluminum and arsenic (e.g., aluminum arsenide).

[0030] Therefore, VCSELs 700a and 700b emit light or beams with different divergence angles. In particular, VCSEL 700a has beam 170a, which has a wider (far-field) divergence angle. For example, at a given far-field distance, the width or diameter of the generated beam 170a is X. At the same far-field distance, the width or diameter of beam 170b is X', which can be substantially smaller than X, for example, 20% to 30% smaller.

[0031] Figure 7A The stress field 135a is shown around the edge of oxide layer 130a and at the interface between oxide layer 130a and aperture region 150. In this case, stress field 130a can be considered relatively small, such that the interaction with the optical field or optical cavity of VCSEL does not affect the wider divergence angle generated by emitted beam 170a.

[0032] exist Figure 7B In this process, stress field 135b also appears around the edge of oxide layer 130b, for example, at the interface between the periphery of aluminum oxide layer 130b and opening region 150. As previously described, aluminum oxide layer 130b includes an (inner) peripheral region that can surround opening region 150. Stress field 135 can exist between the peripheral region and opening region.

[0033] In this case, the stress field 135b is much stronger and therefore exhibits much stronger stress, such as Tresca stress. In at least one example, the stress amplitude can reach 3 gigapascals (GPa). This stronger stress field 135b interacts with the light field to a much greater extent, resulting in a narrower divergence angle for the emitted beam 170b.

[0034] Therefore, for single-junction VCSELs, the formation of an oxide layer with a strong stress field can have a significant or obvious impact on the far-field divergence angle of the emitted light.

[0035] However, in the case of multi-junction VCSELs, beam divergence or beam divergence control becomes a problem. Figure 8 A multi-junction VCSEL 800 is depicted. The VCSEL 800 can be similar to the VCSEL 100, except that multiple junctions are present. Thus, the VCSEL 800 includes a multi-junction active region having multiple sets or portions, wherein each set or portion includes an oxide layer 130a, an aperture region 150 located within the oxide layer 130, an MQW 120, and a tunnel junction 125.

[0036] The oxide layer 130a is an aluminum oxide layer formed from aluminum gallium arsenide.

[0037] For VCSEL 800, the cumulative effect of the stress field from multiple oxide layers 130a on the far-field divergence angle of the emitted light is minimal. In other words, other existing factors of VCSEL 800 have a greater overall impact on the far-field divergence angle.

[0038] For example, in this structure, the divergence angle can be significantly affected by the effective refractive index step. The transverse effective refractive index step depends on the configuration of the oxide aperture tips relative to each other. Different effective refractive index distributions can affect the divergence angle in different ways, for example, producing a wider or narrower divergence angle. Typically, such multi-junction VCSELs produce a more uncontrollable divergence angle.

[0039] Figures 9A to 9C VCSELs 900a to 900c are shown, which are different variations of the multi-junction VCSEL 800. Each of VCSELs 900a to 900c has an aluminum oxide layer 130a formed of aluminum gallium oxide as described herein. However, VCSELs 900a to 900c each have different lateral effective refractive index profiles (LEIP) 910a to 910c.

[0040] LEIP describes the effective refractive index variation of a waveguide or optical structure in the lateral or transverse direction. Effective refractive index is a measure of how light propagates through an optical structure, taking into account both the material's refractive index and the structure's geometry.

[0041] Figure 9A A VCSEL 900a with a square LEIP 910a is shown. The LEIP 910a is formed by the construction of oxide layers 130a aligned in the VCSEL 900a and corresponding openings 150. In particular, the peripheral regions or inner edges of each oxide layer 130a are perpendicularly aligned with each other in the

[001] direction.

[0042] Figure 9B Another VCSEL 900b is shown, which is associated with the LEIP 910b having a ramped platform shape. The oxide layer 130a and the corresponding opening 150 are in a non-vertically aligned configuration, which is consistent with... Figure 9A The situation is different for layer 130a.

[0043] On the contrary, Figure 9BAs the process moves vertically downwards from the uppermost oxide layer 130a along the

[001] direction, the edges of the continuous oxide layers 130a diffuse further relative to the higher oxide layers 130a above or adjacent to them in the

[001] direction. This diffusion occurs laterally along the

[110] direction. That is, as the process moves vertically downwards from the anode 165 to the cathode 160, the opening 150 becomes larger or longer laterally (in the

[110] direction), resulting in a tilted LEIP 910b.

[0044] Figure 9C Another VCSEL 900c associated with the LEIP 910c is shown. In this example, the oxide layer 130a and the corresponding opening 150 are also misaligned, which is consistent with... Figure 9A The oxide layers are different.

[0045] In this case, starting from the uppermost oxide layer 130a (the oxide layer closest to the anode 165) and moving vertically downward along the

[001] direction, the edge of oxide layer 130a further diffuses laterally along the

[110] direction. However, after reaching a certain amount, oxide layer 130a begins to close laterally or tighten to a certain point, and then begins to diffuse laterally.

[0046] In other words, along the vertical direction from anode 165 to cathode 160, opening 150 repeatedly lengthens and shortens laterally (in the

[110] direction) to produce LEIP 910c.

[0047] However, in each of these cases or in VCSELs 900a to 900c, the divergence of the emitted light 170 may still be too large and undesirable, for example, greater than 35 degrees.

[0048] Figures 10A to 10C VCSELs 1000a to 1000c according to various aspects of this disclosure are shown respectively. VCSELs 1000a to 1000c are multi-junction VCSELs, similar to VCSEL 800, except that they include an aluminum oxide layer 130b, which is formed by using an oxidation process (e.g., a wet oxidation process) using aluminum arsenide as the native semiconductor layer, as described in the embodiments herein.

[0049] VCSELs 1000a to 1000c each have LEIPs 1010a to 1010c corresponding to LEIPs 910a to 910c. That is, LEIP 1010a of VCSEL 1000a is the same as or similar to LEIP 910a of VCSEL 900a. Furthermore, LEIPs 1010b and 1010c of VCSELs 1000b and 1000c are the same as or similar to LEIPs 910b and 910c of VCSELs 900b and 900c, respectively.

[0050] Therefore, for VCSEL 1000a, the configuration of its alumina layer 130b is similar to that of VCSEL 900a's oxide layer 130a, thus producing a square LEIP 1010a.

[0051] However, the emitted light 170 of VCSEL 1000a can achieve a much smaller divergence or a smaller divergence angle than the corresponding light emitted from VCSEL 900a.

[0052] For VCSEL 1000b, the alumina layer 130b has a configuration similar to that of the oxide layer 130a in VCSEL 900b. Therefore, VCSEL 1000b has a LEIP1010b with a ramp platform shape similar to that of LEIP 910b in VCSEL 900b.

[0053] Similar to VCSEL 1000a, the emitted light 170 produced by VCSEL 1000b has a smaller divergence or divergence angle compared to the emitted light 170 of VCSEL 900b.

[0054] Furthermore, for VCSEL 1000c, the configuration of the alumina layer 130b is similar to that of the oxide layer 130a in VCSEL 900b. Therefore, VCSEL 1000c has a LEIP 1010c comparable to that of VCSEL 900b's LEIP 910c. Similarly, in this case, the emitted light 170 produced by VCSEL 1000c has a smaller divergence or divergence angle compared to the emitted light from VCSEL 900c.

[0055] Without being bound by theory, VCSELs 1000a to 1000c can achieve a reduced or narrower divergence angle of their emitted light or beam 170 by means of the stress field 135b generated by the alumina layer 130b.

[0056] The stress field 135b has a strong interaction with the optical modes inside (e.g., inside the cavity) of VCSELs 1000a to 1000c. This strong interaction can consistently result in a narrower divergence angle for the emitted light 170. Furthermore, the stress field interaction can neutralize the effect of the effective refractive index step distribution on the variation of the divergence angle.

[0057] In short, by combining or using oxide layers that have or generate strong stress fields, VCSELs 1000a to 1000c and their other variants can experience smaller or narrower (far-field) divergence angles.

[0058] The stress field generated by the oxide layer 130b of VCSEL 1000a to 1000c can have an intensity of at least 2 gigapascals (GPa), for example, 2 GPa to 3 GPa, or in some instances 3 GPa or greater.

[0059] In contrast, VCSELs 900a to 900c or other similar VCSELs with an oxide layer 135a exhibit a weaker stress field. Typically, the aluminum oxide layer 135a (e.g., made of aluminum gallium arsenide) can generate a stress field with an intensity of less than 1 GPa.

[0060] Typically, the stress field of the oxide layer described herein can have varying intensities due to the contraction changes experienced during oxide layer formation. For example, in aluminum gallium arsenide (Al₂O₃) oxide layers... x Ga 1-x As, where 0.98≤x<1), the oxide layer 130a formed undergoes approximately five percent (5%) of volume or thickness shrinkage.

[0061] In contrast, the oxide layer 130b formed on or based on aluminum arsenide (AlAs) experiences a volume or thickness shrinkage of approximately twelve percent (12%). This greater shrinkage or contraction generates a stronger stress field, which in turn can result in a narrower divergence or divergence angle.

[0062] For example, for a single-junction VCSEL, such as Figure 7A The VCSEL 700a depicted in the image has an aluminum oxide layer 130a formed of aluminum gallium arsenide, resulting in a far-field divergence angle greater than 25 degrees. This divergence angle may be too high for many applications. Similarly, for multi-junction VCSELs (such as...) Figures 9A to 9C The far-field divergence angle of the VCSEL depicted in the image is also greater than 35 degrees, which is also too high.

[0063] In contrast, single-junction VCSELs using oxide layers that generate high stress fields (at least 2 GPa) can produce smaller divergence or divergence angles.

[0064] Single-junction VCSEL 700b (such as those that generate high stress fields) Figure 7B The VCSEL shown, including the oxide layer 130b, allows the emitted light 170 of the VCSEL 700b to have a divergence angle of less than 20 degrees. This improved and narrower divergence angle is a result of the aluminum oxide layer 130b (formed from AlAs), which generates a high stress field and interacts with and influences the light field within the VCSEL 700b.

[0065] Similarly, multi-junction VCSELs (such as multi-junction VCSELs 1000a to 1000c) that include multiple oxide layers 130b generating a high stress field (e.g., at least 2 GPa) also result in a smaller far-field divergence angle for the emitted light 170. For example, for multi-junction VCSELs 1000a to 1000c, each can have a far-field divergence angle of less than 20 degrees. The narrower divergence angle is due to the fact that the alumina layer 130b is formed from AlAs.

[0066] Figure 11 Method 1100, according to at least one example of the present disclosure, is illustrated. Method 1100 is for forming a vertical cavity surface-emitting laser (VCSEL) and includes: providing a substrate at 1110.

[0067] At 1120, method 1100 includes: forming a first reflector structure above a first surface of a substrate; and at 1130, the method includes: forming a second reflector structure above the first surface of a substrate.

[0068] At 1140, method 1100 includes: forming a multi-junction active region formed above a first surface of a substrate between a first reflector structure and a second reflector structure.

[0069] The method of forming a multi-junction active region at 1140 further includes forming a plurality of multiple quantum well (MQW) regions at 1150, and the method includes forming a plurality of oxide layers at 1160, each of the plurality of oxide layers including a peripheral region and an aperture region, wherein the peripheral region surrounds the aperture region, and wherein the edge between the peripheral region and the aperture region is a stress field of at least 2 gigapascals.

[0070] Any aspect, example, and / or implementation described herein may be combined appropriately or suitablely.

[0071] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any example or design described as “exemplary” in this document is not necessarily to be construed as preferred or advantageous over other examples or designs.

[0072] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0073] In this disclosure, references to "one embodiment" or "an embodiment" mean that a specific feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. The appearance of the phrase "in one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. The appearance of the phrases "for example," "in one example," or "in some examples" does not necessarily refer to the same example.

[0074] The terms "multiple" and "many" in the specification or claims explicitly refer to a quantity greater than one. The terms "group," "set," "cluster," "series," "sequence," "grouping," etc., and similar terms in the specification or claims refer to a quantity equal to or greater than one, i.e., one or more. Any term expressed in plural form but not explicitly stating "multiple" or "many" also refers to a quantity equal to or greater than one.

[0075] The term “connection” can be understood as (e.g., mechanical, optical, and / or electrical) connection and / or interaction, such as direct or indirect connection and / or interaction. For example, several elements can be mechanically connected together such that they are physically held together (e.g., a plug is connected to a socket) and electrically connected together such that they have a conductive path (e.g., a signal path exists along a communication chain).

[0076] As used herein, unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” “third,” etc., to describe common objects merely indicates that different instances of the same kind of object are being referenced, and is not intended to imply that the objects described in this way must be in a given sequence in chronological, spatial, rank, or any other manner.

[0077] As used herein, the terms “module,” “component,” “system,” “circuit,” “element,” “slice,” “circuit system,” and similar terms are intended to refer to a collection of one or more electronic components, computer-related entities, hardware, software (e.g., in execution), and / or firmware. For example, a circuit or similar term can be a processor, a process running on a processor, a controller, an object, an executable program, a storage device, and / or a computer having processing power. By way of illustration, an application running on a server and a server can also be a circuit. One or more circuits may reside within the same circuit, and circuits may be localized on a single computer and / or distributed across two or more computers. A collection of elements or other circuits may be described herein, wherein the term “collection” can be interpreted as “one or more.”

[0078] Such electrical or electronic circuits can be operated by a software application or firmware application executed by one or more processors. The one or more processors can be internal or external to the device and can execute at least a portion of the software or firmware application. As another example, a circuit can be a device that provides specific functionality through electronic components without having mechanical parts; the electronic components can include one or more processors to execute executable instructions stored in a computer-readable storage medium and / or firmware, which at least partially endow the electronic components with functionality. As yet another example, a circuit or similar term can be implemented in hardware such as application-specific integrated circuits (ASICs), programmable gate arrays (PGAs), discrete digital circuits, etc., or in a combination of hardware and software (e.g., a software model executed by a corresponding processor).

[0079] The term “semiconductor substrate” can mean any structure that includes semiconductor materials, such as a silicon substrate with or without an epitaxial layer, a silicon-on-insulator substrate containing a buried insulating layer, or a substrate with a silicon-germanium layer.

[0080] The lateral direction is understood to mean, in particular, the direction parallel to the main extending surface of the component (especially the layer). The vertical direction is understood to mean, in particular, the direction perpendicular to the orientation of the main extending surface of the component and / or layer. The vertical and lateral directions are substantially orthogonal to each other.

[0081] Furthermore, spatial relative terms (such as “below,” “under,” “lower,” “above,” “upper,” and similar terms) may be used herein to facilitate the description of the relationship between an element or feature and other elements or features shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0082] As used herein, the term "data" can be understood to include information in any suitable analog or digital form, such as as a file, a portion of a file, a collection of files, a signal or stream, a portion of a signal or stream, a collection of signals or streams, etc. Furthermore, the term "data" can also be used to refer to information, such as in the form of a pointer. However, the term "data" is not limited to the examples above and can take various forms and represent any information as understood in the art.

[0083] As used herein, a signal that "indicates" a value or other information can be a digital or analog signal that is encoded or otherwise conveys the value or other information in a manner that can be decoded by a receiving component and / or cause a response action. The signal may be stored in or buffered in a computer-readable storage medium before being received by the receiving component, and the receiving component may retrieve the signal from the storage medium. Furthermore, a "value" that "indicates" a quantity, state, or parameter may be physically implemented as a digital signal, analog signal, or stored bits that encode or otherwise convey the value.

[0084] Unless otherwise stated, the terms “approximately” and “substantially” as used herein should be interpreted as referring to normal measurement and / or manufacturing limitations related to the value or condition modified by the terms “approximately” or “substantially”. Unless otherwise expressly stated, the term “implementation” is used herein to refer to embodiments of this disclosure.

[0085] As used herein, a signal can be transmitted or conducted through a signal chain, where it is processed to alter characteristics such as phase, amplitude, and frequency. Even when these characteristics are modified, the signal can still be referred to as the same signal. Generally, a signal can be considered the same signal as long as it continues to encode the same information. For example, a transmitted signal can be considered to refer to a transmitted signal in baseband, intermediate frequency, and radio frequency.

[0086] Although the above description and related figures may depict the device components as separate elements, those skilled in the art will understand the various possibilities of combining or integrating discrete features and functions into a single element. This may include combining two or more components into a single component. Conversely, those skilled in the art will recognize the possibility of separating a single element into two or more discrete elements, such as splitting a single component into two or more separate components.

[0087] It should be understood that the implementation of the methods detailed herein is exemplary in nature and is therefore to be understood as being capable of being implemented in the corresponding apparatus. Similarly, it should be understood that the implementation of the apparatus detailed herein is to be understood as being capable of being implemented as the corresponding methods. Therefore, it should be understood that the apparatus corresponding to the methods detailed herein may include one or more components configured to perform each aspect of the relevant methods.

[0088] All abbreviations defined in the above description also apply to all claims included herein.

[0089] While embodiments of this disclosure have been described above, it will be apparent that other embodiments can be implemented. For example, other embodiments may include any sub-combination of the features recited in the claims or any sub-combination of the elements described in the foregoing examples. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.

[0090] While this disclosure has been specifically shown and described with reference to particular embodiments, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims. Therefore, the scope of this disclosure is indicated by the appended claims and is thus intended to cover all changes falling within the meaning and scope of equivalents of the claims.

[0091] List of reference numerals

[0092] 100 VCSEL

[0093] 105 p-type DBR

[0094] 110 n-type DBR

[0095] The first layer of 112 105

[0096] The second layer of 114 and 105

[0097] 120 MQW layers

[0098] 125 Tunnel Joint

[0099] 130, 130a, 130b oxide layers

[0100] Stress fields at 135a and 135b

[0101] 140 substrate

[0102] 150 opening area

[0103] 160 Cathode

[0104] 165 Anode

[0105] Beams 170, 170a, and 170b

[0106] 205 Spacer

[0107] 210th floor

[0108] 220a oxide layer

[0109] 220b oxide layer

[0110] 230a Residual material / Opening area

[0111] 230b Residual material / Opening area

[0112] Stress fields of 270a and 270b

[0113] 700a, 700b VCSEL

[0114] 800 VCSEL

[0115] 900a, 900b, 900c VCSEL

[0116] 910a, 910b, 910c Lateral Effective Refractive Index Distribution (LEIP)

[0117] 1000a, 1000b, 1000c VCSEL

[0118] 1010a, 1010b, 1010c Lateral Effective Refractive Index Distribution (LEIP)

[0119] Method 1100.

Claims

1. A vertical-cavity surface-emitting laser (VCSEL), comprising: Substrate; A first reflector structure is formed above a first surface of the substrate; A second reflector structure is formed above the first surface of the substrate; A multi-junction active region is formed above the first surface of the substrate between the first reflector structure and the second reflector structure, the multi-junction active region comprising: Multiple quantum well (MQW) regions; Multiple oxide layers, each including a peripheral region and an opening region, wherein the peripheral region surrounds the opening region, and wherein the edge between the peripheral region and the opening region is a stress field of at least 2 gigapascals.

2. The VCSEL according to claim 1, wherein, The peripheral region of each of the plurality of oxide layers includes aluminum oxide.

3. The VCSEL according to claim 1, wherein, The open-pore region of each of the plurality of oxide layers comprises aluminum and arsenic.

4. The VCSEL according to claim 3, wherein, The open-pore region of each of the plurality of oxide layers is substantially aluminum arsenide.

5. The VCSEL according to any one of claims 1 to 4, wherein, The plurality of said multi-junction active regions have a plurality of sets or portions, wherein each set or portion includes an oxide layer.

6. The VCSEL according to any one of claims 1 to 4, wherein, The multi-junction active region includes multiple tunnel junction regions.

7. The VCSEL according to claim 6, wherein, The multi-junction active region includes alternating portions of the tunnel junction region, the oxide layer, and the MQW region.

8. The VCSEL according to claim 7, wherein, The alternating portions of the multi-junction active region alternate along the emission direction of the VCSEL, and the emission region is perpendicular to the first surface of the substrate.

9. The VCSEL according to any one of claims 1 to 4, wherein, The substrate includes a semiconductor substrate.

10. The VCSEL according to claim 9, wherein, The semiconductor substrate is a gallium arsenide substrate.

11. The VCSEL according to any one of claims 1 to 4, in, The first mirror structure includes a first distributed Bragg reflector (DBR) having a first conductivity type, and The second mirror structure includes a second DBR having a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type.

12. The VCSEL according to claim 11, wherein, The first DBR and / or the second DBR comprises alternating layers of aluminum gallium arsenide (AlGaAs) and gallium arsenide (GaAs).

13. The VCSEL according to any one of claims 1 to 4, wherein, From a view of the first surface facing the substrate, at least two of the aperture regions in the plurality of oxide layers of the multi-junction region are misaligned.

14. The VCSEL according to any one of claims 1 to 4, further comprising: An anode is disposed on the first surface of the substrate and on or above the first reflector structure; as well as A cathode is disposed on or above a second surface of the substrate, the second surface being opposite to the first surface of the substrate.

15. The VCSEL according to any one of claims 1 to 4, wherein, The stress field is at least 3 gigapascals.

16. The VCSEL according to any one of claims 1 to 4, wherein, The VCSEL has a beam divergence angle of less than 20 degrees.

17. A method for forming a vertical-cavity surface-emitting laser, the method comprising: Provide substrate; A first reflector structure is formed above a first surface of the substrate; A second reflector structure is formed above the first surface of the substrate; as well as A multi-junction active region is formed above the first surface of the substrate between the first reflector structure and the second reflector structure, comprising: Multiple quantum well (MQW) regions are formed, and Multiple oxide layers are formed, each of the multiple oxide layers including a peripheral region and an opening region, wherein the peripheral region surrounds the opening region, and wherein the edge between the peripheral region and the opening region is a stress field of at least 2 gigapascals.

18. The method according to claim 17, wherein, Forming each of the plurality of oxide layers includes: forming the peripheral region and the opening region from a first layer comprising aluminum arsenide.

19. The method according to claim 18, wherein, Forming the peripheral region and the opening region from the first layer includes applying an oxidation process to the first layer.

20. The method according to claim 19, wherein, Applying the oxidation process includes applying a wet oxidation process to the first layer.

21. The method according to claim 18, wherein, An oxidation process is applied to form the peripheral region and the opening region.

22. The method according to claim 21, wherein, The resulting outer region is primarily composed of aluminum oxide.

23. The method according to claim 21, wherein, The size of the resulting outer region is smaller compared to the first layer.

24. The method according to claim 23, wherein, The thickness or width of the formed peripheral region is reduced by at least 10% compared to the thickness or width of the first layer.

25. The method according to any one of claims 17 to 24, wherein, The opening area essentially comprises aluminum arsenide.

26. The method according to any one of claims 17 to 24, in, Forming the first mirror structure includes: forming a first distributed Bragg reflector (DBR) having a first conductivity type, and The formation of the second mirror structure includes: forming a second DBR having a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type.

27. The method according to any one of claims 17 to 24, wherein, Forming the multi-junction active region further includes forming a plurality of tunnel junction regions, such that the multi-junction active region includes alternating portions of the tunnel junction regions, the oxide layer, and the MQW region.

28. The method according to any one of claims 17 to 24, further comprising: An anode is formed on or above the first surface of the substrate, and the anode is disposed on or above the first reflector structure; as well as A cathode is formed on or above a second surface of the substrate, the second surface being opposite to the first surface of the substrate.

29. The method according to any one of claims 17 to 24, wherein, The substrate includes a semiconductor substrate.

30. The method according to claim 29, wherein, The semiconductor substrate is a gallium arsenide substrate.

31. The method according to any one of claims 17 to 24, wherein, From a view of the first surface facing the substrate, at least two of the aperture regions in the plurality of oxide layers of the multi-junction region are misaligned.

32. The method according to any one of claims 17 to 24, wherein, The stress field is at least 3 gigapascals.

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