Switching converter controller with adaptive slope compensation

Abstract

A system (100) includes: a power stage (106) having a first terminal (108), a second terminal (110), a third terminal (112), and a fourth terminal (114); and a controller (148) having a first terminal (149), a second terminal (150), a third terminal (151), a fourth terminal (152), and a fifth terminal (153). The first terminal (149) of the controller (148) is coupled to the fourth terminal (114) of the power stage (106). The second terminal (150) of the controller (148) is coupled to the third terminal (112) of the power stage (106). The third terminal (151) of the controller (148) is coupled to the first terminal (108) of the power stage (106). The fourth terminal (152) of the controller (148) is coupled to the second terminal (110) of the controller (106). The controller (106) includes an adaptive slope compensation circuit (168) configured to: obtain an input parameter (IN_P); adjust a scaling factor in response to the input parameter (IN_P); adjust a slope compensation current in response to the scaling factor; and output a slope compensation signal (I_ASC) in response to the adjusted slope compensation current.

Description

[0001] This application claims priority to U.S. Provisional Application No. 63 / 602,807, filed November 27, 2023, entitled "Novel Technique for SelfAdaptive Slope Compensation Circuit for Most Optimal Transient Performance Without External Components for DCDC Switching Converters," Agent's License No. T104015US01, which is incorporated herein by reference in its entirety. Background Technology

[0002] A switching converter is used to provide a direct current (DC) output voltage (VOUT) based on an input voltage (VIN). A typical switching converter includes a power stage with switches and inductors, and a controller for switching the power stage. The efficiency of a switching converter varies depending on the proper management of the switching control in response to changes in VIN, VOUT, load, operating frequency, and inductance. Controller mode shifts in response to load changes (e.g., from light load to heavy load, or from heavy load to light load) can cause problems, typically leading to inefficient operation and / or VOUT overshoot, undershoot, and other disturbances. Summary of the Invention

[0003] In one example, a system includes: a power stage having a first terminal, a second terminal, a third terminal, and a fourth terminal; and a controller having a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of the controller is coupled to the fourth terminal of the power stage. The second terminal of the controller is coupled to the third terminal of the power stage. The third terminal of the controller is coupled to the first terminal of the power stage. The fourth terminal of the controller is coupled to the second terminal of the controller. The controller includes an adaptive slope compensation circuit configured to: obtain input parameters; adjust a scaling factor in response to the input parameters; adapt a slope compensation current in response to the scaling factor; and output a slope compensation signal in response to the adapted slope compensation current.

[0004] In another example, a switch converter controller includes: a current sensing circuit system having a first terminal and a second terminal; an adaptive slope compensation circuit system having a first terminal and a second terminal, the second terminal of the adaptive slope compensation circuit system being coupled to the second terminal of the current sensing circuit system, and the adaptive slope compensation circuit system including a multiplier; a comparator having a first terminal, a second terminal, and a third terminal, the first terminal of the comparator being coupled to the second terminal of the current sensing circuit system and the second terminal of the adaptive slope compensation circuit system; and mode control logic having a first terminal and a second terminal, the first terminal of the mode control logic being coupled to the third terminal of the comparator.

[0005] In another example, a switch-converter controller includes: a current sensing circuit system; an adaptive slope compensation circuit system coupled to the current sensing circuit system; and a comparator coupled to both the current sensing circuit system and the adaptive slope compensation circuit system. The adaptive slope compensation circuit system includes an adjustable current source circuit system, a capacitor, and a switch. The adaptive slope compensation circuit system is configured to: obtain input parameters and a switch control signal; use the adjustable current source circuit system to adjust the slope compensation current in response to the input parameters; control the switch to adjust the charge on the capacitor in response to the adjusted slope compensation current and the switch control signal; and output a slope compensation signal based on the charge on the capacitor. Attached Figure Description

[0006] Figure 1 This is a diagram illustrating an example system.

[0007] Figure 2 This is a diagram illustrating another example system.

[0008] Figure 3A This is a diagram of an example adaptive slope compensation circuit system.

[0009] Figure 3B This is a timing diagram showing the slope compensation current and related control signals in the example.

[0010] Figure 4 This is a diagram of an example switch converter controller.

[0011] Figure 5 This is a schematic diagram of an example adaptive slope compensation circuit system.

[0012] Figure 6 This is a schematic diagram of the quadrant multiplier in Example 4.

[0013] Figure 7A This is a schematic diagram of an example current ripple tracker circuit.

[0014] Figure 7BThis is a diagram illustrating example current ripple tracking.

[0015] Figure 8 This is a flowchart illustrating the instance adaptive slope compensation method. Detailed Implementation

[0016] The same or other reference numerals are used in the accompanying drawings to denote the same or similar features. Such features may be the same or similar in function and / or structure.

[0017] Figure 1 This is a diagram illustrating an example system 100. System 100 includes a power supply 102, a power stage 106, an output capacitor COUT1, a load 142, and a controller 148. The power supply 102 has a terminal 104. The power stage 106 has a first terminal 108, a second terminal 110, a third terminal 112, a fourth terminal 114, a fifth terminal 116, and a sixth terminal 118. The output capacitor COUT1 has a first terminal and a second terminal. The load 142 has a first terminal 144 and a second terminal 146. The controller 148 has a first terminal 149, a second terminal 150, a third terminal 151, a fourth terminal 152, a fifth terminal 153, and a sixth terminal 154.

[0018] As shown in the figure, power stage 106 includes a high-side (HS) switch 120, a low-side (LS) switch 128, and an inductor 136, arranged as shown. In some instances, the HS switch 120, LS switch 128, and associated control circuitry are components of an integrated circuit (IC), while the inductor 136 is an external component relative to the IC. Figure 1 The component arrangement of power stage 106 is referred to as a buck converter topology, where the output voltage VOUT is lower than the input voltage VIN. In other instances, the topology of power stage 106 can be varied (e.g., it can use...). Figure 2 The boost converter topology in the diagram can be used, or a boost-buck converter topology can be used. Figure 1 In one example, HS switch 120 has a first terminal 122, a second terminal 124, and a control terminal 126. LS switch 128 has a first terminal 130, a second terminal 132, and a control terminal 134. In some examples, HS switch 120 may be a p-channel field-effect transistor (“PFET”) or an n-channel field-effect transistor (“NFET”), and LS switch 128 may be an NFET. Inductor 136 has a first terminal 138 and a second terminal 140.

[0019] The controller 148 includes a valley control circuit system 155, a peak control circuit system 160, a pulse frequency modulation (PFM) timer circuit system 164, an adaptive slope compensation (SC) circuit system 168, mode control logic 172, and a driver circuit system 184. The valley control circuit system 155 has a first terminal 156, a second terminal 157, and a third terminal 158. The peak control circuit system 160 has a first terminal 161, a second terminal 162, and a third terminal 163. The PFM timer circuit system 164 has a first terminal 165 and a second terminal 166. The adaptive slope compensation circuit system 168 has a first terminal 169, a second terminal 170, and a third terminal 171. The mode control logic 172 has a first terminal 173, a second terminal 174, a third terminal 176, a fourth terminal 179, a fifth terminal 180, and a sixth terminal 182. The driver circuit system 184 has a first terminal 186, a second terminal 188, a third terminal 190, and a fourth terminal 192.

[0020] The first terminal 108 of power stage 106 is coupled to the third terminal 151 of controller 148. The second terminal 110 of power stage 106 is coupled to the fourth terminal 152 of controller 148. The third terminal 112 of power stage 106 is coupled to the first terminal of output capacitor COUT1, the first terminal 144 of load 142, and the second terminal 150 of controller 148. The second terminal of output capacitor COUT1 is coupled to ground or a grounded terminal. The second terminal 146 of load 142 is coupled to ground or a grounded terminal. The fourth terminal 114 of power stage 106 is coupled to the first terminal 149 of controller 148. The fifth terminal 116 of power stage 106 is coupled to terminal 104 of power supply 102. Terminal 104 of power supply 102 is also coupled to the fifth terminal 153 of controller 148. The sixth terminal 118 of power stage 106 is coupled to ground or a grounded terminal. The sixth terminal 154 of controller 148 is also coupled to ground or a grounded terminal.

[0021] As shown in the figure, the first terminal 122 of HS switch 120 is coupled to the fifth terminal 116 of power stage 106. The second terminal 124 of HS switch 120 is coupled to the first terminal 130 of LS switch 128 and the first terminal 138 of inductor 136. The second terminal 140 of inductor 136 is coupled to the third terminal 112 of power stage 106. The control terminal 126 of HS switch 120 is coupled to the first terminal 108 of power stage 106. The second terminal 132 of LS switch 128 is coupled to the sixth terminal 118 of power stage 106. The control terminal 134 of LS switch 128 is coupled to the second terminal 110 of power stage 106. As shown in the figure, the fourth terminal 114 of the power stage is coupled to the switching node 135 between HS switch 120 and LS switch 128.

[0022] As shown in the figure, the first terminal 156 of the valley control circuit system 155 receives the control signal CS1. In some instances, CS1 includes a valley threshold and an inductor current sensing signal. In some instances, the valley threshold and / or the inductor current sensing signal undergoes a slope change. The first terminal 161 of the peak control circuit system 160 receives the control signal CS2. In some instances, CS2 includes a peak threshold and an inductor current sensing signal. The first terminal 165 of the PFM timer circuit system 164 receives the control signal CS3. In some instances, CS3 includes a control voltage (e.g., V_CTRL in this context). In some instances, V_CTRL is the error result between VOUT and a reference voltage (VREF). The first terminal 169 of the adaptive slope compensation circuit system 168 receives the input parameter IN_P. Instance input parameters include VIN, VOUT, L (the value of inductor 136), the switching frequency (FSW) of the power stage switch, the current sensing gain, and / or other input parameters. The second terminal 170 of the adaptive slope compensation circuit system 168 receives the switch control signal CS_S1. The third terminal 171 of the adaptive slope compensation circuit system 168 is coupled to the second terminal 157 of the valley control circuit system 155 and the second terminal 162 of the peak control circuit system 160.

[0023] The first terminal 173 of mode control logic 172 is coupled to the third terminal 158 of valley control circuit system 155. The second terminal 174 of mode control logic 172 is coupled to the third terminal 163 of peak control circuit system 160. The third terminal 176 of mode control logic 172 is coupled to the second terminal 166 of PFM timer circuit system 164. The fourth terminal 179 of mode control logic 172 receives the clock signal (CLK1). The fifth terminal 180 of mode control logic 172 is coupled to the first terminal 186 of driver circuit system 184. The sixth terminal 182 of mode control logic 172 is coupled to the second terminal 188 of driver circuit system 184. The third terminal 190 of driver circuit system 184 is coupled to the third terminal 151 of controller 148. The fourth terminal 192 of driver circuit system 184 is coupled to the fourth terminal 152 of controller 148.

[0024] In operation, controller 148 is configured to: receive VIN1 at its fifth terminal 153; and receive VIN1 at its first terminal 149. SW1 ; receives VOUT1 at its second terminal 150; responds to VIN1, V SW1The operation of VOUT1, the adaptive slope compensation circuit system 168, the valley control circuit system 155, the peak control circuit system 160, the PFM timer circuit system 164, the mode control logic 172, and the driver circuit system 184 provides HS_CS at its third terminal 151; and in response to VIN1, V SW1 The operation of VOUT11, adaptive slope compensation circuitry 168, valley control circuitry 155, peak control circuitry 160, PFM timer circuitry 164, mode control logic 172, and driver circuitry 184 is provided at its fourth terminal 152 as LS_CS. In some instances, the controller 148 supports modes including pulse width modulation (PWM) mode and PFM mode. In some instances, valley control circuitry 155, peak control circuitry 160, and PFM timer circuitry 164 can provide the controller 148 with corresponding independent control options (i.e., only one of valley control circuitry 155, peak control circuitry 160, and PFM timer circuitry 164 is active). In other instances, valley control circuitry 155, peak control circuitry 160, and PFM timer circuitry 164 can provide different combinations of control options. In one instance, valley control circuitry 155 and peak control circuitry 160 are both active. In another example, the valley control circuit system 155 and the PFM timer circuit system 164 are both active. In another example, the peak control circuit system 160 and the PFM timer circuit system 164 are both active. In yet another example, the valley control circuit system 155, the peak control circuit system 160, and the PFM timer circuit system 164 are all active.

[0025] In operation, power stage 106 is configured to: receive VIN1 at its fifth terminal 116; receive HS_CS at its first terminal 108; receive LS_CS at its second terminal 110; provide VOUT1 at its third terminal 112 in response to VIN1, HS_CS, and LS_CS; and provide VOUT1 at its fourth terminal 114 in response to VIN1, HS_CS, and LS_CS. SW1More specifically, HS switch 120 couples VIN1 to switching node 135 in response to HS_CS, which increases the current in inductor 136. LS switch 128 couples the sixth terminal 118 to switching node 135 in response to LS_CS, which decreases the current in inductor 136. The average current in inductor 136 is considered as the load current (I_out1) supplied to load 142. In some instances, VIN1 can be 2.5 V to 40 V, and VOUT1 can be 0.3 V to 6 V. In some instances, I_out1 can be 0 A to 1 A during PFM mode. During PWM mode, I_out1 can be 0 A to 10 A.

[0026] Figure 2 This is a diagram illustrating another example system 200. Compared to system 100, system 200 has a boost converter topology instead of a buck converter. System 200 includes a power supply 202, a power stage 206, an output capacitor COUT2, a load 242, and a controller 248. Power supply 202 has terminal 204. Power stage 206 has a first terminal 208, a second terminal 210, a third terminal 212, a fourth terminal 214, a fifth terminal 216, and a sixth terminal 218. Output capacitor COUT2 has a first terminal and a second terminal. Load 242 has a first terminal 244 and a second terminal 246. Controller 248 has a first terminal 249, a second terminal 250, a third terminal 251, a fourth terminal 252, a fifth terminal 253, and a sixth terminal 254.

[0027] As shown in the figure, power stage 206 includes inductor 220, first switch 228, and second switch 236, arranged as shown. In some instances, the first switch 228, second switch 236, and associated control circuitry are components of the IC, while the inductor 220 is an external component relative to the IC. Figure 2 The component arrangement of power stage 206 is referred to as a boost converter topology, where the output voltage VOUT2 is higher than the input voltage VIN2. In other instances, the power stage may have a buck-boost converter topology. Figure 2 In one example, the first switch 228 has a first terminal 230, a second terminal 232, and a control terminal 234. The second switch 236 has a first terminal 238, a second terminal 240, and a control terminal 241. In some examples, the first switch 228 may be an NFET, and the second switch 236 may be a PFET or an NFET. The inductor 220 has a first terminal 222 and a second terminal 224.

[0028] The controller 248 includes a valley control circuit system 255, a peak control circuit system 260, a PFM timer circuit system 264, an adaptive slope compensation circuit system 268, mode control logic 272, and a driver circuit system 284. The valley control circuit system 255 has a first terminal 256, a second terminal 257, and a third terminal 258. The peak control circuit system 260 has a first terminal 261, a second terminal 262, and a third terminal 263. The PFM timer circuit system 264 has a first terminal 265 and a second terminal 266. The adaptive slope compensation circuit system 268 has a first terminal 269, a second terminal 270, and a third terminal 271. The mode control logic 272 has a first terminal 273, a second terminal 274, a third terminal 276, a fourth terminal 279, a fifth terminal 280, and a sixth terminal 282. The driver circuit system 284 has a first terminal 286, a second terminal 288, a third terminal 290, and a fourth terminal 292.

[0029] The first terminal 208 of power stage 206 is coupled to the third terminal 251 of controller 248. The second terminal 210 of power stage 206 is coupled to the fourth terminal 252 of controller 248. The third terminal 212 of power stage 206 is coupled to the first terminal of output capacitor COUT2, the first terminal 244 of load 142, and the second terminal 250 of controller 248. The second terminal of output capacitor COUT2 is coupled to ground or a grounded terminal. The second terminal 246 of load 242 is coupled to ground or a grounded terminal. The fourth terminal 214 of power stage 206 is coupled to the first terminal 249 of controller 248. The fifth terminal 216 of power stage 206 is coupled to terminal 204 of power supply 202. Terminal 204 of power supply 202 is also coupled to the fifth terminal 253 of controller 248. The sixth terminal 218 of power stage 206 is coupled to ground or a grounded terminal. The sixth terminal 254 of controller 248 is also coupled to ground or a grounded terminal.

[0030] As shown in the figure, the first terminal 222 of inductor 220 is coupled to the fifth terminal 216 of power stage 106. The second terminal 224 of inductor 220 is coupled to the first terminal 230 of first switch 228 and the first terminal 238 of second switch 236. The second terminal 232 of first switch 228 is coupled to the sixth terminal 218 of power stage 206. The control terminal 234 of first switch 228 is coupled to the first terminal 208 of power stage 206. The second terminal 240 of second switch 236 is coupled to the third terminal 212 of power stage 206. The control terminal 241 of second switch 236 is coupled to the second terminal 210 of power stage 106. As shown in the figure, the fourth terminal 214 of power stage 106 is coupled to the switching node 235 between first switch 228 and second switch 236.

[0031] As shown in the figure, the first terminal 256 of the valley control circuit system 255 receives the control signal CS1. In some instances, CS1 includes a valley threshold and an inductor current sensing signal. In some instances, the valley threshold and / or the inductor current sensing signal undergoes a slope change. The first terminal 261 of the peak control circuit system 260 receives the control signal CS2. In some instances, CS2 includes a peak threshold and an inductor current sensing signal. The first terminal 265 of the PFM timer circuit system 264 receives the control signal CS3. In some instances, CS3 includes a control voltage (e.g., V_CTRL in this context). In some instances, V_CTRL is the error result between VOUT and a reference voltage (VREF). The first terminal 269 of the adaptive slope compensation circuit system 268 receives the input parameter IN_P. Instance input parameters include VIN, VOUT, L (the value of inductor 220), the FSW of the power stage switch, the current sensing gain, and / or other input parameters. The second terminal 270 of the adaptive slope compensation circuit system 268 receives the switch control signal CS_S1. The third terminal 271 of the adaptive slope compensation circuit system 268 is coupled to the second terminal 257 of the valley control circuit system 255 and the second terminal 262 of the peak control circuit system 260.

[0032] The first terminal 273 of mode control logic 272 is coupled to the third terminal 258 of valley control circuit system 255. The second terminal 274 of mode control logic 272 is coupled to the third terminal 263 of peak control circuit system 260. The third terminal 276 of mode control logic 272 is coupled to the second terminal 266 of PFM timer circuit system 264. The fourth terminal 279 of mode control logic 272 receives the clock signal (CLK2). The fifth terminal 280 of mode control logic 272 is coupled to the first terminal 286 of driver circuit system 284. The sixth terminal 282 of mode control logic 272 is coupled to the second terminal 288 of driver circuit system 284. The third terminal 290 of driver circuit system 284 is coupled to the third terminal 251 of controller 248. The fourth terminal 292 of driver circuit system 284 is coupled to the fourth terminal 252 of controller 248.

[0033] In operation, controller 248 is configured to: receive VIN2 at its fifth terminal 253; and receive V at its first terminal 249. SW2 ; receives VOUT2 at its second terminal 250; responds to VIN2, V SW2The operation of VOUT2, adaptive slope compensation circuit system 268, valley control circuit system 255, peak control circuit system 260, PFM timer circuit system 264, mode control logic 272, and driver circuit system 284 provides SW1_CS at its third terminal 251; and in response to VIN2, V SW2 The operation of VOUT2, the adaptive slope compensation circuit system 268, the valley control circuit system 255, the peak control circuit system 260, the PFM timer circuit system 264, the mode control logic 272, and the driver circuit system 284 is provided at its fourth terminal 252 as SW2_CS. In some instances, the controller 248 supports modes including PWM mode and PFM mode.

[0034] In operation, power stage 206 is configured to: receive VIN2 at its fifth terminal 216; receive SW1_CS at its first terminal 208; receive SW2_CS at its second terminal 210; provide VOUT2 at its third terminal 212 in response to VIN2, SW1_CS, and SW2_CS; and provide VOUT2 at its fourth terminal 214 in response to VIN2, SW1_CS, and SW2_CS. SW2 More specifically, when the first switch 228 is on and the second switch 236 is off, the current in inductor 220 increases. When the first switch 228 is off and the second switch 236 is on, the current in inductor 220 decreases. The average current in inductor 136 is considered as the load current (I_out2) supplied to load 242.

[0035] Figure 3A This is a diagram of the adaptive slope compensation circuit system 302. The adaptive slope compensation circuit system 302 is... Figure 1 The adaptive slope compensation circuit system 168 or Figure 2 An example of an adaptive slope compensation circuit system 268 is shown. The adaptive slope compensation circuit system 302 has a first terminal 304, a second terminal 306, a third terminal 308, a fourth terminal 310, and a fifth terminal 312. As shown, the first terminal 304 of the adaptive slope compensation circuit system 302 is coupled to a voltage source (VDD) terminal 322. The second terminal 306 of the adaptive slope compensation circuit system 302 receives the input parameter IN_P. Example input parameters include the input voltage VIN, output voltage VOUT, inductance L, FSW, current sensing gain, and / or other input parameters. The third terminal 308 receives a control signal (CS_S1). The fourth terminal 310 provides the adaptive slope compensation current (I_ASC). The fifth terminal 312 is coupled to ground or a ground terminal.

[0036] exist Figure 3AIn this example, the adaptive slope compensation circuit system 302 includes an adjustable current source circuit system 314, a capacitor C_SC, and a switch S1, arranged as shown in the figure. The adjustable current source circuit system 314 has a first terminal 316, a second terminal 318, and a control terminal 320. The capacitor C_SC has a first terminal and a second terminal. The switch S1 has a first terminal T1, a second terminal T2, and a control terminal T3.

[0037] As shown in the figure, the first terminal 316 of the adjustable current source circuit system 314 is coupled to the first terminal of the adaptive slope compensation circuit system 302. The second terminal 318 of the adjustable current source circuit system 314 is coupled to the first terminal 304 of the capacitor C_SC and the first terminal T1 of the switch S1. The control terminal 320 of the adjustable current source circuit system 314 is coupled to the second terminal 306 of the adaptive slope compensation circuit system 302. The second terminal of the capacitor C_SC and the second terminal T2 of the switch S1 are coupled to the fifth terminal 312 of the adaptive slope compensation circuit system 302. The control terminal T3 of the switch S1 is coupled to the third terminal 308 of the adaptive slope compensation circuit system 302. As shown in the figure, the fourth terminal 310 of the adaptive slope compensation circuit system 302 is coupled to the second terminal 318 of the adjustable current source circuit system 314, the first terminal of the capacitor C_SC, and the first terminal T1 of the switch S1.

[0038] In operation, the adaptive slope compensation circuit system 302 is configured to: receive VDD at the first terminal 304; receive the input parameter at the second terminal 306; receive CS_S1 at the third terminal 308; and generate an I_ASC waveform at the fourth terminal 310 in response to VDD, the input parameter, and CS_S1. In some instances, the current output from the second terminal 318 of the adjustable current source circuit system 314 varies with VOUT, VIN, FSW, I_RIPPLE, and C_SC. In some instances, the current output from the second terminal 318 of the adjustable current source circuit system 314 is expressed as: ,in It is a scaling factor.

[0039] In some instances, Figure 3B This is timing diagram 330 showing the I_ASC waveform and CS_S1. In Figure 3B In this context, I_ASC has a sawtooth shape formed by positive slope intervals 332 and turn-off intervals 334. In some instances, each of the positive slope intervals 332 corresponds to having a first state (e.g., Figure 3B CS_S1 (the assertion state in the middle), and each of the shutdown intervals 334 corresponds to having a second state (e.g., Figure 3BThe slope 338 of I_ASC may vary during each of the positive slope intervals 332 and is controlled by the current supplied by the adjustable current source circuit system 314. In some instances, the current supplied by the adjustable current source circuit system 314 varies in response to input parameters. During each of the positive slope intervals 332, CS_S1 turns off switch S1, and I_ASC increases as capacitor C_SC is charged by the current supplied by the adjustable current source circuit system 314, causing I_ASC to reach a threshold or maximum current level 336 for each of the positive slope intervals 332. During each of the turn-off intervals 334, CS_S1 turns on switch S1, and I_ASC decreases as capacitor C_SC discharges to ground.

[0040] Figure 4 This is a diagram of an example switch converter controller 400. The switch converter controller 400 is... Figure 1 Controller 148 or Figure 2 An example of controller 248. As shown, the switch converter controller 400 includes a PFM timer circuit system 464, an error amplifier 432, a resistor R1, a capacitor C1, a voltage-to-current converter 440, a current sensing circuit system 420, an adaptive slope compensation circuit system 302, a slope compensation controller 410, a peak comparator 446, a valley comparator 454, mode control logic 472, and a driver circuit system 484. The adaptive slope compensation circuit system 302 is... Figure 1 The adaptive slope compensation circuit system in 168 Figure 2 The adaptive slope compensation circuit system 268 or Figure 3A An example of the adaptive slope compensation circuit system 302. The PFM timer circuit system 464 is... Figure 1 The PFM timer circuit system 164 and / or Figure 2 An example of the PFM timer circuit system 264. The driver circuit system 484 is... Figure 1 The driver circuit system 184 and / or Figure 2 An example of the driver circuit system 284 in the example.

[0041] exist Figure 4 In this example, the error amplifier 432, the voltage-to-current converter 440, and the peak comparator 446 are Figure 1 Peak control circuit system 160 and / or Figure 2 Example components of the peak control circuit system 260. Error amplifier 432, voltage-to-current converter 440, and valley comparator 454 are... Figure 1 Valley control circuit system 155 and / or Figure 2 Example components of the valley control circuit system 255.

[0042] Error amplifier 432 has a first (inverting or "-") terminal 434, a second (non-inverting or "+") terminal 436, and a third terminal 438. Voltage-to-current converter 442 has a first terminal 442, a second terminal 443, and a third terminal 444. Current sensing circuit system 420 has a first terminal 422 and a second terminal 424. Adaptive slope compensation circuit system 302 has a first terminal 304, a second terminal 306, a third terminal 308, a fourth terminal 310, and a fifth terminal 312 as described in FIG. 3. Slope compensation controller 410 has a first terminal 412 and a second terminal 414. Peak comparator 446 has a first (non-inverting or "+") terminal 448, a second (inverting or "-") terminal 450, and a third terminal 452. Valley comparator 456 has a first (non-inverting or "+") terminal 456, a second (inverting or "-") terminal 458, and a third terminal 460. The mode control logic 472 has a first terminal 473, a second terminal 474, a third terminal 476, a fourth terminal 479, a fifth terminal 480, and a sixth terminal 482. The driver circuit system 484 has a first terminal 486, a second terminal 488, a third terminal 490, and a fourth terminal 492.

[0043] The first terminal 434 of the error amplifier 432 is coupled to the output terminal of the power stage (e.g., Figure 1 The third terminal 112 of the power stage 106, or Figure 2 The third terminal 212 of the power stage 206 in the error amplifier 432 is coupled to a reference voltage source (not shown) and receives VOUT as the feedback voltage (V_fb). Alternatively, V_fb can be a scaled version of VOUT (e.g., using a voltage divider). The second terminal 436 of the error amplifier 432 is coupled to a reference voltage source (not shown) and receives a reference voltage (V_ref). The third terminal 438 of the error amplifier 432 is coupled to the first terminal of the resistor R1 and the first terminal 442 of the voltage-to-current converter 440. The second terminal of the resistor R1 is coupled to the first terminal of the capacitor C1. The second terminal of the capacitor C1 is coupled to ground or a ground terminal. The second terminal 443 of the voltage-to-current converter 440 is coupled to the second terminal 450 of the peak comparator 446. The first terminal 448 of the peak comparator 446 is coupled to the second terminal 424 of the current sensing circuit system 420 and the fourth terminal 310 of the adaptive slope compensation circuit system 302. In some instances, the first terminal 422 of the current sensing circuit system 420 is coupled to... Figure 1 The fourth terminal 114 of the power stage 106 in the middle Figure 2 The fourth terminal 214 of the power stage 206 is configured to monitor V. SWOr a related current sensing circuit system. The third terminal 444 of the voltage-to-current converter 440 is coupled to the first terminal 456 of the valley comparator 454. The second terminal 458 of the valley comparator 454 is coupled to the second terminal 424 of the current sensing circuit system 420 and the fourth terminal 310 of the adaptive slope compensation circuit system 302. As shown, the first terminal 304 of the adaptive slope compensation circuit system 302 is coupled to the VDD source. The second terminal of the adaptive slope compensation circuit system 302 receives the input parameter IN_P. The third terminal 308 of the adaptive slope compensation circuit system 302 is coupled to the second terminal 414 of the slope compensation controller 410. The first terminal 412 of the slope compensation controller 410 receives the adaptive slope compensation control signal (CS_ASC).

[0044] The first terminal 473 of mode control logic 472 is coupled to the third terminal 460 of valley comparator 454. The second terminal 474 of mode control logic 472 is coupled to the third terminal 452 of peak comparator 446. The third terminal 476 of mode control logic 472 is coupled to the second terminal 468 of PFM timer circuit system 464. The fourth terminal 479 of mode control logic 472 is coupled to clock generator and receives clock signal (CLK3). The fifth terminal 480 of mode control logic 472 is coupled to the first terminal 486 of driver circuit system 484. The sixth terminal 482 of mode control logic 472 is coupled to the second terminal 488 of driver circuit system 484. The third terminal 490 of driver circuit system 484 is coupled to the first switch (e.g., ...). Figure 1 High-side switch 120, or Figure 2 The control terminal of the first switch 228 in the driver circuit system 484. The fourth terminal 492 of the driver circuit system 484 is coupled to the second switch (e.g., Figure 1 The low-side switch 128, or Figure 2 The control terminal of the second switch 236 in the middle.

[0045] Error amplifier 432 is configured to: receive V_fb at a first terminal 434; receive V_ref at a second terminal 436; and provide V_CTRL at a third terminal 438 in response to V_fb and V_ref. The value of V_CTRL is based on the difference between V_fb and V_ref, as well as the values ​​of resistor R1 and capacitor C1, which form a compensation circuit system for the control loop. Specifically, R1 and C1 convert the error amplifier current to voltage based on proportional-integral (PI) control. The transconductance of error amplifier 432 defines the gain applied when converting the voltage error at the input of error amplifier 432 to the output current. Voltage-to-current converter 440 is configured to: receive V_CTRL at a first terminal 442; provide a peak reference current (I_ref_peak) at a second terminal 443 in response to V_CTRL; and provide a valley reference current (I_ref_valley) at a third terminal 444 in response to V_CTRL. In some instances, the voltage-to-current converter 440 converts V_CTRL to I_ref_valley based on a given transconductance in PWM mode. In PFM mode, the voltage-to-current converter 440 sets I_ref_valley to zero. In some instances, the voltage-to-current converter 440 can convert V_CTRL to I_ref_peak using a given transconductance. In some instances, I_ref_valley and / or I_ref_peak generation is also based on a hysteresis current, which defines the difference between the valley level and the peak level. In PWM mode, the hysteresis current can be a predefined value (e.g., related to a fixed current level). In PFM mode, the hysteresis current can be related to the inductor current ripple in the PWM mode.

[0046] Peak comparator 446 is configured to: receive I_sense (compensated by I_ASC) at a first terminal 448; receive I_ref_peak at a second terminal 450; and provide a peak comparison result (Peak_comp) at a third terminal 452 in response to I_sense (compensated by I_ASC) and I_ref_peak. Valley comparator 454 is configured to: receive I_ref_peak at a first (non-inverting) terminal 456; receive I_sense (compensated by I_ASC) at a second (inverting) terminal 458; and provide a comparison result Valley_comp at a third terminal 460 in response to I_sense (compensated by I_ASC) and I_ref_valley. PFM timer circuitry 464 is configured to: receive V_CTRL at a first terminal 466; and provide a PFM timer control signal (PFM_timer_comp) in response to V_CTRL and a possible PFM mode signal.

[0047] The mode control logic 472 is configured to: receive Valley_comp at the first terminal 473; receive Peak_comp at the second terminal 474; receive PFM_timer_comp at the third terminal 476; receive CLK3 at the fourth terminal 479; control the state of the PWM control signal (PWM_CS) at the fifth terminal 480 in response to Valley_comp, Peak_comp, CLK3, PFM_timer_comp and / or current mode; and provide a high impedance (HIZ) control signal (HIZ_CS) at the sixth terminal 482 in response to Valley_comp, Peak_comp, PFM_timer_comp and / or current mode.

[0048] In some instances, mode control logic 472 is configured to control the state of PWM_CS at terminal 480 and the state of HIZ_CS at terminal 482 during PWM mode operation and PFM mode operation of the switching converter controller 400. In some instances, during PWM mode, mode control logic 472 is configured to maintain HIZ_CS in a second state (e.g., deasserted or logic low). With HIZ_CS in the second state, PWM_CS controls the states of HS_CS and LS_CS during PWM mode to support HS and LS intervals. During PWM mode, PWM_CS can be asserted in response to Valley_comp or Peak_comp assertion (indicating that the inductor current has reached a threshold), and can be deasserted in response to a timer, clock signal, Valley_comp assertion, or Peak_comp assertion (indicating that the inductor current has reached a threshold). For each HS interval, HS_CS can be asserted while LS_CS is deasserted. For each LS interval, the assertion HS_CS can be de-asserted while the assertion LS_CS is performed. For each cycle, the duration of the HS interval relative to the LS interval defines the duty cycle provided by the switch converter controller 400. For example, if the HS interval and the LS interval are equal in duration, the duty cycle provided by the switch converter controller 400 is 50%.

[0049] In response to light load conditions, mode control logic 472 is configured to switch from PWM mode to PFM mode. During PFM mode, mode control logic 472 is configured to support PFM mode operation, including asserting HIZ_CS as needed to provide a pause between the HS interval and the LS interval during PFM mode.

[0050] In response to the detection of a light load condition, mode control logic 472 initiates the transition from PWM to PFM mode. In some instances, a comparator (not shown) can be used to detect the light load condition to detect when V_CTRL drops below V_valley_zero (indicating that the valley current level is below zero). Alternatively, the host system can provide a control signal (e.g., a low power request) to trigger the transition from PWM mode to PFM mode.

[0051] During PFM mode, mode control logic 472 is configured to assert HIZ_CS as needed between PFM pulses to enable a pause interval between the HS and LS intervals (e.g., both HS switch 120 and LS switch 128 are turned off during each pause interval). Furthermore, during PFM mode, PFM_pulse_comp can be asserted to initiate a PFM pulse (HS interval) when HIZ_CS is deasserted and PWM_CS is asserted. During PFM mode, asserted Peak_comp can initiate the LS interval when PWM_CS is deasserted. During PFM mode, Valley_comp can be used to detect zero current and trigger an assertion of HIZ_CS.

[0052] The driver circuitry 484 is configured to: receive PWM_CS at a first terminal 486; receive HIZ_CS at a second terminal 488; in response to PWM_CS having a first state (e.g., PWM_CS is asserted) and HIZ_CS having a second state (e.g., HIZ_CS is deasserted), provide HS_CS with the first state (e.g., HS_CS is asserted) at a third terminal 190 and provide LS_CS with the second state (e.g., LS_CS is deasserted) at a fourth terminal 492; in response to PWM_CS having the second state (e.g., PWM_CS is deasserted) and HIZ_CS having the second state (e.g., HIZ_CS is deasserted), provide HS_CS with the second state (e.g., HS_CS is deasserted) at a third terminal 490 and provide LS_CS with the first state at a fourth terminal 492. (e.g., LS_CS is asserted); and in response to HIZ_CS having a first state (e.g., HIZ_CS is asserted), HS_CS having a second state (e.g., HS_CS is deasserted) is provided at the third terminal 490 and LS_CS having a second state (e.g., LS_CS is deasserted) is provided at the fourth terminal 492.

[0053] By utilizing the adaptive slope compensation circuit system 302, the slope 338 of the slope compensation ramp provided by the adaptive slope compensation circuit system 302 takes into account the variation of the input parameters, which improves the accuracy of the I_sense ramp used by the peak comparator 446 and / or the valley comparator 454 and related control operations. With the improved slope compensation, the control loop is more precise, resulting in advantages such as reduced VOUT ripple.

[0054] Figure 5 This is a schematic diagram of an example adaptive slope compensation circuit system 500. The adaptive slope compensation circuit 500 is... Figure 3AThe adaptive slope compensation circuit system 302 or Figure 4 An example of an adaptive slope compensation circuit system 302 is shown. As illustrated, the adaptive slope compensation circuit system 500 has a first terminal 580, a second terminal 582, a third terminal 584, a fourth terminal 586, a fifth terminal 588, a sixth terminal 590, a seventh terminal 592, and an eighth terminal 594. The first terminal 580 is... Figure 3A and 4 An example of the first terminal 304. The second terminal 582, the third terminal 584, the fourth terminal 586, and the fifth terminal 588 are... Figure 3A and 4 An example of the second terminal 306. The sixth terminal 590 is... Figure 3A and 4 An example of the third terminal 308. The seventh terminal 592 is... Figure 3A and 4 An example of the fourth terminal 310. The eighth terminal 594 is... Figure 3A and 4 An example of the fifth terminal 312.

[0055] exist Figure 5 In this example, the adaptive slope compensation circuit system 500 includes a voltage-to-current converter circuit system 502, a current scaling circuit system 518, multipliers 540, 550, and 560, a current mirror 570, resistors R7 to R11, capacitor C_SC, and switch S1, arranged as shown in the figure. The voltage-to-current converter circuit system 502 has a first terminal 503, a second terminal 504, a third terminal 505, and a fourth terminal 506. The current scaling circuit system 518 has a first terminal 519, a second terminal 520, and a third terminal 521. The multiplier 540 has a first terminal 542, a second terminal 544, a third terminal 545, a fourth terminal 546, a fifth terminal 548, and a sixth terminal 549. The multiplier 550 has a first terminal 552, a second terminal 554, a third terminal 555, a fourth terminal 556, a fifth terminal 558, and a sixth terminal 559. Multiplier 560 has a first terminal 562, a second terminal 564, a third terminal 565, a fourth terminal 566, a fifth terminal 568, and a sixth terminal 569. Current mirror 570 has a first terminal 572, a second terminal 574, and a third terminal 575. Each of resistors R7 to R11 has a corresponding first terminal and a corresponding second terminal.

[0056] exist Figure 5In this example, the first terminal 580 of the adaptive slope compensation circuit system 500 is coupled to the first terminal 519 of the current scaling circuit system 518. The second terminal 582 of the adaptive slope compensation circuit system 500 is coupled to the second terminal 504 of the voltage-to-current converter circuit system 502. The third terminal 584 of the adaptive slope compensation circuit system 500 is coupled to the first terminal 503 of the voltage-to-current converter circuit system 502. The fourth terminal 586 of the adaptive slope compensation circuit system 500 is coupled to the second terminal 520 of the current scaling circuit system 518. The fifth terminal 588 of the adaptive slope compensation circuit system 500 is coupled to the second terminal of the multiplier 550. The sixth terminal 590 of the adaptive slope compensation circuit system 500 is coupled to the control terminal T3 of the switch S1. The seventh terminal 592 of the adaptive slope compensation circuit system 500 is coupled to the first terminal of the resistor R11, the first terminal of the capacitor C_SC, and the first terminal T1 of the switch S1. The eighth terminal 594 of the adaptive slope compensation circuit system 500 is coupled to ground or grounding terminal.

[0057] exist Figure 5 In this example, the voltage-to-current converter circuit system 502 includes resistors R1 to R6, operational amplifiers 507 and 512, and transistors M1 to M6, arranged as shown in the figure. Each of the resistors R1 to R6 has a corresponding first terminal and a second terminal. Operational amplifier 507 has a first terminal 508, a second terminal 509, and a third terminal 510. Operational amplifier 512 has a first terminal 514, a second terminal 516, and a third terminal 517. Each of the transistors M1 to M6 has a corresponding first terminal, a corresponding second terminal, and a corresponding control terminal.

[0058] The first terminal of resistor R1 is coupled to the first terminal 503 of voltage-to-current converter circuit system 502. The second terminal of resistor R2 is coupled to the first terminal of resistor R2 and the first (non-inverting or "+") terminal 508 of operational amplifier 507. The second terminal of resistor R2 is coupled to ground or a ground terminal. The third terminal 510 of operational amplifier 507 is coupled to the control terminal of transistor M1. The first terminal of transistor M1 is coupled to the second terminal of transistor M2 and the control terminals of transistors M2 and M3. The second terminal of transistor M1 is coupled to the first terminal of resistor R3 and the second (inverting or "-") terminal 509 of operational amplifier 507. The second terminal of resistor R3 is coupled to ground or a ground terminal. The first terminal of transistor M2 is coupled to the first terminal of transistor M3. The second terminal of transistor M3 is coupled to the third terminal 505 of voltage-to-current converter circuit system 502.

[0059] The first terminal of resistor R4 is coupled to the second terminal 504 of voltage-to-current converter circuit system 502. The second terminal of resistor R4 is coupled to the first terminal of resistor R5 and the first (non-inverting or "+") terminal 514 of operational amplifier 512. The second terminal of resistor R5 is coupled to ground or a ground terminal. The third terminal 517 of operational amplifier 512 is coupled to the control terminal of transistor M6. The first terminal of transistor M6 is coupled to the second terminal of transistor M5 and the control terminal of transistors M5 and M5. The second terminal of transistor M6 is coupled to the first terminal of resistor R6 and the second (inverting or "-") terminal 516 of operational amplifier 512. The second terminal of resistor R6 is coupled to ground or a ground terminal. The first terminal of transistor M4 is coupled to the first terminal of transistor M5. The second terminal of transistor M4 is coupled to the fourth terminal 506 of voltage-to-current converter circuit system 502. Figure 6 In this example, transistors M1 and M6 are n-channel metal-oxide-semiconductor (NMOS) transistors, and transistors M2 through M5 are p-channel metal-oxide-semiconductor (PMOS) transistors. In other examples, the type of transistors used for the voltage-to-current converter 502 can vary.

[0060] The first terminals of resistors R7 and R8 are coupled to the third terminal 505 of voltage-to-current converter circuit system 502. The second terminal of resistor R7 is coupled to the fourth terminal 546 of multiplier 540. The first terminals of resistors R9 and R10 are coupled to the fourth terminal 506 of voltage-to-current converter circuit system 502. The second terminal of resistor R10 is coupled to the second terminal 544 of multiplier 540.

[0061] The first terminal 542 of the multiplier 540 is coupled to the VDD source. Figure 5 In this example, the third terminal 545 of multiplier 540 is not used. The fifth terminal 548 of multiplier 540 is coupled to the second terminal 564 of multiplier 560. The sixth terminal 549 of multiplier 540 is coupled to ground or a ground terminal. The first terminal 552 of multiplier 550 is coupled to a VDD source. The second terminal 554 of multiplier 550 is coupled to the fifth terminal 588 of the adaptive slope compensation circuit system 500 and receives the ripple current (I_RIPPLE) signal. Figure 5 In this example, the third terminal 555 and the fourth terminal 556 of multiplier 550 are not used. The fifth terminal 558 of multiplier 550 is coupled to the third terminal 565 of multiplier 560. The sixth terminal 559 of multiplier 550 is coupled to ground or a ground terminal. The first terminal 562 of multiplier 560 is coupled to a VDD source. Figure 5In this example, the fourth terminal 566 of multiplier 560 is not used. The fifth terminal 568 of multiplier 560 is coupled to the third terminal 521 of current scaling circuit system 518 and the first terminal 572 of current mirror 570. The sixth terminal 569 of multiplier 560 is coupled to ground or ground terminal.

[0062] The first terminal of resistor R11 is coupled to the seventh terminal 592 of the adaptive slope compensation circuit system 500, the first terminal of capacitor C_SC, and the first terminal T1 of switch S1. The second terminal of resistor R11 is coupled to the second terminal 574 of current mirror 570. The third terminal 575 of current mirror 570 is coupled to ground or a grounded terminal. The second terminal of capacitor C_SC is coupled to ground or a grounded terminal. The second terminal T2 of switch S1 is coupled to ground or a grounded terminal. The control terminal T3 of switch S1 is coupled to the sixth terminal 590 of the adaptive slope compensation circuit system 500.

[0063] exist Figure 5 In one example, the current scaling circuit system 518 includes transistors M7 to M12, transmission gates 522 and 530, and a scaling circuit system 576, arranged as shown in the figure. The scaling circuit system 576 has a first terminal 577, a second terminal 578, and a third terminal 579. Each of transistors M7 to M12 has a corresponding first terminal, a corresponding second terminal, and a corresponding control terminal. Transmission gate 522 has a first terminal 523, a second terminal 524, a third terminal 526, and a fourth terminal 528. Transmission gate 530 has a first terminal 532, a second terminal 534, a third terminal 536, and a fourth terminal 538. Non-limitingly, in... Figure 5 In this example, transistors M7 to M12 are PMOS transistors.

[0064] The first terminals of transistors M8, M9, M10, and M11 are coupled to the first terminal 519 of current scaling circuit system 518. The second terminal of transistor M8 is coupled to the first terminal of transistor M7. The second terminal of transistor M7 is coupled to the first terminal 523 of transmission gate 522. The second terminal 524 of transmission gate 522 is coupled to the second terminal 520 of current scaling circuit system 518. The second terminal of transistor M9 is coupled to the control terminals of transistors M8 and M11 and the second terminal 578 of scaling circuit system 576. The second terminal of transistor M10 is coupled to the control terminals M7 and M12 and the third terminal 579 of scaling circuit system 576. The second terminal of transistor M11 is coupled to the first terminal of transistor M12. The second terminal of transistor M12 is coupled to the first terminal 532 of transmission gate 530. The second terminal 534 of transmission gate 530 is coupled to the fifth terminal 568 of multiplier 560 and the first terminal 572 of current mirror 570.

[0065] exist Figure 5 In one example, the current mirror 570 includes transistors M13 and M14, arranged as shown in the figure. Non-limitingly, in Figure 5 In this example, transistors M13 and M14 are NMOS transistors. Each of transistors M13 and M14 has a corresponding first terminal, a corresponding second terminal, and a corresponding control terminal. The first terminal of transistor M13 is coupled to the first terminal 572 of the current mirror 570. The control terminal of transistors M13 and M14 is also coupled to the first terminal 572 of the current mirror. The first terminal of transistor M14 is coupled to the second terminal 574 of the current mirror 570. The second terminals of transistors M13 and M14 are coupled to the third terminal 575 of the current mirror 570. Non-limitingly, transistor M14 is sized in a 4:1 ratio relative to M13.

[0066] In some instances, the adaptive slope compensation circuitry 500 is configured to: receive VDD at a first terminal 580; receive VIN at a second terminal 582; receive VOUT at a third terminal 584; receive the switching frequency value I_FSW at a fourth terminal 586; receive the current ripple metric I_RIPPLE at a fifth terminal 588; and provide a slope compensation current I_ASC at a seventh terminal 592 in response to VIN, VOUT, I_FSW, and I_RIPPLE. In other instances, the input parameters used to determine the slope compensation current I_ASC can vary. The adaptive slope compensation circuitry 500 is also configured to: receive CS_S1 at a sixth terminal 590; charge capacitor C_SC based on the slope compensation current I_ASC in response to CS_S1 having a first state (e.g., asserted or logic "1"); and discharge capacitor C_SC in response to CS_S1 having a second state (e.g., deasserted or logic "0"). In some instances, the adaptive slope compensation circuitry system 500 is configured to charge and discharge capacitor C_SC in response to CS_S1 and I_ASC such that the slope compensation current has a sawtooth pattern and the slope of I_ASC (e.g., slope 338) is 0.5 to 1.0 times that of the current sensing slope.

[0067] More specifically, the voltage-to-current converter circuit system 502 is configured to: receive VIN at a first terminal 503; receive VOUT at a second terminal 504; provide a VIN current value based on VIN at a third terminal 505; and provide a VOUT current value based on VOUT at a fourth terminal 506. Resistors R7 and R8 form a first scaling circuit to scale the VIN current value, which is provided to the fourth terminal 546 of the multiplier 540. Resistors R9 and R10 form a second scaling circuit to scale the VOUT current value, which is provided to the second terminal 544 of the multiplier 540. The multiplier 540 is configured to: receive VDD at a first terminal 542; receive the VOUT value at a second terminal 544; receive the VIN value at a fourth terminal 546; and provide a VOUT / VIN value at a fifth terminal 548 in response to the VOUT and VIN values. Multiplier 550 is configured to: receive VDD at a first terminal 552; receive I_RIPPLE at a second terminal 554; and provide the I_RIPPLE value at a fifth terminal 558. Multiplier 560 is configured to: receive VDD at a first terminal 562; receive the VOUT / VIN value at a second terminal 564; receive the I_RIPPLE value at a third terminal 565; and, in response to the I_RIPPLE value and the VOUT / VIN value, provide (VOUT / VIN)*I_RIPPLE at a fifth terminal 568.

[0068] The current scaling circuit system 518 is configured to: receive VDD at a first terminal 519; receive the I_FSW value at a second terminal 520; and, in response to the I_FSW value and the operation of the current scaling circuit system 518, provide a scaled I_FSW value at a third terminal 521. In some instances, the current scaling circuit system 518 can scale the I_FSW value to, for example, an integer of 2 or 4. The scaled I_FSW value is combined with (VOUT / VIN)*I_RIPPLE, and the combined current is provided to the current mirror 570. The current mirror 570 is configured to: receive the combined current at a first terminal 572; and, based on the size relationship of transistors M13 and M14, provide a scaled version of the combined current at a second terminal 574. In some instances, M14 is sized relative to M13 such that the scaled version of the combined current is four times the combined current. When switch S1 is turned off by CS_S1, the scaled combined current charges capacitor C_SC via resistor R11. When switch S1 is turned on by CS_S1, the charge on capacitor C_SC returns to ground.

[0069] Figure 6 This is a schematic diagram of the 4-quadrant multiplier 600. The 4-quadrant multiplier 600 is... Figure 5An instance of each of the multipliers 540, 550, and 560 in the dataset. Figure 6 In this example, the 4-quadrant multiplier 600 has a first terminal 602, a second terminal 604, a third terminal 605, a fourth terminal 606, a fifth terminal 608, and a sixth terminal 609. The first terminal 602 of the 4-quadrant multiplier 600 is... Figure 5 Examples of the first terminal 542 of multiplier 540, the first terminal 552 of multiplier 550, or the first terminal 562 of multiplier 560. The second terminal 604 of the 4-quadrant multiplier 600 is... Figure 5 Examples of the second terminal 544 of multiplier 540, the second terminal 554 of multiplier 550, or the second terminal 564 of multiplier 560. The third terminal 605 of the 4-quadrant multiplier 600 is... Figure 5 Examples of the third terminal 545 of multiplier 540, the third terminal 555 of multiplier 550, or the third terminal 565 of multiplier 560. The fourth terminal 606 of the 4-quadrant multiplier 600 is... Figure 5 Examples of the fourth terminal 546 of multiplier 540, the fourth terminal 556 of multiplier 550, or the fourth terminal 566 of multiplier 560. The fifth terminal 608 of the 4-quadrant multiplier 600 is... Figure 5 Examples of the fifth terminal 548 of multiplier 540, the fifth terminal 558 of multiplier 550, or the fifth terminal 568 of multiplier 560. The sixth terminal 609 of the 4-quadrant multiplier 600 is... Figure 5 Examples of the sixth terminal 549 of multiplier 540, the sixth terminal 559 of multiplier 550, or the sixth terminal 569 of multiplier 560.

[0070] exist Figure 6In one example, the 4-quadrant multiplier 600 includes transistors BP1 through BP4 and transistor M15, arranged as shown in the figure. In some examples, transistors BP1 through BP4 are bipolar transistors, while transistor M15 is an NMOS transistor. Each of transistors BP1 through BP4 and transistor M14 has a corresponding first terminal, a corresponding second terminal, and a control terminal. As shown, the first terminal of transistor BP1 is coupled to the second (“A”) terminal 604 of the 4-quadrant multiplier 600. The second terminal of transistor BP1 is coupled to the sixth terminal 609 of the 4-quadrant multiplier 600. The control terminal of transistor BP1 is coupled to the third (“B”) terminal 605 of the 4-quadrant multiplier 600. The first terminals of transistors BP2 and BP3 are coupled to the first terminal 602 of the 4-quadrant multiplier 600. The second terminal of transistor BP2 is coupled to the third (“B”) terminal 605 of the 4-quadrant multiplier 600. The second terminal of transistor BP3 is coupled to the fourth (“C”) terminal 606 of the 4-quadrant multiplier 600. The control terminals of transistors BP2 and BP3 are coupled to the second (“A”) terminal 604 of the 4-quadrant multiplier 600. The first terminal of transistor M15 is coupled to the second (“A”) terminal 604 of the 4-quadrant multiplier 600. The second terminal of transistor M15 is coupled to the sixth terminal 609 of the 4-quadrant multiplier 600. The control terminal of transistor M15 receives the enable control signal (EN_CS). In some instances, transistor M15 and EN_CS may be omitted. The first terminal of transistor BP4 is coupled to the fifth terminal 608 of the 4-quadrant multiplier 600. The second terminal of transistor BP4 is coupled to the sixth terminal 609 of the 4-quadrant multiplier 600. The control terminal of transistor MP4 is coupled to the fourth terminal 606 of the 4-quadrant multiplier 600.

[0071] In operation, the 4-quadrant multiplier 600 is configured to: receive VDD at the first terminal 602; receive the first ("A") value at the second ("A") terminal 604; receive the second ("B") value at the third ("B") terminal 605; receive the third ("C") value at the fourth ("C") terminal 606; and provide an output at the fifth terminal 608. If value A is omitted and values ​​B and C are provided instead, the 4-quadrant multiplier 600 outputs at terminal 608. If values ​​A and C are provided while value B is omitted, the 4-quadrant multiplier 600 outputs at terminal 608. If values ​​A and B are provided while value C is omitted, the 4-quadrant multiplier 600 outputs at terminal 608. And so on.

[0072] Figure 7AThis is a schematic diagram of an example current ripple tracker circuit 700. The current ripple tracker circuit 700 is used to provide I_RIPPLE / 2, which can be provided by an adaptive slope compensation circuit system (e.g., adaptive slope compensation circuit system 302 in Figure 3). Figure 4 The adaptive slope compensation circuit system 302 or Figure 5 The adaptive slope compensation circuit system 500 is used as the input parameter. In some instances, the current ripple tracker circuit 700 may be included together with the adaptive slope compensation circuit system. Figure 7A In one example, the current ripple tracker circuit 700 has a first terminal 702, a second terminal 704, a third terminal 706, a fourth terminal 708, and a fifth terminal 709.

[0073] exist Figure 7A In this example, the current ripple tracker circuit 700 includes switches S2 and S3, capacitors C1 and C2, arranged as shown in the figure. Each of switches S2 and S3 has a corresponding first terminal T1, a corresponding second terminal T2, and a corresponding control terminal T3. Each of capacitors C1 and C2 has a corresponding first terminal and a corresponding second terminal. The first terminal T1 of switch S2 is coupled to the first terminal 702 of the current ripple tracker circuit 700. The second terminal T2 of switch S2 is coupled to the first terminal of capacitor C1 and the first terminal T1 of switch S3. The control terminal T3 of switch S2 is coupled to the second terminal 704 of the current ripple tracker circuit 700. The second terminal of capacitor C1 is coupled to the fifth terminal 709 of the current ripple tracker circuit 700. The second terminal T2 of switch S3 is coupled to the first terminal of capacitor C2 and the fourth terminal of the current ripple tracker circuit 700. The control terminal T3 of switch S3 is coupled to the third terminal 706 of the current ripple tracker circuit 700. The second terminal of capacitor C2 is coupled to the fifth terminal 709 of current ripple tracker circuit 700.

[0074] The current ripple tracker circuit 700 is configured to: receive I_SENSE at the first terminal 702; receive an on-interval signal (TON) at the second terminal 704; receive an off-interval signal (TOFF) at the third terminal 706; and provide a current ripple metric (e.g., the I_RIPPLE / 2 value) in response to I_SENSE, TON, and TOFF.

[0075] Figure 7B This illustrates a current ripple tracker circuit (e.g., Figure 7AFigure 710 illustrates an example of current ripple tracking performed by a current ripple tracker circuit 700. In Figure 710, I_SENSE is shown as a ramp-up and ramp-down, and has an average value (AVG). In some instances, the current ripple metric output by the current ripple tracker circuit relative to the average value is equal to I_RIPPLE / 2.

[0076] Figure 8 This is a flowchart illustrating an adaptive slope compensation method 800. The adaptive slope compensation method 800 can be, for example, a switching converter controller (e.g., Figure 1 Controller 148 in Figure 2 Controller 248 or Figure 4 The adaptive slope compensation method 800 is executed by the switch converter controller 400 in the figure. As shown, the adaptive slope compensation method 800 includes operating the switch converter at block 802. At block 804, input parameters are obtained during the operation of the switch converter. Example input parameters include, but are not limited to, VIN, VOUT, FSW, I_RIPPLE, C_SC, and / or L. At block 806, the slope compensation current (e.g., I_ASC in this document) is adjusted in response to the input parameters. In some boost converters and some buck converter examples, the adaptive slope compensation current may vary with (VOUT / VIN)*FSW*I_RIPPLE*C_SC. At block 808, the slope compensation current is combined with the sensed current to obtain a compensated sensed current. At block 810, the compensated sensed current is used for switch converter control operation. For example, the compensated sensed current may affect when current peaks and / or current valleys are detected during switch converter control operation. Such switch converter control operation can be used to determine the switching of the power stage (e.g., Figure 1 The HS switch 120 and LS switch 128 in the power stage 106, or Figure 2 The on-time interval, off-time interval, or pause interval of the first switch 228 and the second switch 236 of the power stage 206 in the middle.

[0077] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0078] Furthermore, in this specification, the phrase "based on" means "at least partially based on". Therefore, if X is based on Y, then X may depend on Y and any number of other factors.

[0079] A device “configured to” perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or a combination thereof.

[0080] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnects or the ends thereof between device elements, circuit elements, integrated circuits, devices or other electronic or semiconductor components and / or conductors.

[0081] The circuits or devices described herein as containing certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may substantially contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the said passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0082] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used in practice with minimal alteration to the rest of the circuitry. For example, field-effect transistors (“FETs”) (e.g., NFETs or PFETs), bipolar junction transistors (BJTs, such as NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0083] Reference may be made to the control terminal of the transistor, as well as its first and second terminals, in the claims. In the context of a FET, the control terminal is the gate, and the first and second terminals are the drain and source, respectively. In the context of a BJT, the control terminal is the base, and the first and second terminals are the collector and emitter, respectively.

[0084] In this article, "FET on" means that there is a conductive channel in the FET and drain current can flow through it. "FET off" means that there is no conductive channel, and therefore drain current does not flow through the FET. However, "turning off" the FET allows current to flow through the body diode of the transistor.

[0085] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0086] While some elements in the described examples are contained within the integrated circuit, and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Furthermore, some or all features described as external to the integrated circuit may be contained within the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0087] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, and / or any other form of grounding connection applicable to or suited to the teachings herein. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter, or, if the parameter is zero, within a reasonable range of approximately zero.

[0088] Within the scope of the claims, modifications may be made in the described examples, and other examples are possible.

Claims

1. A system comprising: A power stage having a first terminal, a second terminal, a third terminal, and a fourth terminal; as well as A controller has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of the controller is coupled to the fourth terminal of the power stage. The second terminal of the controller is coupled to the third terminal of the power stage. The third terminal of the controller is coupled to the first terminal of the power stage. The fourth terminal of the controller is coupled to the second terminal of the controller. The controller includes an adaptive slope compensation circuit configured to: Obtain the input parameters; Adjust the scaling factor in response to the input parameters; In response to the scaling factor, the slope compensation current is adjusted; and In response to the adjusted slope compensation current, a slope compensation signal is output.

2. The system of claim 1, wherein the power stage is a boost converter, and the input parameters include input voltage (VIN), output voltage (VOUT), current ripple metric (I_RIPPLE), switching frequency (FSW), and slope compensation capacitor (C_SC).

3. The system of claim 2, wherein the adaptive slope compensation circuit is configured to adjust the scaling factor, the scaling factor varying with (VOUT / VIN)*FSW*I_RIPPLE*C_SC.

4. The system of claim 1, wherein the power stage is a buck converter, and the input parameters include input voltage (VIN), output voltage (VOUT), current ripple metric (I_RIPPLE), switching frequency (FSW), and slope compensation capacitor (C_SC).

5. The system of claim 4, wherein the adaptive slope compensation circuit is configured to adjust the scaling factor based on a function of (VIN / VOUT)*FSW*I_RIPPLE*C_SC.

6. The system according to claim 1, wherein the adaptive slope compensation circuit has a first terminal, a second terminal, a third terminal, a fourth terminal and a fifth terminal, the first terminal of the adaptive slope compensation circuit being adapted to receive a first input parameter, the second terminal of the adaptive slope compensation circuit being adapted to receive a second input parameter, the third terminal of the adaptive slope compensation circuit being adapted to receive a third input parameter, and the fourth terminal of the adaptive slope compensation circuit being adapted to receive a fourth input parameter.

7. The system of claim 6, wherein the adaptive slope compensation circuit comprises an adjustable current source circuit system having a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal, wherein the first terminal of the adjustable current source circuit system is coupled to the first terminal of the adaptive slope compensation circuit, the second terminal of the adjustable current source circuit system is coupled to the second terminal of the adaptive slope compensation circuit, the third terminal of the adjustable current source circuit system is coupled to the third terminal of the adaptive slope compensation circuit, and the fourth terminal of the adjustable current source circuit system is coupled to the fourth terminal of the adaptive slope compensation circuit.

8. The system of claim 7, wherein the adaptive slope compensation circuit comprises: A capacitor having a first terminal and a second terminal; and A switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the capacitor is coupled to the fifth terminal of the adjustable current source circuit system and the first terminal of the switch, and the second terminal of the switch is coupled to the fifth terminal of the adaptive slope compensation circuit.

9. The system of claim 8, wherein the adaptive slope compensation circuit comprises a 4-quadrant multiplier.

10. A switch converter controller, comprising: A current sensing circuit system having a first terminal and a second terminal; An adaptive slope compensation circuit system having a first terminal and a second terminal, the second terminal of the adaptive slope compensation circuit system being coupled to the second terminal of the current sensing circuit system, and the adaptive slope compensation circuit system including a multiplier; A comparator having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the comparator is coupled to the second terminal of the current sensing circuit system and the second terminal of the adaptive slope compensation circuit system; as well as A mode control logic having a first terminal and a second terminal, wherein the first terminal of the mode control logic is coupled to the third terminal of the comparator.

11. The switch converter controller of claim 10, wherein the adaptive slope compensation circuit system comprises a first voltage-to-current converter having a first terminal and a second terminal, a second voltage-to-current converter having a first terminal and a second terminal, the multiplier having a first terminal, a second terminal and a third terminal, the second terminal of the first voltage-to-current converter being coupled to the first terminal of the multiplier, and the second terminal of the second voltage-to-current converter being coupled to the second terminal of the multiplier.

12. The switch converter controller of claim 11, wherein the multiplier is a first multiplier, and the adaptive slope compensation circuit system includes a second multiplier having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the second multiplier is coupled to the third terminal of the first multiplier.

13. The switch converter controller of claim 12, wherein the adaptive slope compensation circuit system includes a third multiplier having a first terminal, a second terminal, and a third terminal, the first terminal of the third multiplier being coupled to the third terminal of the second multiplier.

14. The switch converter controller of claim 13, wherein the first voltage-to-current converter is configured to receive an input voltage from the power stage at a first terminal of the first voltage-to-current converter, and the second voltage-to-current converter is configured to receive an output voltage from the power stage at a first terminal of the second voltage-to-current converter.

15. The switch converter controller of claim 14, wherein the second multiplier is configured to receive a current ripple metric at a second terminal of the second multiplier, and the third multiplier is configured to receive a switching frequency at a second terminal of the third multiplier.

16. A switch converter controller, comprising: Current sensing circuit system; An adaptive slope compensation circuit system, which is coupled to the current sensing circuit system; as well as A comparator coupled to the current sensing circuitry and the adaptive slope compensation circuitry, the adaptive slope compensation circuitry including an adjustable current source circuitry, a capacitor, and a switch, and configured to: Obtain input parameters and switch control signals; The adjustable current source circuit system is used to adjust the slope compensation current in response to the input parameters. The switch is controlled to adjust the charge on the capacitor in response to an adjusted slope compensation current and the switch control signal; and A slope compensation signal is output based on the charge on the capacitor.

17. The switch converter controller of claim 16, wherein the adjustable current source circuit system is configured to: The input voltage to the power stage is converted into the first current; The output voltage from the power stage is converted into a second current; and The slope compensation current is adjusted in response to the first current and the second current.

18. The switch converter controller of claim 17, wherein the adjustable current source circuit system is configured to: Determine the ratio of the second current to the first current; Multiply the ratio by the current ripple metric to obtain the first multiplication result; The first multiplication result is multiplied by the switching frequency to obtain the second multiplication result; and In response to the result of the second multiplication, the slope compensation current is adjusted.

19. The switch converter controller of claim 17, wherein the adjustable current source is configured to: Determine the ratio of the second current to the first current; Multiply the ratio by the current ripple metric to obtain the first multiplication result; The first multiplication result is multiplied by the switching frequency to obtain the second multiplication result; and In response to the result of the second multiplication, the slope compensation current is adjusted.

20. The switch converter controller of claim 17, further comprising mode control logic, wherein the switch converter controller is configured to: The adjusted slope-compensated current is combined with the current sensing signal from the current sensing circuit to obtain a compensated current sensing signal. The compensated current sensing signal is provided to the comparator to obtain a comparison result; The comparison result is provided to the mode control logic; and In response to the comparison result, the switching control signal for the power stage is adjusted.

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