A preparation process of an embedded microfluidic chip

Abstract

The present application relates to the technical field of microfluidic chip preparation, and particularly relates to a preparation process of embedded microfluidic chip, which comprises substrate pretreatment, microchannel maskless etching, in-situ functional layer embedding, cover plate matching treatment, low-temperature hetero-bonding and post-treatment and detection. The femtosecond laser maskless etching technology is used to save the high-cost link of custom photomask, the in-situ plasma functional layer deposition process avoids secondary transportation pollution, and the low-temperature hetero-bonding method retains the complete performance of the functional layer, thereby solving the problems of traditional microfluidic preparation process, such as large workshop investment, low mask reuse rate, difficulty in adapting to small-batch customization demand, insufficient yield, poor versatility, and realizing mass production without high-end clean workshop, improving overall yield, reducing production cost, and simultaneously adapting to two application scenarios by adjusting the functional precursor composition, and taking into account the core technical effects of manufacturing cost control, product performance improvement and multi-scene process reuse.

Description

Technical Field

[0001] This invention relates to the field of microfluidic chip fabrication technology, and more specifically to a fabrication process for an embedded microfluidic chip. Background Technology

[0002] Microfluidic chips, as the core platform for miniaturized fluid control and processing, have been widely used in many fields such as bioanalysis, chemical synthesis, drug screening, and heat dissipation of high-power chips.

[0003] Currently available embedded microfluidic chip fabrication processes generally suffer from the following technical bottlenecks: First, traditional photolithography relies on nanoscale masks and cleanrooms of class 10,000 or above. Equipment investment costs account for more than 30% of the total production cost, and the mask reuse rate is low, making it difficult to adapt to the demand for multi-model small-batch customization. Second, microchannel functionalization modification often adopts a post-assembly soaking method, which not only requires additional cleaning and drying steps, but also easily introduces particulate contamination leading to channel blockage, resulting in a yield rate generally below 50%. Third, the bonding of heterogeneous materials often involves high-temperature treatment at temperatures above 100°C, which can easily damage the pre-modified biomolecular coating or heat dissipation functional layer, leading to a decrease in chip performance. Fourth, existing processes are mostly designed for single application scenarios and cannot meet the needs of hydrophilic and hydrophobic modification in biological detection scenarios as well as the need for high thermal conductivity layer deposition in heat dissipation scenarios, resulting in poor process versatility. Publicly available patents, such as the CN223717179U patent from Suzhou Baijie Chip Technology Co., Ltd., only focus on the structural design of microfluidic devices and do not involve the optimization of the underlying fabrication process; the embedded heat dissipation microfluidic chip process disclosed by the Swiss Federal Institute of Technology in Lausanne is only for the heat dissipation scenario of GaN power chips and does not consider the material compatibility requirements of biological detection scenarios, so it cannot achieve process reuse.

[0004] Therefore, there is an urgent need to develop a fabrication process for embedded microfluidic chips to solve the above problems. Summary of the Invention

[0005] To address the technical problems existing in the prior art, this invention proposes a fabrication process for embedded microfluidic chips. Through substrate pretreatment, maskless etching of microchannels, in-situ functional layer embedding, cover plate matching treatment, low-temperature heterogeneous bonding, and post-processing and inspection, the process employs femtosecond laser maskless etching, in-situ plasma functional layer deposition, and low-temperature heterogeneous bonding to achieve the technical effects of eliminating the need for high-end cleanrooms, improving yield, and being adaptable to dual application scenarios.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A fabrication process for an embedded microfluidic chip includes the following steps: S1. Substrate pretreatment: Cleaning and surface activation treatment of the selected substrate material; S2. Microchannel maskless etching: Microchannel structures are formed by directly etching the substrate surface using a femtosecond laser along a preset path, without the need to prepare a photomask. S3. In-situ functional layer embedding: After etching, the substrate is not removed. The functional precursor is directly introduced into the etching cavity and the required functional layer is formed in-situ on the inner wall of the microchannel by plasma deposition. S4. Cover plate matching process: Clean and activate the cover plate material, and pre-etch the corresponding microchannel inlet and outlet. S5. Low-temperature heterogeneous bonding: After aligning the treated substrate with the cover plate, apply uniform pressure within a temperature range of 30-50℃ to complete covalent bonding; S6. Post-processing and inspection: The bonded chips are rinsed and tested for air tightness. After passing the test, they are packaged. Preparation can be completed without a cleanroom of Class 10,000 or above, with a high yield rate per batch. It can be adapted to different application scenarios such as biomedical detection or high-power chip heat dissipation simply by adjusting the composition of the functional precursor.

[0007] In some specific embodiments, the substrate pretreatment step specifically involves: sequentially ultrasonically cleaning the substrate with deionized water, anhydrous ethanol, and acetone for 15 minutes each, with a cleaning power of 120W and a temperature controlled at 25°C. After cleaning, the substrate is dried with 99.99% pure nitrogen at a pressure of 0.3MPa, and then placed in an oxygen plasma cleaning chamber for 5-8 minutes at a power of 100W and a vacuum degree of 0.5Torr. This process can completely remove organic contaminants and particulate impurities from the substrate surface. After treatment, the substrate surface has a small water contact angle, which can significantly improve the uniformity of subsequent etching and avoid etching depth deviations exceeding 5%.

[0008] In some specific embodiments, the maskless etching step of the microchannel employs a femtosecond laser with a wavelength of 1030 nm and a pulse width of 200 fs. The etching power is set to 1.2–2.0 W, and the scanning speed is 5–15 mm / s. The scanning is repeated 2–6 times depending on the required etching depth. After etching, the etching debris is removed by plasma purging with compressed air or a corresponding etching gas. The prepared microchannel has low edge roughness, and can meet the requirements for fluid directional flow without subsequent polishing. The etching accuracy error is controlled within ±2 μm, which is much higher than ±5 μm of traditional processes. With a precision level of m, the etching path can be directly modified through CAD files to adapt to the customized needs of multiple models; at the same time, the microchannel topology can be adjusted according to actual needs, including but not limited to parallel straight channels, sawtooth channels, manifold fractal channels, droplet generation cross channels, etc., without the need for additional mask template replacement. This makes the process adaptable to more subdivided application scenarios such as microfluidic droplet generation, single-cell sequencing, and digital PCR, significantly improving the process versatility. For small-batch customized models, the production cycle can be shortened from 7 days of traditional processes to less than 1 day.

[0009] In some specific embodiments, when applied to biomedical detection scenarios, the precursor for the in-situ functional layer embedding step uses polyethylene glycol diacrylate vapor with a mass fraction of 1%–3%, maintaining a cavity vacuum of 0.6–1.0 Torr, a plasma power of 60–100 W, and a deposition time of 10–15 minutes to form a hydrophilic functional layer with a thickness of 100–300 nm on the inner wall of the microchannel. The adhesion between the hydrophilic functional layer and the substrate can reach more than 5 MPa. It does not fall off after being soaked in a solution with pH 3–11 for 72 hours. The water contact angle in the microchannel is less than 15°, which can significantly reduce fluid flow resistance and prevent substances such as proteins and nucleic acids in biological samples from being adsorbed on the inner wall of the channel, thus avoiding a decrease in detection sensitivity.

[0010] In some specific embodiments, when applied to high-power chip heat dissipation scenarios, the precursor for the in-situ functional layer embedding step uses a mixture of methane and hydrogen gas and diamond nanoparticles with a particle size of 5-10 nm as the precursor. The cavity temperature is maintained at 280-320°C, the plasma power is 120-180W, and the deposition time is 15-25 minutes. A nanodiamond composite thermally conductive layer with a thickness of 300-800 nm is formed on the inner wall of the microchannel. The thermal conductivity of the prepared diamond functional layer can reach 1200 W / (m·K), which is more than 3 times that of pure silicon material. This can significantly improve the heat dissipation capacity of the microchannel. The bonding force between the functional layer and the silicon substrate can reach more than 8 MPa. It can operate for 1000 hours at a working temperature of 150°C without falling off or increasing interlayer thermal resistance.

[0011] In some specific embodiments, the cover material can be selected from any one of borosilicate glass, PMMA, PDMS, or monocrystalline silicon, depending on the application scenario. The cover pretreatment process is the same as the substrate pretreatment process. The liquid inlet and outlet are pre-etched using a carbon dioxide laser or femtosecond laser. After etching, plasma polishing is used to remove burrs from the edges of the through holes. The pre-etched through hole position error is small and can perfectly match the port position of the substrate microchannel, avoiding channel blockage or liquid leakage caused by alignment deviation during subsequent assembly. The roughness of the through hole edge is small and will not generate additional resistance to the flowing fluid.

[0012] In some specific embodiments, the low-temperature heterogeneous bonding step first aligns the substrate and cover plate using a visual recognition alignment system with an alignment accuracy of ±1μm. Then, the aligned chip is placed in the bonding cavity, and a uniform pressure of 0.2-0.5MPa is applied while the temperature is controlled at 30-50℃ for 10-25 minutes. Covalent bonds are formed by dangling bonds generated on the surface after plasma activation. The low-temperature bonding process does not damage the molecular structure of the pre-deposited functional layer. The bonded chip can withstand fluid pressures of over 0.8MPa without leakage, fully meeting the fluid drive requirements in biological detection processes and the high-flow-rate coolant delivery requirements in heat dissipation scenarios.

[0013] In some specific embodiments, the post-processing and testing steps are as follows: First, deionized water is introduced into the microchannel to rinse it three times, with each rinsing time being 3-5 minutes. Then, an airtightness test is performed by introducing compressed air at 0.2 MPa into the channel and immersing it in anhydrous ethanol for 1 minute. If no bubbles overflow, it is considered qualified. Qualified products are packaged after corresponding disinfection or anti-oxidation treatment according to the application scenario. The airtightness test can screen out chips with poor bonding and prevent unqualified products from flowing into downstream application scenarios. The rinsing process can completely remove the precursors and debris remaining in the channel and avoid contamination of the test sample or coolant.

[0014] In some specific embodiments, when preparing a microfluidic chip for POCT nucleic acid detection, a 1.1 mm thick borosilicate glass substrate is used, a 1.5 mm thick medical-grade PMMA cover is used, the microchannel width is set to 100-150 μm, the etching depth is 70-100 μm, and the functional layer uses a hydrophilic polyethylene glycol diacrylate coating. The prepared nucleic acid detection microfluidic chip has a faster sample loading speed than traditional PDMS chips, and the nucleic acid detection sensitivity can reach 200 copies / mL, which is two orders of magnitude higher than chips prepared by traditional processes. The total nucleic acid detection time can be shortened to less than 15 minutes, meeting the needs of rapid on-site detection.

[0015] In some specific embodiments, when fabricating a microfluidic chip for heat dissipation of high-power chips, a 500μm thick single-crystal silicon wafer is used as the substrate, a 1mm thick single-crystal silicon wafer is used as the cover plate, the microchannels adopt a sawtooth structure with a width of 80-120μm and an etching depth of 120-180μm, and the functional layer adopts a nanodiamond composite thermally conductive layer. The heat dissipation microfluidic chip fabricated with these parameters achieves a heat flux density of 3000W / cm². 2 Under these operating conditions, the highest surface temperature of the chip does not exceed 75℃, and the thermal resistance is as low as 0.08℃·cm. 2 / W, which improves heat dissipation performance compared to traditional embedded microfluidic heat dissipation chips, with a cooling power consumption of only 0.8W / cm². 2 It can meet the heat dissipation needs of next-generation high-power AI chips and GPU chips.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. The core process flow requires no adjustment; only the composition of the functional layer precursor needs to be changed to switch between different application scenarios. This allows for the production of multiple product categories without large-scale modifications to the production line. It can simultaneously cover the market demands of biomedical testing and high-power device heat dissipation. The process reusability and industrial value far exceed traditional single-scenario processes. Compared to the high-investment model of traditional processes requiring independent production lines and dedicated technical teams for different application scenarios, this invention only requires 1-2 days of precursor replacement training for production personnel to achieve multi-scenario product switching. The high production line reusability significantly reduces the barriers and investment risks for enterprises expanding into other fields.

[0017] 2. High-strength bonding of heterogeneous materials is achieved through dangling bonds on the surface after plasma activation, with a bonding strength exceeding 1.2 MPa. It can withstand fluid pressures exceeding 0.8 MPa without leakage, and the entire process is conducted in a low-temperature environment without damaging the molecular structure of the pre-deposited hydrophilic coating or thermally conductive functional layer. Compared to the complex process of traditional high-temperature bonding, which requires additional functional layer protection and post-bonding repair, the low-temperature bonding step of this invention directly preserves the original performance of the functional layer without additional post-processing. This further simplifies the production process, reduces the risk of performance loss during production, and provides long-term stability far superior to traditional high-temperature bonded products.

[0018] 3. Employing in-situ functional layer embedding technology, the functional layer can be deposited directly within the same etching chamber after microchannel etching without removing the substrate. This completely avoids the risk of particulate contamination introduced during secondary transport and assembly. The microchannel yield is improved compared to traditional post-modification processes, and the overall chip yield is higher than that of traditional processes. Downstream application requirements can be met without additional sorting steps. Compared to traditional complex processes, integrating functional layer fabrication with microchannel etching reduces process steps, significantly improves production efficiency, and reduces product loss caused by multiple process transfers.

[0019] 4. Employing femtosecond laser maskless etching technology, this method eliminates the need for high-end cleanrooms and custom masks. Microchannel etching can be completed simply by importing CAD path files, reducing single-batch production costs compared to traditional processes and shortening the production cycle for small-batch customized models. It fully adapts to the cost control requirements of China's IVD centralized procurement model while meeting customers' flexible customization needs for multiple models. No additional production line investment is required, and the same production line can simultaneously produce multiple chip products with different structures and application scenarios, significantly reducing the overall production cost of multiple product categories. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart illustrating the fabrication process of the embedded microfluidic chip described in this invention. Figure 2 This is a schematic cross-sectional view of the embedded microfluidic chip for six-in-one detection of respiratory pathogens prepared in Example 1; Figure 3 The thermal resistance-heat flux density test comparison curves of the embedded microfluidic chip prepared in Example 2 are shown below. Figure 4 This is a bar chart comparing the production cost and yield of the process of this invention with that of traditional photolithography. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0022] Unless otherwise stated, all percentages, parts, ratios, etc. in this document are by weight.

[0023] The materials, methods, and embodiments described herein are exemplary and should not be construed as limiting unless otherwise stated.

[0024] Example 1 This embodiment provides a fabrication process for an embedded microfluidic chip for practical applications of a six-in-one respiratory pathogen detection system. It can simultaneously detect six common pathogens: influenza A virus, influenza B virus, respiratory syncytial virus, adenovirus, mycoplasma pneumoniae, and chlamydia pneumoniae. The process includes the following steps: S1. Substrate Pretreatment: A 1.1mm thick borosilicate glass substrate was selected. The substrate was ultrasonically cleaned sequentially with deionized water, anhydrous ethanol, and acetone for 15 minutes each. The cleaning power was set at 120W, and the temperature was controlled at 25℃. After cleaning, the surface residual solvent was dried with 99.99% pure nitrogen at a pressure of 0.3MPa. Subsequently, the substrate was placed in an oxygen plasma cleaning chamber for 5 minutes at a power of 100W and a vacuum degree of 0.5Torr to completely remove organic contaminants and particulate impurities from the substrate surface. This step included a batch sampling quality control point: one substrate out of every 20 substrates was sampled to test the surface contact angle. Unqualified batches were re-washed. The batch pass rate was required to be ≥99.5%, meeting the quality control requirements for large-scale mass production. The contact angle of the treated substrate surface was less than 5°, which improved the uniformity of subsequent etching and avoided etching depth deviations.

[0025] S2. Microchannel Maskless Etching: A femtosecond laser with a wavelength of 1030nm and a pulse width of 200fs is used to etch microchannels onto the pretreated glass substrate. The etching path is directly imported from the CAD file, eliminating the need for a photomask. The etching power is set to 1.5W, the scanning speed to 10mm / s, and the scan is repeated 3 times. The etching depth is controlled at 80μm, and the microchannel width is set to 120μm. After etching, compressed air is used to blow away the glass debris generated during etching. This step includes an online visual inspection quality control point: after etching, the channel size of each substrate is automatically scanned, and products with an etching depth deviation exceeding ±5% are automatically rejected. The online inspection efficiency can reach 120 pieces / hour, adapting to mass production cycles, and the edge roughness of the prepared microchannels is less than 0.4μm.

[0026] S3. In-situ Functional Layer Embedding: After etching, without removing the substrate, a 2% (w / w) polyethylene glycol diacrylate (PEGDA) precursor vapor is directly introduced into the etching chamber to maintain a vacuum of 0.8 Torr. The plasma generator is turned on at 80W, and the deposition time is 12 minutes, forming a 200nm thick hydrophilic functional layer in situ on the inner wall of the microchannel. After deposition, nitrogen gas is purged into the chamber for 5 minutes to remove any unreacted precursor residue. The functional layer prepared in this step has an adhesion strength of over 5MPa to the glass substrate and does not detach after immersion in a solution with pH 3-11 for 72 hours, thus forming the microchannel.

[0027] S4. Cover Plate Matching Process: 1.5mm thick medical-grade PMMA is selected as the cover plate. It undergoes the same pretreatment process as the substrate, including cleaning and oxygen plasma activation. Subsequently, a carbon dioxide laser is used to pre-etch 1.5mm diameter through-holes at the corresponding microchannel inlet and outlet positions on the cover plate. The edges of the through-holes are plasma polished to remove any burrs. The positional error of the pre-etched through-holes in this step is less than ±10μm, ensuring a perfect match with the port positions of the substrate microchannels and preventing alignment deviations during subsequent assembly.

[0028] S5. Low-Temperature Heterogeneous Bonding: A glass substrate with etched microchannels and a pre-drilled PMMA cover plate are placed on a high-precision alignment platform. A visual recognition system aligns the microchannels and vias with an accuracy of ±1μm. The aligned chip is then placed in a bonding cavity, and a uniform pressure of 0.3MPa is applied while maintaining a temperature of 40℃ for 15 minutes. Covalent bonds are formed using dangling bonds generated on the surface after plasma activation, completing the bonding process. This low-temperature bonding process does not damage the molecular structure of the PEGDA hydrophilic functional layer. The bonded chip can withstand a fluid pressure of 0.8MPa without leakage, fully meeting the fluid-driven requirements of nucleic acid detection.

[0029] S6. Post-processing and testing: After bonding, the chip is rinsed with deionized water 3 times, each time for 5 minutes. Then, an airtightness test is performed by introducing 0.2MPa compressed air into the channel and immersing it in anhydrous ethanol for 1 minute. If no bubbles overflow, it is considered qualified. Qualified chips are then packaged after UV sterilization.

[0030] In this embodiment, the prepared respiratory pathogen six-in-one microfluidic chip was tested and verified by clinical samples. It has a high positive concordance rate and a high negative concordance rate. The total detection time can be controlled within 20 minutes, which meets the rapid detection needs of clinical outpatient and emergency departments. The mass production process has excellent stability. The yield fluctuation of 10 consecutive batches of large-scale production does not exceed 2%. The manufacturing cost of a single chip is low, which meets the domestic IVD centralized procurement pricing requirements.

[0031] Example 2 This embodiment provides a fabrication process for an embedded microfluidic chip, adapted to the actual heat dissipation requirements of NVIDIA H100 / H200 level AI GPUs, and also compatible with the heat dissipation scenarios of high-power chips for automotive autonomous driving. The process includes the following steps: S1. Substrate Pretreatment: A 500μm thick monocrystalline silicon wafer was selected as the substrate. The wafer underwent organic cleaning, deionized water rinsing, and dilute hydrofluoric acid immersion to remove the oxide layer, following the standard RCA cleaning process. After cleaning, it was dried with nitrogen and treated with oxygen plasma for 8 minutes to remove residual hydrofluoric acid and impurities. This step resulted in an oxide layer thickness of less than 1nm on the silicon wafer surface, which improved the adhesion of the subsequent diamond functional layers and prevented increased interlayer thermal resistance during heat dissipation.

[0032] S2. Maskless Microchannel Etching: A femtosecond laser is used to etch serrated microchannels onto a silicon substrate. The etching power is 2W, the scanning speed is 8mm / s, and the scan is repeated 5 times. The etching depth is controlled at 150μm, the channel width is 100μm, and the spacing between adjacent channels is 80μm. After etching, isotropic etching is performed with XeF2 gas for 3 minutes to remove silicon debris and the surface recast layer generated during etching. The serrated microchannels prepared in this step can enhance fluid turbulence and improve heat dissipation efficiency. The small surface roughness of the etched channels can reduce fluid pressure.

[0033] S3. In-situ Functional Layer Embedding: After etching, a mixture of methane and hydrogen gas is directly introduced into the cavity, along with a suspension of 5nm diamond nanoparticles in aerosol. The cavity temperature is maintained at 300℃ (far lower than the 800℃ or higher temperature required for traditional CVD diamond deposition). The plasma power is 150W, and the deposition time is 20 minutes. A 500nm thick nanodiamond composite thermally conductive layer is formed in-situ on the inner wall of the microchannel. After deposition, argon gas is introduced to purge the cavity for 10 minutes. The thermal conductivity of the diamond functional layer prepared in this step can reach 1200W / (m·K), which is more than three times that of pure silicon. This significantly improves the heat dissipation capacity of the microchannel. The bonding strength between the functional layer and the silicon substrate can reach over 8MPa, and it does not detach during long-term operation at a working temperature of 150℃.

[0034] S4. Cover Plate Matching Process: A 1mm thick silicon wafer is selected as the cover plate. After RCA cleaning and plasma activation, the inlet and outlet are etched at corresponding positions on the cover plate. Simultaneously, a 1μm thick copper layer is deposited on the cover plate surface as a circuit connection layer. This copper layer deposition is completed simultaneously with the cover plate pretreatment, eliminating the need for additional assembly steps and achieving the integration of heat dissipation and electrical connection functions.

[0035] S5. Low-Temperature Heterogeneous Bonding: After aligning the silicon substrate and silicon cover plate on the alignment platform, place them in the bonding cavity, apply a pressure of 0.4 MPa, and maintain the temperature at 50°C for 20 minutes to complete the silicon-silicon covalent bonding. This low-temperature bonding step does not damage the structure of the diamond thermally conductive layer, nor does it cause copper layer oxidation. The bonding strength can reach over 1.5 MPa and can withstand a coolant flow rate of 2 m / s without leakage.

[0036] S6. Post-processing and testing: After bonding is completed, deionized water is introduced into the channel to rinse away residual impurities, and then the heat dissipation performance is tested.

[0037] In this embodiment, actual installation verification shows that when the H100 GPU is running at full load, the maximum core temperature is lower than that of traditional water cooling solutions, improving the overall energy efficiency of the data center at a heat flux density of 3000W / cm². 2 Under these operating conditions, the highest surface temperature of the chip does not exceed 75℃, and the thermal resistance is as low as 0.08℃·cm. 2 / W, which can fully meet the heat dissipation requirements of H100 / H200 level AI GPUs during long-term full-load operation. Meanwhile, this product has passed automotive-grade reliability verification: no leakage and no functional layer delamination after 1000 temperature cycles from -40℃ to 125℃, meeting the heat dissipation requirements of automotive autonomous driving chips. The single-batch mass production yield of this embodiment can reach 86%, and the production cost is lower than that of traditional photolithography processes, making it suitable for large-scale application needs.

[0038] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A fabrication process for an embedded microfluidic chip, characterized in that, Includes the following steps: S1. Substrate pretreatment: Cleaning and surface activation treatment of the selected substrate material; S2. Microchannel maskless etching: Microchannel structures are formed by directly etching the substrate surface using a femtosecond laser along a preset path, without the need to prepare a photomask. S3. In-situ functional layer embedding: After etching, the substrate is not removed. The functional precursor is directly introduced into the etching cavity and the required functional layer is formed in-situ on the inner wall of the microchannel by plasma deposition. S4. Cover plate matching process: Clean and activate the cover plate material, and pre-etch the corresponding microchannel inlet and outlet. S5. Low-temperature heterogeneous bonding: After aligning the treated substrate with the cover plate, apply uniform pressure within a temperature range of 30-50℃ to complete covalent bonding; S6. Post-processing and inspection: After bonding, the chip is rinsed and tested for air tightness. If it passes the test, it is packaged.

2. The fabrication process of an embedded microfluidic chip according to claim 1, characterized in that, In step S1, the specific steps are as follows: the substrate is ultrasonically cleaned for 15 minutes each with deionized water, anhydrous ethanol, and acetone in sequence, with a cleaning power of 120W and a temperature controlled at 25°C. After cleaning, it is dried with 99.99% pure nitrogen gas at a pressure of 0.3MPa, and then placed in an oxygen plasma cleaning chamber for 5-8 minutes with a power of 100W and a vacuum degree of 0.5Torr.

3. The fabrication process of an embedded microfluidic chip according to claim 1, characterized in that, In step S2, a femtosecond laser with a wavelength of 1030nm and a pulse width of 200fs is used. The etching power is set to 1.2-2.0W and the scanning speed is 5-15mm / s. The scanning is repeated 2-6 times according to the required etching depth. After etching, the etching debris is removed by plasma purging with compressed air or the corresponding etching gas.

4. The fabrication process of an embedded microfluidic chip according to claim 1, characterized in that, When applied to biomedical detection scenarios, the precursor for the in-situ functional layer embedding step is polyethylene glycol diacrylate vapor with a mass fraction of 1%–3%, maintaining a cavity vacuum of 0.6–1.0 Torr, a plasma power of 60–100 W, and a deposition time of 10–15 minutes, forming a hydrophilic functional layer with a thickness of 100–300 nm on the inner wall of the microchannel.

5. The fabrication process of an embedded microfluidic chip according to claim 1, characterized in that, When applied to high-power chip heat dissipation scenarios, the precursor for the in-situ functional layer embedding step uses a mixture of methane and hydrogen gas and diamond nanoparticles with a particle size of 5-10 nm as the precursor. The cavity temperature is maintained at 280-320℃, the plasma power is 120-180W, and the deposition time is 15-25 minutes, forming a nanodiamond composite thermally conductive layer with a thickness of 300-800 nm on the inner wall of the microchannel.

6. The fabrication process of an embedded microfluidic chip according to claim 1, characterized in that, The cover material can be selected from any one of borosilicate glass, PMMA, PDMS or monocrystalline silicon, depending on the application scenario. The cover pretreatment process is the same as the substrate pretreatment process. The liquid inlet and outlet are pre-etched using a carbon dioxide laser or femtosecond laser. After etching, plasma polishing is used to remove burrs from the edges of the through holes.

7. The fabrication process of an embedded microfluidic chip according to claim 1, characterized in that, In step S5, the substrate and cover plate are first aligned using a visual recognition alignment system with an alignment accuracy of ±1μm. Then, the aligned chip is placed into the bonding cavity, a uniform pressure of 0.2-0.5MPa is applied, the temperature is controlled at 30-50℃, and maintained for 10-25 minutes. Covalent bonds are formed by dangling bonds generated on the surface after plasma activation.

8. The fabrication process of an embedded microfluidic chip according to claim 1, characterized in that, In step S6, the specific steps are as follows: First, deionized water is introduced into the microchannel to rinse it 3 times, each rinsing time is 3-5 minutes. Then, an airtightness test is performed by introducing 0.2MPa compressed air into the channel and immersing it in anhydrous ethanol for 1 minute. If no bubbles overflow, it is considered qualified. Qualified products are then packaged after corresponding disinfection or anti-oxidation treatment according to the application scenario.

9. The fabrication process of an embedded microfluidic chip according to claim 1, characterized in that, When preparing a microfluidic chip for POCT nucleic acid detection, a 1.1 mm thick borosilicate glass substrate is selected, a 1.5 mm thick medical-grade PMMA cover is selected, the microchannel width is set to 100-150 μm, the etching depth is 70-100 μm, and the functional layer adopts a hydrophilic coating of polyethylene glycol diacrylate.

10. The fabrication process of an embedded microfluidic chip according to claim 1, characterized in that, When fabricating microfluidic chips for heat dissipation of high-power chips, a 500μm thick single-crystal silicon wafer is selected as the substrate, a 1mm thick single-crystal silicon wafer is selected as the cover plate, the microchannel adopts a sawtooth structure with a width of 80-120μm and an etching depth of 120-180μm, and the functional layer adopts a nanodiamond composite thermal conductive layer.

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