Membrane structure and method of manufacturing and testing thereof

Abstract

The application relates to a MEMS structure and a preparation method and a testing method thereof, the MEMS structure comprising a substrate, a device unit and a testing unit; the testing unit comprises a first testing electrode, a second testing electrode and a third testing electrode, the first testing electrode is formed in the same process as a fixed electrode layer in the device unit, the second testing electrode and the third testing electrode are both formed in the same process as a movable electrode layer in the device unit, a testing boss structure provided on one side of the second testing electrode towards the first testing electrode is formed in the same process as a boss structure provided on one side of the movable electrode layer towards the fixed electrode layer; the first testing electrode and the second testing electrode and the first testing electrode and the third testing electrode are both separated by an insulating medium; the areas of the second testing electrode, the testing boss structure and the third testing electrode opposite to the first testing electrode are respectively S1, S2 and S3, and S3=S1-S2. In this way, the distance between the boss structure and the fixed electrode layer can be measured on line.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a MEMS structure and its fabrication and testing methods. Background Technology

[0002] MEMS (Micro-Electro-Mechanical System) devices have advantages such as small size and low power consumption, and are widely used in various electronic devices.

[0003] In MEMS devices, movable electrode layers are typically suspended from fixed electrode layers by cantilever beams, allowing them to move towards the fixed electrode layers under the influence of electric fields, inertial forces, etc. To prevent excessive movement of the movable electrode layers from damaging the cantilever beams and to prevent large-area contact between the movable electrode layers and the fixed electrode layers, which could lead to engagement failure, a boss structure is usually provided on the side of the movable electrode layer facing the fixed electrode layer. This boss structure acts as a mechanical stop, limiting the maximum displacement of the movable electrode layer, thereby ensuring reliable operation of the device within a safe displacement range.

[0004] The distance between the boss structure and the fixed electrode layer directly determines the maximum allowable movement distance of the movable electrode layer. Precise control of this distance is crucial for device performance and functional assurance. However, existing technologies lack effective means for online measurement of the distance between the boss structure and the fixed electrode layer. Summary of the Invention

[0005] In view of this, the present application provides a MEMS structure and its fabrication and testing methods to solve at least one problem existing in the background art.

[0006] In a first aspect, embodiments of this application provide a MEMS structure, including: a substrate, and device units and test units located on the substrate; wherein, The test unit includes a first test electrode, a second test electrode, and a third test electrode. The second test electrode and the third test electrode are located on the side of the first test electrode away from the substrate. The first test electrode is formed in the same process as the fixed electrode layer in the device unit. The second test electrode and the third test electrode are located in the same layer and are both formed in the same process as the movable electrode layer in the device unit. A test boss structure is provided on the side of the second test electrode facing the first test electrode. The test boss structure and the boss structure provided on the side of the movable electrode layer facing the fixed electrode layer are formed in the same process. An insulating medium separates the first test electrode from the second test electrode and from the third test electrode. The second test electrode, the first test electrode, and the insulating medium between them constitute a first test capacitor structure, and the third test electrode, the first test electrode, and the insulating medium between them constitute a second test capacitor structure. The area of ​​the second test electrode facing the first test electrode is S1, the area of ​​the test boss structure facing the first test electrode is S2, and the area of ​​the third test electrode facing the first test electrode is S3, where S3 = S1 - S2.

[0007] In conjunction with the first aspect of this application, in an optional embodiment, the number of test boss structures in the test unit is greater than the number of boss structures in the device unit.

[0008] In conjunction with the first aspect of this application, in an optional embodiment, the projection of the second test electrode and / or the third test electrode in the substrate thickness direction lies within the projection of the first test electrode in the substrate thickness direction.

[0009] Secondly, embodiments of this application provide a method for fabricating a MEMS structure, the method comprising: Provide a base; A fixed electrode layer and a first test electrode are formed on the substrate through the same process; A movable electrode layer, a second test electrode, and a third test electrode are formed through the same process. The movable electrode layer is located on the side of the fixed electrode layer away from the substrate, and a boss structure is provided on the side of the movable electrode layer facing the fixed electrode layer. Both the second and third test electrodes are located on the side of the first test electrode away from the substrate, and a test boss structure is provided on the side of the second test electrode facing the first test electrode. An insulating medium separates the first test electrode from the second test electrode and from the third test electrode. The second test electrode, the first test electrode, and the insulating medium between them constitute a first test capacitor structure, and the third test electrode, the first test electrode, and the insulating medium between them constitute a second test capacitor structure. The area of ​​the second test electrode facing the first test electrode is S1, the area of ​​the test boss structure facing the first test electrode is S2, and the area of ​​the third test electrode facing the first test electrode is S3, where S3 = S1 - S2.

[0010] In conjunction with a second aspect of this application, in an optional embodiment, the formation of the movable electrode layer, the second test electrode, and the third test electrode includes: A sacrificial layer is formed covering the substrate, the fixed electrode layer, and the first test electrode; The sacrificial layer is etched using the same mask pattern and the same etching process in the same process to form a first blind hole opposite to the fixed electrode layer and a second blind hole opposite to the first test electrode. A conductive material layer is formed to fill the first blind via and the second blind via and to cover the sacrificial layer; The conductive material layer is etched to form the movable electrode layer, the second test electrode, and the third test electrode; wherein, the conductive material layer located in the first blind via forms the boss structure, and the conductive material layer located in the second blind via forms the test boss structure; the portion of the sacrificial layer located between the first test electrode and the second test electrode, and between the first test electrode and the third test electrode, forms the insulating medium.

[0011] In conjunction with a second aspect of this application, in an optional embodiment, after forming the conductive material layer and before etching the conductive material layer, the method further includes: A first pad and a second pad are formed on the conductive material layer. The first pad corresponds to a preset position of the second test electrode, and the second pad corresponds to a preset position of the third test electrode. After etching the conductive material layer, the first pad is electrically connected to the second test electrode, and the second pad is electrically connected to the third test electrode.

[0012] In conjunction with the second aspect of this application, in an optional embodiment, the fixed electrode layer and the movable electrode layer constitute a device unit; the first test capacitor structure and the second test capacitor structure constitute a test unit; The number of test boss structures in the test unit is greater than the number of boss structures in the device unit.

[0013] In conjunction with a second aspect of this application, in an optional embodiment, the projection of the second test electrode and / or the third test electrode in the substrate thickness direction lies within the projection of the first test electrode in the substrate thickness direction.

[0014] Thirdly, embodiments of this application provide a testing method for MEMS structures, the method comprising: Provide a MEMS structure as described in any one of the first aspects or a MEMS structure prepared by the method described in any one of the second aspects; Measure the capacitance values ​​of the first test capacitor structure and the second test capacitor structure; Based on the capacitance difference between the first test capacitor structure and the second test capacitor structure, the spacing between the boss structure and the fixed electrode layer is determined.

[0015] In conjunction with a third aspect of this application, in an optional embodiment, the capacitance difference between the first test capacitor structure and the second test capacitor structure is equal to the capacitance value of the capacitor structure formed by the test boss structure, the first test electrode, and the insulating medium between them; determining the spacing between the boss structure and the fixed electrode layer based on the capacitance difference between the first test capacitor structure and the second test capacitor structure includes: Using the capacitance calculation formula of a parallel plate capacitor, based on the capacitance difference between the first test capacitor structure and the second test capacitor structure, S2, and the relative permittivity of the insulating medium, the distance between the test boss structure and the first test electrode is calculated. The distance between the boss structure and the fixed electrode layer is equal to the distance between the test boss structure and the first test electrode.

[0016] Compared with the prior art, the embodiments of this application have the following beneficial effects: The MEMS structure, its fabrication method, and testing method provided in this application embodiment are as follows: In the testing unit of the MEMS structure, the first test electrode and the fixed electrode layer in the device unit are formed in the same process; the second and third test electrodes are located in the same layer and are both formed in the same process as the movable electrode layer in the device unit; the test boss structure on the side of the second test electrode facing the first test electrode and the boss structure on the side of the movable electrode layer facing the fixed electrode layer are formed in the same process; therefore, the distance between the test boss structure and the first test electrode is equal to the distance between the boss structure and the fixed electrode layer; in the testing unit, the second test electrode... The areas S1, S2, and S3 of the test protrusion structure and the first test electrode facing each other satisfy S3 = S1 - S2. This ensures that the capacitance difference between the first and second test capacitor structures is equal to the capacitance value of the capacitor structure formed by the test protrusion structure, the first test electrode, and the insulating medium between them. Therefore, by measuring the capacitance values ​​of the first and second test capacitor structures and combining them with the parallel plate capacitance formula, the distance between the test protrusion structure and the first test electrode can be calculated, which is also the spacing between the protrusion structure and the fixed electrode layer. In this embodiment, the test units in the MEMS structure can be fabricated simultaneously with the device units without adding additional process steps or monitoring equipment, and without incurring additional costs. Online measurement of the spacing between the protrusion structure and the fixed electrode layer can be achieved through electrical testing. Furthermore, the number and position of the test units on the wafer can be flexibly set, thus enabling simultaneous evaluation of the process uniformity across the entire wafer based on the spacing between the protrusion structure and the fixed electrode layer at different locations on the wafer.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the structure of MEMS devices in related technologies; Figure 2 This is a schematic diagram of the MEMS structure provided in the embodiments of this application; Figure 3 A top view schematic diagram of the first test capacitor structure in the MEMS structure provided in the embodiments of this application; Figure 4 A schematic flowchart illustrating the fabrication method of the MEMS structure provided in the embodiments of this application; Figures 5 to 11 A cross-sectional structural diagram of the fabrication method of the MEMS structure provided in the embodiments of this application during the fabrication process; Figure 12 A flowchart illustrating the testing method for MEMS structures provided in this application embodiment. Detailed Implementation

[0019] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0020] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0021] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0022] When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0023] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship of one element or feature shown in the figure to other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. The terms “comprising” and / or “including,” when used in this specification, identify the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0025] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0026] For related technologies, please refer to Figure 1 The MEMS device includes a substrate 100, a fixed electrode layer 210 located on the substrate 100, and a movable electrode layer 220 suspended from the fixed electrode layer 210 away from the substrate 100 by a cantilever beam 211. A boss structure 221 is provided on the side of the movable electrode layer 220 facing the fixed electrode layer 210. The boss structure 221 limits the maximum displacement of the movable electrode layer 220, thereby ensuring reliable operation of the device within a safe displacement range. Precise control of the distance between the boss structure 221 and the fixed electrode layer 210 is crucial for achieving device performance and ensuring functionality.

[0027] Based on this, the embodiments of this application provide a MEMS structure, please refer to... Figure 2The MEMS structure includes a substrate 100, and a device unit 200 and a test unit 300 located on the substrate 100. The test unit 300 includes a first test electrode 310, a second test electrode 320, and a third test electrode 330. The second test electrode 320 and the third test electrode 330 are located on the side of the first test electrode 310 away from the substrate 100. The first test electrode 310 is formed in the same process as the fixed electrode layer 210 in the device unit 200. The second test electrode 320 and the third test electrode 330 are located in the same layer and are both formed in the same process as the movable electrode layer 220 in the device unit 200. A test boss structure 321 is provided on the side of the second test electrode 320 facing the first test electrode 310. The test boss structure 321 and the movable electrode layer 220 face... The boss structure 221 provided on one side of the fixed electrode layer 210 is formed in the same process; the first test electrode 310 and the second test electrode 320, as well as the first test electrode 310 and the third test electrode 330, are separated by an insulating medium 340; the second test electrode 320, the first test electrode 310 and the insulating medium 340 between them constitute the first test capacitor structure, and the third test electrode 330, the first test electrode 310 and the insulating medium 340 between them constitute the second test capacitor structure; the area of ​​the second test electrode 320 facing the first test electrode 310 is S1, the area of ​​the test boss structure 321 facing the first test electrode 310 is S2, and the area of ​​the third test electrode 330 facing the first test electrode 310 is S3, where S3 = S1 - S2.

[0028] In this embodiment, in the MEMS structure test unit 300, the first test electrode 310 and the fixed electrode layer 210 in the device unit 200 are formed in the same process. The second test electrode 320 and the third test electrode 330 are located in the same layer and are both formed in the same process as the movable electrode layer 220 in the device unit 200. The test boss structure 321 on the side of the second test electrode 320 facing the first test electrode 310 and the boss structure 221 on the side of the movable electrode layer 220 facing the fixed electrode layer 210 are formed in the same process. Therefore, the distance between the part of the second test electrode 320 other than the test boss structure 321 and the first test electrode 310, and the distance between the third test electrode 330 and the first test electrode 310 are both equal to the distance between the part of the movable electrode layer 220 other than the boss structure 221 and the fixed electrode layer 210. Moreover, the test boss structure 321 and the boss structure 221 have the same shape and size. Thus, the distance between the test boss structure 321 and the first test electrode 310 is equal to the distance between the boss structure 221 and the fixed electrode layer 210. In the test unit 300, the area S1 of the second test electrode 320 facing the first test electrode 310, the area S2 of the test boss structure 321 facing the first test electrode 310, and the area S3 of the third test electrode 330 facing the first test electrode 310 satisfy S3=S1-S2, so that the capacitance difference between the first test capacitor structure and the second test capacitor structure is equal to the capacitance value of the capacitor structure composed of the test boss structure 321, the first test electrode 310, and the insulating medium 340 between them. Thus, by measuring the capacitance values ​​of the first test capacitor structure and the second test capacitor structure, and combining them with the parallel plate capacitance formula, the distance between the test boss structure 321 and the first test electrode 310 can be calculated, which is also the distance between the boss structure 221 and the fixed electrode layer 210. In this embodiment, the test unit 300 in the MEMS structure can be fabricated simultaneously with the device unit 200 without requiring additional process steps or monitoring equipment, and without incurring additional costs. This allows for online measurement of the distance between the protrusion structure 221 and the fixed electrode layer 210 through electrical testing. Furthermore, the number and position of the test units 300 on the wafer can be flexibly configured, thus enabling simultaneous evaluation of the process uniformity across the entire wafer based on the distance between the protrusion structure 221 and the fixed electrode layer 210 at different locations on the wafer. Further, the test results of the distance between the protrusion structure 221 and the fixed electrode layer 210, as well as the process uniformity across the entire wafer, can also provide a reference for the analysis of MEMS device yield test results.

[0029] It is understood that in the embodiments of this application, the test unit 300 and the device unit 200 can be arranged at intervals in the middle of the wafer. In some specific embodiments, the test unit 300 may be located in the dicing area of ​​the wafer. This helps to save the area of ​​the wafer device area and improve the integration density. Of course, this application does not exclude the possibility that the test unit 300 is located in the wafer device area.

[0030] In some embodiments, please refer to Figure 2 The substrate 100 may include a substrate 101 and a dielectric layer 102 located on the substrate.

[0031] In this embodiment, the dielectric layer 102 can be used to insulate and isolate the substrate 101 and fix the electrode layer 210, as well as the substrate 101 and the first test electrode 310. The substrate 101 can be, for example, a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, etc., and this application does not specifically limit its application. The material of the dielectric layer 102 can be, for example, at least one of insulating materials such as oxides, nitrides, and oxynitrides. In a specific example, the material of the dielectric layer 102 can be an oxide (specifically, for example, silicon oxide).

[0032] In some embodiments, the materials of the fixed electrode layer 210 and the movable electrode layer 220 can be conductive materials. Exemplarily, the materials of the fixed electrode layer 210 and the movable electrode layer 220 can each be independently a semiconductor material or a metallic material. In a specific example, both the fixed electrode layer 210 and the movable electrode layer 220 are made of polycrystalline silicon.

[0033] In some embodiments, please refer to Figure 2 The device unit 200 may also include a cantilever beam 211 capable of supporting and suspending the movable electrode layer 220 on the side of the fixed electrode layer 210 away from the substrate 100.

[0034] In some specific embodiments, the material of the cantilever beam 211 can be the same as the material of the movable electrode layer 220. Thus, in the actual fabrication process, the cantilever beam 211 and the movable electrode layer 220 can be formed in a single step, thereby simplifying the process and reducing costs. Of course, this application does not exclude the possibility that the materials of the cantilever beam 211 and the movable electrode layer 220 may be different.

[0035] Please continue to refer to this. Figure 2 The cantilever beam 211 can be connected to the substrate 100 via a conductive pad 212, and the conductive pad 212 is electrically insulated from the fixed electrode layer 210.

[0036] In this embodiment, both the cantilever beam 211 and the conductive pad 212 can be made of conductive materials and are conductively connected to the movable electrode layer 220. The conductive pad 212 and the fixed electrode layer 210 are located on the same layer and are electrically insulated from each other, so that the movable electrode layer 220 and the fixed electrode layer 210 can be electrically connected through the pads located on the same layer, simplifying the wiring and manufacturing process.

[0037] In some specific embodiments, the material of the conductive pad 212 can be the same as the material of the fixed electrode layer 210. Thus, in the actual fabrication process, the conductive pad 212 and the fixed electrode layer 210 can be formed in a single step, thereby simplifying the process and reducing costs. Of course, this application does not exclude the possibility that the materials of the conductive pad 212 and the fixed electrode layer 210 are different.

[0038] It is understood that since the first test electrode 310 and the fixed electrode layer 210 are formed in the same process, the material of the first test electrode 310 is the same as the material of the fixed electrode layer 210. Since both the second test electrode 320 and the third test electrode 330 are formed in the same process as the movable electrode layer 220, the materials of the second test electrode 320 and the third test electrode 330 are the same as the material of the movable electrode layer 220.

[0039] In this embodiment, the insulating medium 340 can be an insulating medium layer, an air medium, or a combination of an insulating medium layer and an air medium. When the insulating medium 340 is an air medium, it can be considered that the first test electrode 310 and the second test electrode 320, as well as the first test electrode 310 and the third test electrode 330, are isolated by cavities.

[0040] In some embodiments, the insulating medium 340 may include an insulating medium layer connected between the first test electrode 310 and the second test electrode 320 and between the first test electrode 310 and the third test electrode 330.

[0041] The insulating dielectric layer provides support, keeping the distances between the first test electrode 310 and the second test electrode 320, as well as between the first test electrode 310 and the third test electrode 330, constant. This ensures more stable and reliable test results when measuring the capacitance values ​​of the first and second test capacitor structures. Furthermore, in the actual fabrication process of the device unit 200, a sacrificial layer is typically formed between the fixed electrode layer 210 and the movable electrode layer 220, and then removed to create a cavity between them, providing space for the movable electrode layer 220. Therefore, in the actual fabrication process, the portion of the sacrificial layer extending between the first test electrode 310 and the second test electrode 320, and between the first test electrode 310 and the third test electrode 330, can serve as the insulating dielectric layer without requiring additional processes. This simplifies the process and reduces costs.

[0042] For example, the material of the insulating dielectric layer can be at least one of insulating materials such as oxides, nitrides, and oxynitrides. In a specific example, the material of the insulating dielectric layer can be an oxide (specifically, for example, silicon oxide).

[0043] In this embodiment, the number of test boss structures 321 can be one or more. When the number of test boss structures 321 is multiple, S2 refers to the area of ​​all test boss structures 321 facing the first test electrode 310.

[0044] In some embodiments, the number of test boss structures 321 in the test unit 300 may be greater than the number of boss structures 221 in the device unit 200.

[0045] A wafer may include multiple device units 200 and multiple test units 300. The number of protrusion structures 221 in a single device unit 200 is generally small. When the number of test protrusion structures 321 in a single test unit 300 is small, the capacitance value of the capacitor structure formed by the test protrusion structure 321, the first test electrode 310, and the insulating medium 340 between them is too small, which may lead to relatively large measurement errors. In this embodiment, by setting the number of test protrusion structures 321 in a single test unit 300 to be greater than the number of protrusion structures 221 in a single device unit 200, it can be ensured that the area S2 of all test protrusion structures 321 facing the first test electrode 310 reaches a relatively large value. That is, it ensures that the capacitance value of the capacitor structure formed by the test protrusion structure 321, the first test electrode 310, and the insulating medium 340 between them is large, reducing the impact of test errors on the measurement results, thereby improving the accuracy of the distance test results between the protrusion structure 221 and the fixed electrode layer 210.

[0046] Please refer to Figure 3 The multiple test boss structures 321 in the test unit 300 can be arranged in a matrix. This reduces the complexity of the manufacturing process of the test boss structures 321 and makes it easier to control the alignment accuracy between the test boss structures 321 and the first test electrode 310, thereby helping to ensure the accuracy of the distance test results between the boss structures 221 and the fixed electrode layer 210.

[0047] It should be noted that the patterns of the projections of the boss structure 221 and the test boss structure 321 onto the thickness direction of the substrate 100 can be of any shape, such as a circle, rectangle, square or triangle.

[0048] In some embodiments, the radial dimension of the boss structure 221 is less than or equal to 3 μm. This effectively prevents the boss structure 221 from making large-area contact with the fixed electrode layer 210, which could lead to adhesion failure.

[0049] In some embodiments, the projections of the second test electrode 320 and / or the third test electrode 330 in the thickness direction of the substrate 100 lie within the projection of the first test electrode 310 in the thickness direction of the substrate 100. This facilitates the design and control of the facing areas of the second test electrode 320 and the third test electrode 330 with the first test electrode 310, thereby ensuring the accuracy of the spacing test results between the boss structure 221 and the fixed electrode layer 210.

[0050] Furthermore, the edges of the projections of the second test electrode 320 and / or the third test electrode 330 in the thickness direction of the substrate 100 are spaced apart from the edges of the projections of the first test electrode 310 in the thickness direction of the substrate 100. In this way, the projection of the first test electrode 310 in the thickness direction of the substrate 100 not only completely covers the projections of the second test electrode 320 and / or the third test electrode 330 in the thickness direction of the substrate 100, but also exceeds a certain range. This reduces the requirements for process alignment and avoids the problem of fluctuations in the capacitance values ​​of the first test capacitor structure and / or the second test capacitor structure due to process alignment errors between the second test electrode 320 and / or the third test electrode 330 and the first test electrode 310, which could affect the test accuracy.

[0051] In some embodiments, please refer to Figure 2 The test unit 300 may also include a first test electrode outlet 311 that is electrically connected to the first test electrode 310. This facilitates testing the capacitance values ​​of the first test capacitor structure and the second test capacitor structure.

[0052] Optionally, the first test electrode outlet 311 can be located on the same layer as the second test electrode 320. In this way, the second test electrode 320, the third test electrode 330, and the first test electrode outlet 311 can be fabricated in the same process, thereby simplifying the process and reducing costs.

[0053] In some embodiments, please refer to Figure 2 The test unit 300 may also include a conductive plug 312, one end of which is connected to the first test electrode 310 and the other end is connected to the first test electrode outlet 311.

[0054] In some embodiments, please refer to Figure 2 The test unit 300 may also include a first pad 301 and a second pad 302, wherein the first pad 301 is electrically connected to the second test electrode 320 and the second pad 302 is electrically connected to the third test electrode 330.

[0055] In some embodiments, please refer to Figure 2 The test unit 300 may also include a third pad 303, which is electrically connected to the first test electrode lead-out portion 311.

[0056] The second test electrode 320, the third test electrode 330, and the first test electrode 310 are electrically led out through the first pad 301, the second pad 302, and the third pad 303, respectively, so as to facilitate the testing of the capacitance value of the first test capacitor structure through the first pad 301 and the third pad 303, and the testing of the capacitance value of the second test capacitor structure through the second pad 302 and the third pad 303.

[0057] This application also provides a method for fabricating a MEMS structure; please refer to [reference needed]. Figure 4 The method for fabricating the MEMS structure provided in this application includes: Step S101, provide a substrate; Step S102: Through the same process, a fixed electrode layer and a first test electrode are formed on the substrate; In step S103, a movable electrode layer, a second test electrode, and a third test electrode are formed through the same process. The movable electrode layer is located on the side of the fixed electrode layer away from the substrate, and a boss structure is provided on the side of the movable electrode layer facing the fixed electrode layer. The second test electrode and the third test electrode are both located on the side of the first test electrode away from the substrate, and a test boss structure is provided on the side of the second test electrode facing the first test electrode. An insulating medium separates the first test electrode from the second test electrode and from the third test electrode. The second test electrode, the first test electrode, and the insulating medium between them constitute a first test capacitor structure, and the third test electrode, the first test electrode, and the insulating medium between them constitute a second test capacitor structure. The area of ​​the second test electrode facing the first test electrode is S1, the area of ​​the test boss structure facing the first test electrode is S2, and the area of ​​the third test electrode facing the first test electrode is S3, where S3 = S1 - S2.

[0058] It is understood that in the above method, by forming the fixed electrode layer and the first test electrode in the same process, and by forming the movable electrode layer, the second test electrode, and the third test electrode in the same process, the distance between the portion of the second test electrode (excluding the test boss structure) and the first test electrode, and the distance between the third test electrode and the first test electrode, are equal to the distance between the portion of the movable electrode layer (excluding the boss structure) and the fixed electrode layer. Furthermore, the test boss structures have the same shape and size as the boss structures, thus the distance between the test boss structure and the first test electrode is equal to the distance between the boss structure and the fixed electrode layer; in the test unit, the second... The area S1 of the test electrode facing the first test electrode, the area S2 of the test protrusion structure facing the first test electrode, and the area S3 of the third test electrode facing the first test electrode satisfy S3 = S1 - S2. This ensures that the capacitance difference between the first and second test capacitor structures is equal to the capacitance value of the capacitor structure formed by the test protrusion structure, the first test electrode, and the insulating medium between them. Therefore, by measuring the capacitance values ​​of the first and second test capacitor structures and combining them with the parallel plate capacitance formula, the distance between the test protrusion structure and the first test electrode can be calculated, which is also the spacing between the protrusion structure and the fixed electrode layer. In this embodiment, the test units in the MEMS structure can be fabricated simultaneously with the device units without adding additional process steps or monitoring equipment, and without incurring additional costs. Online measurement of the spacing between the protrusion structure and the fixed electrode layer can be achieved through electrical testing. Furthermore, the number and position of the test units on the wafer can be flexibly set, thus enabling simultaneous evaluation of the process uniformity across the entire wafer based on the spacing between the protrusion structure and the fixed electrode layer at different locations on the wafer.

[0059] Below, in conjunction with Figures 5 to 11and Figure 2 The present application provides a more detailed description of the fabrication method of the MEMS structure and the corresponding beneficial effects of the MEMS structure.

[0060] First, please refer to Figure 5 Step S101 is executed to provide substrate 100.

[0061] In some embodiments, providing the substrate 100 may include providing a substrate 101 and forming a dielectric layer 102 on the substrate 101.

[0062] The substrate 101 may be, for example, a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, etc., and this application does not specifically limit it. The dielectric layer 102 may be formed, for example, by a deposition process and / or a thermal oxidation process, wherein the material of the dielectric layer 102 may be, for example, at least one of insulating materials such as oxides, nitrides, and oxide oxynitrides. In a specific example, the material of the dielectric layer 102 may be an oxide (specifically, for example, silicon oxide).

[0063] Next, please refer to Figure 6 In step S102, a fixed electrode layer 210 and a first test electrode 310 are formed on the substrate 100 through the same process.

[0064] In the actual fabrication process, a first conductive material layer (not shown in the figure) can first be formed on the substrate 100. Then, the first conductive material layer is patterned to form a fixed electrode layer 210 and a first test electrode 310. The first conductive material layer can be formed, for example, using a deposition process. The patterning process can include: first, forming a patterned photoresist layer on the first conductive material layer to define the patterns of the fixed electrode layer 210 and the first test electrode 310; then, using the patterned photoresist layer as a mask, etching the first conductive material layer to form the fixed electrode layer 210 and the first test electrode 310. Because they are formed through the same process, the fixed electrode layer 210 and the first test electrode 310 are located in the same layer and have the same thickness. Here, "the same" can be understood as the thickness being the same within the allowable tolerance range of the process.

[0065] For example, the material of the first conductive material layer may be a semiconductor material or a metallic material. In a specific example, the material of the first conductive material layer may be polycrystalline silicon.

[0066] In some embodiments, please refer to Figure 6 In the step of patterning the first conductive material layer to form the fixed electrode layer 210 and the first test electrode 310, a conductive pad 212 can be formed simultaneously, and the conductive pad 212 is electrically insulated from the fixed electrode layer 210.

[0067] Finally, please refer to Figures 7 to 11 and Figure 2 In step S103, a movable electrode layer 220, a second test electrode 320, and a third test electrode 330 are formed through the same process. The movable electrode layer 220 is located on the side of the fixed electrode layer 210 away from the substrate 100, and a boss structure 221 is provided on the side of the movable electrode layer 220 facing the fixed electrode layer 210. The second test electrode 320 and the third test electrode 330 are both located on the side of the first test electrode 310 away from the substrate 100, and a test boss structure 321 is provided on the side of the second test electrode 320 facing the first test electrode 310. The first test electrode 310 and the second test electrode 320, as well as the third test electrode 330, are connected by a test boss structure 321. The first test electrode 310 and the third test electrode 330 are separated by an insulating medium 340; the second test electrode 320, the first test electrode 310 and the insulating medium 340 between them constitute the first test capacitor structure, and the third test electrode 330, the first test electrode 310 and the insulating medium 340 between them constitute the second test capacitor structure; the area of ​​the second test electrode 320 facing the first test electrode 310 is S1, the area of ​​the test boss structure 321 facing the first test electrode 310 is S2, and the area of ​​the third test electrode 330 facing the first test electrode 310 is S3, where S3 = S1 - S2.

[0068] In some embodiments, performing step S103 may include the following steps: Step S1031: Please refer to Figure 7 A sacrificial layer 110 is formed covering the substrate 100, the fixed electrode layer 210, and the first test electrode 310.

[0069] In actual fabrication processes, the sacrificial layer 110 can be formed, for example, using a deposition process. The material of the sacrificial layer 110 can be at least one of insulating materials such as oxides, nitrides, and oxynitrides. In a specific example, the material of the sacrificial layer 110 can be an oxide (specifically, for example, silicon oxide).

[0070] like Figure 7 As shown, when the conductive pad 212 is formed, the sacrificial layer 110 also covers the conductive pad 212.

[0071] In this embodiment, a portion of the sacrificial layer 110 is located between the subsequently formed first test electrode 310 and the second test electrode 320, and between the first test electrode 310 and the third test electrode 330. This ensures that the distances between the first test electrode 310 and the second test electrode 320, and between the first test electrode 310 and the third test electrode 330, remain fixed, thereby guaranteeing more stable and reliable test results when measuring the capacitance values ​​of the first and second test capacitor structures. Specifically, the sacrificial layer 110 located between the first test electrode 310 and the second test electrode 320, and between the first test electrode 310 and the third test electrode 330, serves as an insulating medium 340 between the first test electrode 310 and the second test electrode 320, and between the first test electrode 310 and the third test electrode 330.

[0072] Step S1032: Please refer to Figure 9 In the same process, the same mask pattern and the same etching process are used to etch the sacrificial layer 110 to form a first blind hole 2210 opposite to the fixed electrode layer 210 and a second blind hole 3210 opposite to the first test electrode 310.

[0073] The first blind via 2210 and the second blind via 3210 formed by etching the sacrificial layer 110 in the same process using the same mask pattern and the same etching process are identical. Here, "identical" can be understood as the first blind via 2210 and the second blind via 3210 being identical within the allowable range of mask pattern error and etching process error. The portion of the subsequently fabricated movable electrode layer located in the first blind via 2210 forms a boss structure, and the portion of the subsequently fabricated second test electrode located in the second blind via 3210 forms a test boss structure. Thus, by controlling the first blind via 2210 and the second blind via 3210 to be identical, the boss structure and the test boss structure can be controlled to have the same size and morphology. The number of first blind vias 2210 and the number of second blind vias 3210 can both be one or more. When the number of first blind vias 2210 and the number of second blind vias 3210 are both multiple, each first blind via 2210 and each second blind via 3210 is considered identical.

[0074] It should be noted that the projection patterns of the first blind hole 2210 and the second blind hole 3210 in the thickness direction of the substrate 100 can be of any shape, such as a circle, rectangle, square, or triangle. The projection patterns of the subsequently fabricated boss structure and the test boss structure in the thickness direction of the substrate 100 are the corresponding shapes.

[0075] Please refer to Figure 8Before or after forming the first blind hole 2210 and the second blind hole 3210, the fabrication method of the MEMS structure may further include: etching the sacrificial layer 110 to form the first through hole 2110 and the second through hole 3120, wherein the first through hole 2110 exposes the surface of the conductive pad 212 and the second through hole 3120 exposes part of the surface of the first test electrode 310.

[0076] Subsequently, a cantilever beam connecting the conductive pad 212 and the movable electrode layer can be formed in the first through hole 2110, and a conductive plug can be formed in the second through hole 3120 to conductively connect the first test electrode 310, which facilitates the capacitance value testing of the first test capacitor structure and the second test capacitor structure.

[0077] Since the depths of the first through hole 2110 and the second through hole 3120 are different from the depths of the first blind hole 2210 and the second blind hole 3210, forming the first through hole 2110 and the second through hole 3120 and the first blind hole 2210 and the second blind hole 3210 in two etching steps is beneficial to ensuring the stability and controllability of the process.

[0078] Step S1033: Please refer to Figure 10 A conductive material layer 120 is formed, which fills the first blind via 2210 and the second blind via 3210 and covers the sacrificial layer 110.

[0079] The conductive material layer 120 here can also be referred to as the second conductive material layer, which can be formed, for example, by a deposition process. The material of the second conductive material layer can be, for example, a semiconductor material or a metallic material. In a specific example, the material of the second conductive material layer can be polycrystalline silicon.

[0080] If the first through-hole 2110 and the second through-hole 3120 are also formed in the sacrificial layer 110, please refer to the step of forming the second conductive material layer. Figure 10 The second conductive material layer is also filled in the first through hole 2110 and the second through hole 3120. The second conductive material layer filled in the first through hole 2110 forms a cantilever beam 211, and the second conductive material layer filled in the second through hole 3120 forms a conductive plug 312. This simplifies the manufacturing process.

[0081] Step S1034: Please refer to Figure 2The conductive material layer 120 is etched to form a movable electrode layer 220, a second test electrode 320, and a third test electrode 330. The conductive material layer 120 located in the first blind hole 2210 forms a boss structure 221, and the conductive material layer 120 located in the second blind hole 3210 forms a test boss structure 321. The portion of the sacrificial layer 110 located between the first test electrode 310 and the second test electrode 320 and between the first test electrode 310 and the third test electrode 330 forms an insulating medium 340.

[0082] In this embodiment, the movable electrode layer 220, the second test electrode 320, and the third test electrode 330 can be formed by etching the conductive material layer 120 in one step. Since they are formed through the same process, the movable electrode layer 220, the second test electrode 320, and the third test electrode 330 are located in the same layer and have the same thickness. "The same" here can be understood as the thickness of the three being the same within the allowable error range of the process. Simultaneously, as described above, since the first blind hole 2210 and the second blind hole 3210 are identical, the formed boss structure 221 and the test boss structure 321 have the same size and morphology. Thus, the distance between the test boss structure 321 and the first test electrode 310 is equal to the distance between the boss structure 221 and the fixed electrode layer 210. Furthermore, the distance between the boss structure 221 and the fixed electrode layer 210 can be determined by measuring the distance between the test boss structure 321 and the first test electrode 310.

[0083] It should be noted that the same process described in the embodiments of this application may include one process step or multiple process steps. For example, in the above embodiments, the three steps of etching the sacrificial layer 110 to form the first blind hole 2210 and the second blind hole 3210, forming the conductive material layer 120, and etching the conductive material layer 120 can be regarded as the same process of forming the movable electrode layer 220, the second test electrode 320, and the third test electrode 330.

[0084] In this embodiment, the number of test protrusion structures 321 formed can be one or more. When the number of test protrusion structures 321 is multiple, S2 refers to the area of ​​all test protrusion structures 321 facing the first test electrode 310.

[0085] Please refer to Figure 2 In this embodiment, the fixed electrode layer 210 and the movable electrode layer 220 constitute the device unit 200; the first test capacitor structure and the second test capacitor structure constitute the test unit 300. In some embodiments, the number of test boss structures 321 in the test unit 300 may be greater than the number of boss structures 221 in the device unit 200.

[0086] By setting the number of test boss structures 321 in a single test unit 300 to be greater than the number of boss structures 221 in a single device unit 200, it can be ensured that the area S2 of all test boss structures 321 facing the first test electrode 310 reaches a relatively large value. That is, it ensures that the capacitance value of the capacitor structure formed by the test boss structure 321, the first test electrode 310 and the insulating medium 340 between them is large, reducing the impact of test errors on the measurement results, thereby improving the accuracy of the distance test results between the boss structure 221 and the fixed electrode layer 210.

[0087] The multiple test boss structures 321 in the test unit 300 can be arranged in a matrix. That is, the multiple second blind holes 3210 in the above embodiment can be arranged in a matrix. This can reduce the fabrication complexity of the mask pattern corresponding to the second blind holes 3210, improve the controllability and stability of the fabrication process, and facilitate the control of the alignment accuracy between the test boss structure 321 and the first test electrode 310. This helps to ensure the accuracy of the distance test results between the boss structure 221 and the fixed electrode layer 210.

[0088] In the actual preparation process, please refer to... Figure 2 In the step of etching the conductive material layer 120 to form the movable electrode layer 220, the second test electrode 320 and the third test electrode 330, the first test electrode outlet 311 can also be formed simultaneously. The first test electrode outlet 311 can be connected to the conductive plug 312.

[0089] The first test electrode lead-out portion 311 is formed simultaneously with the movable electrode layer 220, the second test electrode 320, and the third test electrode 330. This not only simplifies the process but also facilitates the conductive connection of the first test electrode lead-out portion 311, the second test electrode 320, and the third test electrode 330, enabling testing of the capacitance values ​​of the first and second test capacitor structures. For example, it facilitates the fabrication of pads corresponding to the first test electrode lead-out portion 311, the second test electrode 320, and the third test electrode 330 in subsequent processes using the same step.

[0090] In some embodiments, please refer to Figure 11 After forming the conductive material layer 120 and before etching the conductive material layer 120, the fabrication method of the MEMS structure may further include: forming a first pad 301 and a second pad 302 on the conductive material layer 120, wherein the first pad 301 corresponds to a preset position of the second test electrode 320, and the second pad 302 corresponds to a preset position of the third test electrode 330; after etching the conductive material layer 120, please refer to... Figure 2 The first pad 301 is electrically connected to the second test electrode 320, and the second pad 302 is electrically connected to the third test electrode 330.

[0091] In the actual fabrication process, a metal layer (not shown in the figure) can first be formed on the conductive material layer 120, and then the metal layer can be patterned to form the first pad 301 and the second pad 302. Since the conductive material layer 120 has a flat surface before etching, the process of forming the metal layer on the conductive material layer 120 and etching the metal layer to form the first pad 301 and the second pad 302 is relatively easy to operate.

[0092] In some embodiments, please refer to Figure 11 In the steps of etching the conductive material layer 120 to form the first pad 301 and the second pad 302, a third pad 303 can also be formed simultaneously. The third pad 303 corresponds to a preset position of the first test electrode lead-out portion 311. After etching the conductive material layer 120, please refer to... Figure 2 The third pad 303 is electrically connected to the first test electrode outlet 311.

[0093] By fabricating the first pad 301, the second pad 302, and the third pad 303, the second test electrode 320, the third test electrode 330, and the first test electrode 310 are brought out to conduct electricity, thereby facilitating the testing of the capacitance value of the first test capacitor structure through the first pad 301 and the third pad 303, and the testing of the capacitance value of the second test capacitor structure through the second pad 302 and the third pad 303.

[0094] In some embodiments, the projections of the second test electrode 320 and / or the third test electrode 330 in the thickness direction of the substrate 100 lie within the projection of the first test electrode 310 in the thickness direction of the substrate 100. This facilitates the design and control of the facing areas of the second test electrode 320 and the third test electrode 330 with the first test electrode 310, thereby ensuring the accuracy of the test.

[0095] Furthermore, the edges of the projections of the second test electrode 320 and / or the third test electrode 330 in the thickness direction of the substrate 100 are spaced apart from the edges of the projections of the first test electrode 310 in the thickness direction of the substrate 100. In this way, the projection of the first test electrode 310 in the thickness direction of the substrate 100 not only completely covers the projections of the second test electrode 320 and / or the third test electrode 330 in the thickness direction of the substrate 100, but also exceeds a certain range. This reduces the requirements for process alignment and avoids the problem of fluctuations in the capacitance values ​​of the first test capacitor structure and / or the second test capacitor structure due to process alignment errors between the second test electrode 320 and / or the third test electrode 330 and the first test electrode 310, which could affect the test accuracy.

[0096] In some embodiments, the method for fabricating a MEMS structure may further include: removing the portion of the sacrificial layer 110 located between the fixed electrode layer 210 and the movable electrode layer 220, thereby forming a cavity between the fixed electrode layer 210 and the movable electrode layer 220. The formed cavity can provide movable space for the movable electrode layer 220.

[0097] Of course, this application does not exclude the possibility that, when removing the portion of the sacrificial layer 110 located between the fixed electrode layer 210 and the movable electrode layer 220, the portions of the sacrificial layer 110 located between the first test electrode 310 and the second test electrode 320, and between the first test electrode 310 and the third test electrode 330, may also be removed. In this case, the portions between the first test electrode 310 and the second test electrode 320, and between the first test electrode 310 and the third test electrode 330, are separated by cavities, i.e., the distance between the first test electrode 310 and the second test electrode 320, and the insulating medium 340 between the first test electrode 310 and the third test electrode 330, are air.

[0098] This application also provides a testing method for MEMS structures. Please refer to [link / reference]. Figure 12 The testing method for MEMS structures provided in this application includes: Step S201: Provide a MEMS structure as described in any of the foregoing embodiments or a MEMS structure prepared by the fabrication method of the MEMS structure described in any of the foregoing embodiments; Step S202: Measure the capacitance values ​​of the first test capacitor structure and the second test capacitor structure; Step S203: Based on the capacitance difference between the first test capacitor structure and the second test capacitor structure, determine the spacing between the boss structure and the fixed electrode layer.

[0099] It is understood that in the above method, the capacitance values ​​of the first and second test capacitor structures are first measured. Since the area S1 of the second test electrode facing the first test electrode, the area S2 of the test boss structure facing the first test electrode, and the area S3 of the third test electrode facing the first test electrode in the test unit satisfy S3=S1-S2, the capacitance difference between the first and second test capacitor structures is equal to the capacitance value of the capacitor structure formed by the test boss structure, the first test electrode, and the insulating medium between them. Then, based on the capacitance difference between the first and second test capacitor structures, the distance between the test boss structure and the first test electrode can be calculated using the parallel plate capacitance formula, which is also the distance between the boss structure and the fixed electrode layer. In this embodiment, the distance between the boss structure and the fixed electrode layer is measured online through electrical testing.

[0100] In this embodiment, the capacitance difference between the first test capacitor structure and the second test capacitor structure is equal to the capacitance value of the capacitor structure formed by the test boss structure, the first test electrode, and the insulating medium between them. Based on the capacitance difference between the first and second test capacitor structures, the distance between the boss structure and the fixed electrode layer is determined, including: using the capacitance calculation formula for a parallel plate capacitor, and based on the capacitance difference between the first and second test capacitor structures, S2, and the relative permittivity of the insulating medium, the distance between the test boss structure and the first test electrode is calculated. The distance between the boss structure and the fixed electrode layer is equal to the distance between the test boss structure and the first test electrode.

[0101] For details, please refer to Figure 2 According to the formula for calculating the capacitance of a parallel-plate capacitor, the capacitance value of the first test capacitor structure is... The capacitance value of the second test capacitor structure Where ε is the relative permittivity of the insulating medium 340, and k is 9.0 × 10⁻⁶. 9 N·m 2 / C 2 d is the distance between the third test electrode 330 and the first test electrode 310 (that is, the distance between the part of the second test electrode 320 excluding the test boss structure 321 and the first test electrode 310), and d1 is the distance between the test boss structure 321 and the first test electrode 310. Since S3 = S1 - S2, therefore, In this equation, ε, S2, π, and k are all known values. d1 can be calculated by measuring C1 and C2, thus obtaining the distance between the test protrusion structure 321 and the first test electrode 310. In the above MEMS structure design, the distance between the test protrusion structure 321 and the first test electrode 310 is equal to the distance between the protrusion structure 221 and the fixed electrode layer 210. This allows for online measurement of the distance between the protrusion structure 221 and the fixed electrode layer 210 through electrical testing.

[0102] In actual measurement, the capacitance value C1 of the first test capacitor structure can be tested through the first pad 301 and the third pad 303, and the capacitance value C2 of the second test capacitor structure can be tested through the second pad 302 and the third pad 303.

[0103] It should be noted that the MEMS structure embodiments, MEMS structure fabrication method embodiments, and MEMS structure testing method embodiments provided in this application belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict. However, it should be further noted that the combination of technical features of the MEMS structure provided in the embodiments of this application can already solve the technical problem to be solved by this application; therefore, the MEMS structure provided in the embodiments of this application is not limited to the fabrication method of the MEMS structure provided in the embodiments of this application, and any MEMS structure prepared by the fabrication method that can form the MEMS structure provided in the embodiments of this application is within the scope of protection of this application.

[0104] It should be understood that the above embodiments are exemplary and not intended to encompass all possible implementations. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A MEMS structure, characterized in that, Includes: a substrate, and device units and test units located on the substrate; wherein, The test unit includes a first test electrode, a second test electrode, and a third test electrode. The second test electrode and the third test electrode are located on the side of the first test electrode away from the substrate. The first test electrode is formed in the same process as the fixed electrode layer in the device unit. The second test electrode and the third test electrode are located in the same layer and are both formed in the same process as the movable electrode layer in the device unit. A test boss structure is provided on the side of the second test electrode facing the first test electrode. The test boss structure and the boss structure provided on the side of the movable electrode layer facing the fixed electrode layer are formed in the same process. An insulating medium separates the first test electrode from the second test electrode and from the third test electrode. The second test electrode, the first test electrode, and the insulating medium between them constitute a first test capacitor structure, and the third test electrode, the first test electrode, and the insulating medium between them constitute a second test capacitor structure. The area of ​​the second test electrode facing the first test electrode is S1, the area of ​​the test boss structure facing the first test electrode is S2, and the area of ​​the third test electrode facing the first test electrode is S3, where S3 = S1 - S2.

2. The MEMS structure according to claim 1, characterized in that, The number of test boss structures in the test unit is greater than the number of boss structures in the device unit.

3. The MEMS structure according to claim 1, characterized in that, The projection of the second test electrode and / or the third test electrode in the thickness direction of the substrate is located within the projection of the first test electrode in the thickness direction of the substrate.

4. A method for fabricating a MEMS structure, characterized in that, The method includes: Provide a base; A fixed electrode layer and a first test electrode are formed on the substrate through the same process; A movable electrode layer, a second test electrode, and a third test electrode are formed through the same process. The movable electrode layer is located on the side of the fixed electrode layer away from the substrate, and a boss structure is provided on the side of the movable electrode layer facing the fixed electrode layer. Both the second and third test electrodes are located on the side of the first test electrode away from the substrate, and a test boss structure is provided on the side of the second test electrode facing the first test electrode. An insulating medium separates the first test electrode from the second test electrode and from the third test electrode. The second test electrode, the first test electrode, and the insulating medium between them constitute a first test capacitor structure, and the third test electrode, the first test electrode, and the insulating medium between them constitute a second test capacitor structure. The area of ​​the second test electrode facing the first test electrode is S1, the area of ​​the test boss structure facing the first test electrode is S2, and the area of ​​the third test electrode facing the first test electrode is S3, where S3 = S1 - S2.

5. The method for fabricating a MEMS structure according to claim 4, characterized in that, The formation of the movable electrode layer, the second test electrode, and the third test electrode includes: A sacrificial layer is formed covering the substrate, the fixed electrode layer, and the first test electrode; The sacrificial layer is etched using the same mask pattern and the same etching process in the same process to form a first blind hole opposite to the fixed electrode layer and a second blind hole opposite to the first test electrode. A conductive material layer is formed to fill the first blind via and the second blind via and to cover the sacrificial layer; The conductive material layer is etched to form the movable electrode layer, the second test electrode, and the third test electrode; wherein, the conductive material layer located in the first blind via forms the boss structure, and the conductive material layer located in the second blind via forms the test boss structure; the portion of the sacrificial layer located between the first test electrode and the second test electrode, and between the first test electrode and the third test electrode, forms the insulating medium.

6. The method for fabricating a MEMS structure according to claim 5, characterized in that, After forming the conductive material layer and before etching the conductive material layer, the method further includes: A first pad and a second pad are formed on the conductive material layer. The first pad corresponds to a preset position of the second test electrode, and the second pad corresponds to a preset position of the third test electrode. After etching the conductive material layer, the first pad is electrically connected to the second test electrode, and the second pad is electrically connected to the third test electrode.

7. The method for fabricating a MEMS structure according to claim 4, characterized in that, The fixed electrode layer and the movable electrode layer constitute a device unit; the first test capacitor structure and the second test capacitor structure constitute a test unit. The number of test boss structures in the test unit is greater than the number of boss structures in the device unit.

8. The method for fabricating a MEMS structure according to claim 4, characterized in that, The projection of the second test electrode and / or the third test electrode in the thickness direction of the substrate is located within the projection of the first test electrode in the thickness direction of the substrate.

9. A testing method for MEMS structures, characterized in that, The method includes: Provide a MEMS structure as described in any one of claims 1 to 3 or a MEMS structure prepared by the method described in any one of claims 4 to 8; Measure the capacitance values ​​of the first test capacitor structure and the second test capacitor structure; Based on the capacitance difference between the first test capacitor structure and the second test capacitor structure, the spacing between the boss structure and the fixed electrode layer is determined.

10. The testing method for MEMS structures according to claim 9, characterized in that, The capacitance difference between the first test capacitor structure and the second test capacitor structure is equal to the capacitance value of the capacitor structure formed by the test boss structure, the first test electrode, and the insulating dielectric between them; determining the spacing between the boss structure and the fixed electrode layer based on the capacitance difference between the first test capacitor structure and the second test capacitor structure includes: Using the capacitance calculation formula of a parallel plate capacitor, based on the capacitance difference between the first test capacitor structure and the second test capacitor structure, S2, and the relative permittivity of the insulating medium, the distance between the test boss structure and the first test electrode is calculated. The distance between the boss structure and the fixed electrode layer is equal to the distance between the test boss structure and the first test electrode.

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