Multi-stage exposure differential count iToF imaging circuit, method and system

Abstract

The application discloses a multi-stage exposure type differential counting iToF imaging circuit, method and system, solves the problems of short detection distance and the influence of non-ideal effects of a detection device and a circuit itself on ranging accuracy in the prior art, improves the ranging accuracy of a sensor, and makes the ranging result not affected by errors; the circuit comprises the following: a SPAD and quenching circuit output a time-of-flight pulse; a multiplexer selects an output time-of-flight pulse or a quantization clock; a signal conditioning circuit generates first and second pulse signals; a time window circuit generates first and second window signals; a logic gate circuit outputs a counting pulse when the window signal is valid; an analog counter counts and outputs an analog voltage; a comparator compares the analog voltage with a reset signal, a first input end of the comparator is connected with an output of the analog counter, and a second input end of the comparator is connected with the reset signal; and a row selection circuit transmits a comparison result to a column-shared digital counter under the control of a row selection signal.

Description

Technical Field

[0001] This invention relates to the field of mixed-signal integrated circuit technology, and in particular to a multi-stage exposure differential counting iToF imaging circuit, method, and system. Background Technology

[0002] Time-of-Flight (ToF) imaging is one of the core technologies in the field of 3D ranging imaging with lidar. Its basic principle is to emit modulated or pulsed laser signals from a laser source towards the target in the field of view. After the laser is reflected by the target, it is received by a photoelectric sensor. By measuring the flight time of the laser from emission to reception and combining this with the speed of light, the distance between the sensor and the target is calculated, thereby reconstructing the target's three-dimensional spatial information. ToF technology can be divided into two categories based on the signal modulation method and detection mechanism: Direct Time-of-Flight (dToF) technology emits high-intensity short pulses from a pulsed light source and uses a high-speed photon detector to record the time difference between the emitted and received pulses; Indirect Time-of-Flight (iToF) technology uses continuous wave modulation and calculates the time difference by measuring the phase shift between the emitted and reflected signals. Among these, iToF technology, with its advantages of high frame rate, low cost, and easy integration, is widely used in CMOS image sensors, charge-coupled devices, and other fields. The core of iToF technology is to use photodetectors to capture the time-of-flight information of a single photon, select useful time-of-flight information using time window signals with different phases, count these time-of-flight information using an analog counter, calculate the phase shift between the reflected signal and the emitted signal based on the counting results, and then estimate the time of flight of the photon.

[0003] In iToF imaging systems, the calculation error of the phase shift between the reflected and transmitted signals directly determines the ranging accuracy. This phase shift is related to the counting of time-of-flight information under different phase time windows. Therefore, accurately counting the time-of-flight information under different phase time windows improves ranging accuracy. Traditional iToF technology primarily uses analog counters to directly count the time-of-flight information. While this approach has advantages such as simple circuit structure and small chip area, the counting value of the analog counter inevitably has errors due to non-ideal effects such as afterpulse and dark counting, significantly reducing ranging accuracy. Furthermore, the circuit itself also exhibits non-ideal effects, such as linearity errors in the analog counter, comparator threshold mismatch, and the bus settling time required for the circuit output signal to be transmitted to the digital counter. These effects also negatively impact ranging accuracy. In addition, traditional iToF technology mostly uses ordinary photodiodes as detectors, resulting in a relatively short maximum detection distance for the entire imaging system, typically only a few tens of meters.

[0004] Therefore, a new iToF imaging method is urgently needed to solve the problem of short detection distance and the impact of non-ideal effects of the detection device and circuit itself on the ranging accuracy. Summary of the Invention

[0005] This invention provides a multi-stage exposure-based differential counting iToF imaging circuit, method, and system, which solves the problems of short detection distance and the impact of non-ideal effects of the detection device and circuit itself on ranging accuracy in the prior art. It eliminates the influence of non-ideal effects of the single-photon avalanche diode (SPAD) and the circuit itself, improves the ranging accuracy of the sensor, and makes the ranging results unaffected by the linearity error of the analog counter, comparator threshold mismatch, and bus settling time.

[0006] In a first aspect, the present invention provides a multi-stage exposure-based differential counting iToF imaging circuit, the circuit comprising: Single-photon avalanche diode and quenching circuit, used to respond to incident photons and output time-of-flight pulses; A multiplexer is used to select and output the time-of-flight pulse or the quantization clock signal according to a control signal; wherein, the first input terminal of the multiplexer is connected to the time-of-flight pulse, and the second input terminal is connected to the quantization clock signal; A signal conditioning circuit, connected to the output terminal of the multiplexer, is used to invert and delay the output signal of the multiplexer to generate a first pulse signal and a second pulse signal. A time window generation circuit is used to generate a first time window signal and a second time window signal; A logic gate circuit is used to output a counting pulse when the time window signal is valid; wherein, the input terminals of the logic gate circuit are respectively connected to the first pulse signal, the second pulse signal and the time window signal; An analog counter is used to count the counting pulses, and its output terminal outputs an analog voltage representing the count value; wherein, the input terminal of the analog counter is connected to the output terminal of the logic gate circuit; A comparator is used to compare the analog voltage with a reset signal and output the comparison result; wherein, the first input terminal of the comparator is connected to the output terminal of the analog counter, and the second input terminal is connected to the reset signal; A row selection circuit is used to transmit the comparison result to a column-shared digital counter under the control of a row selection signal; wherein the input terminal of the row selection circuit is connected to the output terminal of the comparator, and the control terminal is connected to the row selection signal.

[0007] In conjunction with the first aspect, in one possible implementation, the signal conditioning circuit includes: a first inverter and a delay unit; The first inverter has its input terminal connected to the output terminal of the multiplexer, and its output terminal outputs the first pulse signal; The delay unit has its input terminal connected to the output terminal of the first inverter, and its output terminal outputs the second pulse signal. The second pulse signal has the same waveform as the first pulse signal but has a preset delay.

[0008] In conjunction with the first aspect, in one possible implementation, the logic gate is a three-input OR gate, with the first input connected to the first pulse signal, the second input connected to the second pulse signal, and the third input connected to the time window signal.

[0009] In conjunction with the first aspect, in one possible implementation, the analog counter includes: A pair of reset transistors is used to charge the output node to the supply voltage during the reset phase; A charge transfer branch is used to respond to an input pulse during the counting phase by transferring charge from the load capacitor to the parasitic capacitor, thereby causing the output voltage to decrease by one step; wherein, the charge transfer branch includes: a first transfer transistor and a second transfer transistor connected in series; A holding transistor is used to discharge the parasitic capacitance during the non-counting phase to maintain a stable output voltage; A compensation transistor is used to compensate the output for charge during the counting phase.

[0010] In conjunction with the first aspect, in one possible implementation, the comparator is a 2-T comparator, comprising: a comparator pull-up transistor and a comparator pull-down transistor; The comparator pull-up transistor is a PMOS transistor, and the gate of the comparator pull-up transistor serves as the inverting input terminal, which is connected to the output terminal of the analog counter. The comparator pull-down transistor is an NMOS transistor, and the gate of the comparator pull-down transistor serves as the non-inverting input terminal, which is connected to the reset signal. The pull-up transistor of the comparator is connected to the drain of the pull-down transistor of the comparator, serving as the output terminal of the comparator.

[0011] In conjunction with the first aspect, in one possible implementation, the row selection circuit includes: a transmission gate NMOS transistor and a transmission gate PMOS transistor connected in parallel, wherein the gates of the transmission gate NMOS transistor and the transmission gate PMOS transistor are jointly connected to the row selection signal.

[0012] Secondly, the present invention provides a multi-stage exposure-based differential counting iToF imaging method, the method comprising: Reset the analog counter and comparator; In the first exposure stage, the multiplexer selects the time-of-flight pulse output by the single-photon avalanche diode. Under the control of the first time window signal and the second time window signal, the analog counter counts the time-of-flight pulse to obtain analog voltage V1 and analog voltage V2. In the first quantization stage, the analog voltage V1 and the analog voltage V2 are quantized, the multiplexer selects the quantization clock signal, and the analog counter counts the quantization clock signal to obtain a first counting result and a second counting result. In the second exposure stage, the multiplexer selects the time-of-flight pulse again. Under the control of the first time window signal and the second time window signal, the analog counter counts the time-of-flight pulse to obtain analog voltage V3 and analog voltage V4. In the second quantization stage, the analog voltages V3 and V4 are quantized, the multiplexer switches to the quantization clock signal again, and the analog counter counts the quantization clock signal to obtain the third and fourth counting results. The phase delay of the reflected light is calculated based on the difference between the third counting result and the first counting result, and the difference between the fourth counting result and the second counting result, thereby obtaining the target distance.

[0013] In conjunction with the second aspect, in one possible implementation, In the first exposure stage, the phase difference between the first time window signal and the exposure signal is 90°; the phase difference between the second time window signal and the exposure signal is 0°. In the second exposure stage, the phase difference between the first time window signal and the exposure signal is 270°; the phase difference between the second time window signal and the exposure signal is 180°.

[0014] In conjunction with the second aspect, one possible implementation also includes an inter-frame multiplexing step: After the first frame measurement is completed, only the count results of the first exposure stage and the first quantization stage are cleared, while the count results of the second exposure stage and the second quantization stage are retained; At the start of the second frame measurement, the first exposure stage and the first quantization stage are performed to obtain a new first count result and a new second count result. The new first count result and the new second count result are then differentially calculated with the retained third count result and the fourth count result to generate the depth information of the second frame.

[0015] Thirdly, the present invention provides a multi-stage exposure-based differential counting iToF imaging system, the system comprising: The pixel array is composed of multiple indirect time-of-flight imaging circuits arranged together. The timing control circuit is used to generate exposure signals, time window signals, quantization clock signals and control signals for each stage, so as to control the pixel array to sequentially execute the first exposure stage, the first quantization stage, the second exposure stage and the second quantization stage. A digital counter array is used to receive and store the comparison results transmitted by the row selection circuit; The calculation unit is used to perform differential operations based on the counting results obtained in each stage, calculate the phase delay of the reflected light and the target distance, and execute the inter-frame multiplexing strategy to clear only the counting results of some stages to improve the frame rate.

[0016] One or more technical solutions provided in this invention have at least the following technical effects or advantages: This invention utilizes a SPAD and a quenching circuit to respond to incident photons and output time-of-flight pulses. The circuit employs a SPAD as the detection core, capable of detecting weak light signals at the single-photon level. Combined with the quenching circuit, rapid reset is achieved, ensuring high sensitivity and high time resolution in time-of-flight detection, providing a fundamental signal source for high-precision distance measurement. A multiplexer, with its first input connected to the time-of-flight pulse and its second input connected to the quantization clock signal, selects between outputting the time-of-flight pulse or the quantization clock signal based on a control signal. By selecting the time-of-flight pulse during the exposure stage and the quantization clock signal during the quantization stage, this multiplexer allows core circuits such as analog counters to be multiplexed in two operating modes, avoiding the need for separate counting circuits for each function, effectively reducing pixel area and improving array integration. A signal conditioning circuit, connected to the output of the multiplexer, inverts and delays the output signal to generate a first pulse signal and a second pulse signal. This circuit uses two inverters to ensure a precise time delay difference between the first and second pulse signals. This design enables subsequent logic gates to generate adjustable-width counting pulses within a time window, achieving precise gating sampling of time-of-flight information. The time window generation circuit generates a first time window signal and a second time window signal. This circuit, in conjunction with a multi-stage exposure strategy, can output time windows with specific phase differences from the laser modulation signal at different exposure stages, thereby achieving indirect measurement of the reflected light phase delay and providing crucial timing control signals for subsequent differential calculations. The logic gates, with inputs connected to the first pulse signal, the second pulse signal, and the time window signal, output counting pulses when the time window signal is valid. This three-input OR gate logically combines two pulse signals with a phase difference with the time window signal, ensuring that the analog counter counts valid pulses only within a precise time window, thus suppressing noise and interference outside the window and improving counting accuracy. The analog counter, with its input connected to the output of the logic gates, counts the counting pulses and outputs an analog voltage representing the count value. This analog counter employs a charge transfer mechanism; each input pulse causes the output voltage to decrease by a step, achieving integral counting of the number of pulses. Its continuously varying output voltage allows the counting result to be directly transmitted to the subsequent comparator in analog signal form, avoiding the area and power consumption overhead of complex analog-to-digital conversion circuits. The comparator has its first input connected to the output of the analog counter and its second input connected to the reset signal. It compares the analog voltage with the reset signal and outputs the comparison result. This comparator uses a 2-T structure, which greatly simplifies the circuit structure and effectively reduces pixel area while ensuring reliable comparison functionality. The binarized result output by the comparator indicates whether the analog counter has completed the preset count, realizing the signal conversion from the analog domain to the digital domain.The row selection circuit, with its input connected to the comparator's output and its control terminal connected to the row selection signal, transmits the comparison result to the column-shared digital counter under the control of the row selection signal, achieving low on-resistance and high-speed signal transmission. Through row-by-row gating, this circuit ensures the orderly output of the pixel array's comparison results to the column-shared digital counter, providing a reliable signal path for row-by-row readout of large-scale pixel arrays. It also supports arbitrary row masking and selection, enhancing the system's operational flexibility. These modules work together to form a complete indirect time-of-flight imaging pixel circuit. The multiplexer multiplexes the core counting circuit, the signal conditioning circuit and time window circuit work together to complete time-gated sampling, the analog counter and 2-T comparator perform analog counting and digital conversion in a simplified structure, and the row selection circuit ensures efficient array readout. The entire circuit significantly reduces pixel area and power consumption while maintaining ranging accuracy, providing a reliable circuit foundation for high-resolution, high-frame-rate iToF imaging systems. Attached Figure Description

[0017] Figure 1 A schematic diagram of an indirect time-of-flight imaging circuit with multi-stage exposure and differential counting provided in an embodiment of the present invention; Figure 2 A detailed schematic diagram of an analog counter provided in an embodiment of the present invention; Figure 3 A schematic diagram of a comparator provided in an embodiment of the present invention; Figure 4 This is a timing diagram of the multi-stage exposure-based differential counting iToF imaging method provided in an embodiment of the present invention; Figure 5 A schematic diagram of the output of the analog counter in the exposure stage and quantization stage and a schematic diagram of the calculation of the phase delay of the reflected light provided in the embodiments of the present invention; Figure 6 This is a schematic diagram illustrating the programmable segmented voltage and counting step size setting method of an analog counter provided in an embodiment of the present invention; Figure 7 A schematic diagram illustrating the non-ideal effects provided in this embodiment of the invention; Figure 8 A diagram illustrating the differences between the method provided by this invention and traditional calculation methods, provided for embodiments of this invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] In a first aspect, the present invention provides a multi-stage exposure-based differential counting iToF imaging circuit, see [link to relevant documentation]. Figure 1 The circuit includes: a single-photon avalanche diode and quenching circuit, a multiplexer, a signal conditioning circuit, a time window generation circuit, logic gate circuits, and an analog counter.

[0020] A single-photon avalanche diode and quenching circuit are used to respond to incident photons and output time-of-flight pulses.

[0021] A multiplexer is used to select the output time-of-flight pulse or quantization clock signal according to the control signal; wherein, the first input terminal of the multiplexer is connected to the time-of-flight pulse, and the second input terminal is connected to the quantization clock signal.

[0022] A signal conditioning circuit, connected to the output of a multiplexer, is used to invert and delay the output signal of the multiplexer to generate a first pulse signal and a second pulse signal. Specifically, the signal conditioning circuit includes: a first inverter and a delay unit; the first inverter has its input connected to the output of the multiplexer and outputs a first pulse signal; the delay unit has its input connected to the output of the first inverter and outputs a second pulse signal, the second pulse signal having the same waveform as the first pulse signal but with a preset delay.

[0023] A time window generation circuit is used to generate a first time window signal and a second time window signal; a logic gate circuit is used to output a counting pulse when the time window signal is valid; wherein, the input terminals of the logic gate circuit are respectively connected to the first pulse signal, the second pulse signal and the time window signal; here, the logic gate circuit is a three-input OR gate circuit, the first input terminal is connected to the first pulse signal, the second input terminal is connected to the second pulse signal and the third input terminal is connected to the time window signal.

[0024] An analog counter is used to count counting pulses, and its output terminal outputs an analog voltage representing the count value. The input terminal of the analog counter is connected to the output terminal of a logic gate circuit. Here, the analog counter includes: a reset transistor pair for charging the output node to the power supply voltage during the reset phase; a charge transfer branch for transferring charge from the load capacitor to the parasitic capacitance in response to the input pulse during the counting phase, causing the output voltage to decrease by one step; the charge transfer branch includes: a first transfer transistor and a second transfer transistor connected in series; a holding transistor for discharging the parasitic capacitance during the non-counting phase to maintain a stable output voltage; and a compensation transistor for compensating the output terminal for charge during the counting phase.

[0025] The control logic generates row selection signals, quantization clock signals, and time window signals to control the operation of the circuit array and data transmission.

[0026] The function of a buffer is to increase the driving capability of a signal, enabling the signal to drive such a large circuit array.

[0027] For example, see Figure 2 , Figure 2 The diagram shown is a schematic of the analog counter in an embodiment of the present invention. During the reset phase, RSTN is low, PM1 and PM2 are turned on, and both point X and the output terminal are charged to VDD; V PULSE High level, V PULSEN When the signal is low, PM3, NM2, and NM4 are off, NM3 is on, and the parasitic capacitance of NM3 discharges through NM3, resulting in the output signal V. COUNTER VDD remains constant. During the counting phase, RSTN is high, PM1 and PM2 are off, and capacitor C... L Being charged; V PULSE V is low level. PULSEN When the voltage level is high, PM3, NM2, and NM4 are turned on, NM3 is turned off, the parasitic capacitance of NM3 cannot discharge, and the capacitance C... L The charge in PM3 is transferred to the parasitic capacitance of NM3 through PM3 and NM2, resulting in the output signal V. COUNTER Decrease by one step, i.e., count "1". During the hold phase, RSTN remains high, and V... PULSE After the low-level pulse ends, it returns to a high level, causing V to... PULSEN When the voltage returns to low, PM3, NM2, and NM4 are off, NM3 is on, and the parasitic capacitance of NM3 discharges through NM3, and capacitor C... L The charge in the capacitor cannot be transferred to the parasitic capacitance of NM3 through PM3 and NM2, therefore the output signal V... COUNTER The value remains unchanged after the count until the next V. PULSEThe pulse arrives. The function of NM4 is to reduce leakage current at the output terminal. During the counting phase, NM4 is turned on, and the charge at point X can compensate for the output terminal, making the decrease in output voltage even lower, thereby making the output signal more stable.

[0028] A comparator is used to compare an analog voltage with a reset signal and output the comparison result. The first input of the comparator is connected to the output of an analog counter, and the second input is connected to the reset signal. Here, the comparator is a 2-T comparator, including a comparator pull-up transistor and a comparator pull-down transistor. The comparator pull-up transistor is a PMOS transistor, and its gate serves as the inverting input, connected to the output of the analog counter. The comparator pull-down transistor is an NMOS transistor, and its gate serves as the non-inverting input, connected to the reset signal. The drains of the comparator pull-up transistor and the comparator pull-down transistor are connected together, forming the output of the comparator.

[0029] For example, see Figure 3 , Figure 3 The diagram shown is a schematic of the comparator in an embodiment of the present invention. To reduce chip area, this comparator is constructed using a comparator pull-up transistor and a comparator pull-down transistor, hence it is also called a 2-T comparator. The counting result of the analog counter is connected to the gate of the PMOS transistor as an inverting input signal; the reset signal is connected to the gate of the NMOS transistor as a non-inverting input signal. During the reset phase, the output signal V of the analog counter... COUNTER Maintaining VDD constant, the reset signal RSTC is also set to VDD and kept constant. Therefore, the PMOS is off, the NMOS is on, and the output signal is "0". During the counting phase, the reset signal RSTC is set to low, and the output signal VDD of the analog counter is... COUNTER As the count gradually decreases, the PMOS turns on and the NMOS turns off after the count is complete, resulting in an output signal of "1".

[0030] A row selection circuit, under the control of a row selection signal, transmits the comparison result to a column-shared digital counter. The input of the row selection circuit is connected to the output of the comparator, and the control terminal is connected to the row selection signal. Here, the row selection circuit comprises a parallel NMOS transistor and a PMOS transistor, whose gates are both connected to the row selection signal.

[0031] For example, in a specific embodiment of the present invention, Figure 7The diagram illustrates the non-ideal effects inherent in the circuit of this invention. Due to the different counting step sizes used in different operating stages of the circuit, the output of the analog counter will produce linearity errors. During the fabrication process, process deviations on different transistors are unavoidable. These deviations lead to inconsistencies in parameters such as transistor threshold voltage, device size, or carrier mobility, causing the output signal to not flip when the comparator input voltages are equal. This phenomenon is called comparator threshold mismatch. For this circuit, the final output signal needs to be transmitted to the digital counter for further processing, and this transmission process requires a certain amount of time, called the bus settling time. In traditional iToF imaging methods, these non-ideal effects all affect the ranging results. This invention changes the counting order. In the first counting stage, the phase difference between the two time window signals and the exposure signal is 0° and 90°, respectively. In the second counting stage, the phase difference between the two time window signals and the exposure signal is 180° and 270°, respectively. In calculating the phase delay of the reflected light, this approach ensures that the two count results used in the subtraction operation are identical due to the use of the same analog counter, comparator, and signal transmission path. Therefore, the linearity error of the analog counter, the threshold mismatch of the comparator, and the bus settling time are all the same. These non-ideal effects can be eliminated through the subtraction operation, thereby improving the ranging accuracy.

[0032] Figure 8 The diagram illustrates the difference between the iToF result calculation method in this embodiment and the traditional calculation method. In the traditional iToF imaging method, the ranging result for each frame is calculated based on a completely new counting result. That is, after the first frame ends, the traditional iToF imaging method resets all the counting results of the first and second stages to zero, restarts the counting of the first and second stages at the start of the second frame, and repeats this process. The iToF imaging method proposed in this invention differs in that after the first frame ends, only the counting result of the first stage is reset to zero, while the counting result of the second stage is retained. At the start of the second frame, the counting of the first stage is restarted, and this counting result, along with the second-stage counting result of the first frame, is used to calculate the phase delay and distance of the reflected light. The advantage of this approach is that since the subsequent frame uses the counting result of the previous frame, only one stage of counting is needed at the start of the next frame, doubling the circuit's operating speed and thus doubling the frame rate.

[0033] Secondly, the present invention provides a multi-stage exposure-based differential counting iToF imaging method, which includes the following steps S101 to S106.

[0034] S101 resets the analog counter and comparator; S102, in the first exposure stage, the multiplexer selects the time-of-flight pulse output by the single-photon avalanche diode. Under the control of the first time window signal and the second time window signal, the analog counter counts the time-of-flight pulse to obtain analog voltage V1 and analog voltage V2. Here, in the first exposure stage, the phase difference between the first time window signal and the exposure signal is 90°; the phase difference between the second time window signal and the exposure signal is 0°.

[0035] S103, in the first quantization stage, analog voltage V1 and analog voltage V2 are quantized, the multiplexer selects the quantization clock signal, and the analog counter counts the quantization clock signal to obtain the first counting result and the second counting result; S104, in the second exposure stage, the multiplexer selects the time-of-flight pulse again. Under the control of the first time window signal and the second time window signal, the analog counter counts the time-of-flight pulse to obtain analog voltage V3 and analog voltage V4. Here, in the second exposure stage, the phase difference between the first time window signal and the exposure signal is 270°; the phase difference between the second time window signal and the exposure signal is 180°.

[0036] S105, in the second quantization stage, analog voltages V3 and V4 are quantized, the multiplexer switches to the quantization clock signal again, and the analog counter counts the quantization clock signal to obtain the third and fourth counting results; S106, based on the difference between the third and first counting results, and the difference between the fourth and second counting results, the phase delay of the reflected light is calculated, thereby obtaining the target distance. That is, since the full-scale range is the same, the difference between the first and third counting results is equal to the difference between the fourth and second counting results. Therefore, based on the difference between the fourth and second counting results, the phase delay of the reflected light can be calculated, thereby obtaining the target distance.

[0037] The multi-stage exposure differential counting iToF imaging method also includes an inter-frame multiplexing step: (1) After the first frame measurement is completed, only the count results of the first exposure stage and the first quantization stage are cleared, while the count results of the second exposure stage and the second quantization stage are retained; (2) At the start of the second frame measurement, the first exposure stage and the first quantization stage are performed to obtain the new first count result and the new second count result. The new first count result and the new second count result are then differentially calculated with the retained third count result and fourth count result to generate the depth information of the second frame.

[0038] For example, the SPAD and quenching circuit are used to detect time-of-flight pulses, and the time interval between its output and the start of the laser is the time of flight.

[0039] In the first exposure stage, the multiplexer selects the time-of-flight pulse and outputs it.

[0040] In the first exposure stage, the time-of-flight pulse, after being processed by the first inverter, serves as the first input signal of the three-input OR gate circuit. The delay of this first inverter is negligible. The second input signal of the three-input OR gate circuit is the signal obtained by further processing the first input signal by the inverter in the delay unit. However, the delay of the inverter in this delay unit is relatively large, resulting in a significant delay between the waveform of the second input signal and the time-of-flight pulse, although the two waveforms are consistent. The third input signal of the three-input OR gate circuit is the time window signals TWA and TWB. In the first exposure stage, TWA and TWB have different phase differences from the exposure signal, with phase differences of 90° and 0°, respectively.

[0041] During the first exposure stage, when the time window signals TWA and TWB are low, the analog counter counts the output pulses of the three-input OR gate circuit, and the counting result is output to the comparator circuit.

[0042] In the first exposure stage, the count result of the analog counter is connected to a comparator and compared with the reset signal. The comparator consists of a comparator pull-up transistor (PMOS) and a comparator pull-down transistor (NMOS), and is called a 2-T comparator. The gate of the comparator pull-up transistor (PMOS) is the inverting input terminal, connected to the count result of the analog counter, while the gate of the comparator pull-down transistor (NMOS) is the non-inverting input terminal, connected to the reset signal.

[0043] In the first exposure stage, the comparator's output is connected to the row selection circuit. The row selection circuit is a transmission gate circuit consisting of an NMOS transistor and a PMOS transistor connected in parallel. The gates of the NMOS and PMOS transistors are connected to the row selection signal. To acquire the output signal of a specific row, the row selection signal is controlled to turn on the transmission gate circuit, and the output signal of that row is transmitted to the column shared digital counter. Conversely, to block the output signal of a specific row, the row selection signal is controlled to turn off the transmission gate circuit, and the output signal of that row is not transmitted to the column shared digital counter.

[0044] In the first quantization stage, the multiplexer selects and outputs the quantized clock signal.

[0045] In the first quantization stage, the quantization clock signal, after being processed by the first inverter, serves as the first input signal of the three-input OR gate circuit. The delay of this first inverter is negligible. The second input signal of the three-input OR gate circuit is the signal obtained by further processing the first input signal by the inverter in the delay unit. However, the delay of the inverter in this delay unit is relatively large, resulting in a significant time delay between the waveform of the second input signal and the quantization clock signal, although they are identical. The third input signal of the three-input OR gate circuit is the time window signals TWA and TWB. During the first quantization stage, TWA and TWB have a different phase difference from the exposure signal.

[0046] In the first quantization stage, when the time window signals TWA and TWB are low, the analog counter counts the output pulses of the three-input OR gate circuit, and the counting result is output to the comparator circuit.

[0047] In the first quantization stage, the count result of the analog counter is connected to a comparator and compared with the reset signal. The comparator consists of a comparator pull-up transistor (PMOS) and a comparator pull-down transistor (NMOS), called a 2-T comparator. The gate of the comparator pull-up transistor is the inverting input, connected to the count result of the analog counter. The gate of the comparator pull-down transistor is the non-inverting input, connected to the reset signal.

[0048] In the first quantization stage, the comparator's output is connected to the row selection circuit. The row selection circuit is a transmission gate circuit consisting of a parallel NMOS and a PMOS transmission gate, with their gates connected to the row selection signal. To acquire the output signal of a specific row, the row selection signal is controlled to turn on the transmission gate circuit, and the output signal of that row is transmitted to the column-shared digital counter. Conversely, to block the output signal of a specific row, the row selection signal is controlled to turn off the transmission gate circuit, and the output signal of that row is not transmitted to the column-shared digital counter.

[0049] In the second exposure stage, the multiplexer selects the time-of-flight pulse and outputs it.

[0050] In the second exposure stage, the time-of-flight pulse, after being processed by the first inverter, serves as the first input signal of the three-input OR gate circuit. The delay of this first inverter is negligible. The second input signal of the three-input OR gate circuit is the signal obtained by further processing the first input signal by the inverter in the delay unit. However, the delay of this inverter is relatively large, resulting in a significant time delay between the waveform of the second input signal and the time-of-flight pulse, although the waveforms of the two signals are consistent. The third input signal of the three-input OR gate circuit consists of the time window signals TWA and TWB. In the second exposure stage, the phase differences between TWA and TWB and the exposure signal are 270° and 180°, respectively.

[0051] During the second exposure stage, when the time window signals TWA and TWB are low, the analog counter counts the output pulses of the three-input OR gate circuit, and the counting result is output to the comparator circuit.

[0052] In the second exposure stage, the count result of the analog counter is connected to a comparator and compared with the reset signal. The comparator consists of a comparator pull-up transistor and a comparator pull-down transistor, called a 2-T comparator. The comparator pull-up transistor is a PMOS transistor, whose gate is the inverting input terminal, connected to the count result of the analog counter. The comparator pull-down transistor is an NMOS transistor, whose gate is the non-inverting input terminal, connected to the reset signal.

[0053] In the second exposure stage, the comparator's output is connected to the row selection circuit. The row selection circuit is a transmission gate circuit consisting of a parallel NMOS and a PMOS transmission gate, with their gates connected to the row selection signal. To acquire the output signal of a specific row, the row selection signal is controlled to turn on the transmission gate circuit, and the output signal of that row is transmitted to the column shared digital counter. Conversely, to block the output signal of a specific row, the row selection signal is controlled to turn off the transmission gate circuit, and the output signal of that row is not transmitted to the column shared digital counter.

[0054] In the second quantization stage, the multiplexer selects and outputs the quantized clock signal.

[0055] In the second quantization stage, the quantization clock signal, after being processed by the first inverter, becomes the first input signal of the three-input OR gate circuit. The delay of this first inverter is negligible. The second input signal of the three-input OR gate circuit is the signal obtained by further processing the first input signal by the inverter in the delay unit. However, the delay of this inverter is relatively large, resulting in a significant time delay between the waveform of the second input signal and the quantization clock signal, even though they are identical. The third input signal of the three-input OR gate circuit is the time window signals TWA and TWB. In the second quantization stage, TWA and TWB have a different phase difference from the exposure signal.

[0056] In the second quantization stage, when the time window signals TWA and TWB are low, the analog counter counts the output pulses of the three-input OR gate circuit, and the counting result is output to the comparator circuit.

[0057] In the second quantization stage, the count result of the analog counter is connected to a comparator and compared with the reset signal. The comparator consists of a comparator pull-up transistor and a comparator pull-down transistor, called a 2-T comparator. The comparator pull-up transistor is a PMOS transistor, with its gate as the inverting input, connected to the count result of the analog counter. The comparator pull-down transistor is an NMOS transistor, with its gate as the non-inverting input, connected to the reset signal.

[0058] In the second quantization stage, the comparator's output is connected to the row selection circuit. The row selection circuit is a transmission gate circuit consisting of a parallel NMOS and a PMOS transmission gate, with their gates connected to the row selection signal. To acquire the output signal of a specific row, the row selection signal is controlled to turn on the transmission gate circuit, and the output signal of that row is transmitted to the column-shared digital counter. Conversely, to block the output signal of a specific row, the row selection signal is controlled to turn off the transmission gate circuit, and the output signal of that row is not transmitted to the column-shared digital counter.

[0059] See Figure 4 , Figure 4 The diagram shown illustrates the operating timing of this invention. The imaging method operates as follows: first, all parts of the circuit are reset; then, an exposure signal is applied to the light source to expose the circuit. After exposure, each row is sequentially quantized and read out. During the quantization phase, a quantization clock signal is applied to the circuit, and an analog counter counts the pulses of the quantization clock signal. During the readout phase, the row selection signal controls the on / off state of the row selection circuit, determining whether the circuit's output signal is read by the digital counter.

[0060] See Figure 5 , Figure 5The diagram illustrates the output of the analog counters during the exposure and quantization stages, and the method for calculating the phase delay of reflected light, in an embodiment of the present invention. In the first exposure stage, an exposure signal is applied to the light source for exposure. The multiplexer selects and outputs the time-of-flight information generated by the SPAD. The phase differences between the first time window signal TWA and the second time window signal TWB and the exposure signal are 90° and 0°, respectively. The analog counter counts the time-of-flight information for this stage. After exposure, the first quantization stage begins. At this time, the exposure signal and the time window signal are canceled. The multiplexer selects and outputs the quantization clock signal, and the analog counter counts the quantization clock for this stage. In the second exposure stage, an exposure signal is applied to the light source for exposure. The multiplexer selects and outputs the time-of-flight information generated by the SPAD. The phase differences between the first time window signal TWA and the second time window signal TWB and the exposure signal are 270° and 180°, respectively. The analog counter counts the time-of-flight information for this stage. After exposure, the second quantization stage begins. At this time, the exposure signal and the time window signal are canceled. The multiplexer selects and outputs the quantization clock signal, and the analog counter counts the quantization clock for this stage. Since the sum of the time-of-flight information count and the quantization clock count is within the full-scale range, the time-of-flight information count equals the difference between the full-scale range and the quantization clock count. Because the full-scale range is the same for different phase differences, the difference in time-of-flight information counts equals the difference in quantization clock counts when calculating the reflected light phase delay. Therefore, the reflected light phase delay can be obtained simply by calculating the number of quantization clocks at different quantization stages. This calculation method yields a high-precision reflected light phase delay, avoiding errors caused by trigger pulses resulting from non-ideal effects such as SPAD dark counting or afterpulses.

[0061] See Figure 6 , Figure 6 The diagram illustrates the programmable segmented voltage and counting step size settings for the analog counter in an embodiment of the present invention. To extend the dynamic range, the output of the analog counter is divided into two parts by the segmented voltage, regardless of whether it is in the exposure or quantization stage: when the output voltage is greater than the segmented voltage, a smaller counting step size is used to increase the counting depth; when the output voltage is less than the segmented voltage, a larger counting step size is used to achieve the counting level under photon noise constraints. The segmented voltage is programmable, and different segmented voltages can be used to achieve the counting requirements according to different application scenarios.

[0062] Thirdly, the present invention provides a multi-stage exposure-based differential counting iToF imaging system, the system comprising: The pixel array is composed of multiple indirect time-of-flight imaging circuits arranged together. The timing control circuit is used to generate exposure signals, time window signals, quantization clock signals and control signals for each stage, so as to control the pixel array to execute the first exposure stage, the first quantization stage, the second exposure stage and the second quantization stage in sequence. A digital counter array is used to receive and store the comparison results transmitted by the row selection circuit; The calculation unit is used to perform differential operations based on the counting results obtained in each stage, calculate the phase delay of the reflected light and the target distance, and execute the inter-frame multiplexing strategy to clear only the counting results of some stages to improve the frame rate.

[0063] For example, the pixel array adopts a 320×240 pixel scale, and each pixel circuit adopts the aforementioned pixel circuit structure, including SPAD and quenching circuit, multiplexer, first inverter, delay unit, three-input OR gate circuit, analog counter, 2-T comparator and row selection circuit.

[0064] Timing control circuit: Generates a 100MHz laser modulation signal and accordingly generates four sets of timing control waveforms: First exposure stage: The phase difference between the first time window signal TWA and the laser modulation signal is 90°, the phase difference between the second time window signal TWB is 0°, and the exposure time is set to 10μs; First quantization stage: The multiplexer switches to a 100MHz quantization clock. The first time window signal TWA and the second time window signal TWB maintain the same timing as the first exposure stage. The quantization time is 10μs. Second exposure stage: The phase difference between the first time window signal TWA and the laser modulation signal is 270°, the phase difference between the second time window signal TWB is 180°, and the exposure time is also 10μs; Second quantization stage: Switch back to the quantization clock, with timing consistent with the second exposure stage, and quantization time of 10μs.

[0065] Digital counter array: Each column is equipped with a 12-bit digital counter to receive the comparison result output by the row selection circuit. The row selection signal adopts a row-by-row scanning method, and the gating time of each row is matched with the duration of each stage.

[0066] Calculation Unit: Within each measurement cycle, the calculation unit records the quantization count corresponding to the first exposure stage and the quantization count corresponding to the second exposure stage, calculates the reflected light phase delay, and then converts it into the target distance. Simultaneously, in continuous frame measurements, the calculation unit only clears the first-stage count result of the previous frame, retaining the second-stage count result for the next frame, thus doubling the frame rate compared to traditional methods. For example, at a modulation frequency of 100MHz, real-time depth image output at 120fps can be achieved.

[0067] Through the above configuration, the system effectively suppresses circuit non-ideal effects while maintaining high ranging accuracy, and achieves high frame rate imaging.

[0068] This invention provides a multi-stage exposure-based differential counting iToF imaging method, achieving a longer detection distance. By multiple exposures and changing the counting order, the influence of non-ideal effects of SPAD and the circuit itself is eliminated, improving the ranging accuracy of the sensor and making the ranging results unaffected by the linearity error of the analog counter, comparator threshold mismatch, and bus settling time. This invention also provides an improved analog counter structure that eliminates the operational amplifier, resulting in a smaller circuit area, lower power consumption, and faster quantization rate.

[0069] The various embodiments described in this specification are presented in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. All or part of this invention can be used in numerous general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices, etc.

[0070] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A multi-stage exposure-based differential counting iToF imaging circuit, characterized in that, include: Single-photon avalanche diode and quenching circuit, used to respond to incident photons and output time-of-flight pulses; A multiplexer is used to select and output the time-of-flight pulse or the quantization clock signal according to a control signal; wherein, the first input terminal of the multiplexer is connected to the time-of-flight pulse, and the second input terminal is connected to the quantization clock signal; A signal conditioning circuit, connected to the output terminal of the multiplexer, is used to invert and delay the output signal of the multiplexer to generate a first pulse signal and a second pulse signal. A time window generation circuit is used to generate a first time window signal and a second time window signal; A logic gate circuit is used to output a counting pulse when the time window signal is valid; wherein, the input terminals of the logic gate circuit are respectively connected to the first pulse signal, the second pulse signal and the time window signal; An analog counter is used to count the counting pulses, and its output terminal outputs an analog voltage representing the count value; wherein, the input terminal of the analog counter is connected to the output terminal of the logic gate circuit; A comparator is used to compare the analog voltage with a reset signal and output the comparison result; wherein, the first input terminal of the comparator is connected to the output terminal of the analog counter, and the second input terminal is connected to the reset signal; A row selection circuit is used to transmit the comparison result to a column-shared digital counter under the control of a row selection signal; wherein the input terminal of the row selection circuit is connected to the output terminal of the comparator, and the control terminal is connected to the row selection signal.

2. The multi-stage exposure differential counting iToF imaging circuit according to claim 1, characterized in that, The signal conditioning circuit includes: a first inverter and a delay unit; The first inverter has its input terminal connected to the output terminal of the multiplexer, and its output terminal outputs the first pulse signal; The delay unit has its input terminal connected to the output terminal of the first inverter, and its output terminal outputs the second pulse signal. The second pulse signal has the same waveform as the first pulse signal but has a preset delay.

3. The multi-stage exposure differential counting iToF imaging circuit according to claim 1, characterized in that, The logic gate circuit is a three-input OR gate circuit, with the first input terminal connected to the first pulse signal, the second input terminal connected to the second pulse signal, and the third input terminal connected to the time window signal.

4. The multi-stage exposure differential counting iToF imaging circuit according to claim 1, characterized in that, The analog counter includes: A pair of reset transistors is used to charge the output node to the supply voltage during the reset phase; A charge transfer branch is used to respond to an input pulse during the counting phase by transferring charge from the load capacitor to the parasitic capacitor, thereby causing the output voltage to decrease by one step; wherein, the charge transfer branch includes: a first transfer transistor and a second transfer transistor connected in series; A holding transistor is used to discharge the parasitic capacitance during the non-counting phase to maintain a stable output voltage; A compensation transistor is used to compensate the output for charge during the counting phase.

5. The multi-stage exposure differential counting iToF imaging circuit according to claim 1, characterized in that, The comparator is a 2-T comparator, including: a comparator pull-up transistor and a comparator pull-down transistor; The comparator pull-up transistor is a PMOS transistor, and the gate of the comparator pull-up transistor serves as the inverting input terminal, which is connected to the output terminal of the analog counter. The comparator pull-down transistor is an NMOS transistor, and the gate of the comparator pull-down transistor serves as the non-inverting input terminal, which is connected to the reset signal. The pull-up transistor of the comparator is connected to the drain of the pull-down transistor of the comparator, serving as the output terminal of the comparator.

6. The multi-stage exposure differential counting iToF imaging circuit according to claim 1, characterized in that, The row selection circuit includes: a transmission gate NMOS transistor and a transmission gate PMOS transistor connected in parallel, wherein the gates of the transmission gate NMOS transistor and the transmission gate PMOS transistor are connected to the row selection signal.

7. A multi-stage exposure-based differential counting iToF imaging method, characterized in that, include: Reset the analog counter and comparator; In the first exposure stage, the multiplexer selects the time-of-flight pulse output by the single-photon avalanche diode. Under the control of the first time window signal and the second time window signal, the analog counter counts the time-of-flight pulse to obtain analog voltage V1 and analog voltage V2. In the first quantization stage, the analog voltage V1 and the analog voltage V2 are quantized, the multiplexer selects the quantization clock signal, and the analog counter counts the quantization clock signal to obtain a first counting result and a second counting result. In the second exposure stage, the multiplexer selects the time-of-flight pulse again. Under the control of the first time window signal and the second time window signal, the analog counter counts the time-of-flight pulse to obtain analog voltage V3 and analog voltage V4. In the second quantization stage, the analog voltages V3 and V4 are quantized, the multiplexer switches to the quantization clock signal again, and the analog counter counts the quantization clock signal to obtain the third and fourth counting results. The phase delay of the reflected light is calculated based on the difference between the third counting result and the first counting result, and the difference between the fourth counting result and the second counting result, thereby obtaining the target distance.

8. The multi-stage exposure differential counting iToF imaging method according to claim 7, characterized in that, In the first exposure stage, the phase difference between the first time window signal and the exposure signal is 90°; the phase difference between the second time window signal and the exposure signal is 0°. In the second exposure stage, the phase difference between the first time window signal and the exposure signal is 270°; the phase difference between the second time window signal and the exposure signal is 180°.

9. The multi-stage exposure differential counting iToF imaging method according to claim 7, characterized in that, It also includes the inter-frame multiplexing step: After the first frame measurement is completed, only the count results of the first exposure stage and the first quantization stage are cleared, while the count results of the second exposure stage and the second quantization stage are retained; At the start of the second frame measurement, the first exposure stage and the first quantization stage are performed to obtain a new first count result and a new second count result. The new first count result and the new second count result are then differentially calculated with the retained third count result and the fourth count result to generate the depth information of the second frame.

10. A multi-stage exposure differential counting iToF imaging system, characterized in that, include: The pixel array is composed of multiple indirect time-of-flight imaging circuits arranged together. The timing control circuit is used to generate exposure signals, time window signals, quantization clock signals and control signals for each stage, so as to control the pixel array to sequentially execute the first exposure stage, the first quantization stage, the second exposure stage and the second quantization stage. A digital counter array is used to receive and store the comparison results transmitted by the row selection circuit; The calculation unit is used to perform differential operations based on the counting results obtained in each stage, calculate the phase delay of the reflected light and the target distance, and execute the inter-frame multiplexing strategy to clear only the counting results of some stages to improve the frame rate.

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