A single trimming CMOS bandgap reference source and a single trimming method

Abstract

The application provides a single trimming CMOS band gap reference source and a single trimming method, and belongs to the technical field of CMOS band gap reference sources. EB The gain coefficient A1 and the gain coefficient B1 in the voltage generating circuit are trimmed and compensated to generate a trimmed and compensated gain coefficient A2 and a trimmed and compensated gain coefficient B2, and the voltage V EB1 , the voltage V EB2 and the voltage V EB3 are trimmed through the trimmed and compensated gain coefficient A2 and the trimmed and compensated gain coefficient B2, so that the non-PTAT error of the voltage V EB in the voltage generating circuit (CMOS band gap reference source) is eliminated, the purpose of eliminating the non-PTAT error through the circuit corresponding to the CMOS band gap reference source is achieved, and the technical problems of multiple temperature trimming and multiple trimming in the prior art for eliminating the non-PTAT error, increased trimming difficulty and production cost are solved.

Description

Technical Field

[0001] This invention belongs to the field of CMOS bandgap reference technology, and relates to error correction technology in CMOS bandgap references, specifically a single-time correction CMOS bandgap reference and a single-time correction method. Background Technology

[0002] Battery voltage monitoring is the most basic and core part of the battery management system, and it also has the most stringent accuracy requirements. It requires extremely high accuracy in calculating the battery's state of charge and needs a stable, low-temperature drift reference voltage as a measurement reference.

[0003] Bandgap reference sources, capable of generating temperature-independent reference voltages, are a core module for battery voltage monitoring in battery management systems. The core principle of a bandgap reference source is to superimpose the emitter-junction voltage of a bipolar transistor (which has characteristics complementary to absolute temperature) with the PTAT voltage generated by the PTAT current. This means that a voltage with a positive temperature coefficient cancels out a voltage with a negative temperature coefficient, eliminating the temperature dependence of the reference voltage and thus generating a temperature-independent reference voltage. CMOS bandgap reference sources are a commonly used type of bandgap reference source and are a crucial foundational module in analog and mixed-signal chips, determining the accuracy of the entire system.

[0004] However, existing CMOS bandgap reference sources contain non-absolute temperature proportionality error (NPTAT error). This NPTAT error is caused by a combination of factors, including curvature error, operational amplifier offset, current mirror mismatch, resistor tolerance, and β compensation error. It cannot be eliminated by a single room temperature adjustment. The main reason is that the NPTAT error cannot be directly eliminated by the circuitry corresponding to the CMOS bandgap reference source. It requires multiple temperature adjustments and calibrations, which increases the difficulty of adjustment and production costs. Moreover, even after multiple temperature adjustments, the NPTAT error cannot be completely eliminated and will remain, affecting the accuracy of the generated reference voltage. Summary of the Invention

[0005] In view of the above-described background technology, the non-PTAT error in the prior art cannot be eliminated by the circuit corresponding to the CMOS bandgap reference source. This leads to technical problems such as increased adjustment difficulty and production cost due to multiple temperature adjustments, and the inability to completely eliminate the error after multiple temperature adjustments, which affects the accuracy of the generated reference voltage. To address these technical problems, this invention proposes a single-adjustment CMOS bandgap reference source and a single-adjustment method.

[0006] This invention adjusts V through a single circuit. EBThe gain coefficients A1 and B1 in the voltage generation circuit are adjusted and compensated to generate adjusted and compensated gain coefficients A2 and B2. The voltage V is then adjusted using these adjusted and compensated gain coefficients A2 and B2. EB1 Voltage V EB2 and voltage V EB3 Adjustments are made to eliminate V. EB The non-PTAT error in the voltage generation circuit (CMOS bandgap reference source) is eliminated by the circuit corresponding to the CMOS bandgap reference source. This solves the technical problem in the prior art that multiple temperature adjustments are required to eliminate non-PTAT errors, which increases the adjustment difficulty and production cost.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A single-adjustment CMOS bandgap reference source, including V EB The voltage generation circuit, the primary adjustment circuit, and the superposition calculation circuit, wherein the V EB The voltage generation circuit, the primary adjustment circuit, and the superposition calculation circuit are connected sequentially from front to back. The V EB Voltage generation circuit, used to generate voltage V EB1 Voltage V EB2 and voltage V EB3 ; The primary adjustment circuit is used to adjust V EB The gain coefficients A1 and B1 in the voltage generation circuit are adjusted and compensated to eliminate non-PTAT errors, generating adjusted and compensated gain coefficients A2 and B2. The superposition calculation circuit is used to adjust the voltage V based on the adjusted and compensated gain coefficient A2 and the adjusted and compensated gain coefficient B2. EB1 Voltage V EB2 and voltage V EB3 Perform a weighted summation to obtain the reference voltage V. REF .

[0008] Further specifying, the primary adjustment circuit includes a sampling input module and a switched capacitor adjustment module, wherein the input terminal of the sampling input module is connected to V. EB The voltage generation circuit is connected, and the output terminal of the sampling input module is connected to the switched capacitor adjustment module; The sampling input module is used to receive V EB The voltage V generated by the voltage generation circuit EB1 Voltage V EB2 and voltage V EB3 And according to voltage V EB1 Voltage VEB2 and voltage V EB3 Generate the reference voltage to be adjusted; The switched capacitor adjustment module is used to adjust V EB The gain coefficients A1 and B1 in the voltage generation circuit are adjusted and compensated to eliminate non-PTAT errors, generating adjusted and compensated gain coefficients A2 and B2. The superposition calculation circuit is used to perform a weighted summation operation on the reference voltage to be adjusted based on the adjusted and compensated gain coefficient A2 and the adjusted and compensated gain coefficient B2 to obtain the reference voltage V. REF。

[0009] Further specifying, the sampling input module includes switched capacitors C arranged in parallel. SP1O and switched capacitor C SN1O ; The switched capacitor C SP1O and switched capacitor C SN1O Both are used to receive V EB The voltage V generated by the voltage generation circuit EB1 Voltage V EB2 and voltage V EB3 And according to voltage V EB1 Voltage V EB2 and voltage V EB3 Generate the reference voltage to be adjusted.

[0010] Further specifying, the switched capacitor adjustment module includes a switched capacitor C. SP1C Switched capacitor C SN1C Switched capacitor C SP1F and switched capacitor C SN1F The switched capacitor C SP1O Switched capacitor C SP1C and switched capacitor C SP1F Parallel connection; the switched capacitor C SN1O Switched capacitor C SN1C and switched capacitor C SN1F Parallel connection; the switched capacitor C SP1C Switched capacitor C SN1C Switched capacitor C SP1F and switched capacitor C SN1F Used for V EB The gain coefficient A1 in the voltage generation circuit is adjusted and compensated to generate the adjusted and compensated gain coefficient A2. The adjusted and compensated gain coefficient A2 is: In the formula, This refers to the switched capacitor C. SP1O The value; This refers to the switched capacitor C. SP1C The value; This refers to the switched capacitor C. SP1F The value; This refers to the switched capacitor C. SN1O The value; This refers to the switched capacitor C. SN1C The value; This refers to the switched capacitor C. SN1F The value; This refers to the switched capacitor C. FP The value; This refers to the switched capacitor C. FN The value of .

[0011] Furthermore, the switched capacitor adjustment module also includes a switched capacitor C. SP2 and switched capacitor C SN2 The switched capacitor C SP2 With switched capacitor C SP1F The switched capacitor C is connected in parallel. SN2 With switched capacitor C SN1F Parallel connection; the switched capacitor C SP2 and switched capacitor C SN2 Used for V EB The gain coefficient B1 in the voltage generation circuit is adjusted and compensated to generate the adjusted and compensated gain coefficient B2. The adjusted and compensated gain coefficient B2 is: In the formula, This refers to the switched capacitor C. SP2 The value; This refers to the switched capacitor C. SN2 The value of .

[0012] Furthermore, the primary adjustment circuit also includes a capacitor rotation module, which is connected to the switched capacitor adjustment module; the capacitor rotation module is used to rotate the capacitor in the switched capacitor adjustment module to eliminate PTAT error. The capacitor rotation module includes a switched capacitor C. FP and switched capacitor C FN The switched capacitor C FP It is a switched capacitor and switched capacitors The switched capacitor C obtained after rotating the capacitor. FN It is a switched capacitor and switched capacitors This was obtained after rotating the capacitor.

[0013] Further specifying, the superposition calculation circuit is a summing operational amplifier, and the V calculated by the summing operational amplifier is... REF for: In the formula, This is the positive terminal output voltage of the switched capacitor adjustment module; The negative terminal output voltage of the switched capacitor trimming module; φ1 and φ2 are two non-overlapping clocks; The voltage V in stage φ1 EB2 The value; For the φ2 stage voltage V EB2 The value; The voltage V in stage φ1 EB1 The value; For the φ2 stage voltage V EB1 The value; For the φ2 stage voltage V EB3 The value of .

[0014] Further specifying, the V EB The voltage generation circuit includes a dynamic matching circuit, which includes a current source, a dynamic element matching switch network, and at least three PNP transistors. The current source is connected to all three PNP transistors through the dynamic element matching switch network. The voltage V EB1 and voltage V EB2 All are generated by using PNP transistors through a current source and by using a dynamic element matching switch network for dynamic matching.

[0015] Further specifying, the V EB The voltage generation circuit also includes a bias current circuit, which is connected in parallel with the dynamic matching circuit; The bias current circuit includes a resistor R. C Transistor Q3 and current bias module, the resistor R C Both transistor Q3 and resistor R are connected to the current bias module. C The current bias module generates a bias current I. CON The bias current I CON After passing through transistor Q3, voltage V is generated. EB3 .

[0016] The single-adjustment method based on the above-mentioned single-adjustment CMOS bandgap reference source includes the following steps: S1: Using V EB The voltage generating circuit generates voltage V EB1 Voltage VEB2 and voltage V EB3 ; S2: For V EB The gain coefficients A1 and B1 in the voltage generation circuit are adjusted and compensated to eliminate non-PTAT errors, generating adjusted and compensated gain coefficients A2 and B2. S3: Adjust the voltage V based on the adjusted and compensated gain coefficients A2 and B2. EB1 Voltage V EB2 and voltage V EB3 Perform a weighted summation to obtain the reference voltage V. REF .

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention provides a single-adjustment CMOS bandgap reference source, which adjusts the V bandgap through a single-adjustment circuit. EB The gain coefficients A1 and B1 in the voltage generation circuit are adjusted and compensated to generate adjusted and compensated gain coefficients A2 and B2. The voltage V is then adjusted using these adjusted and compensated gain coefficients A2 and B2. EB1 Voltage V EB2 and voltage V EB3 Adjustments are made to eliminate V. EB The non-PTAT error in the voltage generation circuit (CMOS bandgap reference source) is eliminated by the circuit corresponding to the CMOS bandgap reference source. This solves the technical problem in the prior art that multiple temperature adjustments are required to eliminate non-PTAT errors, which increases the adjustment difficulty and production cost.

[0018] 2. This invention utilizes voltage V EB1 Voltage V EB2 and voltage V EB3 The adjustment process eliminates non-PTAT errors, allowing the capacitor to be rotated at room temperature via a capacitor rotation module after the CMOS bandgap reference source is manufactured. This means that the adjustment is performed only once at room temperature to eliminate PTAT errors, simplifying the production process and improving mass production efficiency.

[0019] 3. The single-adjustment CMOS bandgap reference source of this invention operates over a wide temperature range ( The average temperature drift is less than 6 ppm / ℃ within a temperature range of 40℃ to 125℃; while existing CMOS bandgap reference sources exhibit an average temperature drift of less than 6 ppm / ℃ over a wide temperature range. The average temperature drift within the range of 40℃ to 125℃ is greater than 10ppm / ℃. Therefore, this invention greatly reduces the error caused by temperature drift in CMOS bandgap reference sources.

[0020] 4. The dynamic matching circuit of the present invention adopts the synergistic technology of "β compensation circuit + dynamic component matching + capacitor rotation" to reduce non-PTAT error to a negligible level without the need for systematic digital correction.

[0021] 5. The single-adjustment CMOS bandgap reference source of the present invention has good process compatibility and can be implemented based on 0.18-micron complementary metal-oxide-semiconductor process without special processes (such as high-precision resistor process, dedicated BJT process), thus reducing the cost of fabrication. Attached Figure Description

[0022] Figure 1 This is a simplified schematic diagram of the single-adjustment CMOS bandgap reference source of the present invention; Figure 2 This is a circuit diagram of the single-adjustment CMOS bandgap reference source of the present invention; Figure 3 A schematic diagram of the switched capacitor adjustment circuit and the superposition calculation circuit. Figure 4 Simplified schematic diagrams for non-PTAT error and PTAT error; Figure 5 This is a schematic diagram of the rough adjustment circuit; Figure 6 A schematic diagram of the circuit for fine-tuning; Figure 7 This is a schematic diagram showing the connection between the switched capacitor adjustment circuit, the superposition calculation circuit, the coarse adjustment circuit, and the fine adjustment circuit. Detailed Implementation

[0023] The technical solution of the present invention will be further explained and described below with reference to the accompanying drawings and embodiments, but the present invention is not limited to the embodiments described below.

[0024] The base voltage V output from the emitter of a bipolar junction transistor (PNP transistor) EB Due to its robustness in the manufacturing process, it is often used in precision voltage reference sources, but the base voltage V EB It contains a component that varies with temperature, resulting in temperature-dependent errors. Therefore, the circuit corresponding to the CMOS bandgap reference source needs to compensate for this error through a correction loop. When the absolute temperature is T, the base voltage V EB It can be represented as: In the formula, It is the bandgap voltage at a temperature of 0K; It is the specified reference temperature. It is a process-related constant, the value of which depends on the chip manufacturing process. In this formula, It will pass through the base voltage V EBThe subtraction operation is canceled out, and has no effect on the result; It is related to the collector bias current I C The temperature-dependent variables take values ​​of 0 or 1; It is the thermal voltage, which is 26mV at room temperature. In this formula, the first term is a constant value independent of temperature, the second term is the component complementary to absolute temperature (CTAT), and the third term is the nonlinear characteristic that varies with temperature, which is the source of non-PTAT error.

[0025] See Figure 1 In the CMOS bandgap reference source of this invention, two different bias currents are provided, namely PTAT current I. PTAT and temperature-independent current I CON To generate a voltage V that compensates for temperature variations. EB1 and voltage V EB2 .

[0026] This invention provides a single-adjustment CMOS bandgap reference source, including V EB Voltage generation circuit, primary adjustment circuit, and superposition calculation circuit, V EB The voltage generation circuit, the primary adjustment circuit, and the superposition calculation circuit are connected sequentially from front to back. V EB Voltage generation circuit, used to generate voltage V EB1 Voltage V EB2 and voltage V EB3 V EB The voltage generation circuit includes a dynamic matching circuit, which comprises a current source, a dynamic element matching switch network, and at least three parallel PNP transistors. The current source is connected to all three parallel PNP transistors through the dynamic element matching switch network. The voltage V EB1 and voltage V EB2 All are generated by using PNP transistors with a current source and dynamic matching via a dynamic element matching switching network. For details, see [link to documentation]. Figure 2 The dynamic matching circuit contains four PNP transistors: PNP transistor Q1, PNP transistor Q2, PNP transistor Q... B1 and PNP transistor Q B2 The four PNP transistors and the dynamic element matching switching network constitute a β compensation circuit. When using the β compensation circuit to generate PTAT current, the matching accuracy of resistor R, resistor R / n, and current sources is crucial. If the ratio between current sources and the ratio between resistor R and resistor R / n can be accurately maintained, then the absolute value error of the resistor will only affect the base voltage V. EB To generate PTAT error, dynamic component matching technology is used to rotate the PNP transistor Q.B1 PNP transistor Q B2 The current source connection of PNP transistors Q1 and Q2 is used to average the current source offset, thereby reducing the offset between different branches of the current source. Within one switching cycle, PNP transistor Q... B1 PNP transistor Q B2 The equivalent bias currents of PNP transistors Q1 and Q2 are determined by the average current of a (2+2n) unit current source, with a ratio of 1:n:1:n, where n is the ratio of the currents flowing through PNP transistors Q2 and Q1.

[0027] exist Figure 2 In order to achieve better matching of the current gain factor β, digital error averaging technology is also applied to bipolar junction transistors (BJTs). Each BJT uses resistors R and R / n, and the switch is placed in a path where no DC current flows to prevent the on-resistance of the switch from affecting the bias current. Digital error averaging technology is implemented by controlling the switch at the input of amplifier A1 and the base of the PNP transistor. By combining this with power source switching technology, the circuit topology of the PNP transistor is rotated within one cycle to achieve the highest circuit accuracy by averaging the mismatch between resistors R and R / n and the PNP transistor β value. Through β compensation combined with dynamic component matching technology of the BJT and current source, the influence of the current gain factor β and temperature dependence on the collector current is eliminated.

[0028] See Figure 2 In order to generate voltage V EB1 and voltage V EB2 PNP transistors are biased using the collector current PTAT to compensate for the temperature-dependent base voltage V. EB It employs β compensation technology, with a clock-controlled switch used to enable and disable β compensation. The collector current I is affected by the forward current gain β of the PNP transistor. C It can be represented as: In the formula, It is the emitter current of a PNP transistor; if β is high enough, even if β changes with temperature, The dependence on β is negligible. However, if β is low, the temperature dependence of β will lead to non-PTAT I. C This non-PTAT I C This will generate a base voltage V that is different from the desired temperature dependence. EB .

[0029] In phase φ1, β compensation is enabled by closing the switch. Assume β... B1and β B2 An ideal match is achieved by a loop consisting of an error amplifier, a current source, a resistor, and a vertical PNP transistor, which generates an emitter current related to β. and The PNP transistor Q flows through the φ1 stage respectively. B1 and Q B2 The collector current is used to obtain the reference voltage V for PNP transistors Q1 and Q2 in the φ1 stage, which is independent of β. EB . This is the forward current gain of the PNP transistor Q1; Q is a PNP transistor B2 The positive current gain; For φ1 stage PNP type transistor Q B2 voltage, For φ1 stage PNP type transistor Q B1 The voltage is given by R, where R is the value of the resistance R. This is the ratio of the current flowing through PNP transistor Q2 and PNP transistor Q1.

[0030] For curvature correction, a reference voltage V generated using a temperature-independent collector bias current is required. EB Unlike PNP transistors Q1 and Q2, transistor Q3 uses a bias current without β compensation; therefore, the voltage V... EB3 This is related to β. To eliminate this β-dependency, two β-dependent VL transistors Q2 and Q3 are used. EB The voltage difference between them. In the φ2 stage, by Q B2 The base node grounding disables β compensation, V EB2_φ2 Collector current without β compensation Sure: In the formula, This is the forward current gain of the PNP transistor Q2; For φ2 stage PNP type transistor Q B2 The voltage; For φ2 stage PNP type transistor Q B1 The voltage.

[0031] Assuming at the specified reference temperature n× equals I CON Then the voltage difference can be expressed as: In the formula, The voltage of PNP transistor Q2 in the φ2 stage; The voltage of PNP transistor Q3 in the φ2 stage; This is the forward current gain of transistor Q3; Absolute temperature; This is the thermal voltage, which is 26mV at room temperature; T r The specified reference temperature.

[0032] If β is ideally matched, a voltage independent of β is generated. During the φ2 stage, the V1 of PNP transistors Q1 and Q2 is... EB The voltage difference is: In the formula, This is the voltage of the PNP transistor Q1 in the φ2 stage.

[0033] Therefore, when β1=β2=β3, the effect of β on the circuit of the PNP transistor is completely eliminated.

[0034] V EB The voltage generation circuit also includes an error amplifier A1. The offset of the error amplifier A1 is the main source of non-PTAT error. To eliminate the error caused by the offset of the error amplifier A1, the error amplifier A1 adopts a folded common-source common-gate amplifier with chopping technology.

[0035] V EB The voltage generation circuit also includes a bias current circuit, which is connected in parallel with the dynamic matching circuit. The voltage V EB3 This current is generated through a bias current circuit. The bias current circuit includes a resistor R. C Transistor Q3 and current bias module, resistor R C Both transistor Q3 and resistor R are connected to the current bias module. C The current bias module generates a bias current I. CON Bias current I CON After passing through transistor Q3, voltage V is generated. EB3 That is, voltage V EB3 It is a temperature-independent current I CON The biased PNP transistor Q3 is generated.

[0036] In this invention, a primary adjustment circuit is used to adjust V. EB The gain coefficients A1 and B1 in the voltage generation circuit are adjusted and compensated to eliminate non-PTAT errors, generating adjusted and compensated gain coefficients A2 and B2; see [link to relevant documentation]. Figure 1 The voltage V generated by PNP transistors Q1 and Q2 EB1 and voltage V EB2 By setting the base voltage V EB The calculation formula uses m=1 to represent the voltage V. EB3 By setting the base voltage V EB The formula uses m=0 to represent the gain coefficients A1 and B1, as shown below: Voltage V EB3 The component complementary to the absolute temperature is compensated by the PTAT voltage, which is determined by V. EB2 and V EB1 The difference is used to generate the gain coefficient A1. Since transistors Q2 and Q1 are respectively composed of 4×I PTAT and I PTAT The bias, where the second term of the PTAT voltage can be expressed as: Therefore, it can be deduced that: In the formula, It is the thermal voltage, which is 26mV at room temperature; It is the ratio of the current flowing through PNP transistor Q2 and PNP transistor Q1; It is Boltzmann's constant. It is absolute temperature; It is the charge of the electron.

[0037] In a 0.18-micron complementary metal-oxide-semiconductor process, the voltage V EB2 exist The simulated curvature error over a temperature range of 40°C to 125°C is approximately 3-4 mV. To improve the temperature drift accuracy to above 20 ppm / °C, this error needs to be eliminated. To compensate for this curvature error, a voltage V is used. EB2 and voltage V EB3 The voltage difference and gain coefficient B1 between them are used to achieve this. Since PNP transistors Q2 and Q3 are respectively composed of n×I... PTAT and I PTAT The bias, where the third term used for curvature correction can be expressed as: Wherein, at the specified reference temperature T r Below, n×I PTAT equals I CON .use As gain coefficient It can eliminate non-PTAT errors.

[0038] See Figure 4 b, c, and d in the text illustrate V EB (Voltage V) EB1 Voltage V EB2 and voltage V EB3 The simplified implementation principle of the single-adjustment CMOS bandgap reference source proposed in this invention is based on the voltage V. EB2 ( Figure 4 (as shown in b) and curvature correction voltage ( Figure 4 (as shown in c) and the voltage generated using PTAT current ( Figure 4 Adding (b) and (d) as shown in the diagram achieves a constant reference voltage over a temperature range, thus eliminating non-PTAT errors; then, a single adjustment is performed at room temperature to eliminate PTAT errors. Figure 4 (as shown in a).

[0039] The superposition calculation circuit is used to calculate the voltage V based on the adjusted and compensated gain coefficients A2 and B2. EB1 Voltage V EB2 and voltage V EB3 Perform a weighted summation to obtain the reference voltage V. REF .

[0040] In this invention, the primary adjustment circuit includes a sampling input module, a switched capacitor adjustment module, and a capacitor rotation module connected sequentially from front to back; the input terminal of the sampling input module is connected to V... EB The voltage generation circuit is connected, and the output terminal of the sampling input module is connected to the switched capacitor adjustment module; The sampling input module is used to receive V. EB The voltage V generated by the voltage generation circuit EB1 Voltage V EB2 and voltage V EB3 And according to voltage V EB1 Voltage V EB2 and voltage V EB3 Generate the reference voltage to be adjusted; Switched capacitor adjustment module, used for adjusting V EB The gain coefficients A1 and B1 in the voltage generation circuit are adjusted and compensated to eliminate non-PTAT errors, generating adjusted and compensated gain coefficients A2 and B2. The capacitor rotation module is used to rotate the capacitors in the switched capacitor adjustment module to eliminate PTAT error. The superposition calculation circuit is used to perform a weighted summation operation on the reference voltage to be adjusted based on the adjusted and compensated gain coefficients A2 and B2, to obtain the reference voltage V.REF。

[0041] See Figure 3 The sampling input module includes switched capacitors C arranged in parallel. SP1O and switched capacitor C SN1O Switched capacitor C SP1O and switched capacitor C SN1O Both are used to receive V EB The voltage V generated by the voltage generation circuit EB1 Voltage V EB2 and voltage V EB3 And according to voltage V EB1 Voltage V EB2 and voltage V EB3 Generate the reference voltage to be adjusted.

[0042] See Figure 3 The switched capacitor adjustment module includes a switched capacitor C. SP1C Switched capacitor C SN1C Switched capacitor C SP1F and switched capacitor C SN1F Switched capacitor C SP1O Switched capacitor C SP1C and switched capacitor C SP1F Parallel connection; switched capacitor C SN1O Switched capacitor C SN1C and switched capacitor C SN1F Parallel connection; switched capacitor C SP1C Switched capacitor C SN1C Switched capacitor C SP1F and switched capacitor C SN1F Used for V EB The gain coefficient A1 in the voltage generation circuit is adjusted and compensated to generate the adjusted and compensated gain coefficient A2. After adjustment and compensation, the gain coefficient A2 is: In the formula, This refers to the switched capacitor C. SP1O The value; This refers to the switched capacitor C. SP1C The value; This refers to the switched capacitor C. SP1F The value; This refers to the switched capacitor C. SN1O The value; This refers to the switched capacitor C. SN1C The value; This refers to the switched capacitor C. SN1F The value; This refers to the switched capacitor C. FP The value; This refers to the switched capacitor C. FN The value of .

[0043] See Figure 3 The switched capacitor adjustment module also includes a switched capacitor C. SP2 and switched capacitor C SN2 Switched capacitor C SP2 With switched capacitor C SP1F Parallel connection, switched capacitor C SN2 With switched capacitor C SN1F Parallel connection; switched capacitor C SP2 and switched capacitor C SN2 Used for V EB The gain coefficient B1 in the voltage generation circuit is adjusted and compensated to generate the adjusted and compensated gain coefficient B2. The adjusted and compensated gain coefficient B2 is: In the formula, This refers to the switched capacitor C. SP2 The value; This refers to the switched capacitor C. SN2 The value of .

[0044] The capacitor rotation module includes a switched capacitor C. FP and switched capacitor C FN Switched capacitor C FP It is a switched capacitor and switched capacitors The switched capacitor C obtained after rotating the capacitor. FN It is a switched capacitor and switched capacitors This was obtained after rotating the capacitor.

[0045] The superposition calculation circuit is a summing operational amplifier, which calculates V. REF for: In the formula, This is the positive terminal output voltage of the switched capacitor adjustment module; The negative terminal output voltage of the switched capacitor trimming module; φ1 and φ2 are two non-overlapping clocks; The voltage V in stage φ1 EB2 The value; For the φ2 stage voltage V EB2 The value; The voltage V in stage φ1 EB1 The value; For the φ2 stage voltage VEB1 The value; For the φ2 stage voltage V EB3 The value of . That is and Together they form the reference voltage to be adjusted.

[0046] This invention utilizes non-overlapping clocks φ1 and φ2 to control V EB The bias mode of the voltage generation circuit enables or disables β compensation and sampling / charge transfer in the primary trimming circuit, forming a discrete-time domain curvature correction scheme, utilizing voltage V. EB2 and voltage V EB1 The difference achieves adaptive curvature correction without the need for complex analog circuits, adapting to process fluctuations.

[0047] See Figure 5 and Figure 7 The blue section represents the coarse adjustment module, which employs a binary capacitor array adjustment method. Each capacitor in the adjustment module is a unit capacitor of the same design, C. C It is formed by connecting a certain number of components in parallel. The signal D is configured using an 8-bit digital configuration. TRIM_C Configure and control access to C using <7:0>. SP1O The capacitance value is 0.5C. C ~127.5C C Range. Capacitors not selected for connection will be grounded as filter capacitors, having no impact on the circuit.

[0048] See Figure 6 and Figure 7 This is a schematic diagram of the fine-tuning module, which uses an 8-bit external control signal D. TRIM_F Generate 256 levels of V REF Adjusted 1-bit PWM signal D PWM The digital Σ-Δ modulator employs a minimalist structure of "integrator + 1-bit quantizer" (8-bit accumulator + comparator), operating at a clock frequency far exceeding the circuit signal bandwidth. TRIM_F The input is a digital Σ-Δ modulator. The modulator accumulates the input error through integration, and then outputs a 1-bit bit stream D via a quantizer. PWM This ensures that the average duty cycle γ of the potential flow accurately reflects D. TRIM_F The value of D. For example, D TRIM_F When γ = 120, γ = 120 / 255 ≈ 0.47, D PWM The proportion of high-frequency signals is approximately 47%. High-precision capacitor interpolation is achieved using bitstream duty cycle, replacing traditional binary weighted capacitor arrays. Time resolution replaces spatial resolution, requiring only two fixed-value capacitors and a single-bit switching switch to achieve multi-level capacitor output, significantly simplifying the hardware structure. The 8-bit control signal D is then converted using a digital Σ-Δ modulator. TRIM_F Convert to a 1-bit PDM bitstream, so that CSP1 and C SN1 The equivalent capacitance fine-tuning resolution reaches C SP1F / 256 and C SN1F At 256°C and 27°C, the fine-tuning resolution is approximately 37.5 μV. This fine-tuning accuracy ensures... V REF The residual PTAT error is less than ±25μV; the 8-bit coarse adjustment + 8-bit fine adjustment can achieve an adjustment range of more than 60mV at 27℃, which is sufficient to compensate for the PTAT error caused by device mismatch and process corner chip differences.

[0049] This invention also proposes a single-stage adjustment method, which is based on the above-mentioned single-stage adjustment CMOS bandgap reference source, and includes the following steps: S1: Using V EB The voltage generating circuit generates voltage V EB1 Voltage V EB2 and voltage V EB3 ; S2: For V EB The gain coefficients A1 and B1 in the voltage generation circuit are adjusted and compensated to generate adjusted and compensated gain coefficients A2 and B2; the adjusted and compensated gain coefficients A2 and B2 are then used to adjust the voltage V. EB1 Voltage V EB2 and voltage V EB3 Adjustments are made to eliminate non-PTAT errors, resulting in the N-type adjustment voltage V. REFN and P-type adjustment voltage V REFP ; S3: Adjust the N-type voltage V REFN and P-type adjustment voltage V REFP By performing superposition calculations, the reference voltage V is obtained. REF .

[0050] It should be noted that the single-adjustment method of the present invention corresponds to the single-adjustment CMOS bandgap reference source described above. For details not described in detail here, please refer to the description of the single-adjustment CMOS bandgap reference source described above.

[0051] The above description is only used to illustrate the technical solutions of the present invention, and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing, those skilled in the art should understand that modifications can still be made to the technical solutions described above, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A single-adjustment CMOS bandgap reference source, characterized in that, Including V EB The voltage generation circuit, the primary adjustment circuit, and the superposition calculation circuit, wherein the V EB The voltage generation circuit, the primary adjustment circuit, and the superposition calculation circuit are connected sequentially from front to back. The V EB Voltage generation circuit, used to generate voltage V EB1 Voltage V EB2 and voltage V EB3 ; The primary adjustment circuit is used to adjust V EB The gain coefficients A1 and B1 in the voltage generation circuit are adjusted and compensated to eliminate non-PTAT errors, generating adjusted and compensated gain coefficients A2 and B2. The superposition calculation circuit is used to adjust the voltage V based on the adjusted and compensated gain coefficient A2 and the adjusted and compensated gain coefficient B2. EB1 Voltage V EB2 and voltage V EB3 Perform a weighted summation to obtain the reference voltage V. REF .

2. The single-adjustment CMOS bandgap reference source according to claim 1, characterized in that, The primary adjustment circuit includes a sampling input module and a switched capacitor adjustment module. The input terminal of the sampling input module is connected to V. EB The voltage generation circuit is connected, and the output terminal of the sampling input module is connected to the switched capacitor adjustment module; The sampling input module is used to receive V EB The voltage V generated by the voltage generation circuit EB1 Voltage V EB2 and voltage V EB3 And according to voltage V EB1 Voltage V EB2 and voltage V EB3 Generate the reference voltage to be adjusted; The switched capacitor adjustment module is used to adjust V EB The gain coefficients A1 and B1 in the voltage generation circuit are adjusted and compensated to eliminate non-PTAT errors, generating adjusted and compensated gain coefficients A2 and B2. The superposition calculation circuit is used to perform a weighted summation operation on the reference voltage to be adjusted based on the adjusted and compensated gain coefficient A2 and the adjusted and compensated gain coefficient B2 to obtain the reference voltage V. REF .

3. The single-adjustment CMOS bandgap reference source according to claim 2, characterized in that, The sampling input module includes parallel-arranged switched capacitors C SP1O and switched capacitor C SN1O ; The switched capacitor C SP1O and switched capacitor C SN1O Both are used to receive V EB The voltage V generated by the voltage generation circuit EB1 Voltage V EB2 and voltage V EB3 And according to voltage V EB1 Voltage V EB2 and voltage V EB3 Generate the reference voltage to be adjusted.

4. The single-adjustment CMOS bandgap reference source according to claim 3, characterized in that, The switched capacitor adjustment module includes a switched capacitor C. SP1C Switched capacitor C SN1C Switched capacitor C SP1F and switched capacitor C SN1F The switched capacitor C SP1O Switched capacitor C SP1C and switched capacitor C SP1F Parallel connection; the switched capacitor C SN1O Switched capacitor C SN1C and switched capacitor C SN1F Parallel connection; the switched capacitor C SP1C Switched capacitor C SN1C Switched capacitor C SP1F and switched capacitor C SN1F Used for V EB The gain coefficient A1 in the voltage generation circuit is adjusted and compensated to generate the adjusted and compensated gain coefficient A2. The adjusted and compensated gain coefficient A2 is: In the formula, This refers to the switched capacitor C. SP1O The value; This refers to the switched capacitor C. SP1C The value; This refers to the switched capacitor C. SP1F The value; This refers to the switched capacitor C. SN1O The value; This refers to the switched capacitor C. SN1C The value; This refers to the switched capacitor C. SN1F The value; This refers to the switched capacitor C. FP The value; This refers to the switched capacitor C. FN The value of .

5. The single-adjustment CMOS bandgap reference source according to claim 4, characterized in that, The switched capacitor adjustment module also includes a switched capacitor C. SP2 and switched capacitor C SN2 The switched capacitor C SP2 With switched capacitor C SP1F The switched capacitor C is connected in parallel. SN2 With switched capacitor C SN1F Parallel connection; the switched capacitor C SP2 and switched capacitor C SN2 Used for V EB The gain coefficient B1 in the voltage generation circuit is adjusted and compensated to generate the adjusted and compensated gain coefficient B2. The adjusted and compensated gain coefficient B2 is: In the formula, This refers to the switched capacitor C. SP2 The value; This refers to the switched capacitor C. SN2 The value of .

6. The single-adjustment CMOS bandgap reference source according to claim 5, characterized in that, The primary adjustment circuit also includes a capacitor rotation module, which is connected to the switched capacitor adjustment module. The capacitor rotation module is used to rotate the capacitor in the switched capacitor adjustment module to eliminate PTAT error. The capacitor rotation module includes a switched capacitor C. FP and switched capacitor C FN The switched capacitor C FP It is a switched capacitor and switched capacitors The switched capacitor C obtained after rotating the capacitor. FN It is a switched capacitor and switched capacitors This was obtained after rotating the capacitor.

7. The single-adjustment CMOS bandgap reference source according to claim 6, characterized in that, The superposition calculation circuit is a summing operational amplifier, and the summing operational amplifier calculates V. REF for: In the formula, This is the positive terminal output voltage of the switched capacitor adjustment module; The negative terminal output voltage of the switched capacitor trimming module; φ1 and φ2 are two non-overlapping clocks; The voltage V in stage φ1 EB2 The value; For the φ2 stage voltage V EB2 The value; The voltage V in stage φ1 EB1 The value; For the φ2 stage voltage V EB1 The value; For the φ2 stage voltage V EB3 The value of .

8. The single-adjustment CMOS bandgap reference source according to claim 1, characterized in that, The V EB The voltage generation circuit includes a dynamic matching circuit, which includes a current source, a dynamic element matching switch network, and at least three PNP transistors. The current source is connected to all three PNP transistors through the dynamic element matching switch network. The voltage V EB1 and voltage V EB2 All are generated by using PNP transistors through a current source and by using a dynamic element matching switch network for dynamic matching.

9. The single-adjustment CMOS bandgap reference source according to claim 8, characterized in that, The V EB The voltage generation circuit also includes a bias current circuit, which is connected in parallel with the dynamic matching circuit; The bias current circuit includes a resistor R. C Transistor Q3 and current bias module, the resistor R C Both transistor Q3 and resistor R are connected to the current bias module. C The current bias module generates a bias current I. CON The bias current I CON After passing through transistor Q3, voltage V is generated. EB3 .

10. The single-stage adjustment method for forming a CMOS bandgap reference source based on claim 1, characterized in that, Includes the following steps: S1: Using V EB The voltage generating circuit generates voltage V EB1 Voltage V EB2 and voltage V EB3 ; S2: For V EB The gain coefficients A1 and B1 in the voltage generation circuit are adjusted and compensated to eliminate non-PTAT errors, generating adjusted and compensated gain coefficients A2 and B2. S3: Adjust the voltage V based on the adjusted and compensated gain coefficients A2 and B2. EB1 Voltage V EB2 and voltage V EB3 Perform a weighted summation to obtain the reference voltage V. REF .

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