Power consumption calculation method and device of NPU architecture, equipment and storage medium

Abstract

Embodiments of the present application provide a power consumption calculation method and device of NPU architecture, equipment and storage medium, and relate to the technical field of power consumption calculation of intelligent computing platform. For each die, a matrix unit, a vector unit and a scalar unit are selected as target units one by one; unit operation energy consumption of the target units is obtained, unit dynamic power is calculated according to the unit operation energy consumption, unit static power of the target units is obtained, module power of the target units is obtained according to the unit dynamic power and the unit static power, storage power of on-chip storage is calculated, network power of on-chip network is calculated; for each die, die power is obtained according to the corresponding module power, storage power and network power, interconnection power between two dies is obtained, and total power consumption of a target device is obtained according to at least the die power and the interconnection power. The modeling process includes power consumption of each functional unit in the die, and also includes interaction power consumption between the dies, which significantly improves the accuracy of power consumption modeling.

Description

Technical Field

[0001] This application relates to the field of power consumption calculation technology for intelligent computing platforms, and in particular to power consumption calculation methods, devices, equipment, and storage media for NPU architecture. Background Technology

[0002] Deep learning-based intelligent computing platforms are driving the evolution of computing power from single-chip to multi-chip, multi-rack, and even cross-data center scales. NPU intelligent computing platforms for matrix / vector intensive workloads have become mainstream model accelerators, and their energy consumption share continues to rise. Power consumption modeling is the core foundation for architecture design, computing power scheduling, and energy efficiency optimization (including frequency and voltage control, power capping, and task orchestration).

[0003] Related technologies build power consumption models around general-purpose CPU and GPU architectures, enabling layered modeling capabilities for arrays, interconnects, logic, and clocks. However, they lack modeling of NPU architectures, and do not adequately cover the coordination, hierarchical local buffering, and cross-layer direct transport of the three types of specialized resources in NPU architectures, including matrix arrays / vector arrays / scalar units. This makes it difficult to fully map operators and data flows into energy consumption, and also lacks modeling of the energy consumption of multi-die interconnects within the package and on-chip high-bandwidth caches. Summary of the Invention

[0004] The main objective of this application is to propose a power consumption calculation method, apparatus, device, and storage medium for NPU architecture, thereby improving the accuracy of power consumption modeling for NPU architecture.

[0005] To achieve the above objectives, a first aspect of this application proposes a power consumption calculation method for an NPU architecture. The NPU architecture of the target device includes at least two bare dies, each bare die including at least: a matrix unit, a vector unit, a scalar unit, on-chip memory, and an on-chip network. The method includes:

[0006] For each of the bare crystals, the matrix unit, the vector unit, and the scalar unit are selected one by one as the target unit; The unit operation power consumption of the target unit is obtained, the unit dynamic power is calculated based on the unit operation power consumption, the unit static power of the target unit is obtained, the module power of the target unit is obtained based on the unit dynamic power and the unit static power, the storage power of the on-chip storage is calculated, and the network power of the on-chip network is calculated. For each of the bare dies, the bare die power is obtained based on the corresponding module power, storage power, and network power. The interconnect power between any two bare dies is then obtained. The total power consumption of the target device is obtained based at least on the bare die power and the interconnect power.

[0007] In some embodiments, obtaining the unit operating energy consumption of the target unit includes: The idle power of the target unit in the idle state is obtained, the target unit is saturated for a preset time period, the corresponding saturation power and number of operations are obtained, and the incremental power is calculated based on the saturation power and the idle power. The unit number of operations is obtained by dividing the number of operations by the preset duration, and the unit operating energy consumption is obtained by dividing the incremental power by the unit number of operations.

[0008] In some embodiments, calculating the unit dynamic power based on the unit operating energy consumption includes: Obtain the percentage of effective computation state cycles and the percentage of clock on time within the preset duration; The precision operation energy consumption is obtained based on the unit operation energy consumption corresponding to each calculation precision. The unit dynamic power is obtained by multiplying the effective computing state cycle ratio, the clock on time ratio, and the precision operation energy consumption.

[0009] In some embodiments, the on-chip storage includes at least one storage layer, and calculating the storage power of the on-chip storage includes: Each storage layer is selected as a target layer, a fixed working set is placed in the target layer, all target cells are kept idle, the idle power corresponding to the target layer is obtained, and read, write, and cross-layer read and write operations are performed on the fixed working set in the target layer to obtain read power, write power and read and write power respectively. Based on the idle power, the read power, the write power, and the read-write power, the read increment power, the write increment power, and the read-write increment power are obtained. The byte rate corresponding to the target layer is obtained. The storage layer read parameters are obtained according to the quotient of the read increment power and the byte rate. The storage layer write parameters are obtained according to the quotient of the write increment power and the byte rate. The storage layer read-write parameters are obtained according to the quotient of the read-write increment power and the byte rate. The storage power is obtained based on the storage layer read parameters, the storage layer write parameters, and the storage layer read / write parameters.

[0010] In some embodiments, obtaining the storage power based on the storage layer read parameters, the storage layer write parameters, and the storage layer read / write parameters includes: For each target layer, the target layer parameters are obtained based on the storage layer read parameters and the storage layer write parameters. The static power of the target layer is obtained. All the target layer parameters are summed to obtain the first parameter. All the static power is summed to obtain the second parameter. Select two cross-layers in pairs and sum the corresponding storage layer read / write parameters to obtain the third parameter; The storage power is obtained by summing the first parameter, the second parameter, and the third parameter.

[0011] In some embodiments, calculating the network power of the on-chip network includes: For each on-chip route of the bare die, buffer parameters are obtained based on the acquired buffer event power and buffer trigger rate, arbitration parameters are obtained based on the acquired arbitration event power and arbitration trigger rate, and cross switch parameters are obtained based on the acquired cross switch event power and cross trigger rate. The buffer parameters, arbitration parameters, and cross switch parameters are summed to obtain the routing parameters. For each on-chip link of the bare die, obtain the power consumption per unit bit transmission; Based on all the routing parameters, on-chip routing parameters are obtained; on-chip link parameters are obtained based on all the unit bit transmission power consumption; on-chip idle power is obtained; and the network power of the bare crystal is obtained based on the on-chip routing parameters, the on-chip link parameters, and the on-chip idle power.

[0012] In some embodiments, obtaining the interconnect power between any two of the bare dies includes: For each pair of interconnected bare crystals, obtain the interconnect idle power, select one of the bare crystals, and obtain the corresponding unit bit transmission power consumption, data transmission rate, unit bit reception power consumption, and data reception rate. Interconnection transmission parameters are obtained by multiplying the unit bit transmission power consumption and the data transmission rate, and interconnection reception parameters are obtained by multiplying the unit bit reception power consumption and the data reception rate. The interconnect power is obtained based on the interconnect transmission parameters, the interconnect reception parameters, and the interconnect idle power.

[0013] In some embodiments, the method further includes: If the manufacturing processes of the modeling and measurement equipment and the target equipment are different, obtain the modeling circuit parameters of the modeling and measurement equipment and the target circuit parameters of the target equipment; The energy consumption scaling factor is calculated based on the modeling circuit parameters and the target circuit parameters, and the total power consumption is scaled based on the energy consumption scaling factor.

[0014] To achieve the above objectives, a second aspect of this application proposes a power-efficient computing device with an NPU architecture. The target device's NPU architecture includes at least two dies, each die comprising at least: a matrix unit, a vector unit, a scalar unit, on-chip memory, and an on-chip network. The device includes: Target cell selection module: used to select the matrix cell, the vector cell, and the scalar cell as target cells for each bare die; Bare die power calculation module: used to obtain the unit operating power consumption of the target unit, calculate the unit dynamic power based on the unit operating power consumption, obtain the unit static power of the target unit, obtain the module power of the target unit based on the unit dynamic power and the unit static power, calculate the storage power of the on-chip memory, and calculate the network power of the on-chip network. Total power consumption calculation module: For each of the bare dies, the bare die power is obtained based on the corresponding module power, storage power and network power, the interconnect power between any two of the bare dies is obtained, and the total power consumption of the target device is obtained based at least on the bare die power and the interconnect power.

[0015] To achieve the above objectives, a third aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the method described in the first aspect.

[0016] To achieve the above objectives, a fourth aspect of the present application provides a storage medium that stores a computer program, which, when executed by a processor, implements the method described in the first aspect.

[0017] The NPU architecture power consumption calculation method, apparatus, device, and storage medium proposed in this application embodiment include at least two bare dies in the target device's NPU architecture. Each bare die includes at least a matrix unit, a vector unit, a scalar unit, on-chip memory, and an on-chip network. For each bare die, matrix units, vector units, scalar units, on-chip memory, and on-chip network are selected one by one as target units. The unit operation power consumption of each target unit is obtained, and the unit dynamic power is calculated based on the unit operation power consumption. The unit static power of the target unit is obtained, and the module power of the target unit is obtained based on the unit dynamic power and unit static power. The storage power of the on-chip memory is calculated, and the network power of the on-chip network is calculated. For each bare die, the bare die power is obtained based on the corresponding module power, storage power, and network power. The interconnect power between any two bare dies is obtained, and the total power consumption of the target device is obtained based at least on the bare die power and interconnect power. This application embodiment decomposes the power consumption of each functional unit one by one, improving the granularity of modeling and accurately capturing the differences in power consumption characteristics of different units. For each target unit, the module power is calculated progressively based on unit operating power consumption, unit dynamic power, and unit static power, achieving power consumption quantification. This avoids the one-sidedness of considering only dynamic or static power consumption and ensures that the power consumption calculation results of each functional unit closely match its actual operating state. Furthermore, considering that the power consumption of inter-chip communication in a multi-die architecture increases significantly with the frequency of data interaction, ignoring this power consumption would lead to significant deviations in the modeling results. Therefore, the interconnect power between each pair of dies is also modeled. Finally, the total power consumption of the target device is obtained by summing all die power and the interconnect power between dies. This encompasses both the power consumption of each functional unit within a die and the power consumption of interactions between dies, constructing a comprehensive and high-precision NPU architecture power consumption model, significantly improving the accuracy of power consumption modeling. Attached Figure Description

[0018] Figure 1 This is a flowchart of the power consumption calculation method for the NPU architecture provided in the embodiments of this application.

[0019] Figure 2 This is a flowchart of obtaining the unit operating energy consumption of the target unit provided in an embodiment of this application.

[0020] Figure 3 This is a flowchart of calculating the unit dynamic power based on the unit operating energy consumption provided in the embodiments of this application.

[0021] Figure 4 This is a flowchart illustrating the calculation of on-chip storage power provided in an embodiment of this application.

[0022] Figure 5 This is a flowchart illustrating the calculation of network power of an on-chip network provided in an embodiment of this application.

[0023] Figure 6 This is a flowchart of obtaining the interconnect power between two bare dies provided in an embodiment of this application.

[0024] Figure 7 This is a block diagram of the power consumption computing device structure of the NPU architecture provided in another embodiment of this application.

[0025] Figure 8 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0027] It should be noted that although functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0029] Deep learning-based intelligent computing platforms are driving the evolution of computing power from single-chip to multi-chip, multi-rack, and even cross-data center scales. NPU intelligent computing platforms for matrix / vector intensive workloads have become mainstream model accelerators, and their energy consumption share continues to rise. Power consumption modeling is the core foundation for architecture design, computing power scheduling, and energy efficiency optimization (including frequency and voltage control, power capping, and task orchestration).

[0030] Related technologies build power consumption models around general-purpose CPU and GPU architectures, enabling layered modeling capabilities for arrays, interconnects, logic, and clocks. However, they lack modeling of NPU architectures, and do not adequately cover the coordination, hierarchical local buffering, and cross-layer direct transport of the three types of specialized resources in NPU architectures, including matrix arrays / vector arrays / scalar units. This makes it difficult to fully map operators and data flows into energy consumption, and also lacks modeling of the energy consumption of multi-die interconnects within the package and on-chip high-bandwidth caches.

[0031] Based on this, embodiments of this application provide a power consumption calculation method, apparatus, device, and storage medium for an NPU architecture. By decomposing the power consumption of each functional unit as a target unit, the granularity of modeling is improved, enabling accurate capture of the power consumption characteristics differences of different units. For each target unit, the module power is calculated progressively based on unit operating power consumption, unit dynamic power, and unit static power, achieving power consumption quantification. This avoids the one-sidedness of only considering dynamic or static power consumption, ensuring that the power consumption calculation results of each functional unit closely match its actual working state. In addition, considering that the power consumption of inter-chip communication in a multi-die architecture increases significantly with the increase of data interaction frequency, ignoring this part of the power consumption would lead to significant deviations in the modeling results. Therefore, the interconnect power between pairs of dies is also modeled. Finally, the total power consumption of the target device is obtained by summing all die power and the interconnect power between dies, which includes both the power consumption of each functional unit within the die and the interaction power consumption between dies, constructing a full-dimensional, high-precision NPU architecture power consumption model, significantly improving the accuracy of power consumption modeling.

[0032] This application provides a power consumption calculation method, apparatus, device, and storage medium for an NPU architecture, which are specifically described through the following embodiments. First, the power consumption calculation method for the NPU architecture in this application embodiment is described.

[0033] The power consumption calculation method for the NPU architecture provided in this application relates to the field of power consumption calculation technology for intelligent computing platforms. This method can be applied to terminals, servers, or computer programs running on either terminal or server. For example, the computer program can be a native program or software module in an operating system; it can be a native application (APP), i.e., a program that needs to be installed in the operating system to run, such as a client supporting power consumption calculation for the NPU architecture, i.e., a program that only needs to be downloaded to a browser environment to run; or it can be a small program that can be embedded into any APP. In short, the above-mentioned computer program can be any form of application, module, or plugin. The terminal communicates with the server via a network. This power consumption calculation method for the NPU architecture can be executed by the terminal or server, or by the terminal and server working together.

[0034] In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, or smartwatch, etc. Additionally, the terminal can also be a smart in-vehicle device. This smart in-vehicle device uses the power consumption calculation method of the NPU architecture of this embodiment to provide related services and improve the driving experience. The server can be a standalone server, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms; it can also be a service node in a blockchain system, where the service nodes in the blockchain system form a peer-to-peer (P2P) network. The P2P protocol is an application layer protocol running on top of the Transmission Control Protocol (TCP). The terminal and the server can be connected via Bluetooth, Universal Serial Bus (USB), or network communication methods; this embodiment does not impose any limitations.

[0035] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0036] The following describes the power consumption calculation method of the NPU architecture in the embodiments of this application.

[0037] First, the NPU architecture of the target device is described. The target device's NPU architecture employs a dual-die packaging design, with the two dies interconnected via an on-chip high-bandwidth link to form a collaborative computing unit. Each die, as the core computing carrier, contains at least five core functional units: matrix unit, vector unit, scalar unit, on-chip storage, and on-chip network. Simultaneously, the NPU architecture also integrates a storage array with at least one storage layer.

[0038] Specifically, each bare die contains approximately 24 matrix units (Cubes) and 48 vector units (Vectors), supporting multiple precision calculations including FP16, BF16, and INT8. Matrix units primarily handle large-scale matrix operations and tensor multiplication, while vector units possess efficient vector operation capabilities, handling vector-based computation tasks with high data parallelism. This complements the computational scenario coverage of the matrix units, flexibly adapting to AI computational tasks with varying precision requirements. Furthermore, scalar units serve as auxiliary computation modules, working in conjunction with the matrix and vector units to handle lightweight computation and control instruction execution, ensuring smooth computation flow.

[0039] In one embodiment, the on-chip storage of the bare die adopts a multi-level architecture, including three core storage layers: Global Storage (GM), L1 cache, and L0 cache, forming a complete storage array. The L0 cache is further subdivided into three sub-modules: L0A, L0B, and L0C, each oriented towards the three operands of the matrix unit, enabling high-speed access to computational data from the nearest location. The L1 cache includes a Unified Buffer and an array-oriented L1 buffer, serving as an intermediate cache layer between the L0 cache and the Global Storage. The Global Storage (GM) is the core layer of the storage array, encapsulating and integrating 128GB of HBM on-chip storage with a total bandwidth of approximately 3.2TB / s, providing large-capacity, high-bandwidth storage support.

[0040] In one embodiment, direct cross-layer access paths (such as GM->L0A / B) are supported between storage layers, and there is asymmetric bandwidth (the transmission bandwidth of L1->L0A is higher than that of L1->L0B). Data transfer is scheduled by multiple memory transfer engine (MTE) units. Data within the queue adopts a serial transmission mode, while parallel transfer can be achieved across MTE units, effectively improving data transmission efficiency.

[0041] In one embodiment, each bare die has two types of external network interfaces, which constitute the core extension links of the on-chip network: one is the scale-up UB plane, which is composed of several 224Gbps transceivers and is used for high-speed communication between the bare die and upper-layer devices or control units; the other is the scale-out RDMA plane, which has a transmission rate of up to 200Gbps and supports distributed interconnection between multiple NPU devices to meet the needs of large-scale cluster deployment.

[0042] In one embodiment, the two bare dies achieve internal interconnection through an on-chip high-bandwidth network. Combined with the aforementioned external expansion interface, they form an internally collaborative and externally scalable network architecture, which fully guarantees the communication needs of multi-bare-die collaborative computing and clustered deployment.

[0043] The following describes the power consumption calculation method for the NPU architecture in conjunction with the NPU architecture of the target device.

[0044] In one embodiment, Figure 1 This is an optional flowchart of the power consumption calculation method for the NPU architecture provided in the embodiments of this application. Figure 1 The method may include, but is not limited to, steps 110 to 130. It is also understood that this embodiment... Figure 1 The order of steps 110 to 130 is not specifically limited. The order of steps can be adjusted or some steps can be reduced or added according to actual needs.

[0045] Step 110: For each bare crystal, select matrix units, vector units, and scalar units as target units one by one.

[0046] In one embodiment, the power consumption of each bare die needs to be calculated individually. In order to perform fine modeling, matrix units, vector units, scalar units, on-chip memory and on-chip network are selected as target units one by one.

[0047] Step 120: Obtain the unit operation power consumption of the target unit, calculate the unit dynamic power based on the unit operation power consumption, obtain the unit static power of the target unit, obtain the module power of the target unit based on the unit dynamic power and unit static power, calculate the storage power of the on-chip memory, and calculate the network power of the on-chip network.

[0048] In one embodiment, taking the target unit as the matrix unit as an example, in the NPU architecture, the computation subsystem implements matrix (Cube), vector, and scalar computations based on the multiply-accumulate (MAC) unit. The energy consumption per unit operation is... The definition is the energy consumption of the multiply-accumulate unit (MAC) performing a single multiply-accumulate operation, and its calculation formula is:

[0049] Among them, the multiplier capacitor Adder capacitor Register capacitor Theoretically, it can be extracted from the chip gate-level netlist and layout parasitics; A data-related flip factor; The short-circuit energy consumption is approximately linearly related to V.

[0050] However, in practical applications, since layout information is not easily obtained, the following method can be used to obtain the unit operation energy consumption of matrix cells. . Reference Figure 2 , Figure 2 This is a flowchart of obtaining the unit operating energy consumption of the target unit according to an embodiment of this application, which specifically includes the following steps: Step 210: Obtain the idle power of the target unit in the idle state, run the target unit in saturation for a preset time, obtain the corresponding saturation power and number of operations, and calculate the incremental power based on the saturation power and idle power.

[0051] In one embodiment, when the target unit is a matrix unit, when measuring energy consumption, the operating voltage and frequency (V,f) parameters of the target unit are first set, and the calculation accuracy p is specified. The accuracy can be selected from BF16, FP16, INT8, etc. Then, it is ensured that the voltage, frequency and calculation accuracy remain stable during the test to avoid parameter fluctuations affecting the measurement results.

[0052] Then, the target unit is controlled to be in an idle state with no tasks running, and the operating power of the target unit at this time is recorded and determined as the idle power corresponding to the target unit. Next, a micro-benchmark test matching the function of the target unit is selected, such as the MatMul matrix multiplication operation micro-benchmark test corresponding to the matrix unit. This micro-benchmark test is run on the target unit for a preset duration T. Saturation run means that the target unit continuously operates at full load. During the run, two data points are recorded simultaneously: one is the real-time operating power of the target unit, i.e., the saturation power, and the other is the number of corresponding operations completed by the target unit within the preset duration, such as the number of MAC operations of the matrix unit. These are recorded as follows: .

[0053] Then, based on the difference between the saturated power and the idle power, the incremental power of the target unit under saturated operating conditions is obtained. This incremental power reflects the additional power consumption of the target unit when it is operating at full load, relative to its idle state.

[0054] Step 220: Obtain the unit number of operations based on the quotient of the number of operations and the preset duration, and obtain the unit operating energy consumption based on the quotient of the incremental power and the unit number of operations.

[0055] In one embodiment, based on the previously obtained number of operations... Calculate the unit time operation rate of the target unit against a preset duration T. This refers to the number of operations performed per unit. Unit operation energy consumption is the energy consumed by the target unit to complete a single operation. Therefore, the unit operation energy consumption derived from incremental power and unit-time operation rate is expressed as:

[0056] in, This represents the incremental energy of the matrix array relative to its idle state within a preset time period. This represents the unit operating energy consumption of the target unit under a set voltage frequency (V,f) and calculation accuracy p.

[0057] Next, refer to Figure 3 , Figure 3 This is a flowchart of calculating the unit dynamic power based on the unit operating energy consumption provided in this application embodiment, specifically including the following steps: Step 310: Obtain the percentage of effective computational state cycles and the percentage of clock-on time within the preset duration.

[0058] In one embodiment, the effective computational state period ratio Defined as the ratio of the number of cycles in which the target unit is in an effective computing state to the number of clock-on cycles within a preset observation window, this reflects the actual computing activity level of the target unit during the clock-on period. The clock-on time percentage... Defined as the number of clock cycles of the target unit within the preset observation window. Total number of wall clock cycles The ratio or equivalent switching probability reflects the impact of the clock gating mechanism on the operation of the target unit.

[0059] Specifically, during the execution of the task by the target unit, the number of valid computational state cycles is obtained by querying the NPU's program counter. Clock start cycle count Total number of wall clock cycles Then calculate:

[0060]

[0061] It is evident that the proportion of effective computational state cycles and the proportion of clock-on time are strongly correlated with the specific task load. Real-time acquisition via the program counter can ensure the accuracy and timeliness of the data.

[0062] Step 320: Obtain the precision operation energy consumption based on the unit operation energy consumption corresponding to each calculation precision.

[0063] In one embodiment, when the target unit performs a task, it may support multiple computational precisions p, and complete the amount of computation corresponding to different precisions within a preset observation window. Therefore, for each computational precision p, the unit operation energy consumption under that precision, the number of operations corresponding to that precision within the preset observation window and the window duration are obtained according to the above process, and the corresponding energy consumption contribution is calculated.

[0064] The energy consumption contribution corresponding to all calculation accuracies is summed to obtain the accuracy operation energy consumption of the target unit. The calculation formula is as follows:

[0065] Step 330: Obtain the unit dynamic power by multiplying the effective computational state cycle ratio, the clock on time ratio, and the precision operation energy consumption.

[0066] In one embodiment, the dynamic power of the target unit is obtained by combining the constraints of the effective computational state period ratio, the clock on-time ratio, and the energy consumption contribution of precision operation, and is expressed as:

[0067] Among them, the effective computation state cycle ratio corrects the invalid computation loss during the clock-on period, and the clock-on time ratio corrects the energy savings caused by clock gating. The two are multiplied by the energy consumption of precision operation, which can accurately quantify the dynamic power consumption of the target unit under actual task load.

[0068] Next, the static power of the target cell is obtained. For the target cell, its static power can be regarded as the basic power consumption when the target cell is powered on but has no actual load. Therefore, the static power can be regarded as the leakage power of the target cell. Dominated by circuit leakage current, it is represented as:

[0069]

[0070] in, Indicates the operating voltage of the target unit. Represents the circuit equivalent area of ​​the target cell. The formula represents the equivalent leakage current density of the target cell, where f is the clock frequency. The parameters can be obtained by fitting the measured leakage current values ​​at different temperatures T. From a theoretical modeling perspective, it is necessary to obtain chip design layout information such as the equivalent area of ​​the circuit. However, in practical applications, layout information is usually difficult to obtain. Therefore, the static power of the cell can also be determined by actual measurement.

[0071] Specifically, the NPU chip housing the target unit is kept powered on to ensure normal driver loading and stable device temperature and fan speed. Simultaneously, no actual computational load is assigned to the target unit, placing it in an idle state—maintaining only basic power without any effective computation. Under idle conditions, the real-time operating power of the target unit is measured using a power monitoring tool. This power value is the target unit's static power, equivalent to the leakage power in the theoretical model, directly reflecting the target unit's basic leakage current power consumption under no-load conditions.

[0072] Therefore, for a matrix element as the target element, the module power of the target element can be obtained from the element's dynamic power and static power, expressed as:

[0073] Following the same method, the module power is calculated when vector and scalar units are used as target units. Similar to matrix units, the module power of vector units is expressed as:

[0074] The module power of the scalar unit is expressed as:

[0075] Since on-chip memory also exists within the bare die, the power consumption related to memory also needs to be calculated. On-chip memory includes at least one memory layer, see reference... Figure 4 , Figure 4 This is a flowchart illustrating the calculation of on-chip storage power according to an embodiment of this application, specifically including the following steps: Step 410: Select storage layers one by one as target layers, keep the fixed working set residing in the target layer, keep all target cells idle, obtain the idle power corresponding to the target layer, and perform read, write, and cross-layer read and write operations on the fixed working set in the target layer to obtain the read power, write power, and read and write power respectively.

[0076] In one embodiment, each storage layer in the on-chip memory is selected as the target layer, including layers such as L0, L1, global storage (GM), and UnifiedBuffer. Theoretically, the read / write power consumption of a storage layer can be estimated using an analytical model based on bit line and word line capacitance. For example, the power of a single read operation can be expressed as:

[0077] The power of a single write operation can be expressed as:

[0078] Where V is the operating voltage. This represents the total bit line capacitance, which is proportional to the row depth of the memory array. This is the total capacitance of the word lines, which is proportional to the row width of the memory array. This is a correction factor for the incomplete swing of the bit line voltage during read operations. To ensure the fixed power consumption of the readout amplifier, For write operation bit line correction coefficients, The write driver has a fixed power consumption. However, in practical applications, due to the difficulty in obtaining layout process information (such as capacitors, circuit area, etc.), the following experimental testing method is used to collect power data.

[0079] In one embodiment, a fixed-size working set is prepared and resided in the current target layer to ensure that the working set does not migrate across layers. Simultaneously, all target units, such as matrix units and vector units, are controlled to remain in an idle state, i.e., only maintaining basic operation and not performing effective computations, to avoid interference from the power consumption of the computing units on the power measurement of the storage layer.

[0080] First, with the target layer only residing in a fixed working set and without any read / write operations, the operating power of the target layer is measured and determined as the idle power of the target layer. This power reflects the basic power consumption of the target layer when there is no read / write activity, and can also be regarded as leakage power.

[0081] Then, power acquisition is performed for different operating scenarios. (The sentence is incomplete and requires more context.) For example, in a layer test, a pure read operation is performed on a fixed working set in the target layer while maintaining saturated bandwidth. The total power of the target layer at this time is recorded as the read power. The write operation test involves performing pure write operations on a fixed working set at the target layer while maintaining saturated bandwidth. The total power of the target layer at this time is recorded as the write power. Cross-layer read / write operation testing is conducted at the target layer. Other storage layers Cross-layer read / write operations are performed, such as cross-layer paths like GM→L0A and L1→L0B, while maintaining saturated bandwidth. The total power of the target layer at this time is recorded as the read / write power. It is important to note that due to the asymmetry of bandwidth in the storage layer, such as the transmission bandwidth of L1→L0A being higher than that of L1→L0B, tests need to be performed separately for different cross-layer paths, and the read and write power of the corresponding paths needs to be collected.

[0082] Step 420: Based on idle power, read power, write power, and read-write power, obtain read increment power, write increment power, and read-write increment power; obtain the byte rate corresponding to the target layer; obtain the storage layer read parameters based on the quotient of read increment power and byte rate; obtain the storage layer write parameters based on the quotient of write increment power and byte rate; and obtain the storage layer read-write parameters based on the quotient of read-write increment power and byte rate.

[0083] In one embodiment, the incremental power is the difference between the total power and the idle power under different operating scenarios, reflecting the additional energy consumption corresponding to the operation. Therefore, the read incremental power is obtained based on the idle power, read power, write power, and read / write power. Write incremental power and read / write incremental power .

[0084] Meanwhile, in the saturation bandwidth test, the total number of bytes transmitted (B) and the window duration (T) within the preset observation window are recorded, and the byte rate corresponding to the target layer is calculated. This represents the number of bytes transferred per unit time. Next, the storage layer read parameters are obtained based on the quotient of the read increment power and the byte rate. The storage layer write parameters are obtained by quotienting the write increment power and the byte rate. The storage layer read / write parameters are obtained by quotient of read / write incremental power and byte rate. , is represented as:

[0085] Step 430: Obtain the storage power based on the storage layer read parameters, storage layer write parameters, and storage layer read / write parameters.

[0086] In one embodiment, storage power The storage power consists of four parts: intra-layer read power consumption, intra-layer write power consumption, cross-layer read / write power consumption, and static power of each storage layer. Therefore, the specific process of obtaining the storage power based on the storage layer read parameters, storage layer write parameters, and storage layer read / write parameters is as follows: For each target layer, obtain the target layer parameters based on the storage layer read parameters and storage layer write parameters, obtain the static power of the target layer, accumulate all target layer parameters to obtain the first parameter, accumulate all static power to obtain the second parameter, select cross-layers in pairs, accumulate the corresponding storage layer read / write parameters to obtain the third parameter, and calculate the sum of the first parameter, the second parameter, and the third parameter to obtain the storage power.

[0087] The calculation formula can be expressed as:

[0088] in, Represents the target layer Target layer parameters, Represents the target layer The static power. The first term in the formula is the first parameter, representing the sum of intra-layer read / write power across all memory layers. For the target layer The actual number of bytes read. For the target layer The actual number of bytes written. , These are the actual byte rates for intra-layer reads and writes, respectively. The second item is the third parameter, representing the sum of read and write power for all cross-layer paths. cross-layer path The actual number of bytes transmitted. This represents the actual byte rate of the path. The third item is the second parameter, which represents the sum of the static power of all storage layers, that is, the sum of the leakage power of each storage layer in the no-load state. In practical applications, this can be obtained through actual measurement.

[0089] In one embodiment, if there is also a packaged stacked memory (HBM) in the bare die, its corresponding packaged memory power It is also calculated in the same way as above, and expressed as:

[0090] The last two items are static power and leakage power, which are measured by keeping HBM enabled but under no-load conditions. and Obtained from external memory read / write micro-benchmark tests, i.e., recording incremental power. With stable byte rate Where B is the number of bytes in the window and T is the duration, we get = .

[0091] Next, for on-chip networks, refer to Figure 5 , Figure 5 This is a flowchart of calculating the network power of an on-chip network provided in an embodiment of this application, specifically including the following steps: Step 510: For each on-chip route of the bare die, obtain the buffer parameters based on the obtained buffer event power and buffer trigger rate, obtain the arbitration parameters based on the obtained arbitration event power and arbitration trigger rate, obtain the cross switch parameters based on the obtained cross switch event power and cross trigger rate, and accumulate the buffer parameters, arbitration parameters and cross switch parameters to obtain the routing parameters.

[0092] In one embodiment, for each on-chip route on the bare die, routing parameters are obtained by accumulating event power consumption parameters. For each on-chip route r, three types of events and related parameters are defined: buffer events, arbitration time, and cross-connect switching events. The parameters of the buffer events include the number of buffer triggers. Buffer trigger rate and buffer event power The parameters for arbitration events include the number of arbitration events. Arbitration trigger rate and arbitration event power The parameters of the cross switch event include the number of cross switch crossings. Cross trigger rate and cross switch event power These rates are the ratios of the number of corresponding events to the observation duration, i.e. , , .

[0093] In one embodiment, the event power can be estimated by an analytical model. However, in practical applications, since layout information such as circuit capacitance and size is difficult to obtain, micro-benchmark calibration can be used: by constructing a pure event-triggered micro-benchmark, the route generates only a single type of event, such as only buffered events, and the event triggering rate and the corresponding event power are recorded.

[0094] Next, buffer parameters are obtained based on the acquired buffer event power and buffer trigger rate; arbitration parameters are obtained based on the acquired arbitration event power and arbitration trigger rate; and cross switch parameters are obtained based on the acquired cross switch event power and cross switch trigger rate. The routing parameters are obtained by summing the buffer parameters, arbitration parameters, and cross switch parameters, as follows:

[0095] Step 520: For each on-chip link of the bare die, obtain the power consumption per bit of transmission.

[0096] In one embodiment, the power consumption per bit of transmission is collected for each on-chip link of the bare die, wherein the power consumption per bit of transmission is... This refers to the energy consumption of transmitting 1 bit of data via an on-chip link. Theoretically, its analytical model can be expressed as:

[0097] Where V is the operating voltage. Capacitance per unit length of wire This is the total length of the link. For a single repeater switched capacitor, For the number of repeaters, This model represents the fixed energy consumption for serialization / deserialization operations. It decomposes link energy consumption into: conductor distributed capacitance energy consumption, repeater capacitance energy consumption, and serial-to-parallel conversion energy consumption.

[0098] Since parameters such as capacitance and link length in the theoretical model depend on layout information, they are obtained through actual testing in practical applications: an end-to-end ping-pong test is constructed on the target chip link to saturate the link for data transmission. The incremental power, total number of transmitted bits, and test duration are recorded during the test, and the byte rate is calculated to obtain the energy consumption per bit. Understandably, this method allows for the acquisition of these parameters. , , .

[0099] Step 530: Obtain on-chip routing parameters based on all routing parameters, obtain on-chip link parameters based on all unit bit transmission power consumption, obtain on-chip idle power, and obtain the network power of the bare crystal based on the on-chip routing parameters, on-chip link parameters, and on-chip idle power.

[0100] In one embodiment, the on-chip routing parameters corresponding to all on-chip routes are summed to obtain the on-chip routing parameters of all bare crystal routes per unit time. The calculation formula is as follows:

[0101] Where R is the set of all on-chip routes of the bare die.

[0102] Next, the product of the unit bit transmission power consumption and the actual bit rate of each of the on-chip links is accumulated to obtain the on-chip link parameters per unit time for all links on the bare die. The calculation formula is as follows:

[0103] in, This is the set of all on-chip links on a bare die. This represents the actual number of bits transmitted in the link. This represents the actual bit rate of the link. Simultaneously, the on-chip idle power is obtained, which is the basic static power of the on-chip network in a state of no data transmission and no event triggering. In practical applications, the power can be obtained by keeping the on-chip network powered on but without any data transmission or event triggering. Theoretically, leakage current power consumption should be calculated using layout information, but since layout information is difficult to obtain, the measured value is used.

[0104] Therefore, the network power of bare die The sum of total routing energy consumption, total link energy consumption, and static power is calculated using the following formula:

[0105] Step 130: For each bare die, obtain the bare die power based on the corresponding module power, storage power and network power, obtain the interconnect power between any two bare dies, and at least obtain the total power consumption of the target device based on the bare die power and interconnect power.

[0106] In one embodiment, a bare die includes matrix units, vector units, scalar units, on-chip memory, and on-chip network. The bare die power can be obtained based on the corresponding module power, memory power, and network power, expressed as:

[0107] Furthermore, for bare crystals, the power can be further decomposed into the dynamic power of each component according to the functional unit m in the bare crystal. and static power , is represented as:

[0108] In one embodiment, since data interaction may also occur between bare dies, it is also necessary to roughly calculate the power consumption related to the interaction. (Refer to...) Figure 6 , Figure 6 This is a flowchart of obtaining the interconnect power between two bare dies according to an embodiment of this application, specifically including the following steps: Step 610: For the interconnected bare crystals, obtain the interconnect idle power, select one of the bare crystals, and obtain the corresponding unit bit transmission power consumption, data transmission rate, unit bit reception power consumption, and data reception rate.

[0109] In one embodiment, the power associated with the cross-die interconnect consists of transmission power consumption, reception power consumption, clock-related power consumption, and static power, wherein clock-related power consumption and static power can be calibrated by idle power, and transmission and reception power consumption can be calculated based on power consumption per bit and data rate.

[0110] First, the bare dies of each interconnect are controlled to be in an idle state with no data transmission or reception, while only the interconnect links are powered on. The total power of the interconnect links at this time is measured and determined as the interconnect idle power. This idle power includes clock data recovery power. Clock-locked power and PHY layer drain power These powers can be measured uniformly without the need for separate calculations.

[0111] Next, one of the interconnected bare dies is selected as the target bare die, and the energy consumption per bit transmission, data transmission rate, energy consumption per bit reception, and data reception rate are collected. Among these, the energy consumption per bit transmission... The energy consumption per bit of data when transmitting data from the target die to the interconnected die is calibrated through micro-benchmark tests of end-to-end data transmission. The data transmission rate represents the average transmission rate of the target die within a preset observation window, i.e., the total number of bits transmitted. The ratio to the window duration T. Energy consumption per unit bit received. This represents the energy consumption per bit of data when the target die receives data from the interconnected die, calibrated using micro-benchmark testing. The data reception rate represents the average reception rate of the target die within a preset observation window, i.e., the total number of bits received. The ratio to the window duration T.

[0112] Step 620: Obtain the interconnection transmission parameters based on the product of the unit bit transmission energy consumption and the data transmission rate, and obtain the interconnection reception parameters based on the product of the unit bit reception energy consumption and the data reception rate.

[0113] In one embodiment, the interconnect transmission parameter is the dynamic power consumption for transmitting data to the target bare die, which is equal to the product of the power consumption per unit bit transmission and the data transmission rate, reflecting the real-time power consumption during the transmission process. The calculation formula is as follows:

[0114] The interconnect receiving parameter is the dynamic power consumption of the target bare die for receiving data. It is equal to the product of the energy consumption per unit bit of reception and the data reception rate, reflecting the real-time energy consumption during the reception process. The calculation formula is:

[0115] Step 630: Obtain the interconnect power based on the interconnect transmission parameters, interconnect reception parameters, and interconnect idle power.

[0116] In one embodiment, the interconnect power is obtained based on interconnect transmission parameters, interconnect reception parameters, and interconnect idle power. , is represented as:

[0117] In one embodiment, the power of both the UB network plane and the RDMA network plane for NPU communication is expressed as "power consumption per bit × data rate + leakage power," taking into account idle hold power consumption. The statistics are derived from the link busy / idle cycle and the total number of bytes, and the corresponding calculation formula is as follows:

[0118] Different planes have different transmission / reception power consumption per unit bit due to differences in rate / encoding. , and , Therefore, it is obtained by running different micro-benchmark tests. The specific method is the same as the above measurement method, and will not be repeated here.

[0119] In one embodiment, the total power consumption of the target device is obtained based at least on the die power and interconnect power. Assuming there are two dies, die0 and die1, the total power consumption is... Represented as:

[0120] In one embodiment, considering the equipment manufacturing process, the total power consumption result can be further optimized. Specifically, if the manufacturing processes of the modeling and measurement equipment and the target equipment are different, the total power consumption needs to be corrected by scaling the circuit parameters to ensure the accuracy of power consumption prediction. The modeling circuit parameters of the modeling and measurement equipment and the target circuit parameters of the target equipment are obtained. The energy consumption scaling factor is calculated based on the modeling circuit parameters and the target circuit parameters. The total power consumption is then scaled based on the energy consumption scaling factor.

[0121] Specifically, if the modeling and measurement equipment and the target equipment are manufactured using the same process, there is no need to perform power scaling; the original calculated total power consumption can be used directly. If the two have different processes, such as the modeling and measurement equipment using a 28nm process and the target equipment using a 7nm process, then it is necessary to adjust the unit operating power consumption through circuit parameter scaling to correct the total power consumption and avoid power prediction deviations caused by process differences.

[0122] At this point, the feature length of the modeling and measurement equipment is obtained. Gate circuit capacitors Interconnect capacitors Operating voltage Operating frequency The above parameters together constitute the modeling circuit parameter set. Simultaneously, the feature length of the target device is obtained. Gate circuit capacitors Interconnect capacitors Operating voltage Operating frequency The above parameters together constitute the target circuit parameter set. Next, the feature length scaling factor is calculated. And calculate the gate circuit capacitor scaling factor. Interconnect capacitance scaling factor Because the height of interconnects cannot be reduced proportionally to avoid a sharp increase in resistance, their scaling behavior differs from that of gate circuits and requires separate calculation. This also includes calculating the voltage scaling factor. Frequency scaling factor It is used to correct the effects of voltage and frequency on energy consumption.

[0123] The total energy consumption per unit operation consists of two parts: gate dynamic energy and interconnect dynamic energy. Therefore, the energy scaling factor is derived based on the scaling law of these two energy parts and is expressed as:

[0124] in, The energy consumption scaling factor for the target device. To model and measure the gate dynamic energy of the measuring equipment, To model the dynamic energy of the interconnects of the measurement equipment, the equivalent unit operating energy consumption of the target equipment is obtained by correcting the energy consumption of the gate circuits and interconnects respectively.

[0125] When corrections are needed, based on the energy consumption scaling factor derived above, all previously calculated unit operation energy consumption, such as the unit operation energy consumption of computing units and the unit bit transmission energy consumption of on-chip networks, are uniformly scaled. Then, the power of each module is recalculated based on the scaled unit operation energy consumption and unit bit transmission energy consumption. Finally, the total power consumption of the target device is corrected to ensure that the total power consumption is accurately matched with the process characteristics of the target device.

[0126] As can be seen, the power consumption calculation method for the NPU architecture provided in this application starts from the circuit-level power consumption mechanism, constructs a sub-modular power consumption calculation model oriented towards operators and data flows, and clarifies the input statistics and parameter calibration process. To adapt to different process technology conditions, scalable technical parameters are also provided, and its hierarchical calculation logic follows the general CMOS circuit power consumption and hierarchical modeling principles. A unified power consumption calculation framework based on unit operation energy consumption multiplied by event rate is proposed. The power consumption of NPU's matrix units, vector units, scalar units, and other computing units, L0, L1, UnifiedBuffer, GM, and other on-chip storage units, as well as on-chip networks (NoC), cross-die interconnects, and external I / O interconnect units, is uniformly calculated by explicitly modulating the active duty cycle and clock gating factor, and summing them within the same family of formulas. Furthermore, a mapping relationship between power and area, temperature, and voltage is established, and a parameterized power consumption scaling formula adapted to a specified process is given, realizing hierarchical convergence calculation from sub-module power (module power, storage power, network power, interconnect power, etc.) to the total NPU power consumption. The calibration process for power consumption parameters is clearly defined. The unit energy consumption constant (such as unit operation energy consumption, storage layer read / write / cross-layer read / write parameters, unit bit transmission energy consumption, etc.) is derived by using micro-benchmark tests and board-level power and link / operator count data to provide data support for the accurate power consumption calculation of the model.

[0127] It can be applied to scenarios involving trade-offs in chip front-end architecture, such as area / power consumption quota planning for matrix units, vector units, scalar units, and various storage layers (including L0, L1, UnifiedBuffer, GM); compilation and deployment optimization: operator segmentation, parallelism adjustment of operator-on-chip storage-data transfer; system-side energy efficiency strategy formulation: frequency-voltage coordinated control, computational precision / quantization selection, job orchestration, and power capping configuration, etc. It decomposes end-to-end window power consumption into fine-grained components such as computation, storage, data transfer, on-chip network, interconnect, I / O, and clock, supporting quantitative evaluation of operator optimization and system-level energy-saving strategies. It can also collaboratively explore the optimal energy efficiency with timing / area constraints, accurately outputting the total power consumption of the target device.

[0128] The technical solution provided in this application, for each bare die, selects matrix units, vector units, and scalar units as target units one by one; obtains the unit operation power consumption of the target unit, calculates the unit dynamic power based on the unit operation power consumption, obtains the unit static power of the target unit, obtains the module power of the target unit based on the unit dynamic power and unit static power, calculates the on-chip storage power, and calculates the on-chip network power; for each bare die, obtains the bare die power based on the corresponding module power, storage power, and network power, obtains the interconnect power between any two bare dies, and obtains at least the total power consumption of the target device based on the bare die power and interconnect power. This application embodiment decomposes the power consumption of each functional unit one by one, improving the granularity of modeling and accurately capturing the differences in power consumption characteristics of different units. For each target unit, based on the unit operation power consumption, unit dynamic power, and unit static power, the module power is obtained through progressive calculation, realizing power consumption quantification, avoiding the one-sidedness of only considering dynamic power consumption or static power consumption, and ensuring that the power consumption calculation results of each functional unit closely match its actual working state. Furthermore, considering that the power consumption of inter-chip communication in a multi-die architecture increases significantly with the data interaction frequency, ignoring this power consumption would lead to significant deviations in the modeling results. Therefore, the interconnect power between each pair of dies is also modeled. Finally, the total power consumption of the target device is obtained by summing all die power and the interconnect power between dies. This includes the power consumption of each functional unit within the die, as well as the power consumption of interactions between dies, thus constructing a comprehensive and high-precision NPU architecture power consumption model, significantly improving the accuracy of power consumption modeling.

[0129] This application also provides a power consumption calculation device based on an NPU architecture, which can implement the power consumption calculation method of the above-described NPU architecture, referring to... Figure 7 The device includes: Target cell selection module 710: Used to select matrix cells, vector cells, and scalar cells as target cells for each bare die.

[0130] Bare die power calculation module 720: Used to obtain the unit operating power consumption of the target cell, calculate the cell dynamic power based on the unit operating power consumption, obtain the unit static power of the target cell, obtain the module power of the target cell based on the unit dynamic power and unit static power, calculate the storage power of on-chip memory, and calculate the network power of on-chip network.

[0131] Total power consumption calculation module 730: For each bare die, it is used to obtain the bare die power based on the corresponding module power, storage power and network power, obtain the interconnect power between pairs of bare dies, and at least obtain the total power consumption of the target device based on the bare die power and interconnect power.

[0132] The specific implementation of the power consumption calculation device of the NPU architecture in this embodiment is basically the same as the specific implementation of the power consumption calculation method of the NPU architecture described above, and will not be repeated here.

[0133] This application also provides an electronic device, including: At least one memory; At least one processor; At least one program; The program is stored in memory, and the processor executes the at least one program to implement the power consumption calculation method of the NPU architecture described above in this application. The electronic device can be any smart terminal, including mobile phones, tablets, personal digital assistants (PDAs), and in-vehicle computers.

[0134] Please see Figure 8 , Figure 8 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 801 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 802 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 802 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 802 and is called and executed by the processor 801 to execute the power consumption calculation method of the NPU architecture of this application embodiment. The 803 input / output interface is used to implement information input and output. The communication interface 804 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 805 transmits information between various components of the device (e.g., processor 801, memory 802, input / output interface 803, and communication interface 804); The processor 801, memory 802, input / output interface 803, and communication interface 804 are connected to each other within the device via bus 805.

[0135] This application embodiment also provides a storage medium that stores a computer program. When the computer program is executed by a processor, it implements the power consumption calculation method of the above-described NPU architecture.

[0136] Memory, as a non-transitory storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0137] The power consumption calculation method, apparatus, device, and storage medium of the NPU architecture proposed in this application, for each bare die, selects matrix units, vector units, and scalar units as target units one by one; obtains the unit operation power consumption of the target unit, calculates the unit dynamic power based on the unit operation power consumption, obtains the unit static power of the target unit, obtains the module power of the target unit based on the unit dynamic power and unit static power, calculates the on-chip storage power, and calculates the on-chip network power; for each bare die, obtains the bare die power based on the corresponding module power, storage power, and network power, obtains the interconnect power between any two bare dies, and obtains at least the total power consumption of the target device based on the bare die power and interconnect power. This application embodiment decomposes the power consumption of each functional unit one by one, improving the granularity of modeling and accurately capturing the differences in power consumption characteristics of different units. For each target unit, based on the unit operation power consumption, unit dynamic power, and unit static power, the module power is obtained through progressive calculation, realizing power consumption quantification, avoiding the one-sidedness of only considering dynamic power consumption or static power consumption, and ensuring that the power consumption calculation results of each functional unit closely match its actual working state. Furthermore, considering that the power consumption of inter-chip communication in a multi-die architecture increases significantly with the data interaction frequency, ignoring this power consumption would lead to significant deviations in the modeling results. Therefore, the interconnect power between each pair of dies is also modeled. Finally, the total power consumption of the target device is obtained by summing all die power and the interconnect power between dies. This includes the power consumption of each functional unit within the die, as well as the power consumption of interactions between dies, thus constructing a comprehensive and high-precision NPU architecture power consumption model, significantly improving the accuracy of power consumption modeling.

[0138] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0139] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0140] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0141] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0142] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0143] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0144] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0145] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0146] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0147] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0148] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A power consumption calculation method for an NPU architecture, characterized in that, The target device's NPU architecture includes at least two bare dies, each bare die comprising at least: a matrix unit, a vector unit, a scalar unit, on-chip memory, and an on-chip network. The method includes: For each of the bare crystals, the matrix unit, the vector unit, and the scalar unit are selected one by one as the target unit; The unit operation power consumption of the target unit is obtained, the unit dynamic power is calculated based on the unit operation power consumption, the unit static power of the target unit is obtained, the module power of the target unit is obtained based on the unit dynamic power and the unit static power, the storage power of the on-chip storage is calculated, and the network power of the on-chip network is calculated. For each of the bare dies, the bare die power is obtained based on the corresponding module power, storage power, and network power. The interconnect power between any two bare dies is then obtained. The total power consumption of the target device is obtained based at least on the bare die power and the interconnect power.

2. The power consumption calculation method for the NPU architecture according to claim 1, characterized in that, The step of obtaining the unit operating energy consumption of the target unit includes: The idle power of the target unit in the idle state is obtained, the target unit is saturated for a preset time period, the corresponding saturation power and number of operations are obtained, and the incremental power is calculated based on the saturation power and the idle power. The unit number of operations is obtained by dividing the number of operations by the preset duration, and the unit operating energy consumption is obtained by dividing the incremental power by the unit number of operations.

3. The power consumption calculation method for the NPU architecture according to claim 2, characterized in that, The calculation of the unit dynamic power based on the unit operating energy consumption includes: Obtain the percentage of effective computation state cycles and the percentage of clock on time within the preset duration; The precision operation energy consumption is obtained based on the unit operation energy consumption corresponding to each calculation precision. The unit dynamic power is obtained by multiplying the effective computing state cycle ratio, the clock on time ratio, and the precision operation energy consumption.

4. The power consumption calculation method for the NPU architecture according to claim 1, characterized in that, The on-chip storage includes at least one storage layer, and calculating the storage power of the on-chip storage includes: Each storage layer is selected as a target layer, a fixed working set is placed in the target layer, all target cells are kept idle, the idle power corresponding to the target layer is obtained, and read, write, and cross-layer read and write operations are performed on the fixed working set in the target layer to obtain read power, write power and read and write power respectively. Based on the idle power, the read power, the write power, and the read-write power, the read increment power, the write increment power, and the read-write increment power are obtained. The byte rate corresponding to the target layer is obtained. The storage layer read parameters are obtained according to the quotient of the read increment power and the byte rate. The storage layer write parameters are obtained according to the quotient of the write increment power and the byte rate. The storage layer read-write parameters are obtained according to the quotient of the read-write increment power and the byte rate. The storage power is obtained based on the storage layer read parameters, the storage layer write parameters, and the storage layer read / write parameters.

5. The power consumption calculation method for the NPU architecture according to claim 4, characterized in that, The step of obtaining storage power based on the storage layer read parameters, the storage layer write parameters, and the storage layer read / write parameters includes: For each target layer, the target layer parameters are obtained based on the storage layer read parameters and the storage layer write parameters. The static power of the target layer is obtained. All the target layer parameters are summed to obtain the first parameter. All the static power is summed to obtain the second parameter. Select two cross-layers in pairs and sum the corresponding storage layer read / write parameters to obtain the third parameter; The storage power is obtained by summing the first parameter, the second parameter, and the third parameter.

6. The power consumption calculation method for the NPU architecture according to claim 4, characterized in that, The calculation of the network power of the on-chip network includes: For each on-chip route of the bare die, buffer parameters are obtained based on the acquired buffer event power and buffer trigger rate, arbitration parameters are obtained based on the acquired arbitration event power and arbitration trigger rate, and cross switch parameters are obtained based on the acquired cross switch event power and cross trigger rate. The buffer parameters, arbitration parameters, and cross switch parameters are summed to obtain the routing parameters. For each on-chip link of the bare die, obtain the power consumption per unit bit transmission; Based on all the routing parameters, on-chip routing parameters are obtained; on-chip link parameters are obtained based on all the unit bit transmission power consumption; on-chip idle power is obtained; and the network power of the bare crystal is obtained based on the on-chip routing parameters, the on-chip link parameters, and the on-chip idle power.

7. The power consumption calculation method for the NPU architecture according to claim 1, characterized in that, The acquisition of interconnect power between each pair of bare dies includes: For each pair of interconnected bare crystals, obtain the interconnect idle power, select one of the bare crystals, and obtain the corresponding unit bit transmission power consumption, data transmission rate, unit bit reception power consumption, and data reception rate. Interconnection transmission parameters are obtained by multiplying the unit bit transmission power consumption and the data transmission rate, and interconnection reception parameters are obtained by multiplying the unit bit reception power consumption and the data reception rate. The interconnect power is obtained based on the interconnect transmission parameters, the interconnect reception parameters, and the interconnect idle power.

8. The power consumption calculation method for the NPU architecture according to claim 1, characterized in that, The method further includes: If the manufacturing processes of the modeling and measurement equipment and the target equipment are different, obtain the modeling circuit parameters of the modeling and measurement equipment and the target circuit parameters of the target equipment; The energy consumption scaling factor is calculated based on the modeling circuit parameters and the target circuit parameters, and the total power consumption is scaled based on the energy consumption scaling factor.

9. A power-efficient computing device based on an NPU architecture, characterized in that, The target device's NPU architecture includes at least two bare dies, each bare die comprising at least: a matrix unit, a vector unit, a scalar unit, on-chip memory, and an on-chip network. The device includes: Target cell selection module: used to select the matrix cell, the vector cell, and the scalar cell as target cells for each bare die; Bare die power calculation module: used to obtain the unit operating power consumption of the target unit, calculate the unit dynamic power based on the unit operating power consumption, obtain the unit static power of the target unit, obtain the module power of the target unit based on the unit dynamic power and the unit static power, calculate the storage power of the on-chip memory, and calculate the network power of the on-chip network. Total power consumption calculation module: For each of the bare dies, the bare die power is obtained based on the corresponding module power, storage power and network power, the interconnect power between any two of the bare dies is obtained, and the total power consumption of the target device is obtained based at least on the bare die power and the interconnect power.

10. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the power consumption calculation method of the NPU architecture according to any one of claims 1 to 8.

11. A storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the power consumption calculation method of the NPU architecture according to any one of claims 1 to 8.

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