A semiconductor device, a method of operating a semiconductor device, a system, and an apparatus

Abstract

The present disclosure provides a semiconductor device, an operating method of the semiconductor device, a system and a device, which are applied to the technical field of semiconductor. The semiconductor device comprises a peripheral circuit and a memory cell array, and the peripheral circuit and the memory cell array are coupled. The memory cell array comprises a plurality of memory areas, and each memory area comprises a first number of memory blocks. The peripheral circuit is configured to receive an operation instruction. The operation instruction comprises address information, and the address information is used to determine a target memory area in the plurality of memory areas and a second number of working memory blocks in the target memory area. The second number is less than the first number. In response to the operation instruction, a corresponding operation is performed on the working memory blocks. Through the above implementation, the stability and reliability of the semiconductor device in performing various operations can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method of operating the semiconductor device, a system and an apparatus. Background Technology

[0002] Semiconductor devices, such as NAND flash memory, can perform various operations, such as reading, programming (writing), and erasing, thereby changing the threshold voltage of each memory cell to a desired level. For NAND semiconductor devices, erasing operations can be performed at the block level, programming operations at the page level, and reading operations at the page level. However, due to limitations in manufacturing processes and the number of erase / write cycles, it is difficult to guarantee the consistency of the memory block state. Faulty memory blocks can lead to instability in various operations, resulting in poor reliability of the semiconductor device. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor device, a method for operating the semiconductor device, a system, and an apparatus to improve the stability and reliability of the semiconductor device performing various operations.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] In a first aspect, embodiments of this disclosure provide a semiconductor device including peripheral circuitry and a memory cell array coupled together. The memory cell array includes multiple memory regions, each memory region including a first number of memory blocks. The peripheral circuitry is configured to receive an operation instruction. The operation instruction includes address information used to determine a target memory region among the multiple memory regions and a second number of working memory blocks within the target memory region. The second number is less than the first number. In response to the operation instruction, a corresponding operation is performed on the working memory blocks.

[0006] In some possible implementations, a third number of storage blocks in the first number of storage blocks are used as redundant storage blocks, and the sum of the second and third numbers equals the first number.

[0007] In some possible implementations, the first number of memory blocks includes a third number of faulty memory blocks, and the sum of the second and third numbers equals the first number. The peripheral circuitry is configured to: receive a first operation instruction and a second operation instruction. The address information in the first and second operation instructions is used to determine the same memory region among multiple memory regions and a second number of working memory blocks within the same memory region. And, in response to the first and second operation instructions, to perform corresponding operations on the second number of working memory blocks.

[0008] In some possible implementations, the first number of storage blocks includes a fourth number of faulty storage blocks. The sum of the fourth number and the second number is less than the first number. The second number of storage blocks in the fifth number of normal storage blocks are used as working storage blocks. The sum of the fifth number and the fourth number is equal to the first number.

[0009] In some possible implementations, the multiple operation instructions include a first operation instruction and a second operation instruction. The address information in the first operation instruction is used to determine a first storage region within the multiple storage regions and a second number of working memory blocks within the first storage region. The second operation instruction is used to determine a second storage region within the multiple storage regions and a second number of working memory blocks within the second storage region. If the first storage region and the second storage region are the same storage region, the second number of working memory blocks in the first storage region is different from the second number of working memory blocks in the second storage region.

[0010] In some possible implementations, the first number of storage blocks includes a sixth number of faulty storage blocks. The difference between the physical address of any faulty storage block in the sixth number of faulty storage blocks and the physical address of any normal storage block in the seventh number of normal storage blocks is less than a preset threshold. The sum of the sixth number and the seventh number equals the first number.

[0011] In some possible implementations, in each storage region, the physical distance between any two storage blocks in a first number of storage blocks is less than a threshold.

[0012] In some possible implementations, the address information includes the address of the target storage region and the addresses of a third number of redundant storage blocks.

[0013] In some possible implementations, the peripheral circuitry includes a memory region decoding circuit, a memory block decoding circuit, an XOR logic circuit, and a memory block enable circuit, which are coupled in sequence.

[0014] In some possible implementations, the first number of memory blocks includes a third number of redundant memory blocks, and the sum of the second and third numbers equals the first number. Address information includes the address of the target memory region and the addresses of the third number of redundant memory blocks. A memory region decoding circuit is configured to output a first enable signal based on the address of the target memory region. A memory block decoding circuit is configured to output a second enable signal based on the addresses of the third number of redundant memory blocks and the first enable signal. An XOR logic circuit is configured to receive a third enable signal and output a fourth enable signal based on the second and third enable signals. The fourth enable signal is the XOR result of the second and third enable signals. A memory block enabling circuit is configured to output a fifth enable signal to the second number of working memory blocks based on the fourth enable signal. The fifth enable signal is used to select the second number of working memory blocks.

[0015] In some possible implementations, at least two storage regions in multiple storage regions share a third number of redundant storage blocks.

[0016] In some possible implementations, the operation command further includes a sixth enable signal. The sixth enable signal indicates that the target storage area is configured to perform a data storage operation. The peripheral circuitry is also configured to: write stored data to the target storage area in response to the operation command; or read stored data from the target storage area in response to the operation command; or erase stored data in the target storage area in response to the operation command.

[0017] In some possible implementations, the operation instruction further includes a seventh enable signal. The seventh enable signal indicates that the target storage region is configured to perform a storage operation. Specifically, the peripheral circuitry is configured to: in response to the operation instruction, input operation data to a second number of working storage blocks and obtain the operation result. The operation result is the result of the operation data and the data stored in the working storage blocks.

[0018] In some possible implementations, the working memory block includes a select line and a memory string. The memory string includes multiple transistors, with their drain and source lines alternately coupled. The select line is coupled to the gate line of a transistor at one end of the memory string. The peripheral circuitry is specifically configured to input computation data to the select line in the working memory block in response to an operation command, and to obtain the computation result.

[0019] Secondly, embodiments of this disclosure provide a semiconductor device, including: peripheral circuitry and a memory cell array, the memory cell array and the peripheral circuitry being coupled together. The memory cell array includes a plurality of first-level memory elements, each first-level memory element including a plurality of memory blocks. The plurality of memory blocks are configured in a plurality of second-level memory elements, each second-level memory element including a first number of memory blocks. A second number of memory blocks in the first number of memory blocks are used as working memory blocks. The second number is less than the first number.

[0020] In some possible implementations, a third number of storage blocks in the first number of storage blocks are used as redundant storage blocks, and the sum of the second and third numbers equals the first number.

[0021] In some possible implementations, at least two of the multiple secondary storage elements share a third number of redundant storage blocks.

[0022] In some possible implementations, the first number of storage blocks includes a fourth number of faulty storage blocks. The sum of the fourth number and the second number is less than the first number. The second number of storage blocks in the fifth number of normal storage blocks are used as working storage blocks. The sum of the fifth number and the fourth number is equal to the first number.

[0023] In some possible implementations, the first number of storage blocks includes a sixth number of faulty storage blocks. The difference between the physical address of any faulty storage block in the sixth number of faulty storage blocks and the physical address of any normal storage block in the seventh number of normal storage blocks is less than a preset threshold. The sum of the sixth number and the seventh number equals the first number.

[0024] In some possible implementations, in each second-level storage element, the physical distance between any two storage blocks in a first number of storage blocks is less than a threshold.

[0025] In some possible implementations, the peripheral circuitry includes a memory region decoding circuit, a memory block decoding circuit, an XOR logic circuit, and a memory block enable circuit, which are coupled in sequence.

[0026] In some possible implementations, the peripheral circuitry is configured to: receive an operation instruction. The operation instruction includes address information used to determine a target secondary storage element and a second number of working memory blocks within that target secondary storage element. In response to the operation instruction, data operations are performed on the working memory blocks.

[0027] In some possible implementations, a third number of storage blocks out of the first number are used as redundant storage blocks, and the sum of the second and third numbers equals the first number. The address information includes the address of the target second-level storage element and the addresses of the third number of redundant storage blocks.

[0028] In some possible implementations, the peripheral circuitry includes a memory region decoding circuit, a memory block decoding circuit, an XOR logic circuit, and a memory block enable circuit, sequentially coupled. A first number of memory blocks includes a third number of redundant memory blocks, and the sum of the second and third numbers equals the first number. Address information includes the address of the target second-level memory element and the addresses of the third number of redundant memory blocks. The memory region decoding circuit is configured to output a first enable signal based on the address of the target second-level memory element. The memory block decoding circuit is configured to output a second enable signal based on the address of the third number of redundant memory blocks and the first enable signal. The XOR logic circuit is configured to receive a third enable signal and output a fourth enable signal based on the second and third enable signals. The fourth enable signal is the XOR result of the second and third enable signals. The memory block enable circuit is configured to output a fifth enable signal to a second number of working memory blocks based on the fourth enable signal. The fifth enable signal is used to select the second number of working memory blocks.

[0029] In some possible implementations, the operation command further includes a sixth enable signal. The sixth enable signal indicates that the target secondary storage element is configured to perform a data storage operation. The peripheral circuitry is also configured to: write stored data to the secondary storage element in response to the operation command; or read stored data from the secondary storage element in response to the operation command; or erase stored data from the secondary storage element in response to the operation command.

[0030] In some possible implementations, the operation instruction further includes a seventh enable signal. The seventh enable signal indicates that the target secondary storage element is configured to perform a storage operation. The peripheral circuitry is also configured to: in response to the operation instruction, input operation data to the working memory block and obtain the operation result. The operation result is the result of the operation data and the data stored in the working memory block.

[0031] In some possible implementations, the working memory block includes multiple select lines and a memory string. The memory string includes multiple transistors, with their drain and source lines alternately coupled. The select lines are coupled to the gate lines of the transistors at one end of the memory string. The peripheral circuitry is specifically configured to: in response to an operation command, input computation data to the multiple select lines in the working memory block and obtain the computation result.

[0032] In some possible implementations, the semiconductor device is a die comprising multiple memory surfaces. The first-level memory element is a memory surface comprising multiple memory cells. The second-level memory element is a memory cell comprising multiple memory blocks.

[0033] Thirdly, embodiments of this disclosure provide a method for operating a semiconductor device, including: receiving an operation instruction. The operation instruction includes address information, which is used to determine a target memory region among a plurality of memory regions and a second number of working memory blocks within the target memory region. The second number is less than a first number. In response to the operation instruction, a corresponding operation is performed on the working memory blocks.

[0034] In some possible implementations, the first number of storage blocks includes a third number of faulty storage blocks, and the sum of the second and third numbers equals the first number. Receiving operation instructions includes receiving a first operation instruction and a second operation instruction. The address information in the first and second operation instructions is used to determine the same storage region among multiple storage regions and a second number of working storage blocks within the same storage region. Responding to the operation instructions, performing corresponding operations on the working storage blocks includes performing corresponding operations on the second number of working storage blocks in response to the first and second operation instructions.

[0035] In some possible implementations, the first number of storage blocks includes a third number of redundant storage blocks, and the sum of the second and third numbers equals the first number. Address information includes the address of the target storage region and the addresses of the third number of redundant storage blocks. The method further includes: outputting a first enable signal based on the address of the target storage region; outputting a second enable signal based on the addresses of the third number of redundant storage blocks and the first enable signal; receiving a third enable signal and outputting a fourth enable signal based on the second and third enable signals; the fourth enable signal being the XOR result of the second and third enable signals; and outputting a fifth enable signal to the second number of working storage blocks based on the fourth enable signal. The fifth enable signal is used to select the second number of working storage blocks.

[0036] In some possible implementations, the operation instruction further includes a sixth enable signal. The sixth enable signal is used to indicate that the target storage area is configured to perform a data storage operation. The method further includes: writing storage data to the target storage area in response to the operation instruction; or reading storage data from the target storage area in response to the operation instruction; or erasing storage data in the target storage area in response to the operation instruction.

[0037] In some possible implementations, the operation instruction further includes a seventh enable signal. The seventh enable signal indicates that the target storage region is configured to perform in-memory computation operations. In response to the operation instruction, data operations are performed on a second number of working storage blocks, including: inputting computation data into the second number of working storage blocks in response to the operation instruction, and obtaining a computation result. The computation result is the result of the computation data and the data stored in the working storage blocks.

[0038] In some possible implementations, the working memory block includes multiple select lines and a memory string. The memory string includes multiple transistors, with their drain and source lines alternately coupled. The select lines are coupled to the gate lines of the transistors at one end of the memory string. Responding to an operation command, computation data is input to the working memory block to obtain a computation result, including: responding to an operation command by inputting computation data to the select lines in the working memory block to obtain a computation result.

[0039] Fourthly, embodiments of this disclosure provide a system including a controller and any of the semiconductor devices of the first aspect, wherein the controller and the semiconductor device are coupled. Alternatively, the system includes a controller and any of the semiconductor devices of the second aspect, wherein the controller and the semiconductor device are coupled.

[0040] Fifthly, embodiments of this disclosure provide an electronic device, the electronic device including a host and any system of the fourth aspect, the host and the system being coupled together.

[0041] In a sixth aspect, embodiments of this disclosure provide an electronic device comprising a host and any of the semiconductor devices described in the first aspect, wherein the host and the semiconductor device are coupled together. Alternatively, the electronic device comprises a host and any of the semiconductor devices described in the second aspect, wherein the host and the semiconductor device are coupled together.

[0042] In a seventh aspect, embodiments of this disclosure provide a computer storage medium, the computer-readable storage medium including instructions. When the instructions are executed on a processor, they cause the processor to perform an operation method of any semiconductor device according to the third aspect. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0044] Figure 1 This is a schematic diagram of the structure of an electronic device according to some embodiments. Figure 1 ;

[0045] Figure 2 This is a schematic diagram of the structure of an electronic device according to some embodiments. Figure 2 ;

[0046] Figure 3 This is a schematic diagram of the structure of a memory card according to some embodiments;

[0047] Figure 4 This is a schematic diagram of the structure of a solid-state drive according to some embodiments;

[0048] Figure 5 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 1 ;

[0049] Figure 6 This is a schematic diagram of the structure of a memory cell array according to some embodiments. Figure 1 ;

[0050] Figure 7 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 2 ;

[0051] Figure 8 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 3 ;

[0052] Figure 9 This is a schematic diagram of the structure of an electronic device according to some embodiments. Figure 3 ;

[0053] Figure 10 This is an illustration of a bad block management method according to some embodiments. Figure 1 ;

[0054] Figure 11 This is an illustration of a bad block management method according to some embodiments. Figure 2 ;

[0055] Figure 12 This is an illustration of a bad block management method according to some embodiments. Figure 3 ;

[0056] Figure 13 This is an illustration of a bad block management method according to some embodiments. Figure 4 ;

[0057] Figure 14 This is a schematic diagram of the structure of a memory cell array according to some embodiments. Figure 2 ;

[0058] Figure 15 This is an illustration of a bad block management method according to some embodiments. Figure 5 ;

[0059] Figure 16 This is an illustration of a bad block management method according to some embodiments. Figure 6 ;

[0060] Figure 17 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 4 ;

[0061] Figure 18 This is a schematic diagram of the structure of a memory cell array according to some embodiments. Figure 3 ;

[0062] Figure 19 This is a flowchart illustrating an operation method of a semiconductor device according to some embodiments. Figure 1 ;

[0063] Figure 20 This is a schematic diagram of the structure of a memory computing device according to some embodiments. Figure 1 ;

[0064] Figure 21 This is a schematic diagram of the structure of a memory computing device according to some embodiments. Figure 2 ;

[0065] Figure 22 This is a schematic diagram of the structure of a memory computing device according to some embodiments. Figure 3 ;

[0066] Figure 23 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 5 ;

[0067] Figure 24 This is a flowchart illustrating an operation method of a semiconductor device according to some embodiments. Figure 2 ;

[0068] Figure 25 This is a flowchart illustrating an operation method of a semiconductor device according to some embodiments. Figure 3 . Detailed Implementation

[0069] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0070] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0071] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0072] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0073] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0074] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0075] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0076] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0077] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0078] This disclosure is not limited to three-dimensional (3D) NAND semiconductor devices, although 3D NAND semiconductor devices may be used in some examples for illustration. For example, the techniques disclosed herein can be applied to planar NAND semiconductor devices and NOR semiconductor devices, etc.

[0079] Figure 1A structural diagram of an electronic device 10000 having semiconductor devices is shown according to some aspects. The electronic device 10000 can be a mobile phone (e.g., a cell phone), desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, game console, printer, positioning device, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, power bank, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, electronic device 10000 includes a storage system 11000 and a host 12000. Storage system 11000 includes one or more semiconductor devices 11100 and a controller 11200, with the controller 11200 coupled to the semiconductor devices 11100. Host 12000 may be a processor of electronic device 10000. Exemplarily, the processor may be a chip, specifically a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), an application processor (AP), or other integrated chips.

[0080] In some possible implementations, such as Figure 2 The diagram shows a structural diagram of an electronic device 20000 with semiconductor devices according to some aspects, such as Figure 2 As shown, the electronic device 20000 includes a host 21000 and a semiconductor device 22000 (which can also be as follows). Figure 1 The semiconductor device 11100 shown is coupled to the host 21000 and the semiconductor device 22000. For example... Figure 2 The host 21000 shown integrates, for example, Figure 1 The functions of controller 11200 in the storage system 11000 shown.

[0081] This embodiment uses, as follows Figure 1 The illustrated electronic device 10000 is used as an example for explanation. According to some embodiments, a controller 11200 is coupled to a semiconductor device 11100 and a host 12000, and is configured to control the semiconductor device 11100. The controller 11200 can manage data stored in the semiconductor device 11100 and communicate with the host 12000. In some embodiments, the controller 11200 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash card (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 11200 is designed to operate in a high duty cycle environment, such as a solid-state drive (SSD) or an embedded multimedia card (eMMC), which is used as a data storage device for mobile electronic devices such as smartphones, tablets, personal computers, etc., and for enterprise storage arrays.

[0082] The controller 11200 can be configured to manage data stored in the semiconductor device 11100 and communicate with external devices (such as the host 12000). It controls the operation of the semiconductor device 11100, such as read, erase, and program operations.

[0083] In some implementations, the controller 11200 is also configured to process error correction codes (ECCs) relating to data read from or written to the semiconductor device 11100.

[0084] Controller 11200 can also perform any other suitable functions, such as formatting semiconductor device 11100. Controller 11200 can communicate with external devices (e.g., host 12000) according to a specific communication protocol. For example, controller 11200 can communicate with external devices through at least one of various interface protocols, such as USB, Multimedia Card (MMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0085] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0086] The controller 11200 and one or more semiconductor devices 11100 can be integrated into various types of storage systems 11000, for example, included in the same package, such as an embedded multimedia card (eMMC), universal flash storage (UFS) package, embedded multi-chip package (eMCP) package, or UFS-based multi-chip package (uMCP) package. Specifically, eMMC uses a unified MMC standard interface, encapsulating high-density NAND and the MMC controller in a ball grid array (BGA) package chip. UFS is an advanced version of eMMC, also an array-type storage module composed of multiple flash memory chips and a controller. UFS overcomes the limitation of eMMC, which only supports half-duplex operation (read and write must be performed separately), enabling full-duplex operation and thus doubling performance. eMCP is a package that incorporates volatile memory, such as static random-access memory (SRAM) or dynamic random-access memory (DRAM), on an eMMC.

[0087] In practical implementations, DRAM can be low-power double-data-rate synchronous dynamic random-access memory (LPDDR). uMCP is a packaged form of UFS with volatile memory (such as SRAM or DRAM) mounted on it, offering high performance and large capacity. In practical implementations, DRAM can be LPDDR. That is to say, the storage system 11000 can be implemented and packaged into different types of end electronic devices.

[0088] In such Figure 3 In one example shown, controller 11200 and a single semiconductor device 11100 can be integrated into memory card 400. Memory card 400 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 400 may also include a connection between memory card 400 and a host (e.g., Figure 1 The memory card connector 410 is coupled to the host 12000.

[0089] In such Figure 4In another example shown, controller 11200 and multiple semiconductor devices 11100 can be integrated into SSD 500. SSD 500 may also include interfaces between SSD 500 and a host (e.g.,...). Figure 1 The SSD connector 510 is coupled to the host 12000. In some implementations, the storage capacity and / or operating speed of the SSD 500 is higher than that of the memory card 400.

[0090] Figure 5 A schematic circuit diagram of an exemplary semiconductor device 600, including peripheral circuitry 602, is shown according to some aspects of this disclosure. The semiconductor device 600 may be... Figure 1 An example of semiconductor device 11100 is shown. Semiconductor device 600 may include a memory cell array 601 and peripheral circuitry 602 coupled to the memory cell array 601. The memory cell array 601 may be a NAND flash memory cell array, wherein the memory cells 606 are provided in the form of an array of NAND memory strings 608, all extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 608 includes a plurality of memory cells 606 coupled in series and stacked vertically. Each memory cell 606 is capable of holding a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 606. Each memory cell 606 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0091] In some implementations, each storage cell 606 is a single-level cell (SLC) with two possible storage states (levels) and thus capable of storing one bit of data. Specifically, each storage cell 606 can be configured to store 2... N One of the storage states (levels) stores N bits of data, where N is a natural number greater than 0. This 2 N The storage states include erase state and 2. N-1 non-erasable state. In some implementations, each memory cell 606 is a single-level cell (SLC) having two possible storage states (levels) and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a threshold voltage in a first range, and a second storage state "1" may correspond to a threshold voltage in a second range. In some implementations, each memory cell 606 is an xLC capable of storing more than one bit of data in four or more storage states (levels). For example, an xLC is capable of storing two bits per cell (multi-level cell, MLC), three bits per cell (triple-level cell, TLC), or four bits per cell (quad-level cell, QLC). Each xLC can be programmed to assume a range of possible nominal storage values. In one example, an MLC can be programmed from an erase state to assume one of three possible programming levels by writing one of three possible nominal storage values ​​(e.g., 01, 10, and 11) into memory cell 606. A fourth nominal storage value can be used for the erase state (e.g., 00).

[0092] like Figure 5 As shown, each NAND flash memory string 608 may further include a source select gate (SSG) transistor 610 at its source end and a drain select gate (DSG) transistor 612 at its drain end. The SSG transistor 610 and DSG transistor 612 can be configured to activate the selected NAND flash memory string 608 (column of the array) during read and program operations. In some embodiments, the sources of the NAND flash memory strings 608 in the same block 604 are coupled via the same source line (SL) 614 (e.g., common SL). In other words, according to some embodiments, all NAND flash memory strings 608 in the same block 604 have an array common source (ACS). According to some embodiments, the drain of each NAND flash memory string 608 is coupled to a corresponding bit line 616, enabling data to be read from or written to the corresponding bit line 616 via an output bus (not shown). In some implementations, each NAND memory string 608 is configured to be selected or deselected by applying a selection or deselection voltage to the gate of the corresponding DSG transistor 612 via one or more DSG lines 613 and / or by applying a selection or deselection voltage to the gate of the corresponding SSG transistor 610 via one or more SSG lines 615.

[0093] like Figure 5As shown, NAND memory strings 608 can be organized into multiple memory blocks 604, each of which may have a common source line 614, for example, coupled to the ACS. In some embodiments, each memory block 604 is the basic data unit for erase operations, i.e., all memory cells 606 on the same memory block 604 are erased simultaneously. To erase memory cells 606 in a selected memory block 604, the source lines 614 coupled to the selected memory block 604 and unselected memory blocks 604 in the same plane as the selected memory block 604 can be biased with an erase voltage (Vers), such as a high positive bias voltage (e.g., 20V or higher). Memory cells 606 of adjacent NAND memory strings 608 can be coupled via word lines (WL) 618, which selects which row of memory cells 606 is affected by read and program operations.

[0094] like Figure 5 As shown, the memory cell array 601 may include an array of memory cells 606 in multiple rows and columns within each memory block 604. According to some embodiments, one column of memory cells corresponds to one NAND memory string 608. Multiple rows of memory cells 606 may be coupled to word lines 618, and multiple columns of memory cells 606 may be coupled to bit lines 616.

[0095] like Figure 6 As shown, the memory cell array 601 may include multiple memory planes (memory plane 0, memory plane 1, ..., memory plane P), and the memory plane is the smallest unit for integrating the memory cell array 601 in the manufacturing process. Each memory plane includes multiple memory blocks 604 (memory block 0, memory block 1, memory block 2, memory block 3, ..., memory block Q).

[0096] like Figure 7 This disclosure illustrates, according to some aspects, a three-dimensional (3D) semiconductor device 600 comprising multiple stacked layers. For example... Figure 7 As shown, the semiconductor device 600 includes multiple memory strings 608 and n layers of memory cells (including WL0, WL1, WL2, ..., WLn-1, WLn-2, ​​WLn-1). The multiple memory strings 608 included in the semiconductor device 600 are arranged in a direction parallel to the bearing surface of the substrate, and the multiple memory cells in each memory string 608 are arranged in a direction perpendicular to the bearing surface of the substrate. That is, the multiple memory cells included in the semiconductor device 600 are arranged in a three-dimensional array on the substrate, forming a memory cell array.

[0097] One end of the memory string 608 is connected to bit lines 616 (including BL0, BL2, ..., BLm-1), and the other end is connected to a common source line (CSL) or an array common source (ACS). The BSGs of the memory string 608 can be coupled to the same CSL or to different CSLs (e.g., ...). Figure 7 As shown, CSL0, ..., CSLm-1), there are no restrictions here.

[0098] The memory cells 606 in each memory string 608 are also connected to memory cells 606 in other memory strings via word lines 618. For example, if each memory string 608 may include 64 memory cells 606, then the 3D semiconductor device may include 64 word lines 618WL<63:0>, and each word line 618 is connected to a portion of memory cells 606 located on the same layer (i.e., having the same height relative to the substrate). It should be noted that 64 memory cells 606 is only a specific example, and the application is not limited to this. In some embodiments, each memory string 608 may include more than 64 memory cells 606, such as 128, 196, etc. In the 3D semiconductor device 600, the memory cells 606 connected to the same word line 618 are called a memory page, and all memory strings 608 sharing a set of word lines 618 are called a memory block.

[0099] The memory string 608 also includes an upper select transistor connected to the drain of the first memory cell 606 and a lower select transistor connected to the source of the last memory cell 606. The upper select transistors are also called top select gates (TSGs) or DSG transistors, and include TSG0, TSG1, TSG2, and TSG3. The lower select transistors are also called bottom select gates (BSGs) or SSG transistors.

[0100] The gate of the TSG is connected to the drain select line (DSL), the source of the TSG is connected to the drain of the first memory cell 606, and the drain of the TSG is connected to the bit line 616.

[0101] The gate of the BSG is connected to the source select line (SSL), the drain of the BSG is connected to the source of the last memory cell 606, and the source of the BSG is connected to the source line.

[0102] Depend on Figure 7It is understood that the memory cells 606 in the memory string 608 share a set of word lines 618 with the memory cells 606 in other memory strings 608. Assuming each memory string 608 includes m+1 memory cells 606, the 3D semiconductor device can include m+1 word lines (WL): WL0 to WLm, where m is an integer greater than 1. Each WL is connected to each memory cell 606 located on the same layer (i.e., having the same height relative to the substrate's bearing surface). Alternatively, it can be understood that the control gates of each memory cell 606 located on the same layer, and the gate connection lines between each control gate, constitute a word line 618.

[0103] Return to reference Figure 1 The peripheral circuitry 602 can be coupled to the memory cell array 601 via bit line (BL) 616, word line 618, source line 614, SSG line 615, and DSG line 613. The peripheral circuitry 602 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 601 by applying and sensing voltage and / or current signals to and from each target memory cell 606 via bit line 616, word line 618, source line 614, SSG line 615, and DSG line 613. The peripheral circuitry 602 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0104] For example, Figure 8 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 704, a column decoder / bit line driver 706, a row decoder / word line driver 708, a voltage generator 710, a control logic unit 712, a register 714, an interface (I / F) circuit 716, and a data bus 718. It should be understood that additional peripheral circuitry may be included. Figure 8 Additional peripheral circuitry not shown.

[0105] Page buffer / sensor amplifier 704 can be configured to read and program (write) data from and to memory cell array 601 according to control signals from control logic unit 712. In one example, page buffer / sensor amplifier 704 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 606 coupled to selected word line 618. In yet another example, page buffer / sensor amplifier 704 can also sense a low-power signal representing a data bit stored in memory cell 606 from bit line 616 during a read operation and amplify a small voltage swing to a recognizable logic level. As detailed below and consistent with the scope of this disclosure, during a programming operation, page buffer / sensor amplifier 704 may include a memory module (e.g., latch, cache, register, etc.) for temporarily storing a segment of N bits of data received from data bus 718 and using 2 N -2 N In each programming pass of the multi-pass programming operation, the N-bit data segment is provided to the corresponding target storage unit 606 via the corresponding bit line 616.

[0106] The column decoder / bit line driver 706 can be configured to be controlled by the control logic unit 712 and to select one or more NAND memory strings 608 by applying bit line voltages generated by the voltage generator 710. The row decoder / word line driver 708 can be configured to be controlled by the control logic unit 712 and to select / deselect memory blocks 604 of the memory cell array 601 and to select / deselect word lines 618 of the memory blocks 604. The row decoder / word line driver 708 can also be configured to drive word lines 618 using word line voltages generated by the voltage generator 710. In some embodiments, the row decoder / word line driver 708 can also select / deselect and drive SSG lines 615 and DSG lines 613. The voltage generator 710 can be configured to be controlled by the control logic unit 712 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be provided to the memory cell array 601.

[0107] Control logic unit 712 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 714 can be coupled to control logic unit 712 and includes a status register, a command register, and an address register for storing status information, command operation code (OP), and command address for controlling the operation of each peripheral circuit. Interface circuitry 716 can be coupled to control logic unit 712 and acts as a control buffer to buffer data from the host (e.g., ...). Figure 1The host 2000 receives control commands and forwards them to the control logic unit 712, and buffers the status information received from the control logic unit 712 and forwards it to the host. The interface circuit 716 can also be coupled to the column decoder / bit line driver 706 via the data bus 718, and acts as a data input / output (I / O) interface and data buffer to buffer and forward data to and from the memory cell array 601.

[0108] In practical applications, during the manufacturing and subsequent use of NAND semiconductor devices, to ensure their stable and reliable operation, the controller 11200 can also be configured to manage various functions related to data stored or to be stored in the semiconductor device 11100, including but not limited to bad block management, garbage collection, logic-to-physical address translation, and wear leveling. For example... Figure 9 As shown, a firmware system, Flash Translation Layer (FTL) 11210, can be implemented in controller 11200. The performance, reliability, and durability of storage system 11000 (such as SSD) depend on the implementation of the FTL 11210 algorithm. Currently, a complete FTL 11210 structure mainly includes address mapping, garbage collection, wear leveling, bad block management, and power-down recovery. Controller 11200 also includes host interface circuit 11220 and semiconductor device interface circuit 11230. Host interface circuit 11220 is used to couple host 12000 and FTL 11210. Semiconductor device interface circuit 11230 is used to couple FTL 11210 and semiconductor devices 11100. Semiconductor device interface circuit 11230 includes multiple semiconductor devices 11100 (e.g., semiconductor device 0, semiconductor device 1, semiconductor device 2, ..., semiconductor device N, etc.).

[0109] Due to the erase-before-write characteristic of NAND Flash, data written to the same logical address cannot be modified on the original physical page storing the data; a new physical page must be found to accommodate the updated data. Therefore, the firmware needs to maintain a mapping table from logical address to physical address, continuously recording the correspondence between the logical address accessed by the host and the physical address on the NAND Flash chip. For updated data, the data on the original physical page becomes invalid. This invalid data still occupies Flash storage space, and if this invalid data is not processed, Flash space will be quickly exhausted. To address this, the FTL 11210 performs another important function when Flash available space is low: Garbage Collection (GC), which erases invalid pages and releases available space. The basic unit of erasure is a Flash storage block. A Flash storage block contains many physical pages. Before garbage collection, the pages storing valid data in the selected Flash storage block need to be moved to other free storage blocks. Only after this can the entire Flash storage block be erased.

[0110] Flash memory blocks have a limited lifespan, meaning there's a limit to the number of program / erase cycles a single flash memory block can withstand. Concentrated data writing and garbage collection on certain flash memory blocks can cause them to fail rapidly, reducing the available flash space. When the available space drops to a certain threshold, the SSD is considered faulty. To extend the lifespan of an SSD, the FTL 11210 layer needs to evenly distribute data writing and erasing across all flash memory blocks—a process known as wear leveling. Even with wear leveling algorithms, flash memory blocks will eventually become damaged as they wear down. Damaged flash blocks can be replaced with good flash memory blocks from the flash's over-provision (OP) space; this process is known as bad block management.

[0111] Bad block management mainly involves managing factory bad blocks (FBB) and grown bad blocks (GBB).

[0112] Factory bad blocks (FBBs) are those that occur during the manufacturing process of NAND semiconductor devices due to limitations in the manufacturing process or accidental factors. These are identified and marked during production. When using NAND semiconductor devices, the markings within the blocks are first scanned to identify the bad blocks marked by the manufacturer, generating a bad block table (BBT). Subsequent use will not allow the selection of blocks from the bad block table to avoid data errors or loss at the user's end.

[0113] Growing bad blocks (GBBs), unlike factory-installed bad blocks, gradually form during the normal use of NAND semiconductor devices. This is mainly due to the physical wear and tear on memory cells caused by frequent erase and write operations, leading to data read and write errors. The appearance of these bad blocks is an inherent characteristic of NAND semiconductor device technology and requires dynamic checking and management through the BBB mechanism. When a memory block is detected to have become a bad block, it can no longer be selected for use, and the memory block is recorded in the BBT.

[0114] Bad block management includes two strategies: skipping and replacing.

[0115] The skip strategy allows users to skip bad blocks registered in the table and write the next storage block when they encounter them during data write operations, based on the established BBT (Block Barrier).

[0116] Figure 10 The diagram shows that in the storage system 11000, four semiconductor devices (semiconductor device 0, semiconductor device 1, semiconductor device 2, and semiconductor device 3) sequentially write storage data to each other. When selecting parallel storage blocks, each semiconductor device selects the same block number. According to the user's bad block table, if storage block 0 of semiconductor device 0 is a bad block, it is not added to the parallel storage block strip. Instead, storage blocks 0 of semiconductor device 1, semiconductor device 2, and semiconductor device 3 are combined into a parallel block strip.

[0117] The skip strategy skips bad blocks and does not use the semiconductor device where the bad block is located. Instead, it uses the semiconductor device where the remaining good memory blocks are located to build parallel blocks.

[0118] The advantage of the skip strategy is its simplicity in management; bad blocks can be skipped. Its disadvantage is performance instability. If N semiconductor devices operate concurrently, the system's parallelism will fluctuate between 1 and N, and performance cannot be guaranteed to remain stable with N concurrent chips.

[0119] Unlike the skip strategy, the replacement strategy divides the memory blocks in each die into a main block (main blk) and a redundant block (extra blk). The redundant block is used to replace faulty blocks in the main block. When a bad block is found on a die, the replacement strategy replaces the faulty block in the main block with a good block from the redundant blocks in that die. In other words, under the replacement strategy, upon encountering a faulty block, it searches for another available free block in the redundant blocks of the current die and writes it to the replacement block, rather than skipping the die.

[0120] For example, Figure 11 The diagram illustrates four semiconductor devices (semiconductor device 0, semiconductor device 1, semiconductor device 2, and semiconductor device 3) in the storage system 11000. Data is sequentially written to each of these four devices. If storage block 3 of semiconductor device 0 is faulty, it is replaced with storage block 0 (or storage block 1) from the redundant storage blocks in semiconductor device 0. Then, storage blocks 0 of semiconductor device 0, 3 of semiconductor device 1, 3 of semiconductor device 2, and 3 of semiconductor device 3 are arranged into parallel blocks.

[0121] For example Figure 12 As shown, the faulty storage block (black block) in the main storage block is replaced with a storage block from the redundant storage block (the block filled with diagonal stripes in the figure).

[0122] The replacement strategy demonstrates significant advantages in ensuring the simultaneous operation of N dies and improving performance stability. Furthermore, this strategy's supplementary operations for FBB / GBB are not constrained by physical addresses, allowing for flexible mapping of redundant memory blocks to any location in the logical address space to quickly replace damaged memory blocks.

[0123] However, while the replacement strategy is flexible, when the physical location of the faulty memory block is far from the physical location of the memory block to be replaced, the long power supply wiring path will introduce additional voltage drop due to the parasitic resistance of the semiconductor device, making the voltage drop more severe and significantly aggravating the voltage drop (IR Drop) problem, which will affect the performance of the NAND semiconductor device.

[0124] Voltage drop, an unavoidable voltage loss phenomenon when current flows through resistance, is particularly critical in NAND semiconductor devices. Especially during large-scale data read, write, or erase operations, current demand surges and varies with the location of the memory cells in the array due to the changing parasitic resistance. For cells at the far ends of the array, this results in significant voltage drops in the internal metal wires, transistors, and other components due to the resistive effect. This voltage drop not only affects the voltage stability of different regions within the NAND semiconductor device but can also directly weaken the overall performance and functional reliability of the chip. For example, insufficient voltage during data read, write, or erase operations can lead to unsuccessful operations.

[0125] Furthermore, there is a close relationship between the specific location of memory blocks in NAND semiconductor devices and voltage drop. Due to differences in the physical layout of memory blocks at different locations, particularly variations in the length of additional wiring, current distribution and resistance effects occur, causing each memory block to be affected by voltage drops to varying degrees. This differential voltage drop effect can ultimately manifest as a decrease in memory block read / write performance and fluctuations in stability.

[0126] To solve one or more of the above problems, one can address issues such as... Figure 6 The structure of the storage cell array 601 shown is improved, such as... Figure 13 As shown, storage blocks in the storage plane are configured into multiple storage banks. Each storage bank comprises m+n storage blocks. Any n storage blocks from the m+n blocks are designated as primary storage blocks (or working storage blocks). When performing operations at the storage bank level (such as write, read, erase, or storage-based operations), n storage blocks from each storage bank are selected to execute the corresponding operation. Any m storage blocks from the m+n blocks are designated as redundant storage blocks to replace faulty storage blocks in the storage banks, ensuring that each storage bank has at least n normal storage blocks. If the number of normal storage blocks in a storage bank is less than n, the storage bank will be marked as faulty and will not be used for corresponding data operations.

[0127] like Figure 14 As shown, the memory cell array 601 has six memory planes (memory plane 0, memory plane 1, memory plane 2, memory plane 3, memory plane 4, and memory plane 5). Each memory plane includes multiple memory banks (memory bank 0, memory bank 1, memory bank 2, ..., memory bank M). Each memory bank includes multiple TSGs (TSG0, TSG1, TSG2, TSG3, ..., TSGN). Each TSG is coupled to the gate line 1302 of the select transistor on the memory string 608. TSG slits 1304 are formed between the TSGs to cut off (or isolate) the TSGs. Gate line slits 1306 are formed adjacent to the TSGs to cut off (or isolate) the metal layer corresponding to the gate line of the select transistor on the memory string 608 in the memory cell array 601.

[0128] For example, the TSG can be a coarse TSG. Each memory bank may include 16KB of bit lines (BL).

[0129] To limit the relative physical distance between blocks within the same storage bank, the design ensures that the physical distance between any two blocks in the m+n blocks of each storage bank is less than a threshold. It also ensures that the difference between the physical address of any faulty block and the physical address of any healthy block within the same storage bank is less than a threshold.

[0130] In the scheme disclosed in this application, it is not necessary to specify which m redundant memory blocks are in each memory bank, or which n primary memory blocks are in each memory bank. During use, n normal memory blocks are selected from the (n+m) memory blocks in each memory bank to perform the corresponding operations. By distributing redundant memory blocks across each memory bank, the relative physical location span between memory blocks within the same memory bank is small and relatively fixed, which reduces changes in current distribution and resistance effects, thereby reducing the impact of voltage drop on memory block read / write performance and improving memory block read / write performance, stability, and reliability. Simultaneously, since the n working memory blocks are selected from the m+n memory blocks, the corresponding data operations are relatively evenly distributed among the n memory blocks in the m+n memory blocks, achieving wear leveling and extending the lifespan of the semiconductor device.

[0131] For example Figure 13 The storage cell array 601 structure shown may have a low probability of generating bad blocks in some scenarios, and the probability of multiple storage banks generating bad blocks is even lower. If m redundant storage blocks are configured for each storage bank, it may lead to low utilization of the storage space of the semiconductor device and high hardware material costs.

[0132] To improve storage space utilization efficiency and reduce hardware material costs, some possible implementations include... Figure 15 As shown, the storage cell array 601 can be configured such that at least two storage banks share m redundant storage blocks (m is greater than or equal to 1). Any redundant storage block among the m redundant storage blocks can only be used to replace a faulty storage block in one storage bank at a time.

[0133] In some examples, such as Figure 16As shown, the storage cell array 601 can be configured with four storage banks sharing m redundant storage blocks. Each storage bank includes n primary storage blocks.

[0134] To accurately determine the relative physical location of redundant storage blocks (bank-level extra blocks) at the bank level, i.e., to avoid selecting storage blocks across banks, address decoding (X-Dec) is performed using a two-level decoding method at the bank-level and block-level.

[0135] like Figure 17 A schematic diagram of a semiconductor device 900 is shown. The semiconductor device 900 includes peripheral circuitry 902 and a memory cell array 901, which are coupled together. The peripheral circuitry 902 includes a memory region decoding circuit 904, a memory block decoding circuit 906, and a memory block enable circuit 908, which are coupled sequentially. Figure 18 As shown, the storage cell array 901 includes multiple first-level storage planes, each of which includes multiple storage blocks. These storage blocks are configured in multiple storage regions, which serve as second-level storage banks. Each storage region (or second-level storage element, hereinafter referred to as a storage region) includes a first number of storage blocks. A second number of these first number of storage blocks are used as working storage blocks. The second number is less than the first number.

[0136] like Figure 18 As shown, in the storage area (or second-level storage element), the third number of storage blocks in the first number of storage blocks are used as redundant storage blocks, and the sum of the second number and the third number is equal to the first number.

[0137] In some examples, the storage region (or secondary storage element) can be, for example... Figure 13 , Figure 14 , Figure 15 and Figure 16 The storage bank shown is Figure 18 The third number of redundant storage blocks can be, for example, Figure 13 The m redundant storage blocks shown can be used as follows: Figure 13 The n main storage blocks shown can be, for example, the first number of storage blocks. Figure 13 The m+n storage blocks shown are the sum of m redundant storage blocks and n main storage blocks.

[0138] In other examples, at least two storage regions share a third number of redundant storage blocks. For example, a storage region (or a second-level storage element) can be, for instance, as shown below. Figure 15 and Figure 16 The storage bank shown is Figure 18 The third number of redundant storage blocks can be, for example, Figure 15 or Figure 16 At least one of the m redundant storage blocks shown, and the second number of working storage blocks can be as shown in the figure. Figure 15 or Figure 16 The n main storage blocks shown.

[0139] based on Figure 17 The semiconductor device 900 shown and Figure 18 The memory cell array 901 shown, and the semiconductor device 900 can realize, as Figure 19 The method of operating the semiconductor device shown includes the following steps S110-S120, and the specific steps include:

[0140] S110. Receive an operation instruction, which includes address information. The address information is used to determine the target storage region and a second number of working storage blocks within the target storage region. The second number is less than the first number.

[0141] In some instances, the operation instructions can be as follows: Figure 1 , Figure 3 and Figure 4 The controller 11200 in the middle sends or such Figure 2 The host 21000, semiconductor devices (such as...) Figure 1 , Figure 2 , Figure 3 and Figure 4 (Showing a semiconductor device) receives an operation command. The operation command includes address information used to determine the target memory region (i.e., the selected memory bank) and a second number of working memory blocks (e.g., within the target memory region) from multiple memory regions. Figure 13 (The number of main storage blocks shown is n). The second number (n main storage blocks) is less than the first number (m+n storage blocks).

[0142] In some examples, the address information may include A0-Am and Am+1-An. A0-Am represents the target storage area, i.e., the address of the selected storage bank. The storage bank area decoding circuit 904 resolves the address A0-Am of the selected storage bank. Am+1-An represents the working storage block, i.e., the address of the selected storage block. The storage block decoding circuit 906 resolves the address Am+1-An of the selected storage block to ensure that the selected storage block is a storage block within the same storage bank.

[0143] The storage area decoding circuit 904 receives selected storage bank address signals A0-Am from an external source and selects one or more storage banks for access based on these address signals. It also sends a selected storage bank enable signal to the storage block decoding circuit 906. When the selected storage bank enable signal is activated, it allows access to data within the storage bank.

[0144] The memory block decoding circuit 906 receives a selected memory block address signal (Am+1-An) from an external source, selects a specific memory block within the selected memory bank based on the selected memory block address signal, and activates the selected memory block by sending an enable signal to the selected memory block in the memory cell array 901 through the memory block enable circuit 908. For example, memory block 0 (or memory block Q) in the current memory bank is selected, and memory block 0 (or memory block Q) in other memory banks will not be selected.

[0145] exist Figure 17 In this context, selecting a memory bank and a memory block indicates that, based on the control of the aforementioned memory area decoding circuit 904, memory block decoding circuit 906, and memory block enable circuit 908, as well as the enable signal, specific memory banks and memory blocks are selected. These selected memory banks and memory blocks can then perform corresponding data operations (such as data reading, data writing, data erasure, and storage operations). Not selecting a memory bank or memory block indicates that, without a corresponding enable signal, they will remain inactive and will not participate in the execution of corresponding data operations.

[0146] In some examples, if the first number of storage blocks includes a third number of faulty storage blocks, the sum of the second and third numbers equals the first number. This means that all pre-configured redundant storage blocks in the target storage area or target storage bank are used to replace the faulty storage blocks, leaving only the minimum number of storage blocks required to perform the corresponding operation in the target storage area. For example, if at least n storage blocks are required to perform the corresponding operation, then only n normal storage blocks remain in the target storage area. If the peripheral circuit receives multiple operation instructions, all indicating the same target storage area, then the second number of working storage blocks used to perform the corresponding operation in the target storage area is the same.

[0147] For example, the peripheral circuit 902 receives a first operation instruction and a second operation instruction. The address information in the first and second operation instructions is used to determine the same memory region among multiple memory regions and a second number of working memory blocks within the same memory region. And in response to the first and second operation instructions, corresponding operations are performed on the second number of working memory blocks.

[0148] In some examples, the first number of storage blocks includes a fourth number of faulty storage blocks. The sum of the fourth number and the second number is less than the first number. That is, only a portion of the pre-configured redundant storage blocks in the target storage area or target storage bank are used to replace faulty storage blocks, and the number of remaining normal storage blocks in the target storage area is greater than the second number. If the number of normal storage blocks is a fifth number, then the second number of storage blocks in the fifth number of normal storage blocks are used as working storage blocks. The sum of the fifth number and the fourth number is equal to the first number.

[0149] For example, the peripheral circuit 902 receives a first operation instruction and a second operation instruction. The address information in the first operation instruction is used to determine a first storage region among multiple storage regions and a second number of working memory blocks within the first storage region. The second operation instruction is used to determine a second storage region among multiple storage regions and a second number of working memory blocks within the second storage region. When the first storage region and the second storage region are the same storage region, the second number of working memory blocks in the first storage region is different from the second number of working memory blocks in the second storage region.

[0150] In some examples, within each storage region, the physical distance between any two storage blocks in a first number of storage blocks is less than a threshold. Similarly, ... Figure 13 , Figure 15 and Figure 16In the implementation shown, in order to limit the relative physical location span between storage blocks in the same storage bank, when configuring storage blocks for each storage bank, it is ensured that the physical distance between any two storage blocks among the m+n storage blocks included in each storage bank is less than a threshold.

[0151] For example, the first number of storage blocks includes a sixth number of faulty storage blocks. The difference between the physical address of any faulty storage block in the sixth number of faulty storage blocks and the physical address of any normal storage block in the seventh number of normal storage blocks is less than a preset threshold. Similarly, as... Figure 13 , Figure 15 and Figure 16 The implementation shown can also be limited to a threshold value where the difference between the physical address of any faulty storage block and the physical address of any normal storage block in the same storage bank is less than a threshold value.

[0152] S120. In response to the operation command, perform the corresponding operation on the working storage block.

[0153] In some examples, the corresponding operations may include, but are not limited to, writing stored data to the target storage area; reading stored data from the target storage area; and erasing stored data from the target storage area.

[0154] like Figure 13 , Figure 15 , Figure 16 , Figure 17 and Figure 18 The semiconductor devices in the corresponding implementation can be applied to in-memory computing devices.

[0155] Most current computing platforms are based on the von Neumann architecture. The von Neumann architecture is computation-centric, separating computation and storage modules, which work together to perform data processing and access. However, because the design of computation modules (such as processors) prioritizes increasing computation speed, while storage modules focus more on capacity expansion and cost optimization, a performance mismatch between "storage" and "computation" leads to problems such as low memory access bandwidth, latency, and high power consumption—commonly known as the "memory wall" and "power wall." The more intensive the memory access, the more severe the "wall" problem becomes, and the more difficult it is to improve computing power. With the rapid rise of memory-intensive applications, such as convolutional neural networks (CNNs) and recurrent neural networks (RNNs), memory access latency and power consumption cannot be ignored, making a transformation of the computing architecture particularly urgent.

[0156] Compute-in-Memory (CIM) architecture, as a new computing architecture, fully integrates storage and computation, effectively overcoming the bottlenecks of the von Neumann architecture and achieving orders-of-magnitude improvements in computing energy efficiency. In CIM, the distinction between storage and computation units is eliminated during chip design, truly achieving memory-computing convergence. Essentially, CIM utilizes the physical characteristics of different storage media to redesign storage circuits, enabling them to simultaneously possess computational and storage capabilities, directly eliminating the boundary between "storage" and "computing," thus achieving orders-of-magnitude improvements in computing energy efficiency. Figure 20 A structural diagram of a memory computing device 800 is shown. The memory computing device 800 includes a memory computing array 801 and peripheral circuitry 802, which are coupled together. The memory computing array 801 is configured to store weight matrix data. The memory computing array includes memory computing units arranged in rows and columns. These units can perform various computational operations, such as matrix operations and vector operations, according to a preset algorithm.

[0157] Compared to the von Neumann architecture, in-memory computing has advantages such as faster computing speed, lower power consumption, and higher integration density. In-memory computing integrates computing functions into storage units, reducing the frequent data transfer between data storage modules and computing modules, and also reducing data transmission latency. In addition, in-memory computing integrates computing and storage functions on the same chip, reducing the need for external connections and wiring, resulting in higher chip integration and the ability to be applied to smaller and thinner electronic devices.

[0158] Artificial intelligence algorithms, exemplified by neural networks, involve various tensor and vector computations, with matrix-vector multiplication being the most representative operator. These operators typically feature large data volumes, high computational demands, and high parallelism requirements. In Von Neumann architecture-based computing platforms, processors executing AI algorithms suffer from significant power consumption and latency overhead due to the separation of storage and computation, resulting in data transfer power consumption far exceeding computational power consumption. This has become a bottleneck in the development of Von Neumann architecture accelerators. The core idea of ​​in-memory computing technology is to integrate memory and computation. By storing relatively fixed weight matrix data in memory and inputting feature vectors into an array, matrix-vector multiplication can be performed internally. This effectively avoids the large-scale transfer of weight data while achieving highly parallel data access and computation, thereby improving both computational speed and energy efficiency. Therefore, in-memory computing is highly suitable for accelerating matrix and vector operations in AI algorithms.

[0159] In some examples, the memory array 801 can be used to perform matrix-vector multiplication operations as shown in equation (1), where V IN0 V IN1 ,…,VINN This represents the computational data (or input vector) input to the computing array 801. Taking image recognition applications as an example, the computational data can be image feature information. 00 ,w 01 ,…,w 0M ;w 10 ,w 11 ,…,w 1M ;…,;w N0 ,w N1 ,…,w NM Equations (2), (3), and (4) represent the weight matrix data stored in the memory array 801. The weight matrix data is composed of weight data (e.g., for flash memory, NAND or NOR can be characterized by the threshold voltage of the memory cell. For RRAM memory, it can be characterized by the conductance of the memory cell. This embodiment uses NAND as an example for explanation). Equations (2), (3), and (4) are used to represent the results of the operation of multiplying and accumulating the operation data with the weight matrix data.

[0160]

[0161] I D0 =V IN0 *w 00 +V IN1 *w 10 +…+V INN *w N0 Equation (2)

[0162] I D1 =V IN0 *w 01 +V IN1 *w 11 +…+V INN *w N1 Equation (3)

[0163] …

[0164] I DM =V IN0 *w 0M +V IN1 *w 1M +…+V INN *w NM Equation (4)

[0165] Figure 21 An example of matrix-vector operations performed when the semiconductor device 600 is used as a memory computing device 800 is shown, as in equations (5)-(9):

[0166]

[0167] I D0 =VIN0 *w 00 +V IN1 *w 10 +V IN2 *w 20 Equation (6)

[0168] I D1 =V IN1 *w 01 +V IN1 *w 10 +V IN1 *w 20 Equation (7)

[0169] I D2 =V IN0 *w 01 +V IN1 *w 11 +V IN2 *w 21 Equation (8)

[0170] I D2 =V IN0 *w 02 +V IN1 *w 12 +…+V IN2 *w 22 Equation (9)

[0171] Among them, the weight data w 00 ,w 01 ,w 02 ;w 10 ,w 11 ,w 12 ;w 20 ,w 21 ,w 22 The process of writing to the semiconductor device 600 is completely consistent with the programming process of the memory cell array 601. The operation data (or input vector) V IN0 V IN1 V IN2 Input the gates of TSG0, TSG1, and TSG2 respectively, and process the data (output data or output vector) I. D0 I D1 , I D2 is output from bit lines BL0, BL1, and BL2 respectively.

[0172] like Figure 22 This illustrates a basic principle of stored-data computation, such as Figure 22As shown, the storage cell array 601 shows seven word lines WL: WL0, WL1, WL2, WL3, WL4, WL5, and WL6, and eight storage strings (str): storage string 0 (str0), storage string 1 (str1), storage string 2 (str2), storage string 3 (str3), storage string 4 (str4), storage string 5 (str5), storage string 6 (str6), and storage string 7 (str7).

[0173] Storage cells can be configured as SLC, MLC, TLC, and QLC storage cells, but are not limited to. This example uses an SLC storage cell configured to store weighted array data. Each storage cell can have two states: erase state E or programmable state P. Erasure state E can indicate that the data stored in the current storage cell is 1, denoted as E(1). Programmable state P can indicate that the data stored in the current storage cell is 0, denoted as P(0).

[0174] Table 1 shows the relationship between the input computation data (Vin), the weight data in the memory cell (i.e., the threshold voltage Vth of the memory cell), and the output computation results (such as bit line current, BL current) of the memory cell array 601.

[0175] Table 1

[0176] Calculated data (Vin) Weighted data Calculation result (output) 1 E(1) 1 1 P(0) 0 0 E(1) 0 0 P(0) 0

[0177] During in-memory computing operations, a read voltage Vrd is applied to the selected word line WL (programming word line, where the memory cells store weighted data) to activate the weighted data stored in the memory cells coupled to the selected word line WL. An on-state voltage Vpass is applied to the other WLs. An input voltage (operation data or input vector) is applied to the top selection gate TSG. The output current is collected at the BL terminal. After collecting the output currents of all memory cells, addition is performed by accumulating them.

[0178] For example, such as Figure 22 As shown, taking the weighted data stored in the storage unit of word line WL3 as E(1), P(0), E(1), P(0), E(1), E(1), P(0), P(0) as an example. If... Figure 22 The word line WL3 in the memory cell array 601 shown is given a read voltage Vrd, and an input voltage V is given on the top select gate TSG. IN0 =1, V IN1＝1 V IN2 =0, V IN3＝0 V IN4 =1, V IN5 =1, VIN6 =1, V IN7 =1, then:

[0179] I D0 =1*E(1)+1*P(0)+1*E(1)+1*P(0)+1*E(1)+1*E(1)+1*P(0)+1*P(0)

[0180] Therefore, during vector matrix multiplication and addition operations in the in-memory computing device, the operation in the memory cell array 601 is equivalent to applying voltage and reading current. In the current I... D0 Storage strings 0, 4, and 5 contributed the current.

[0181] In in-memory computing devices, even minute voltage fluctuations can cause deviations in calculation results, especially in high-precision in-memory computing scenarios. Given the stringent accuracy requirements of in-memory computing on voltage drop (IR Drop), methods such as... Figure 13 , Figure 15 , Figure 16 , Figure 17 and Figure 18 The semiconductor device in the corresponding implementation is applied in a memory computing device to reduce the impact of voltage drop on the accuracy of in-memory computing.

[0182] like Figure 17 In the schematic diagram of the semiconductor device shown, if the memory blocks in semiconductor device 900 are used for normal storage operations (such as data writing, data reading, or data erasure), only one memory block needs to be selected for operation at a time. However, if the memory blocks in semiconductor device 900 are used for in-memory computation operations, multiple memory blocks need to be selected each time (because the amount of computation data that a memory block can receive is limited). Therefore, the address of the selected memory block includes the addresses of multiple memory blocks, and the memory block decoding circuit 906 needs to perform multiple decoding operations, outputting multiple high-level memory block enable signals to activate the selected memory block. Therefore, when the memory blocks in semiconductor device 900 are used for in-memory computation operations, the circuit requirements are complex, the operation is inconvenient, and the power consumption is high.

[0183] To reduce circuit complexity and power consumption and facilitate operation, this disclosure provides for the following: Figure 17 The circuit shown has been improved, such as Figure 23 As shown. Figure 23 In the semiconductor device 900 shown, an XOR logic circuit 910 is added to reduce circuit complexity and power consumption. The inverse selection operation of the XOR logic circuit 910 enables flexible selection of multiple memory banks. Specifically, an in-memory computing enable signal controls the memory blocks to perform normal storage operations or in-memory computing operations.

[0184] In some possible implementations, a first number of storage blocks includes a third number of redundant storage blocks, and the sum of the second and third numbers equals the first number. The address information includes the address of the target storage region and the addresses of the third number of redundant storage blocks, for example... Figure 23 The semiconductor device 900 shown can realize, for example Figure 24 The method for operating a semiconductor device, as shown, includes the following steps S121-S124. The specific steps include:

[0185] S121. The storage area decoding circuit outputs the first enable signal according to the address of the target storage area.

[0186] For example, the memory region decoding circuit 904 outputs a first enable signal (i.e., a selected memory address: A0-Am) based on the address of the target memory region (i.e., the selected memory address: A0-Am).

[0187] S122. The memory block decoding circuit outputs a second enable signal based on the address of the third number of redundant memory blocks and the first enable signal.

[0188] S123. The XOR logic circuit receives the third enable signal and outputs a fourth enable signal based on the second and third enable signals. The fourth enable signal is the XOR result of the second and third enable signals.

[0189] In some examples, the third enable signal can be carried in the operation instruction, and can be, for example, ... Figure 1 , Figure 3 or Figure 4 The controller 11200 shown or such Figure 2 The host 21000 and controller 11200 shown can control the level of the third enable signal to control, for example, Figure 23 The semiconductor device 900 shown performs different operations (data writing, data reading, data erasure, or in-memory calculation).

[0190] In one example, if the third enable signal is low, the memory block performs normal storage operations. At this time, the memory block decoding circuit 906 outputs a high-level enable signal to the selected memory block. After passing through the XOR logic circuit 910, the XOR logic circuit 910 outputs a high level, and the selected memory block is activated for normal storage operations (data writing, data reading, or data erasure).

[0191] For example, the operation instructions may include a sixth enable signal (an enable signal when the third enable signal is low). The sixth enable signal indicates that the target storage area is configured to perform a data storage operation. The data storage operation may include, but is not limited to, writing stored data to the target storage area, reading stored data from the target storage area, and erasing stored data from the target storage area.

[0192] In another example, if the third enable signal is high, the XOR logic circuit 910 performs an inverse selection operation, and the memory block performs storage and computation operations. At this time, the memory block decoding circuit 906 outputs a high-level enable signal to the selected memory block. After passing through the XOR logic circuit 910, the XOR logic circuit 910 outputs a low level, the selected memory block is in an inactive state, and the unselected memory blocks are in an active state for storage and computation operations.

[0193] For example, the operation instructions also include a seventh enable signal (an enable signal when the third enable signal is high). The seventh enable signal is used to indicate that the target memory region is configured to perform in-memory computation. Figure 20 , Figure 21 and Figure 22 In the illustrated implementation, the peripheral circuit responds to the operation command by inputting computation data into a second number of working memory blocks to obtain the computation result. The computation result is the result of the computation data and the data stored in the working memory blocks.

[0194] In the above embodiment, both the second and third enable signals are high. After passing through the XOR logic circuit 910, the fourth enable signal output by the XOR logic circuit 910 is low. The selected third number of redundant memory blocks (which may include faulty memory blocks) are in an inactive state, while the unselected second number of working memory blocks are in an active state to perform corresponding operations. The number of the third number of redundant memory blocks is less than the number of the second number of working memory blocks. This is simplified by the inverse selection operation of the XOR logic circuit 910. Figure 23 The control logic of the semiconductor device 900 shown.

[0195] S124. The memory block enable circuit outputs a fifth enable signal to the second number of working memory blocks according to the fourth enable signal. The fifth enable signal is used to select the second number of working memory blocks.

[0196] For example, such as Figure 21 and Figure 22 As shown, the working memory block includes a select line (such as TSG) and a memory string. The memory string includes multiple transistors, with their drain and source lines alternately coupled. The select line is coupled to the gate line of a transistor at one end of the memory string. External circuitry responds to operation commands by inputting computational data (such as V) to the select line in the working memory block. IN0=1, V IN1＝1 V IN2 =0, V IN3＝0 V IN4 =1, V IN5 =1, V IN6 =1, V IN7 =1), to obtain the calculation result, such as: I D0 =1*E(1)+1*P(0)+1*E(1)+1*P(0)+1*E(1)+

[0197] 1*E(1)+1*P(0)+1*P(0).

[0198] In the above embodiments, such as Figure 23 The semiconductor device 900 shown can simplify its circuit structure and control logic, reduce power consumption, and enable flexible selection of multiple memory banks through the inverse selection operation of the XOR logic circuit 910.

[0199] Based on the foregoing Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 20 , Figure 21 , Figure 22 and Figure 23 The semiconductor devices, systems, and electronic devices in the corresponding implementations can achieve, for example... Figure 25 The operation method shown includes the following steps S210-S230, and the specific steps include:

[0200] S210. Obtain the status of the memory block in the semiconductor device.

[0201] In some examples, the controller obtains the status of the memory blocks in the semiconductor device, which includes faulty and normal states. For example, for factory bad blocks, the FTL algorithm needs to identify and manage these bad blocks. When using flash memory, it is first necessary to scan the markings in the memory blocks within the semiconductor device, pick out the bad blocks or faulty memory blocks marked by the manufacturer, and generate a bad block table (BBT). In subsequent use, blocks in the bad block table cannot be selected. For growing bad blocks (GBB): As the semiconductor device is used, along with the wear and tear of the semiconductor device, some good blocks will also become bad blocks during use. The main situations are as follows: (1) When erasing the flash memory block, the bus returns an erase failure status. (2) When writing a flash memory page, the bus returns a write failure status. (3) When reading any data page in the block, if there are too many data errors, exceeding the ECC range, and the error cannot be corrected even after various error mitigation measures. When any of the above three situations occur, the current memory block is considered to have become a faulty memory block, and the block can no longer be selected for use. Convert the block number to its specific location and store it in BBT.

[0202] S220. Based on the state of the memory blocks in the semiconductor device, an operation instruction is sent. The operation instruction includes address information, which is used to determine a target memory region among multiple memory regions and a second number of working memory blocks within the target memory region. The second number is less than the first number.

[0203] In some examples, the operation instructions can be derived from, for example... Figure 1 , Figure 2 and Figure 4 The controller 11200 in the middle sends or such Figure 2 The host 21000 in the middle sends the message.

[0204] S230, in response to the operation command, performs the corresponding operation on the working storage block.

[0205] In some examples, semiconductor devices (such as Figure 1 , Figure 2 , Figure 3 or Figure 4 The semiconductor device (shown) receives and responds to the operation command. The specific execution process of step S230 can be referred to steps S110-S120 and steps S121-S124, which will not be repeated here.

[0206] This application also provides a computer-readable storage medium including instructions. When the instructions are executed on the electronic device or storage system described in the above embodiments, the electronic device or storage system performs the operation method of the semiconductor device described in the above embodiments.

[0207] This application also provides a system, which may include, for example, Figure 1 , Figure 2 or Figure 4 The controller and such Figure 1 , Figure 2 , Figure 3 or Figure 4 A semiconductor device is shown.

[0208] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes peripheral circuitry and a memory cell array, the peripheral circuitry and the memory cell array being coupled together; the memory cell array includes multiple memory regions, each memory region including a first number of memory blocks; the peripheral circuitry is configured to: Receive an operation instruction; the operation instruction includes address information, the address information being used to determine a target storage region among the plurality of storage regions and a second number of working storage blocks within the target storage region; the second number is less than the first number; In response to the operation command, the corresponding operation is performed on the working storage block.

2. The semiconductor device according to claim 1, characterized in that, A third number of storage blocks in the first number of storage blocks are used as redundant storage blocks, and the sum of the second number and the third number is equal to the first number.

3. The semiconductor device according to claim 1, characterized in that, The first number of storage blocks includes a third number of faulty storage blocks, and the sum of the second number and the third number is equal to the first number; The peripheral circuit is configured as follows: Receive a first operation instruction and a second operation instruction; wherein the address information in the first operation instruction and the address information in the second operation instruction are used to determine the same storage region among the plurality of storage regions and the second number of working storage blocks in the same storage region; and In response to the first operation instruction and the second operation instruction, corresponding operations are performed on the second number of working storage blocks.

4. The semiconductor device according to claim 1, characterized in that, The first number of storage blocks includes a fourth number of faulty storage blocks; the sum of the fourth number and the second number is less than the first number; The second number of storage blocks in the fifth number of normal storage blocks are used as working storage blocks; the sum of the fifth number and the fourth number is equal to the first number.

5. The semiconductor device according to claim 4, characterized in that, The plurality of operation instructions include a first operation instruction and a second operation instruction; The address information in the first operation instruction is used to determine the first storage region in the plurality of storage regions and the second number of working storage blocks in the first storage region; The second operation instruction is used to determine the second storage area in the plurality of storage areas and the second number of working storage blocks in the second storage area; When the first storage region and the second storage region are the same storage region, the second number of working storage blocks in the first storage region is different from the second number of working storage blocks in the second storage region.

6. The semiconductor device according to claim 1, characterized in that, The first number of storage blocks includes a sixth number of faulty storage blocks; The difference between the physical address of any faulty storage block in the sixth number of faulty storage blocks and the physical address of any normal storage block in the seventh number of normal storage blocks is less than a preset threshold. The sum of the sixth quantity and the seventh quantity equals the first quantity.

7. The semiconductor device according to claim 1, characterized in that, In each of the storage regions, the physical distance between any two storage blocks in the first number of storage blocks is less than a threshold.

8. The semiconductor device according to claim 2, characterized in that, The address information includes the address of the target storage area and the address of the third number of redundant storage blocks.

9. The semiconductor device according to claim 1, characterized in that, The peripheral circuitry includes a memory area decoding circuit, a memory block decoding circuit, an XOR logic circuit, and a memory block enable circuit, which are coupled in sequence.

10. The semiconductor device according to claim 9, characterized in that, The first number of storage blocks includes a third number of redundant storage blocks, and the sum of the second number and the third number is equal to the first number; the address information includes the address of the target storage region and the address of the third number of redundant storage blocks; The storage area decoding circuit is configured to output a first enable signal based on the address of the target storage area; The memory block decoding circuit is configured to output a second enable signal based on the address of the third number of redundant memory blocks and the first enable signal; The XOR logic circuit is configured to: receive a third enable signal, and output a fourth enable signal based on the second enable signal and the third enable signal; the fourth enable signal is the XOR result of the second enable signal and the third enable signal; The memory block enable circuit is configured to output a fifth enable signal to the second number of working memory blocks according to the fourth enable signal; the fifth enable signal is used to select the second number of working memory blocks.

11. The semiconductor device according to claim 2, characterized in that, At least two of the multiple storage regions share the third number of redundant storage blocks.

12. The semiconductor device according to claim 1, characterized in that, The operation instruction further includes a sixth enable signal; the sixth enable signal is used to indicate that the target storage area is configured to perform a data storage operation; the peripheral circuitry is further configured to: In response to the operation command, storage data is written to the target storage area; or, In response to the operation command, stored data is read from the target storage area; or, In response to the operation command, the stored data in the target storage area is erased.

13. The semiconductor device according to claim 1, characterized in that, The operation instruction further includes a seventh enable signal; the seventh enable signal is used to indicate that the target storage area is configured to perform in-memory computation operations; the peripheral circuit is specifically configured as follows: In response to the operation instruction, computational data is input into the second number of working storage blocks to obtain computational results; the computational results are the result of the computational data and the data stored in the working storage blocks.

14. The semiconductor device according to claim 13, characterized in that, The working memory block includes a select line and a memory string; the memory string includes multiple transistors, the drain lines and source lines of the multiple transistors are alternately coupled, and the select line is coupled to the gate line of a transistor at one end of the memory string; The peripheral circuit is specifically configured as follows: In response to the operation command, computational data is input to the selection line in the working storage block to obtain the computational result.

15. A semiconductor device, characterized in that, The semiconductor device includes: Peripheral circuits; And a storage cell array, the storage cell array being coupled to the peripheral circuitry; the storage cell array includes a plurality of first-level storage elements, each of the first-level storage elements including a plurality of storage blocks; The plurality of storage blocks are configured in a plurality of second-level storage elements, each second-level storage element including a first number of the storage blocks; a second number of the storage blocks in the first number of storage blocks are used as working storage blocks; the second number is less than the first number.

16. The semiconductor device according to claim 15, characterized in that, A third number of storage blocks in the first number of storage blocks are used as redundant storage blocks, and the sum of the second number and the third number is equal to the first number.

17. The semiconductor device according to claim 16, characterized in that, At least two of the plurality of secondary storage elements share the third number of redundant storage blocks.

18. The semiconductor device according to claim 15, characterized in that, The first number of storage blocks includes a fourth number of faulty storage blocks; the sum of the fourth number and the second number is less than the first number; The second number of storage blocks in the fifth number of normal storage blocks are used as working storage blocks; the sum of the fifth number and the fourth number is equal to the first number.

19. The semiconductor device according to claim 15, characterized in that, The first number of storage blocks includes a sixth number of faulty storage blocks; The difference between the physical address of any faulty storage block in the sixth number of faulty storage blocks and the physical address of any normal storage block in the seventh number of normal storage blocks is less than a preset threshold. The sum of the sixth quantity and the seventh quantity equals the first quantity.

20. The semiconductor device according to claim 15, characterized in that, In each of the second-level storage elements, the physical distance between any two storage blocks in the first number of storage blocks is less than a threshold.

21. The semiconductor device according to claim 15, characterized in that, The peripheral circuitry includes a memory area decoding circuit, a memory block decoding circuit, an XOR logic circuit, and a memory block enable circuit, which are coupled in sequence.

22. The semiconductor device according to claim 15, characterized in that, The peripheral circuit is configured as follows: Receive an operation instruction; the operation instruction includes address information, which is used to determine the target second-level storage element and the second number of working storage blocks in the target second-level storage element; In response to the operation command, data operations are performed on the working storage block.

23. The semiconductor device according to claim 22, characterized in that, A third number of storage blocks in the first number of storage blocks are used as redundant storage blocks, and the sum of the second number and the third number is equal to the first number; The address information includes the address of the target second-level storage element and the address of the third number of redundant storage blocks.

24. The semiconductor device according to claim 22, characterized in that, The peripheral circuitry includes a storage area decoding circuit, a storage block decoding circuit, an XOR logic circuit, and a storage block enable circuit, which are coupled in sequence; the first number of storage blocks includes a third number of redundant storage blocks, and the sum of the second number and the third number is equal to the first number; The address information includes the address of the target second-level storage element and the address of the third number of redundant storage blocks; The storage area decoding circuit is configured to output a first enable signal based on the address of the target second-level storage element; The memory block decoding circuit is configured to output a second enable signal based on the address of the third number of redundant memory blocks and the first enable signal; The XOR logic circuit is configured to: receive a third enable signal, and output a fourth enable signal based on the second enable signal and the third enable signal; the fourth enable signal is the XOR result of the second enable signal and the third enable signal; The memory block enable circuit is configured to output a fifth enable signal to the second number of working memory blocks according to the fourth enable signal; the fifth enable signal is used to select the second number of working memory blocks.

25. The semiconductor device according to claim 22, characterized in that, The operation instruction further includes a sixth enable signal; the sixth enable signal is used to indicate that the target second-level storage element is configured to perform a data storage operation; the peripheral circuitry is further configured to: In response to the operation command, stored data is written to the second-level storage element; or, In response to the operation command, stored data is read from the second-level storage element; or, In response to the operation command, the stored data in the second-level storage element is erased.

26. The semiconductor device according to claim 22, characterized in that, The operation instruction further includes a seventh enable signal; the seventh enable signal is used to indicate that the target second-level storage element (bank) is configured to perform stored-value operations; the peripheral circuit is further configured as follows: In response to the operation instruction, computation data is input to the working storage block to obtain a computation result; the computation result is the result of the computation data and the data stored in the working storage block.

27. The semiconductor device according to claim 26, characterized in that, The working memory block includes multiple select lines and memory strings; the memory string includes multiple transistors, the drain lines and source lines of the multiple transistors are alternately coupled, and the select lines are coupled to the gate lines of the transistors at one end of the memory string. The peripheral circuit is specifically configured as follows: In response to the operation command, calculation data is input to the multiple selection lines in the working storage block to obtain the calculation result.

28. The semiconductor device according to any one of claims 15-27, characterized in that, The semiconductor device is a die comprising multiple storage surfaces; the first-level storage element is the storage surface comprising multiple storage cells; the second-level storage element is the storage cell comprising multiple storage blocks.

29. A method of operating a semiconductor device, characterized in that, include: Receive operation instructions; The operation instruction includes address information, which is used to determine a target storage region in multiple storage regions and a second number of working storage blocks in the target storage region; the second number is less than the first number. In response to the operation command, the corresponding operation is performed on the working storage block.

30. The method of operating the semiconductor device according to claim 29, characterized in that, The first number of storage blocks includes a third number of faulty storage blocks, and the sum of the second number and the third number is equal to the first number; The received operation instruction includes: Receive a first operation instruction and a second operation instruction; wherein, the address information in the first operation instruction and the address information in the second operation instruction are used to determine the same storage region among the plurality of storage regions and the second number of working storage blocks in the same storage region; The operation performed on the working storage block in response to the operation instruction includes: In response to the first operation instruction and the second operation instruction, corresponding operations are performed on the second number of working storage blocks.

31. The method of operating the semiconductor device according to claim 29, characterized in that, The first number of storage blocks includes a third number of redundant storage blocks, and the sum of the second number and the third number equals the first number; the address information includes the address of the target storage region and the addresses of the third number of redundant storage blocks; the method further includes: Output a first enable signal based on the address of the target storage region; Based on the addresses of the third number of redundant storage blocks and the first enable signal, output the second enable signal; Receive a third enable signal, and output a fourth enable signal based on the second enable signal and the third enable signal; the fourth enable signal is the XOR result of the second enable signal and the third enable signal; Based on the fourth enable signal, a fifth enable signal is output to the second number of working memory blocks; the fifth enable signal is used to select the second number of working memory blocks.

32. The method of operating the semiconductor device according to claim 29, characterized in that, The operation instruction further includes a sixth enable signal; the sixth enable signal is used to indicate that the target storage area is configured to perform a data storage operation; the method further includes: In response to the operation command, storage data is written to the target storage area; or, In response to the operation command, stored data is read from the target storage area; or, In response to the operation command, the stored data in the target storage area is erased.

33. The method of operating the semiconductor device according to claim 29, characterized in that, The operation instruction also includes a seventh enable signal; the seventh enable signal is used to indicate that the target storage area is configured to perform in-memory computation operations; The operation on the second number of working storage blocks in response to the operation instruction includes: In response to the operation instruction, computational data is input into the second number of working storage blocks to obtain the computational result; The calculation result is the result of the calculation of the calculated data and the data stored in the working storage block.

34. The method of operating the semiconductor device according to claim 29, characterized in that, The working memory block includes multiple select lines and memory strings; the memory string includes multiple transistors, the drain lines and source lines of the multiple transistors are alternately coupled, and the select lines are coupled to the gate lines of the transistors at one end of the memory string. The step of responding to the operation instruction by inputting computation data into the working storage block and obtaining the computation result includes: In response to the operation command, computational data is input to the selection line in the working storage block to obtain the computational result.

35. A system, characterized in that, The system includes a controller and a semiconductor device as described in any one of claims 1-14, wherein the controller and the semiconductor device are coupled; or, the system includes a controller and a semiconductor device as described in any one of claims 15-28, wherein the controller and the semiconductor device are coupled.

36. An electronic device, characterized in that, The electronic device includes a host and the system as described in claim 35; the host and the system are coupled together.

37. An electronic device, characterized in that, The electronic device includes a host and a semiconductor device as described in any one of claims 1-14, wherein the host and the semiconductor device are coupled; or, the electronic device includes a host and a semiconductor device as described in any one of claims 15-28, wherein the host and the semiconductor device are coupled.

38. A computer storage medium, characterized in that, The computer-readable storage medium includes instructions that, when executed on a processor, cause the processor to perform a method of operating the semiconductor device as described in any one of claims 29-34.

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